#include <linux/types.h>
#include <linux/mii.h>

Macros
#define	REG_PM_CTRLSTAT 0x44

#define	REG_PCIE_CAP_LIST 0x58

#define	REG_DEVICE_CAP 0x5C

#define	DEVICE_CAP_MAX_PAYLOAD_MASK 0x7

#define	DEVICE_CAP_MAX_PAYLOAD_SHIFT 0

#define	REG_DEVICE_CTRL 0x60

#define	DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7

#define	DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5

#define	DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7

#define	DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12

#define	REG_VPD_CAP 0x6C

#define	VPD_CAP_ID_MASK 0xff

#define	VPD_CAP_ID_SHIFT 0

#define	VPD_CAP_NEXT_PTR_MASK 0xFF

#define	VPD_CAP_NEXT_PTR_SHIFT 8

#define	VPD_CAP_VPD_ADDR_MASK 0x7FFF

#define	VPD_CAP_VPD_ADDR_SHIFT 16

#define	VPD_CAP_VPD_FLAG 0x80000000

#define	REG_VPD_DATA 0x70

#define	REG_SPI_FLASH_CTRL 0x200

#define	SPI_FLASH_CTRL_STS_NON_RDY 0x1

#define	SPI_FLASH_CTRL_STS_WEN 0x2

#define	SPI_FLASH_CTRL_STS_WPEN 0x80

#define	SPI_FLASH_CTRL_DEV_STS_MASK 0xFF

#define	SPI_FLASH_CTRL_DEV_STS_SHIFT 0

#define	SPI_FLASH_CTRL_INS_MASK 0x7

#define	SPI_FLASH_CTRL_INS_SHIFT 8

#define	SPI_FLASH_CTRL_START 0x800

#define	SPI_FLASH_CTRL_EN_VPD 0x2000

#define	SPI_FLASH_CTRL_LDSTART 0x8000

#define	SPI_FLASH_CTRL_CS_HI_MASK 0x3

#define	SPI_FLASH_CTRL_CS_HI_SHIFT 16

#define	SPI_FLASH_CTRL_CS_HOLD_MASK 0x3

#define	SPI_FLASH_CTRL_CS_HOLD_SHIFT 18

#define	SPI_FLASH_CTRL_CLK_LO_MASK 0x3

#define	SPI_FLASH_CTRL_CLK_LO_SHIFT 20

#define	SPI_FLASH_CTRL_CLK_HI_MASK 0x3

#define	SPI_FLASH_CTRL_CLK_HI_SHIFT 22

#define	SPI_FLASH_CTRL_CS_SETUP_MASK 0x3

#define	SPI_FLASH_CTRL_CS_SETUP_SHIFT 24

#define	SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3

#define	SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26

#define	SPI_FLASH_CTRL_WAIT_READY 0x10000000

#define	REG_SPI_ADDR 0x204

#define	REG_SPI_DATA 0x208

#define	REG_SPI_FLASH_CONFIG 0x20C

#define	SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF

#define	SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0

#define	SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3

#define	SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24

#define	SPI_FLASH_CONFIG_LD_EXIST 0x4000000

#define	REG_SPI_FLASH_OP_PROGRAM 0x210

#define	REG_SPI_FLASH_OP_SC_ERASE 0x211

#define	REG_SPI_FLASH_OP_CHIP_ERASE 0x212

#define	REG_SPI_FLASH_OP_RDID 0x213

#define	REG_SPI_FLASH_OP_WREN 0x214

#define	REG_SPI_FLASH_OP_RDSR 0x215

#define	REG_SPI_FLASH_OP_WRSR 0x216

#define	REG_SPI_FLASH_OP_READ 0x217

#define	REG_TWSI_CTRL 0x218

#define	TWSI_CTRL_LD_OFFSET_MASK 0xFF

#define	TWSI_CTRL_LD_OFFSET_SHIFT 0

#define	TWSI_CTRL_LD_SLV_ADDR_MASK 0x7

#define	TWSI_CTRL_LD_SLV_ADDR_SHIFT 8

#define	TWSI_CTRL_SW_LDSTART 0x800

#define	TWSI_CTRL_HW_LDSTART 0x1000

#define	TWSI_CTRL_SMB_SLV_ADDR_MASK 0x0x7F

#define	TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15

#define	TWSI_CTRL_LD_EXIST 0x400000

#define	TWSI_CTRL_READ_FREQ_SEL_MASK 0x3

#define	TWSI_CTRL_READ_FREQ_SEL_SHIFT 23

#define	TWSI_CTRL_FREQ_SEL_100K 0

#define	TWSI_CTRL_FREQ_SEL_200K 1

#define	TWSI_CTRL_FREQ_SEL_300K 2

#define	TWSI_CTRL_FREQ_SEL_400K 3

#define	TWSI_CTRL_SMB_SLV_ADDR

#define	TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3

#define	TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24

#define	REG_PCIE_DEV_MISC_CTRL 0x21C

#define	PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2

#define	PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1

#define	PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4

#define	PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8

#define	PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10

#define	REG_PCIE_PHYMISC 0x1000

#define	PCIE_PHYMISC_FORCE_RCV_DET 0x4

#define	REG_LTSSM_TEST_MODE 0x12FC

#define	LTSSM_TEST_MODE_DEF 0xE000

#define	REG_MASTER_CTRL 0x1400

#define	MASTER_CTRL_SOFT_RST 0x1

#define	MASTER_CTRL_MTIMER_EN 0x2

#define	MASTER_CTRL_ITIMER_EN 0x4

#define	MASTER_CTRL_MANUAL_INT 0x8

#define	MASTER_CTRL_ITIMER2_EN 0x20

#define	MASTER_CTRL_INT_RDCLR 0x40

#define	MASTER_CTRL_LED_MODE 0x200

#define	MASTER_CTRL_REV_NUM_SHIFT 16

#define	MASTER_CTRL_REV_NUM_MASK 0xff

#define	MASTER_CTRL_DEV_ID_SHIFT 24

#define	MASTER_CTRL_DEV_ID_MASK 0xff

#define	REG_MANUAL_TIMER_INIT 0x1404

#define	REG_IRQ_MODU_TIMER_INIT 0x1408 /* w */

#define	REG_IRQ_MODU_TIMER2_INIT 0x140A /* w */

#define	REG_GPHY_CTRL 0x140C

#define	GPHY_CTRL_EXT_RESET 1

#define	GPHY_CTRL_PIPE_MOD 2

#define	GPHY_CTRL_TEST_MODE_MASK 3

#define	GPHY_CTRL_TEST_MODE_SHIFT 2

#define	GPHY_CTRL_BERT_START 0x10

#define	GPHY_CTRL_GATE_25M_EN 0x20

#define	GPHY_CTRL_LPW_EXIT 0x40

#define	GPHY_CTRL_PHY_IDDQ 0x80

#define	GPHY_CTRL_PHY_IDDQ_DIS 0x100

#define	GPHY_CTRL_PCLK_SEL_DIS 0x200

#define	GPHY_CTRL_HIB_EN 0x400

#define	GPHY_CTRL_HIB_PULSE 0x800

#define	GPHY_CTRL_SEL_ANA_RST 0x1000

#define	GPHY_CTRL_PHY_PLL_ON 0x2000

#define	GPHY_CTRL_PWDOWN_HW 0x4000

#define	GPHY_CTRL_DEFAULT

#define	GPHY_CTRL_PW_WOL_DIS

#define	REG_CMBDISDMA_TIMER 0x140E

#define	REG_IDLE_STATUS 0x1410

#define	IDLE_STATUS_RXMAC 1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */

#define	IDLE_STATUS_TXMAC 2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */

#define	IDLE_STATUS_RXQ 4 /* 1: RXQ state machine is in non-IDLE state. 0: RXQ is idling */

#define	IDLE_STATUS_TXQ 8 /* 1: TXQ state machine is in non-IDLE state. 0: TXQ is idling */

#define	IDLE_STATUS_DMAR 0x10 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling */

#define	IDLE_STATUS_DMAW 0x20 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling */

#define	IDLE_STATUS_SMB 0x40 /* 1: SMB state machine is in non-IDLE state. 0: SMB is idling */

#define	IDLE_STATUS_CMB 0x80 /* 1: CMB state machine is in non-IDLE state. 0: CMB is idling */

#define	REG_MDIO_CTRL 0x1414

#define	MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */

#define	MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register*/

#define	MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */

#define	MDIO_REG_ADDR_SHIFT 16

#define	MDIO_RW 0x200000 /* 1: read, 0: write */

#define	MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */

#define	MDIO_START 0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle*/

#define	MDIO_CLK_SEL_SHIFT 24

#define	MDIO_CLK_25_4 0

#define	MDIO_CLK_25_6 2

#define	MDIO_CLK_25_8 3

#define	MDIO_CLK_25_10 4

#define	MDIO_CLK_25_14 5

#define	MDIO_CLK_25_20 6

#define	MDIO_CLK_25_28 7

#define	MDIO_BUSY 0x8000000

#define	MDIO_AP_EN 0x10000000

#define	MDIO_WAIT_TIMES 10

#define	REG_PHY_STATUS 0x1418

#define	PHY_STATUS_100M 0x20000

#define	PHY_STATUS_EMI_CA 0x40000

#define	REG_BIST0_CTRL 0x141c

#define	BIST0_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */

#define	BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */

#define	BIST0_FUSE_FLAG 0x4 /* 1: Indicating one cell has been fixed */

#define	REG_BIST1_CTRL 0x1420

#define	BIST1_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */

#define	BIST1_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */

#define	BIST1_FUSE_FLAG 0x4

#define	REG_SERDES_LOCK 0x1424

#define	SERDES_LOCK_DETECT 1 /* 1: SerDes lock detected . This signal comes from Analog SerDes */

#define	SERDES_LOCK_DETECT_EN 2 /* 1: Enable SerDes Lock detect function */

#define	REG_MAC_CTRL 0x1480

#define	MAC_CTRL_TX_EN 1 /* 1: Transmit Enable */

#define	MAC_CTRL_RX_EN 2 /* 1: Receive Enable */

#define	MAC_CTRL_TX_FLOW 4 /* 1: Transmit Flow Control Enable */

#define	MAC_CTRL_RX_FLOW 8 /* 1: Receive Flow Control Enable */

#define	MAC_CTRL_LOOPBACK 0x10 /* 1: Loop back at G/MII Interface */

#define	MAC_CTRL_DUPLX 0x20 /* 1: Full-duplex mode 0: Half-duplex mode */

#define	MAC_CTRL_ADD_CRC 0x40 /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */

#define	MAC_CTRL_PAD 0x80 /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */

#define	MAC_CTRL_LENCHK 0x100 /* 1: Instruct MAC to check if length field matches the real packet length */

#define	MAC_CTRL_HUGE_EN 0x200 /* 1: receive Jumbo frame enable */

#define	MAC_CTRL_PRMLEN_SHIFT 10 /* Preamble length */

#define	MAC_CTRL_PRMLEN_MASK 0xf

#define	MAC_CTRL_RMV_VLAN 0x4000 /* 1: to remove VLAN Tag automatically from all receive packets */

#define	MAC_CTRL_PROMIS_EN 0x8000 /* 1: Promiscuous Mode Enable */

#define	MAC_CTRL_TX_PAUSE 0x10000 /* 1: transmit test pause */

#define	MAC_CTRL_SCNT 0x20000 /* 1: shortcut slot time counter */

#define	MAC_CTRL_SRST_TX 0x40000 /* 1: synchronized reset Transmit MAC module */

#define	MAC_CTRL_TX_SIMURST 0x80000 /* 1: transmit simulation reset */

#define	MAC_CTRL_SPEED_SHIFT 20 /* 10: gigabit 01:10M/100M */

#define	MAC_CTRL_SPEED_MASK 0x300000

#define	MAC_CTRL_SPEED_1000 2

#define	MAC_CTRL_SPEED_10_100 1

#define	MAC_CTRL_DBG_TX_BKPRESURE 0x400000 /* 1: transmit maximum backoff (half-duplex test bit) */

#define	MAC_CTRL_TX_HUGE 0x800000 /* 1: transmit huge enable */

#define	MAC_CTRL_RX_CHKSUM_EN 0x1000000 /* 1: RX checksum enable */

#define	MAC_CTRL_MC_ALL_EN 0x2000000 /* 1: upload all multicast frame without error to system */

#define	MAC_CTRL_BC_EN 0x4000000 /* 1: upload all broadcast frame without error to system */

#define	MAC_CTRL_DBG 0x8000000 /* 1: upload all received frame to system (Debug Mode) */

#define	REG_MAC_IPG_IFG 0x1484

#define	MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back inter-packet gap. The default is 96-bit time */

#define	MAC_IPG_IFG_IPGT_MASK 0x7f

#define	MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to enforce in between RX frames */

#define	MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */

#define	MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */

#define	MAC_IPG_IFG_IPGR1_MASK 0x7f

#define	MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */

#define	MAC_IPG_IFG_IPGR2_MASK 0x7f

#define	REG_MAC_STA_ADDR 0x1488

#define	REG_RX_HASH_TABLE 0x1490

#define	REG_MAC_HALF_DUPLX_CTRL 0x1498

#define	MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */

#define	MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff

#define	MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 /* Retransmission maximum, afterwards the packet will be discarded */

#define	MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf

#define	MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */

#define	MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 /* 1: No back-off on collision, immediately start the retransmission */

#define	MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */

#define	MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */

#define	MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */

#define	MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf

#define	MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */

#define	MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */

#define	REG_MTU 0x149c

#define	REG_WOL_CTRL 0x14a0

#define	WOL_PATTERN_EN 0x00000001

#define	WOL_PATTERN_PME_EN 0x00000002

#define	WOL_MAGIC_EN 0x00000004

#define	WOL_MAGIC_PME_EN 0x00000008

#define	WOL_LINK_CHG_EN 0x00000010

#define	WOL_LINK_CHG_PME_EN 0x00000020

#define	WOL_PATTERN_ST 0x00000100

#define	WOL_MAGIC_ST 0x00000200

#define	WOL_LINKCHG_ST 0x00000400

#define	WOL_CLK_SWITCH_EN 0x00008000

#define	WOL_PT0_EN 0x00010000

#define	WOL_PT1_EN 0x00020000

#define	WOL_PT2_EN 0x00040000

#define	WOL_PT3_EN 0x00080000

#define	WOL_PT4_EN 0x00100000

#define	WOL_PT5_EN 0x00200000

#define	WOL_PT6_EN 0x00400000

#define	REG_WOL_PATTERN_LEN 0x14a4

#define	WOL_PT_LEN_MASK 0x7f

#define	WOL_PT0_LEN_SHIFT 0

#define	WOL_PT1_LEN_SHIFT 8

#define	WOL_PT2_LEN_SHIFT 16

#define	WOL_PT3_LEN_SHIFT 24

#define	WOL_PT4_LEN_SHIFT 0

#define	WOL_PT5_LEN_SHIFT 8

#define	WOL_PT6_LEN_SHIFT 16

#define	REG_SRAM_TRD_ADDR 0x1518

#define	REG_SRAM_TRD_LEN 0x151C

#define	REG_SRAM_RXF_ADDR 0x1520

#define	REG_SRAM_RXF_LEN 0x1524

#define	REG_SRAM_TXF_ADDR 0x1528

#define	REG_SRAM_TXF_LEN 0x152C

#define	REG_SRAM_TCPH_ADDR 0x1530

#define	REG_SRAM_PKTH_ADDR 0x1532

#define	REG_LOAD_PTR 0x1534 /* Software sets this bit after the initialization of the head and tail */

#define	REG_RXF3_BASE_ADDR_HI 0x153C

#define	REG_DESC_BASE_ADDR_HI 0x1540

#define	REG_RXF0_BASE_ADDR_HI 0x1540 /* share with DESC BASE ADDR HI */

#define	REG_HOST_RXF0_PAGE0_LO 0x1544

#define	REG_HOST_RXF0_PAGE1_LO 0x1548

#define	REG_TPD_BASE_ADDR_LO 0x154C

#define	REG_RXF1_BASE_ADDR_HI 0x1550

#define	REG_RXF2_BASE_ADDR_HI 0x1554

#define	REG_HOST_RXFPAGE_SIZE 0x1558

#define	REG_TPD_RING_SIZE 0x155C

#define	REG_RSS_KEY0 0x14B0

#define	REG_RSS_KEY1 0x14B4

#define	REG_RSS_KEY2 0x14B8

#define	REG_RSS_KEY3 0x14BC

#define	REG_RSS_KEY4 0x14C0

#define	REG_RSS_KEY5 0x14C4

#define	REG_RSS_KEY6 0x14C8

#define	REG_RSS_KEY7 0x14CC

#define	REG_RSS_KEY8 0x14D0

#define	REG_RSS_KEY9 0x14D4

#define	REG_IDT_TABLE4 0x14E0

#define	REG_IDT_TABLE5 0x14E4

#define	REG_IDT_TABLE6 0x14E8

#define	REG_IDT_TABLE7 0x14EC

#define	REG_IDT_TABLE0 0x1560

#define	REG_IDT_TABLE1 0x1564

#define	REG_IDT_TABLE2 0x1568

#define	REG_IDT_TABLE3 0x156C

#define	REG_IDT_TABLE REG_IDT_TABLE0

#define	REG_RSS_HASH_VALUE 0x1570

#define	REG_RSS_HASH_FLAG 0x1574

#define	REG_BASE_CPU_NUMBER 0x157C

#define	REG_TXQ_CTRL 0x1580

#define	TXQ_CTRL_NUM_TPD_BURST_MASK 0xF

#define	TXQ_CTRL_NUM_TPD_BURST_SHIFT 0

#define	TXQ_CTRL_EN 0x20 /* 1: Enable TXQ */

#define	TXQ_CTRL_ENH_MODE 0x40 /* Performance enhancement mode, in which up to two back-to-back DMA read commands might be dispatched. */

#define	TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length. */

#define	TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff

#define	REG_TX_EARLY_TH 0x1584 /* Jumbo frame threshold in QWORD unit. Packet greater than */

#define	TX_TX_EARLY_TH_MASK 0x7ff

#define	TX_TX_EARLY_TH_SHIFT 0

#define	REG_RXQ_CTRL 0x15A0

#define	RXQ_CTRL_PBA_ALIGN_32 0 /* rx-packet alignment */

#define	RXQ_CTRL_PBA_ALIGN_64 1

#define	RXQ_CTRL_PBA_ALIGN_128 2

#define	RXQ_CTRL_PBA_ALIGN_256 3

#define	RXQ_CTRL_Q1_EN 0x10

#define	RXQ_CTRL_Q2_EN 0x20

#define	RXQ_CTRL_Q3_EN 0x40

#define	RXQ_CTRL_IPV6_XSUM_VERIFY_EN 0x80

#define	RXQ_CTRL_HASH_TLEN_SHIFT 8

#define	RXQ_CTRL_HASH_TLEN_MASK 0xFF

#define	RXQ_CTRL_HASH_TYPE_IPV4 0x10000

#define	RXQ_CTRL_HASH_TYPE_IPV4_TCP 0x20000

#define	RXQ_CTRL_HASH_TYPE_IPV6 0x40000

#define	RXQ_CTRL_HASH_TYPE_IPV6_TCP 0x80000

#define	RXQ_CTRL_RSS_MODE_DISABLE 0

#define	RXQ_CTRL_RSS_MODE_SQSINT 0x4000000

#define	RXQ_CTRL_RSS_MODE_MQUESINT 0x8000000

#define	RXQ_CTRL_RSS_MODE_MQUEMINT 0xC000000

#define	RXQ_CTRL_NIP_QUEUE_SEL_TBL 0x10000000

#define	RXQ_CTRL_HASH_ENABLE 0x20000000

#define	RXQ_CTRL_CUT_THRU_EN 0x40000000

#define	RXQ_CTRL_EN 0x80000000

#define	REG_RXQ_JMBOSZ_RRDTIM 0x15A4

#define	RXQ_JMBOSZ_TH_MASK 0x7ff

#define	RXQ_JMBOSZ_TH_SHIFT 0 /* RRD retirement timer. Decrement by 1 after every 512ns passes*/

#define	RXQ_JMBO_LKAH_MASK 0xf

#define	RXQ_JMBO_LKAH_SHIFT 11

#define	REG_RXQ_RXF_PAUSE_THRESH 0x15A8

#define	RXQ_RXF_PAUSE_TH_HI_SHIFT 0

#define	RXQ_RXF_PAUSE_TH_HI_MASK 0xfff

#define	RXQ_RXF_PAUSE_TH_LO_SHIFT 16

#define	RXQ_RXF_PAUSE_TH_LO_MASK 0xfff

#define	REG_DMA_CTRL 0x15C0

#define	DMA_CTRL_DMAR_IN_ORDER 0x1

#define	DMA_CTRL_DMAR_ENH_ORDER 0x2

#define	DMA_CTRL_DMAR_OUT_ORDER 0x4

#define	DMA_CTRL_RCB_VALUE 0x8

#define	DMA_CTRL_DMAR_BURST_LEN_SHIFT 4

#define	DMA_CTRL_DMAR_BURST_LEN_MASK 7

#define	DMA_CTRL_DMAW_BURST_LEN_SHIFT 7

#define	DMA_CTRL_DMAW_BURST_LEN_MASK 7

#define	DMA_CTRL_DMAR_REQ_PRI 0x400

#define	DMA_CTRL_DMAR_DLY_CNT_MASK 0x1F

#define	DMA_CTRL_DMAR_DLY_CNT_SHIFT 11

#define	DMA_CTRL_DMAW_DLY_CNT_MASK 0xF

#define	DMA_CTRL_DMAW_DLY_CNT_SHIFT 16

#define	DMA_CTRL_TXCMB_EN 0x100000

#define	DMA_CTRL_RXCMB_EN 0x200000

#define	REG_SMB_STAT_TIMER 0x15C4

#define	REG_TRIG_RRD_THRESH 0x15CA

#define	REG_TRIG_TPD_THRESH 0x15C8

#define	REG_TRIG_TXTIMER 0x15CC

#define	REG_TRIG_RXTIMER 0x15CE

#define	REG_HOST_RXF1_PAGE0_LO 0x15D0

#define	REG_HOST_RXF1_PAGE1_LO 0x15D4

#define	REG_HOST_RXF2_PAGE0_LO 0x15D8

#define	REG_HOST_RXF2_PAGE1_LO 0x15DC

#define	REG_HOST_RXF3_PAGE0_LO 0x15E0

#define	REG_HOST_RXF3_PAGE1_LO 0x15E4

#define	REG_MB_RXF1_RADDR 0x15B4

#define	REG_MB_RXF2_RADDR 0x15B8

#define	REG_MB_RXF3_RADDR 0x15BC

#define	REG_MB_TPD_PROD_IDX 0x15F0

#define	REG_HOST_RXF0_PAGE0_VLD 0x15F4

#define	HOST_RXF_VALID 1

#define	HOST_RXF_PAGENO_SHIFT 1

#define	HOST_RXF_PAGENO_MASK 0x7F

#define	REG_HOST_RXF0_PAGE1_VLD 0x15F5

#define	REG_HOST_RXF1_PAGE0_VLD 0x15F6

#define	REG_HOST_RXF1_PAGE1_VLD 0x15F7

#define	REG_HOST_RXF2_PAGE0_VLD 0x15F8

#define	REG_HOST_RXF2_PAGE1_VLD 0x15F9

#define	REG_HOST_RXF3_PAGE0_VLD 0x15FA

#define	REG_HOST_RXF3_PAGE1_VLD 0x15FB

#define	REG_ISR 0x1600

#define	ISR_SMB 1

#define	ISR_TIMER 2 /* Interrupt when Timer is counted down to zero */

#define	ISR_MANUAL 4

#define	ISR_HW_RXF_OV 8 /* RXF overflow interrupt */

#define	ISR_HOST_RXF0_OV 0x10

#define	ISR_HOST_RXF1_OV 0x20

#define	ISR_HOST_RXF2_OV 0x40

#define	ISR_HOST_RXF3_OV 0x80

#define	ISR_TXF_UN 0x100

#define	ISR_RX0_PAGE_FULL 0x200

#define	ISR_DMAR_TO_RST 0x400

#define	ISR_DMAW_TO_RST 0x800

#define	ISR_GPHY 0x1000

#define	ISR_TX_CREDIT 0x2000

#define	ISR_GPHY_LPW 0x4000 /* GPHY low power state interrupt */

#define	ISR_RX_PKT 0x10000 /* One packet received, triggered by RFD */

#define	ISR_TX_PKT 0x20000 /* One packet transmitted, triggered by TPD */

#define	ISR_TX_DMA 0x40000

#define	ISR_RX_PKT_1 0x80000

#define	ISR_RX_PKT_2 0x100000

#define	ISR_RX_PKT_3 0x200000

#define	ISR_MAC_RX 0x400000

#define	ISR_MAC_TX 0x800000

#define	ISR_UR_DETECTED 0x1000000

#define	ISR_FERR_DETECTED 0x2000000

#define	ISR_NFERR_DETECTED 0x4000000

#define	ISR_CERR_DETECTED 0x8000000

#define	ISR_PHY_LINKDOWN 0x10000000

#define	ISR_DIS_INT 0x80000000

#define	REG_IMR 0x1604

#define	IMR_NORMAL_MASK

#define	ISR_TX_EVENT (ISR_TXF_UN \| ISR_TX_PKT)

#define	ISR_RX_EVENT (ISR_HOST_RXF0_OV \| ISR_HW_RXF_OV \| ISR_RX_PKT)

#define	REG_MAC_RX_STATUS_BIN 0x1700

#define	REG_MAC_RX_STATUS_END 0x175c

#define	REG_MAC_TX_STATUS_BIN 0x1760

#define	REG_MAC_TX_STATUS_END 0x17c0

#define	REG_HOST_RXF0_PAGEOFF 0x1800

#define	REG_TPD_CONS_IDX 0x1804

#define	REG_HOST_RXF1_PAGEOFF 0x1808

#define	REG_HOST_RXF2_PAGEOFF 0x180C

#define	REG_HOST_RXF3_PAGEOFF 0x1810

#define	REG_HOST_RXF0_MB0_LO 0x1820

#define	REG_HOST_RXF0_MB1_LO 0x1824

#define	REG_HOST_RXF1_MB0_LO 0x1828

#define	REG_HOST_RXF1_MB1_LO 0x182C

#define	REG_HOST_RXF2_MB0_LO 0x1830

#define	REG_HOST_RXF2_MB1_LO 0x1834

#define	REG_HOST_RXF3_MB0_LO 0x1838

#define	REG_HOST_RXF3_MB1_LO 0x183C

#define	REG_HOST_TX_CMB_LO 0x1840

#define	REG_HOST_SMB_ADDR_LO 0x1844

#define	REG_DEBUG_DATA0 0x1900

#define	REG_DEBUG_DATA1 0x1904

#define	MII_AT001_PSCR 0x10

#define	MII_AT001_PSSR 0x11

#define	MII_INT_CTRL 0x12

#define	MII_INT_STATUS 0x13

#define	MII_SMARTSPEED 0x14

#define	MII_LBRERROR 0x18

#define	MII_RESV2 0x1a

#define	MII_DBG_ADDR 0x1D

#define	MII_DBG_DATA 0x1E

#define	MII_AR_DEFAULT_CAP_MASK 0

#define	MII_AT001_CR_1000T_SPEED_MASK (ADVERTISE_1000FULL \| ADVERTISE_1000HALF)

#define	MII_AT001_CR_1000T_DEFAULT_CAP_MASK MII_AT001_CR_1000T_SPEED_MASK

#define	MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */

#define	MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */

#define	MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */

#define	MII_AT001_PSCR_MAC_POWERDOWN 0x0008

#define	MII_AT001_PSCR_CLK125_DISABLE

#define	MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */

#define	MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */

#define	MII_AT001_PSCR_AUTO_X_1000T

#define	MII_AT001_PSCR_AUTO_X_MODE

#define	MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080

#define	MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100

#define	MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */

#define	MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */

#define	MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */

#define	MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1

#define	MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5

#define	MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7

#define	MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */

#define	MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */

#define	MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */

#define	MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */

#define	MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */

#define	MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */

Functions
s32	atl1e_reset_hw (struct atl1e_hw *hw)

s32	atl1e_read_mac_addr (struct atl1e_hw *hw)

s32	atl1e_init_hw (struct atl1e_hw *hw)

s32	atl1e_phy_commit (struct atl1e_hw *hw)

s32	atl1e_get_speed_and_duplex (struct atl1e_hw hw, u16 speed, u16 *duplex)

u32	atl1e_auto_get_fc (struct atl1e_adapter *adapter, u16 duplex)

u32	atl1e_hash_mc_addr (struct atl1e_hw hw, u8 mc_addr)

void	atl1e_hash_set (struct atl1e_hw *hw, u32 hash_value)

s32	atl1e_read_phy_reg (struct atl1e_hw hw, u16 reg_addr, u16 phy_data)

s32	atl1e_write_phy_reg (struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)

s32	atl1e_validate_mdi_setting (struct atl1e_hw *hw)

void	atl1e_hw_set_mac_addr (struct atl1e_hw *hw)

bool	atl1e_read_eeprom (struct atl1e_hw hw, u32 offset, u32 p_value)

bool	atl1e_write_eeprom (struct atl1e_hw *hw, u32 offset, u32 value)

s32	atl1e_phy_enter_power_saving (struct atl1e_hw *hw)

s32	atl1e_phy_leave_power_saving (struct atl1e_hw *hw)

s32	atl1e_phy_init (struct atl1e_hw *hw)

int	atl1e_check_eeprom_exist (struct atl1e_hw *hw)

void	atl1e_force_ps (struct atl1e_hw *hw)

s32	atl1e_restart_autoneg (struct atl1e_hw *hw)

Macro Definition Documentation

#define BIST0_FUSE_FLAG 0x4 /* 1: Indicating one cell has been fixed */

Definition at line 260 of file atl1e_hw.h.

#define BIST0_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */

Definition at line 256 of file atl1e_hw.h.

#define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */

Definition at line 258 of file atl1e_hw.h.

#define BIST1_FUSE_FLAG 0x4

Definition at line 268 of file atl1e_hw.h.

#define BIST1_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */

Definition at line 264 of file atl1e_hw.h.

#define BIST1_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */

Definition at line 266 of file atl1e_hw.h.

#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7

Definition at line 59 of file atl1e_hw.h.

#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0

Definition at line 60 of file atl1e_hw.h.

#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7

Definition at line 63 of file atl1e_hw.h.

#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5

Definition at line 64 of file atl1e_hw.h.

#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7

Definition at line 65 of file atl1e_hw.h.

#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12

Definition at line 66 of file atl1e_hw.h.

#define DMA_CTRL_DMAR_BURST_LEN_MASK 7

Definition at line 496 of file atl1e_hw.h.

#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4

Definition at line 495 of file atl1e_hw.h.

#define DMA_CTRL_DMAR_DLY_CNT_MASK 0x1F

Definition at line 500 of file atl1e_hw.h.

#define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11

Definition at line 501 of file atl1e_hw.h.

#define DMA_CTRL_DMAR_ENH_ORDER 0x2

Definition at line 492 of file atl1e_hw.h.

#define DMA_CTRL_DMAR_IN_ORDER 0x1

Definition at line 491 of file atl1e_hw.h.

#define DMA_CTRL_DMAR_OUT_ORDER 0x4

Definition at line 493 of file atl1e_hw.h.

#define DMA_CTRL_DMAR_REQ_PRI 0x400

Definition at line 499 of file atl1e_hw.h.

#define DMA_CTRL_DMAW_BURST_LEN_MASK 7

Definition at line 498 of file atl1e_hw.h.

#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7

Definition at line 497 of file atl1e_hw.h.

#define DMA_CTRL_DMAW_DLY_CNT_MASK 0xF

Definition at line 502 of file atl1e_hw.h.

#define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16

Definition at line 503 of file atl1e_hw.h.

#define DMA_CTRL_RCB_VALUE 0x8

Definition at line 494 of file atl1e_hw.h.

#define DMA_CTRL_RXCMB_EN 0x200000

Definition at line 505 of file atl1e_hw.h.

#define DMA_CTRL_TXCMB_EN 0x100000

Definition at line 504 of file atl1e_hw.h.

#define GPHY_CTRL_BERT_START 0x10

Definition at line 187 of file atl1e_hw.h.

#define GPHY_CTRL_DEFAULT

Value:

(\
        GPHY_CTRL_PHY_PLL_ON    |\
        GPHY_CTRL_SEL_ANA_RST   |\
        GPHY_CTRL_HIB_PULSE |\
        GPHY_CTRL_HIB_EN)

Definition at line 198 of file atl1e_hw.h.

#define GPHY_CTRL_EXT_RESET 1

Definition at line 183 of file atl1e_hw.h.

#define GPHY_CTRL_GATE_25M_EN 0x20

Definition at line 188 of file atl1e_hw.h.

#define GPHY_CTRL_HIB_EN 0x400

Definition at line 193 of file atl1e_hw.h.

#define GPHY_CTRL_HIB_PULSE 0x800

Definition at line 194 of file atl1e_hw.h.

#define GPHY_CTRL_LPW_EXIT 0x40

Definition at line 189 of file atl1e_hw.h.

#define GPHY_CTRL_PCLK_SEL_DIS 0x200

Definition at line 192 of file atl1e_hw.h.

#define GPHY_CTRL_PHY_IDDQ 0x80

Definition at line 190 of file atl1e_hw.h.

#define GPHY_CTRL_PHY_IDDQ_DIS 0x100

Definition at line 191 of file atl1e_hw.h.

#define GPHY_CTRL_PHY_PLL_ON 0x2000

Definition at line 196 of file atl1e_hw.h.

#define GPHY_CTRL_PIPE_MOD 2

Definition at line 184 of file atl1e_hw.h.

#define GPHY_CTRL_PW_WOL_DIS

Value:

(\
        GPHY_CTRL_PHY_PLL_ON    |\
        GPHY_CTRL_SEL_ANA_RST   |\
        GPHY_CTRL_HIB_PULSE |\
        GPHY_CTRL_HIB_EN    |\
        GPHY_CTRL_PWDOWN_HW |\
        GPHY_CTRL_PCLK_SEL_DIS  |\
        GPHY_CTRL_PHY_IDDQ)

Definition at line 204 of file atl1e_hw.h.

#define GPHY_CTRL_PWDOWN_HW 0x4000

Definition at line 197 of file atl1e_hw.h.

#define GPHY_CTRL_SEL_ANA_RST 0x1000

Definition at line 195 of file atl1e_hw.h.

#define GPHY_CTRL_TEST_MODE_MASK 3

Definition at line 185 of file atl1e_hw.h.

#define GPHY_CTRL_TEST_MODE_SHIFT 2

Definition at line 186 of file atl1e_hw.h.

#define HOST_RXF_PAGENO_MASK 0x7F

Definition at line 533 of file atl1e_hw.h.

#define HOST_RXF_PAGENO_SHIFT 1

Definition at line 532 of file atl1e_hw.h.

#define HOST_RXF_VALID 1

Definition at line 531 of file atl1e_hw.h.

#define IDLE_STATUS_CMB 0x80 /* 1: CMB state machine is in non-IDLE state. 0: CMB is idling */

Definition at line 226 of file atl1e_hw.h.

#define IDLE_STATUS_DMAR 0x10 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling */

Definition at line 223 of file atl1e_hw.h.

#define IDLE_STATUS_DMAW 0x20 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling */

Definition at line 224 of file atl1e_hw.h.

#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */

Definition at line 219 of file atl1e_hw.h.

#define IDLE_STATUS_RXQ 4 /* 1: RXQ state machine is in non-IDLE state. 0: RXQ is idling */

Definition at line 221 of file atl1e_hw.h.

#define IDLE_STATUS_SMB 0x40 /* 1: SMB state machine is in non-IDLE state. 0: SMB is idling */

Definition at line 225 of file atl1e_hw.h.

#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */

Definition at line 220 of file atl1e_hw.h.

#define IDLE_STATUS_TXQ 8 /* 1: TXQ state machine is in non-IDLE state. 0: TXQ is idling */

Definition at line 222 of file atl1e_hw.h.

#define IMR_NORMAL_MASK

Value:

(\
        ISR_SMB         |\
        ISR_TXF_UN      |\
        ISR_HW_RXF_OV   |\
        ISR_HOST_RXF0_OV|\
        ISR_MANUAL      |\
        ISR_GPHY        |\
        ISR_GPHY_LPW    |\
        ISR_DMAR_TO_RST |\
        ISR_DMAW_TO_RST |\
        ISR_PHY_LINKDOWN|\
        ISR_RX_PKT      |\
        ISR_TX_PKT)

Definition at line 583 of file atl1e_hw.h.

#define ISR_CERR_DETECTED 0x8000000

Definition at line 574 of file atl1e_hw.h.

#define ISR_DIS_INT 0x80000000

Definition at line 576 of file atl1e_hw.h.

#define ISR_DMAR_TO_RST 0x400

Definition at line 558 of file atl1e_hw.h.

#define ISR_DMAW_TO_RST 0x800

Definition at line 559 of file atl1e_hw.h.

#define ISR_FERR_DETECTED 0x2000000

Definition at line 572 of file atl1e_hw.h.

#define ISR_GPHY 0x1000

Definition at line 560 of file atl1e_hw.h.

#define ISR_GPHY_LPW 0x4000 /* GPHY low power state interrupt */

Definition at line 562 of file atl1e_hw.h.

#define ISR_HOST_RXF0_OV 0x10

Definition at line 552 of file atl1e_hw.h.

#define ISR_HOST_RXF1_OV 0x20

Definition at line 553 of file atl1e_hw.h.

#define ISR_HOST_RXF2_OV 0x40

Definition at line 554 of file atl1e_hw.h.

#define ISR_HOST_RXF3_OV 0x80

Definition at line 555 of file atl1e_hw.h.

#define ISR_HW_RXF_OV 8 /* RXF overflow interrupt */

Definition at line 551 of file atl1e_hw.h.

#define ISR_MAC_RX 0x400000

Definition at line 569 of file atl1e_hw.h.

#define ISR_MAC_TX 0x800000

Definition at line 570 of file atl1e_hw.h.

#define ISR_MANUAL 4

Definition at line 550 of file atl1e_hw.h.

#define ISR_NFERR_DETECTED 0x4000000

Definition at line 573 of file atl1e_hw.h.

#define ISR_PHY_LINKDOWN 0x10000000

Definition at line 575 of file atl1e_hw.h.

#define ISR_RX0_PAGE_FULL 0x200

Definition at line 557 of file atl1e_hw.h.

#define ISR_RX_EVENT (ISR_HOST_RXF0_OV | ISR_HW_RXF_OV | ISR_RX_PKT)

Definition at line 598 of file atl1e_hw.h.

#define ISR_RX_PKT 0x10000 /* One packet received, triggered by RFD */

Definition at line 563 of file atl1e_hw.h.

#define ISR_RX_PKT_1 0x80000

Definition at line 566 of file atl1e_hw.h.

#define ISR_RX_PKT_2 0x100000

Definition at line 567 of file atl1e_hw.h.

#define ISR_RX_PKT_3 0x200000

Definition at line 568 of file atl1e_hw.h.

#define ISR_SMB 1

Definition at line 544 of file atl1e_hw.h.

#define ISR_TIMER 2 /* Interrupt when Timer is counted down to zero */

Definition at line 545 of file atl1e_hw.h.

#define ISR_TX_CREDIT 0x2000

Definition at line 561 of file atl1e_hw.h.

#define ISR_TX_DMA 0x40000

Definition at line 565 of file atl1e_hw.h.

#define ISR_TX_EVENT (ISR_TXF_UN | ISR_TX_PKT)

Definition at line 597 of file atl1e_hw.h.

#define ISR_TX_PKT 0x20000 /* One packet transmitted, triggered by TPD */

Definition at line 564 of file atl1e_hw.h.

#define ISR_TXF_UN 0x100

Definition at line 556 of file atl1e_hw.h.

#define ISR_UR_DETECTED 0x1000000

Definition at line 571 of file atl1e_hw.h.

#define LTSSM_TEST_MODE_DEF 0xE000

Definition at line 157 of file atl1e_hw.h.

#define MAC_CTRL_ADD_CRC 0x40 /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */

Definition at line 283 of file atl1e_hw.h.

#define MAC_CTRL_BC_EN 0x4000000 /* 1: upload all broadcast frame without error to system */

Definition at line 303 of file atl1e_hw.h.

#define MAC_CTRL_DBG 0x8000000 /* 1: upload all received frame to system (Debug Mode) */

Definition at line 304 of file atl1e_hw.h.

#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 /* 1: transmit maximum backoff (half-duplex test bit) */

Definition at line 299 of file atl1e_hw.h.

#define MAC_CTRL_DUPLX 0x20 /* 1: Full-duplex mode 0: Half-duplex mode */

Definition at line 282 of file atl1e_hw.h.

#define MAC_CTRL_HUGE_EN 0x200 /* 1: receive Jumbo frame enable */

Definition at line 286 of file atl1e_hw.h.

#define MAC_CTRL_LENCHK 0x100 /* 1: Instruct MAC to check if length field matches the real packet length */

Definition at line 285 of file atl1e_hw.h.

#define MAC_CTRL_LOOPBACK 0x10 /* 1: Loop back at G/MII Interface */

Definition at line 281 of file atl1e_hw.h.

#define MAC_CTRL_MC_ALL_EN 0x2000000 /* 1: upload all multicast frame without error to system */

Definition at line 302 of file atl1e_hw.h.

#define MAC_CTRL_PAD 0x80 /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */

Definition at line 284 of file atl1e_hw.h.

#define MAC_CTRL_PRMLEN_MASK 0xf

Definition at line 288 of file atl1e_hw.h.

#define MAC_CTRL_PRMLEN_SHIFT 10 /* Preamble length */

Definition at line 287 of file atl1e_hw.h.

#define MAC_CTRL_PROMIS_EN 0x8000 /* 1: Promiscuous Mode Enable */

Definition at line 290 of file atl1e_hw.h.

#define MAC_CTRL_RMV_VLAN 0x4000 /* 1: to remove VLAN Tag automatically from all receive packets */

Definition at line 289 of file atl1e_hw.h.

#define MAC_CTRL_RX_CHKSUM_EN 0x1000000 /* 1: RX checksum enable */

Definition at line 301 of file atl1e_hw.h.

#define MAC_CTRL_RX_EN 2 /* 1: Receive Enable */

Definition at line 278 of file atl1e_hw.h.

#define MAC_CTRL_RX_FLOW 8 /* 1: Receive Flow Control Enable */

Definition at line 280 of file atl1e_hw.h.

#define MAC_CTRL_SCNT 0x20000 /* 1: shortcut slot time counter */

Definition at line 292 of file atl1e_hw.h.

#define MAC_CTRL_SPEED_1000 2

Definition at line 297 of file atl1e_hw.h.

#define MAC_CTRL_SPEED_10_100 1

Definition at line 298 of file atl1e_hw.h.

#define MAC_CTRL_SPEED_MASK 0x300000

Definition at line 296 of file atl1e_hw.h.

#define MAC_CTRL_SPEED_SHIFT 20 /* 10: gigabit 01:10M/100M */

Definition at line 295 of file atl1e_hw.h.

#define MAC_CTRL_SRST_TX 0x40000 /* 1: synchronized reset Transmit MAC module */

Definition at line 293 of file atl1e_hw.h.

#define MAC_CTRL_TX_EN 1 /* 1: Transmit Enable */

Definition at line 277 of file atl1e_hw.h.

#define MAC_CTRL_TX_FLOW 4 /* 1: Transmit Flow Control Enable */

Definition at line 279 of file atl1e_hw.h.

#define MAC_CTRL_TX_HUGE 0x800000 /* 1: transmit huge enable */

Definition at line 300 of file atl1e_hw.h.

#define MAC_CTRL_TX_PAUSE 0x10000 /* 1: transmit test pause */

Definition at line 291 of file atl1e_hw.h.

#define MAC_CTRL_TX_SIMURST 0x80000 /* 1: transmit simulation reset */

Definition at line 294 of file atl1e_hw.h.

#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */

Definition at line 333 of file atl1e_hw.h.

#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf

Definition at line 335 of file atl1e_hw.h.

#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */

Definition at line 334 of file atl1e_hw.h.

#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */

Definition at line 330 of file atl1e_hw.h.

#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */

Definition at line 337 of file atl1e_hw.h.

#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */

Definition at line 336 of file atl1e_hw.h.

#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff

Definition at line 327 of file atl1e_hw.h.

#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */

Definition at line 326 of file atl1e_hw.h.

#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 /* 1: No back-off on collision, immediately start the retransmission */

Definition at line 331 of file atl1e_hw.h.

#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */

Definition at line 332 of file atl1e_hw.h.

#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf

Definition at line 329 of file atl1e_hw.h.

#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 /* Retransmission maximum, afterwards the packet will be discarded */

Definition at line 328 of file atl1e_hw.h.

#define MAC_IPG_IFG_IPGR1_MASK 0x7f

Definition at line 313 of file atl1e_hw.h.

#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */

Definition at line 312 of file atl1e_hw.h.

#define MAC_IPG_IFG_IPGR2_MASK 0x7f

Definition at line 315 of file atl1e_hw.h.

#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */

Definition at line 314 of file atl1e_hw.h.

#define MAC_IPG_IFG_IPGT_MASK 0x7f

Definition at line 309 of file atl1e_hw.h.

#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back inter-packet gap. The default is 96-bit time */

Definition at line 308 of file atl1e_hw.h.

#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */

Definition at line 311 of file atl1e_hw.h.

#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to enforce in between RX frames */

Definition at line 310 of file atl1e_hw.h.

#define MASTER_CTRL_DEV_ID_MASK 0xff

Definition at line 171 of file atl1e_hw.h.

#define MASTER_CTRL_DEV_ID_SHIFT 24

Definition at line 170 of file atl1e_hw.h.

#define MASTER_CTRL_INT_RDCLR 0x40

Definition at line 166 of file atl1e_hw.h.

#define MASTER_CTRL_ITIMER2_EN 0x20

Definition at line 165 of file atl1e_hw.h.

#define MASTER_CTRL_ITIMER_EN 0x4

Definition at line 163 of file atl1e_hw.h.

#define MASTER_CTRL_LED_MODE 0x200

Definition at line 167 of file atl1e_hw.h.

#define MASTER_CTRL_MANUAL_INT 0x8

Definition at line 164 of file atl1e_hw.h.

#define MASTER_CTRL_MTIMER_EN 0x2

Definition at line 162 of file atl1e_hw.h.

#define MASTER_CTRL_REV_NUM_MASK 0xff

Definition at line 169 of file atl1e_hw.h.

#define MASTER_CTRL_REV_NUM_SHIFT 16

Definition at line 168 of file atl1e_hw.h.

#define MASTER_CTRL_SOFT_RST 0x1

Definition at line 161 of file atl1e_hw.h.

#define MDIO_AP_EN 0x10000000

Definition at line 246 of file atl1e_hw.h.

#define MDIO_BUSY 0x8000000

Definition at line 245 of file atl1e_hw.h.

#define MDIO_CLK_25_10 4

Definition at line 241 of file atl1e_hw.h.

#define MDIO_CLK_25_14 5

Definition at line 242 of file atl1e_hw.h.

#define MDIO_CLK_25_20 6

Definition at line 243 of file atl1e_hw.h.

#define MDIO_CLK_25_28 7

Definition at line 244 of file atl1e_hw.h.

#define MDIO_CLK_25_4 0

Definition at line 238 of file atl1e_hw.h.

#define MDIO_CLK_25_6 2

Definition at line 239 of file atl1e_hw.h.

#define MDIO_CLK_25_8 3

Definition at line 240 of file atl1e_hw.h.

#define MDIO_CLK_SEL_SHIFT 24

Definition at line 237 of file atl1e_hw.h.

#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */

Definition at line 230 of file atl1e_hw.h.

#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register*/

Definition at line 231 of file atl1e_hw.h.

#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */

Definition at line 232 of file atl1e_hw.h.

#define MDIO_REG_ADDR_SHIFT 16

Definition at line 233 of file atl1e_hw.h.

#define MDIO_RW 0x200000 /* 1: read, 0: write */

Definition at line 234 of file atl1e_hw.h.

#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle*/

Definition at line 236 of file atl1e_hw.h.

#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */

Definition at line 235 of file atl1e_hw.h.

#define MDIO_WAIT_TIMES 10

Definition at line 247 of file atl1e_hw.h.

#define MII_AR_DEFAULT_CAP_MASK 0

Definition at line 644 of file atl1e_hw.h.

#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK MII_AT001_CR_1000T_SPEED_MASK

Definition at line 649 of file atl1e_hw.h.

#define MII_AT001_CR_1000T_SPEED_MASK (ADVERTISE_1000FULL | ADVERTISE_1000HALF)

Definition at line 647 of file atl1e_hw.h.

#define MII_AT001_PSCR 0x10

Definition at line 632 of file atl1e_hw.h.

#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080

Definition at line 662 of file atl1e_hw.h.

#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7

Definition at line 674 of file atl1e_hw.h.

#define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */

Definition at line 671 of file atl1e_hw.h.

#define MII_AT001_PSCR_AUTO_X_1000T

Value:

0x0040  /* 1000BASE-T: Auto crossover,
                             *  100BASE-TX/10BASE-T:
                             *  MDI Mode
                             */

Definition at line 660 of file atl1e_hw.h.

#define MII_AT001_PSCR_AUTO_X_MODE

Value:

0x0060  /* Auto crossover enabled
                             * all speeds.
                             */

Definition at line 661 of file atl1e_hw.h.

#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5

Definition at line 673 of file atl1e_hw.h.

#define MII_AT001_PSCR_CLK125_DISABLE

Value:

0x0010  /* 1=CLK125 low,
                             * 0=CLK125 toggling
                             */

Definition at line 656 of file atl1e_hw.h.

#define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */

Definition at line 670 of file atl1e_hw.h.

#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */

Definition at line 652 of file atl1e_hw.h.

#define MII_AT001_PSCR_MAC_POWERDOWN 0x0008

Definition at line 655 of file atl1e_hw.h.

#define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */

Definition at line 657 of file atl1e_hw.h.

#define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */

Definition at line 659 of file atl1e_hw.h.

#define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100

Definition at line 666 of file atl1e_hw.h.

#define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */

Definition at line 653 of file atl1e_hw.h.

#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1

Definition at line 672 of file atl1e_hw.h.

#define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */

Definition at line 669 of file atl1e_hw.h.

#define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */

Definition at line 654 of file atl1e_hw.h.

#define MII_AT001_PSSR 0x11

Definition at line 633 of file atl1e_hw.h.

#define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */

Definition at line 681 of file atl1e_hw.h.

#define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */

Definition at line 680 of file atl1e_hw.h.

#define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */

Definition at line 679 of file atl1e_hw.h.

#define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */

Definition at line 677 of file atl1e_hw.h.

#define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */

Definition at line 676 of file atl1e_hw.h.

#define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */

Definition at line 678 of file atl1e_hw.h.

#define MII_DBG_ADDR 0x1D

Definition at line 640 of file atl1e_hw.h.

#define MII_DBG_DATA 0x1E

Definition at line 641 of file atl1e_hw.h.

#define MII_INT_CTRL 0x12

Definition at line 634 of file atl1e_hw.h.

#define MII_INT_STATUS 0x13

Definition at line 635 of file atl1e_hw.h.

#define MII_LBRERROR 0x18

Definition at line 637 of file atl1e_hw.h.

#define MII_RESV2 0x1a

Definition at line 638 of file atl1e_hw.h.

#define MII_SMARTSPEED 0x14

Definition at line 636 of file atl1e_hw.h.

#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2

Definition at line 147 of file atl1e_hw.h.

#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1

Definition at line 148 of file atl1e_hw.h.

#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8

Definition at line 150 of file atl1e_hw.h.

#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10

Definition at line 151 of file atl1e_hw.h.

#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4

Definition at line 149 of file atl1e_hw.h.

#define PCIE_PHYMISC_FORCE_RCV_DET 0x4

Definition at line 154 of file atl1e_hw.h.

#define PHY_STATUS_100M 0x20000

Definition at line 251 of file atl1e_hw.h.

#define PHY_STATUS_EMI_CA 0x40000

Definition at line 252 of file atl1e_hw.h.

#define REG_BASE_CPU_NUMBER 0x157C

Definition at line 425 of file atl1e_hw.h.

#define REG_BIST0_CTRL 0x141c

Definition at line 255 of file atl1e_hw.h.

#define REG_BIST1_CTRL 0x1420

Definition at line 263 of file atl1e_hw.h.

#define REG_CMBDISDMA_TIMER 0x140E

Definition at line 214 of file atl1e_hw.h.

#define REG_DEBUG_DATA0 0x1900

Definition at line 627 of file atl1e_hw.h.

#define REG_DEBUG_DATA1 0x1904

Definition at line 628 of file atl1e_hw.h.

#define REG_DESC_BASE_ADDR_HI 0x1540

Definition at line 394 of file atl1e_hw.h.

#define REG_DEVICE_CAP 0x5C

Definition at line 58 of file atl1e_hw.h.

#define REG_DEVICE_CTRL 0x60

Definition at line 62 of file atl1e_hw.h.

#define REG_DMA_CTRL 0x15C0

Definition at line 490 of file atl1e_hw.h.

#define REG_GPHY_CTRL 0x140C

Definition at line 182 of file atl1e_hw.h.

#define REG_HOST_RXF0_MB0_LO 0x1820

Definition at line 613 of file atl1e_hw.h.

#define REG_HOST_RXF0_MB1_LO 0x1824

Definition at line 614 of file atl1e_hw.h.

#define REG_HOST_RXF0_PAGE0_LO 0x1544

Definition at line 396 of file atl1e_hw.h.

#define REG_HOST_RXF0_PAGE0_VLD 0x15F4

Definition at line 530 of file atl1e_hw.h.

#define REG_HOST_RXF0_PAGE1_LO 0x1548

Definition at line 397 of file atl1e_hw.h.

#define REG_HOST_RXF0_PAGE1_VLD 0x15F5

Definition at line 534 of file atl1e_hw.h.

#define REG_HOST_RXF0_PAGEOFF 0x1800

Definition at line 606 of file atl1e_hw.h.

#define REG_HOST_RXF1_MB0_LO 0x1828

Definition at line 615 of file atl1e_hw.h.

#define REG_HOST_RXF1_MB1_LO 0x182C

Definition at line 616 of file atl1e_hw.h.

#define REG_HOST_RXF1_PAGE0_LO 0x15D0

Definition at line 516 of file atl1e_hw.h.

#define REG_HOST_RXF1_PAGE0_VLD 0x15F6

Definition at line 535 of file atl1e_hw.h.

#define REG_HOST_RXF1_PAGE1_LO 0x15D4

Definition at line 517 of file atl1e_hw.h.

#define REG_HOST_RXF1_PAGE1_VLD 0x15F7

Definition at line 536 of file atl1e_hw.h.

#define REG_HOST_RXF1_PAGEOFF 0x1808

Definition at line 608 of file atl1e_hw.h.

#define REG_HOST_RXF2_MB0_LO 0x1830

Definition at line 617 of file atl1e_hw.h.

#define REG_HOST_RXF2_MB1_LO 0x1834

Definition at line 618 of file atl1e_hw.h.

#define REG_HOST_RXF2_PAGE0_LO 0x15D8

Definition at line 518 of file atl1e_hw.h.

#define REG_HOST_RXF2_PAGE0_VLD 0x15F8

Definition at line 537 of file atl1e_hw.h.

#define REG_HOST_RXF2_PAGE1_LO 0x15DC

Definition at line 519 of file atl1e_hw.h.

#define REG_HOST_RXF2_PAGE1_VLD 0x15F9

Definition at line 538 of file atl1e_hw.h.

#define REG_HOST_RXF2_PAGEOFF 0x180C

Definition at line 609 of file atl1e_hw.h.

#define REG_HOST_RXF3_MB0_LO 0x1838

Definition at line 619 of file atl1e_hw.h.

#define REG_HOST_RXF3_MB1_LO 0x183C

Definition at line 620 of file atl1e_hw.h.

#define REG_HOST_RXF3_PAGE0_LO 0x15E0

Definition at line 520 of file atl1e_hw.h.

#define REG_HOST_RXF3_PAGE0_VLD 0x15FA

Definition at line 539 of file atl1e_hw.h.

#define REG_HOST_RXF3_PAGE1_LO 0x15E4

Definition at line 521 of file atl1e_hw.h.

#define REG_HOST_RXF3_PAGE1_VLD 0x15FB

Definition at line 540 of file atl1e_hw.h.

#define REG_HOST_RXF3_PAGEOFF 0x1810

Definition at line 610 of file atl1e_hw.h.

#define REG_HOST_RXFPAGE_SIZE 0x1558

Definition at line 401 of file atl1e_hw.h.

#define REG_HOST_SMB_ADDR_LO 0x1844

Definition at line 624 of file atl1e_hw.h.

#define REG_HOST_TX_CMB_LO 0x1840

Definition at line 623 of file atl1e_hw.h.

#define REG_IDLE_STATUS 0x1410

Definition at line 218 of file atl1e_hw.h.

#define REG_IDT_TABLE REG_IDT_TABLE0

Definition at line 422 of file atl1e_hw.h.

#define REG_IDT_TABLE0 0x1560

Definition at line 418 of file atl1e_hw.h.

#define REG_IDT_TABLE1 0x1564

Definition at line 419 of file atl1e_hw.h.

#define REG_IDT_TABLE2 0x1568

Definition at line 420 of file atl1e_hw.h.

#define REG_IDT_TABLE3 0x156C

Definition at line 421 of file atl1e_hw.h.

#define REG_IDT_TABLE4 0x14E0

Definition at line 414 of file atl1e_hw.h.

#define REG_IDT_TABLE5 0x14E4

Definition at line 415 of file atl1e_hw.h.

#define REG_IDT_TABLE6 0x14E8

Definition at line 416 of file atl1e_hw.h.

#define REG_IDT_TABLE7 0x14EC

Definition at line 417 of file atl1e_hw.h.

#define REG_IMR 0x1604

Definition at line 580 of file atl1e_hw.h.

#define REG_IRQ_MODU_TIMER2_INIT 0x140A /* w */

Definition at line 179 of file atl1e_hw.h.

#define REG_IRQ_MODU_TIMER_INIT 0x1408 /* w */

Definition at line 178 of file atl1e_hw.h.

#define REG_ISR 0x1600

Definition at line 543 of file atl1e_hw.h.

#define REG_LOAD_PTR 0x1534 /* Software sets this bit after the initialization of the head and tail */

Definition at line 383 of file atl1e_hw.h.

#define REG_LTSSM_TEST_MODE 0x12FC

Definition at line 156 of file atl1e_hw.h.

#define REG_MAC_CTRL 0x1480

Definition at line 276 of file atl1e_hw.h.

#define REG_MAC_HALF_DUPLX_CTRL 0x1498

Definition at line 325 of file atl1e_hw.h.

#define REG_MAC_IPG_IFG 0x1484

Definition at line 307 of file atl1e_hw.h.

#define REG_MAC_RX_STATUS_BIN 0x1700

Definition at line 600 of file atl1e_hw.h.

#define REG_MAC_RX_STATUS_END 0x175c

Definition at line 601 of file atl1e_hw.h.

#define REG_MAC_STA_ADDR 0x1488

Definition at line 318 of file atl1e_hw.h.

#define REG_MAC_TX_STATUS_BIN 0x1760

Definition at line 602 of file atl1e_hw.h.

#define REG_MAC_TX_STATUS_END 0x17c0

Definition at line 603 of file atl1e_hw.h.

#define REG_MANUAL_TIMER_INIT 0x1404

Definition at line 174 of file atl1e_hw.h.

#define REG_MASTER_CTRL 0x1400

Definition at line 160 of file atl1e_hw.h.

#define REG_MB_RXF1_RADDR 0x15B4

Definition at line 524 of file atl1e_hw.h.

#define REG_MB_RXF2_RADDR 0x15B8

Definition at line 525 of file atl1e_hw.h.

#define REG_MB_RXF3_RADDR 0x15BC

Definition at line 526 of file atl1e_hw.h.

#define REG_MB_TPD_PROD_IDX 0x15F0

Definition at line 527 of file atl1e_hw.h.

#define REG_MDIO_CTRL 0x1414

Definition at line 229 of file atl1e_hw.h.

#define REG_MTU 0x149c

Definition at line 340 of file atl1e_hw.h.

#define REG_PCIE_CAP_LIST 0x58

Definition at line 56 of file atl1e_hw.h.

#define REG_PCIE_DEV_MISC_CTRL 0x21C

Definition at line 146 of file atl1e_hw.h.

#define REG_PCIE_PHYMISC 0x1000

Definition at line 153 of file atl1e_hw.h.

#define REG_PHY_STATUS 0x1418

Definition at line 250 of file atl1e_hw.h.

#define REG_PM_CTRLSTAT 0x44

Definition at line 54 of file atl1e_hw.h.

#define REG_RSS_HASH_FLAG 0x1574

Definition at line 424 of file atl1e_hw.h.

#define REG_RSS_HASH_VALUE 0x1570

Definition at line 423 of file atl1e_hw.h.

#define REG_RSS_KEY0 0x14B0

Definition at line 404 of file atl1e_hw.h.

#define REG_RSS_KEY1 0x14B4

Definition at line 405 of file atl1e_hw.h.

#define REG_RSS_KEY2 0x14B8

Definition at line 406 of file atl1e_hw.h.

#define REG_RSS_KEY3 0x14BC

Definition at line 407 of file atl1e_hw.h.

#define REG_RSS_KEY4 0x14C0

Definition at line 408 of file atl1e_hw.h.

#define REG_RSS_KEY5 0x14C4

Definition at line 409 of file atl1e_hw.h.

#define REG_RSS_KEY6 0x14C8

Definition at line 410 of file atl1e_hw.h.

#define REG_RSS_KEY7 0x14CC

Definition at line 411 of file atl1e_hw.h.

#define REG_RSS_KEY8 0x14D0

Definition at line 412 of file atl1e_hw.h.

#define REG_RSS_KEY9 0x14D4

Definition at line 413 of file atl1e_hw.h.

#define REG_RX_HASH_TABLE 0x1490

Definition at line 321 of file atl1e_hw.h.

#define REG_RXF0_BASE_ADDR_HI 0x1540 /* share with DESC BASE ADDR HI */

Definition at line 395 of file atl1e_hw.h.

#define REG_RXF1_BASE_ADDR_HI 0x1550

Definition at line 399 of file atl1e_hw.h.

#define REG_RXF2_BASE_ADDR_HI 0x1554

Definition at line 400 of file atl1e_hw.h.

#define REG_RXF3_BASE_ADDR_HI 0x153C

Definition at line 393 of file atl1e_hw.h.

#define REG_RXQ_CTRL 0x15A0

Definition at line 445 of file atl1e_hw.h.

#define REG_RXQ_JMBOSZ_RRDTIM 0x15A4

Definition at line 470 of file atl1e_hw.h.

#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8

Definition at line 482 of file atl1e_hw.h.

#define REG_SERDES_LOCK 0x1424

Definition at line 271 of file atl1e_hw.h.

#define REG_SMB_STAT_TIMER 0x15C4

Definition at line 509 of file atl1e_hw.h.

#define REG_SPI_ADDR 0x204

Definition at line 104 of file atl1e_hw.h.

#define REG_SPI_DATA 0x208

Definition at line 106 of file atl1e_hw.h.

#define REG_SPI_FLASH_CONFIG 0x20C

Definition at line 108 of file atl1e_hw.h.

#define REG_SPI_FLASH_CTRL 0x200

Definition at line 79 of file atl1e_hw.h.

#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212

Definition at line 118 of file atl1e_hw.h.

#define REG_SPI_FLASH_OP_PROGRAM 0x210

Definition at line 116 of file atl1e_hw.h.

#define REG_SPI_FLASH_OP_RDID 0x213

Definition at line 119 of file atl1e_hw.h.

#define REG_SPI_FLASH_OP_RDSR 0x215

Definition at line 121 of file atl1e_hw.h.

#define REG_SPI_FLASH_OP_READ 0x217

Definition at line 123 of file atl1e_hw.h.

#define REG_SPI_FLASH_OP_SC_ERASE 0x211

Definition at line 117 of file atl1e_hw.h.

#define REG_SPI_FLASH_OP_WREN 0x214

Definition at line 120 of file atl1e_hw.h.

#define REG_SPI_FLASH_OP_WRSR 0x216

Definition at line 122 of file atl1e_hw.h.

#define REG_SRAM_PKTH_ADDR 0x1532

Definition at line 380 of file atl1e_hw.h.

#define REG_SRAM_RXF_ADDR 0x1520

Definition at line 375 of file atl1e_hw.h.

#define REG_SRAM_RXF_LEN 0x1524

Definition at line 376 of file atl1e_hw.h.

#define REG_SRAM_TCPH_ADDR 0x1530

Definition at line 379 of file atl1e_hw.h.

#define REG_SRAM_TRD_ADDR 0x1518

Definition at line 373 of file atl1e_hw.h.

#define REG_SRAM_TRD_LEN 0x151C

Definition at line 374 of file atl1e_hw.h.

#define REG_SRAM_TXF_ADDR 0x1528

Definition at line 377 of file atl1e_hw.h.

#define REG_SRAM_TXF_LEN 0x152C

Definition at line 378 of file atl1e_hw.h.

#define REG_TPD_BASE_ADDR_LO 0x154C

Definition at line 398 of file atl1e_hw.h.

#define REG_TPD_CONS_IDX 0x1804

Definition at line 607 of file atl1e_hw.h.

#define REG_TPD_RING_SIZE 0x155C

Definition at line 402 of file atl1e_hw.h.

#define REG_TRIG_RRD_THRESH 0x15CA

Definition at line 510 of file atl1e_hw.h.

#define REG_TRIG_RXTIMER 0x15CE

Definition at line 513 of file atl1e_hw.h.

#define REG_TRIG_TPD_THRESH 0x15C8

Definition at line 511 of file atl1e_hw.h.

#define REG_TRIG_TXTIMER 0x15CC

Definition at line 512 of file atl1e_hw.h.

#define REG_TWSI_CTRL 0x218

Definition at line 125 of file atl1e_hw.h.

#define REG_TX_EARLY_TH 0x1584 /* Jumbo frame threshold in QWORD unit. Packet greater than */

Definition at line 438 of file atl1e_hw.h.

#define REG_TXQ_CTRL 0x1580

Definition at line 429 of file atl1e_hw.h.

#define REG_VPD_CAP 0x6C

Definition at line 68 of file atl1e_hw.h.

#define REG_VPD_DATA 0x70

Definition at line 77 of file atl1e_hw.h.

#define REG_WOL_CTRL 0x14a0

Definition at line 343 of file atl1e_hw.h.

#define REG_WOL_PATTERN_LEN 0x14a4

Definition at line 362 of file atl1e_hw.h.

#define RXQ_CTRL_CUT_THRU_EN 0x40000000

Definition at line 466 of file atl1e_hw.h.

#define RXQ_CTRL_EN 0x80000000

Definition at line 467 of file atl1e_hw.h.

#define RXQ_CTRL_HASH_ENABLE 0x20000000

Definition at line 465 of file atl1e_hw.h.

#define RXQ_CTRL_HASH_TLEN_MASK 0xFF

Definition at line 455 of file atl1e_hw.h.

#define RXQ_CTRL_HASH_TLEN_SHIFT 8

Definition at line 454 of file atl1e_hw.h.

#define RXQ_CTRL_HASH_TYPE_IPV4 0x10000

Definition at line 456 of file atl1e_hw.h.

#define RXQ_CTRL_HASH_TYPE_IPV4_TCP 0x20000

Definition at line 457 of file atl1e_hw.h.

#define RXQ_CTRL_HASH_TYPE_IPV6 0x40000

Definition at line 458 of file atl1e_hw.h.

#define RXQ_CTRL_HASH_TYPE_IPV6_TCP 0x80000

Definition at line 459 of file atl1e_hw.h.

#define RXQ_CTRL_IPV6_XSUM_VERIFY_EN 0x80

Definition at line 453 of file atl1e_hw.h.

#define RXQ_CTRL_NIP_QUEUE_SEL_TBL 0x10000000

Definition at line 464 of file atl1e_hw.h.

#define RXQ_CTRL_PBA_ALIGN_128 2

Definition at line 448 of file atl1e_hw.h.

#define RXQ_CTRL_PBA_ALIGN_256 3

Definition at line 449 of file atl1e_hw.h.

#define RXQ_CTRL_PBA_ALIGN_32 0 /* rx-packet alignment */

Definition at line 446 of file atl1e_hw.h.

#define RXQ_CTRL_PBA_ALIGN_64 1

Definition at line 447 of file atl1e_hw.h.

#define RXQ_CTRL_Q1_EN 0x10

Definition at line 450 of file atl1e_hw.h.

#define RXQ_CTRL_Q2_EN 0x20

Definition at line 451 of file atl1e_hw.h.

#define RXQ_CTRL_Q3_EN 0x40

Definition at line 452 of file atl1e_hw.h.

#define RXQ_CTRL_RSS_MODE_DISABLE 0

Definition at line 460 of file atl1e_hw.h.

#define RXQ_CTRL_RSS_MODE_MQUEMINT 0xC000000

Definition at line 463 of file atl1e_hw.h.

#define RXQ_CTRL_RSS_MODE_MQUESINT 0x8000000

Definition at line 462 of file atl1e_hw.h.

#define RXQ_CTRL_RSS_MODE_SQSINT 0x4000000

Definition at line 461 of file atl1e_hw.h.

#define RXQ_JMBO_LKAH_MASK 0xf

Definition at line 478 of file atl1e_hw.h.

#define RXQ_JMBO_LKAH_SHIFT 11

Definition at line 479 of file atl1e_hw.h.

#define RXQ_JMBOSZ_TH_MASK 0x7ff

Definition at line 476 of file atl1e_hw.h.

#define RXQ_JMBOSZ_TH_SHIFT 0 /* RRD retirement timer. Decrement by 1 after every 512ns passes*/

Definition at line 477 of file atl1e_hw.h.

#define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff

Definition at line 484 of file atl1e_hw.h.

#define RXQ_RXF_PAUSE_TH_HI_SHIFT 0

Definition at line 483 of file atl1e_hw.h.

#define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff

Definition at line 486 of file atl1e_hw.h.

#define RXQ_RXF_PAUSE_TH_LO_SHIFT 16

Definition at line 485 of file atl1e_hw.h.

#define SERDES_LOCK_DETECT 1 /* 1: SerDes lock detected . This signal comes from Analog SerDes */

Definition at line 272 of file atl1e_hw.h.

#define SERDES_LOCK_DETECT_EN 2 /* 1: Enable SerDes Lock detect function */

Definition at line 273 of file atl1e_hw.h.

#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF

Definition at line 109 of file atl1e_hw.h.

#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0

Definition at line 110 of file atl1e_hw.h.

#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000

Definition at line 113 of file atl1e_hw.h.

#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3

Definition at line 111 of file atl1e_hw.h.

#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24

Definition at line 112 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3

Definition at line 96 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22

Definition at line 97 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3

Definition at line 94 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20

Definition at line 95 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_CS_HI_MASK 0x3

Definition at line 90 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_CS_HI_SHIFT 16

Definition at line 91 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3

Definition at line 92 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18

Definition at line 93 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3

Definition at line 98 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24

Definition at line 99 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF

Definition at line 83 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0

Definition at line 84 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_EN_VPD 0x2000

Definition at line 88 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3

Definition at line 100 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26

Definition at line 101 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_INS_MASK 0x7

Definition at line 85 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_INS_SHIFT 8

Definition at line 86 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_LDSTART 0x8000

Definition at line 89 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_START 0x800

Definition at line 87 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_STS_NON_RDY 0x1

Definition at line 80 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_STS_WEN 0x2

Definition at line 81 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_STS_WPEN 0x80

Definition at line 82 of file atl1e_hw.h.

#define SPI_FLASH_CTRL_WAIT_READY 0x10000000

Definition at line 102 of file atl1e_hw.h.

#define TWSI_CTRL_FREQ_SEL_100K 0

Definition at line 137 of file atl1e_hw.h.

#define TWSI_CTRL_FREQ_SEL_200K 1

Definition at line 138 of file atl1e_hw.h.

#define TWSI_CTRL_FREQ_SEL_300K 2

Definition at line 139 of file atl1e_hw.h.

#define TWSI_CTRL_FREQ_SEL_400K 3

Definition at line 140 of file atl1e_hw.h.

#define TWSI_CTRL_HW_LDSTART 0x1000

Definition at line 131 of file atl1e_hw.h.

#define TWSI_CTRL_LD_EXIST 0x400000

Definition at line 134 of file atl1e_hw.h.

#define TWSI_CTRL_LD_OFFSET_MASK 0xFF

Definition at line 126 of file atl1e_hw.h.

#define TWSI_CTRL_LD_OFFSET_SHIFT 0

Definition at line 127 of file atl1e_hw.h.

#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7

Definition at line 128 of file atl1e_hw.h.

#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8

Definition at line 129 of file atl1e_hw.h.

#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3

Definition at line 135 of file atl1e_hw.h.

#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23

Definition at line 136 of file atl1e_hw.h.

#define TWSI_CTRL_SMB_SLV_ADDR

Definition at line 141 of file atl1e_hw.h.

#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x0x7F

Definition at line 132 of file atl1e_hw.h.

#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15

Definition at line 133 of file atl1e_hw.h.

#define TWSI_CTRL_SW_LDSTART 0x800

Definition at line 130 of file atl1e_hw.h.

#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3

Definition at line 142 of file atl1e_hw.h.

#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24

Definition at line 143 of file atl1e_hw.h.

#define TX_TX_EARLY_TH_MASK 0x7ff

Definition at line 440 of file atl1e_hw.h.

#define TX_TX_EARLY_TH_SHIFT 0

Definition at line 441 of file atl1e_hw.h.

#define TXQ_CTRL_EN 0x20 /* 1: Enable TXQ */

Definition at line 432 of file atl1e_hw.h.

#define TXQ_CTRL_ENH_MODE 0x40 /* Performance enhancement mode, in which up to two back-to-back DMA read commands might be dispatched. */

Definition at line 433 of file atl1e_hw.h.

#define TXQ_CTRL_NUM_TPD_BURST_MASK 0xF

Definition at line 430 of file atl1e_hw.h.

#define TXQ_CTRL_NUM_TPD_BURST_SHIFT 0

Definition at line 431 of file atl1e_hw.h.

#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff

Definition at line 435 of file atl1e_hw.h.

#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length. */

Definition at line 434 of file atl1e_hw.h.

#define VPD_CAP_ID_MASK 0xff

Definition at line 69 of file atl1e_hw.h.

#define VPD_CAP_ID_SHIFT 0

Definition at line 70 of file atl1e_hw.h.

#define VPD_CAP_NEXT_PTR_MASK 0xFF

Definition at line 71 of file atl1e_hw.h.

#define VPD_CAP_NEXT_PTR_SHIFT 8

Definition at line 72 of file atl1e_hw.h.

#define VPD_CAP_VPD_ADDR_MASK 0x7FFF

Definition at line 73 of file atl1e_hw.h.

#define VPD_CAP_VPD_ADDR_SHIFT 16

Definition at line 74 of file atl1e_hw.h.

#define VPD_CAP_VPD_FLAG 0x80000000

Definition at line 75 of file atl1e_hw.h.

#define WOL_CLK_SWITCH_EN 0x00008000

Definition at line 353 of file atl1e_hw.h.

#define WOL_LINK_CHG_EN 0x00000010

Definition at line 348 of file atl1e_hw.h.

#define WOL_LINK_CHG_PME_EN 0x00000020

Definition at line 349 of file atl1e_hw.h.

#define WOL_LINKCHG_ST 0x00000400

Definition at line 352 of file atl1e_hw.h.

#define WOL_MAGIC_EN 0x00000004

Definition at line 346 of file atl1e_hw.h.

#define WOL_MAGIC_PME_EN 0x00000008

Definition at line 347 of file atl1e_hw.h.

#define WOL_MAGIC_ST 0x00000200

Definition at line 351 of file atl1e_hw.h.

#define WOL_PATTERN_EN 0x00000001

Definition at line 344 of file atl1e_hw.h.

#define WOL_PATTERN_PME_EN 0x00000002

Definition at line 345 of file atl1e_hw.h.

#define WOL_PATTERN_ST 0x00000100

Definition at line 350 of file atl1e_hw.h.

#define WOL_PT0_EN 0x00010000

Definition at line 354 of file atl1e_hw.h.

#define WOL_PT0_LEN_SHIFT 0

Definition at line 364 of file atl1e_hw.h.

#define WOL_PT1_EN 0x00020000

Definition at line 355 of file atl1e_hw.h.

#define WOL_PT1_LEN_SHIFT 8

Definition at line 365 of file atl1e_hw.h.

#define WOL_PT2_EN 0x00040000

Definition at line 356 of file atl1e_hw.h.

#define WOL_PT2_LEN_SHIFT 16

Definition at line 366 of file atl1e_hw.h.

#define WOL_PT3_EN 0x00080000

Definition at line 357 of file atl1e_hw.h.

#define WOL_PT3_LEN_SHIFT 24

Definition at line 367 of file atl1e_hw.h.

#define WOL_PT4_EN 0x00100000

Definition at line 358 of file atl1e_hw.h.

#define WOL_PT4_LEN_SHIFT 0

Definition at line 368 of file atl1e_hw.h.

#define WOL_PT5_EN 0x00200000

Definition at line 359 of file atl1e_hw.h.

#define WOL_PT5_LEN_SHIFT 8

Definition at line 369 of file atl1e_hw.h.

#define WOL_PT6_EN 0x00400000

Definition at line 360 of file atl1e_hw.h.

#define WOL_PT6_LEN_SHIFT 16

Definition at line 370 of file atl1e_hw.h.

#define WOL_PT_LEN_MASK 0x7f

Definition at line 363 of file atl1e_hw.h.

Function Documentation

u32 atl1e_auto_get_fc	(	struct atl1e_adapter *	adapter,
		u16	duplex
	)

int atl1e_check_eeprom_exist ( struct atl1e_hw * hw )

Definition at line 32 of file atl1e_hw.c.

void atl1e_force_ps ( struct atl1e_hw * hw )

Definition at line 140 of file atl1e_hw.c.

s32 atl1e_get_speed_and_duplex	(	struct atl1e_hw *	hw,
		u16 *	speed,
		u16 *	duplex
	)

Definition at line 596 of file atl1e_hw.c.

u32 atl1e_hash_mc_addr	(	struct atl1e_hw *	hw,
		u8 *	mc_addr
	)

Definition at line 167 of file atl1e_hw.c.

void atl1e_hash_set	(	struct atl1e_hw *	hw,
		u32	hash_value
	)

Definition at line 185 of file atl1e_hw.c.

void atl1e_hw_set_mac_addr ( struct atl1e_hw * hw )

Definition at line 45 of file atl1e_hw.c.

s32 atl1e_init_hw ( struct atl1e_hw * hw )

Definition at line 573 of file atl1e_hw.c.

s32 atl1e_phy_commit ( struct atl1e_hw * hw )

Definition at line 387 of file atl1e_hw.c.

s32 atl1e_phy_enter_power_saving ( struct atl1e_hw * hw )

s32 atl1e_phy_init ( struct atl1e_hw * hw )

Definition at line 420 of file atl1e_hw.c.

s32 atl1e_phy_leave_power_saving ( struct atl1e_hw * hw )

bool atl1e_read_eeprom	(	struct atl1e_hw *	hw,
		u32	offset,
		u32 *	p_value
	)

Definition at line 115 of file atl1e_hw.c.

s32 atl1e_read_mac_addr ( struct atl1e_hw * hw )

Definition at line 151 of file atl1e_hw.c.

s32 atl1e_read_phy_reg	(	struct atl1e_hw *	hw,
		u16	reg_addr,
		u16 *	phy_data
	)

Definition at line 213 of file atl1e_hw.c.

s32 atl1e_reset_hw ( struct atl1e_hw * hw )

Definition at line 515 of file atl1e_hw.c.

s32 atl1e_restart_autoneg ( struct atl1e_hw * hw )

Definition at line 632 of file atl1e_hw.c.

s32 atl1e_validate_mdi_setting ( struct atl1e_hw * hw )

bool atl1e_write_eeprom	(	struct atl1e_hw *	hw,
		u32	offset,
		u32	value
	)

Definition at line 110 of file atl1e_hw.c.

s32 atl1e_write_phy_reg	(	struct atl1e_hw *	hw,
		u32	reg_addr,
		u16	phy_data
	)

Definition at line 247 of file atl1e_hw.c.

Macros

Functions

Macro Definition Documentation

Function Documentation