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drxd_hard.c
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1 /*
2  * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
3  *
4  * Copyright (C) 2003-2007 Micronas
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * version 2 only, as published by the Free Software Foundation.
9  *
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20  * 02110-1301, USA
21  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22  */
23 
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <asm/div64.h>
32 
33 #include "dvb_frontend.h"
34 #include "drxd.h"
35 #include "drxd_firm.h"
36 
37 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
38 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
39 
40 #define CHUNK_SIZE 48
41 
42 #define DRX_I2C_RMW 0x10
43 #define DRX_I2C_BROADCAST 0x20
44 #define DRX_I2C_CLEARCRC 0x80
45 #define DRX_I2C_SINGLE_MASTER 0xC0
46 #define DRX_I2C_MODEFLAGS 0xC0
47 #define DRX_I2C_FLAGS 0xF0
48 
49 #ifndef SIZEOF_ARRAY
50 #define SIZEOF_ARRAY(array) (sizeof((array))/sizeof((array)[0]))
51 #endif
52 
53 #define DEFAULT_LOCK_TIMEOUT 1100
54 
55 #define DRX_CHANNEL_AUTO 0
56 #define DRX_CHANNEL_HIGH 1
57 #define DRX_CHANNEL_LOW 2
58 
59 #define DRX_LOCK_MPEG 1
60 #define DRX_LOCK_FEC 2
61 #define DRX_LOCK_DEMOD 4
62 
63 /****************************************************************************/
64 
65 enum CSCDState {
66  CSCD_INIT = 0,
67  CSCD_SET,
68  CSCD_SAVED
69 };
70 
71 enum CDrxdState {
72  DRXD_UNINITIALIZED = 0,
73  DRXD_STOPPED,
74  DRXD_STARTED
75 };
76 
77 enum AGC_CTRL_MODE {
78  AGC_CTRL_AUTO = 0,
79  AGC_CTRL_USER,
80  AGC_CTRL_OFF
81 };
82 
83 enum OperationMode {
84  OM_Default,
85  OM_DVBT_Diversity_Front,
86  OM_DVBT_Diversity_End
87 };
88 
89 struct SCfgAgc {
90  enum AGC_CTRL_MODE ctrlMode;
91  u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
92  u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
93  u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
94  u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
95  u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
96 
97  u16 R1;
98  u16 R2;
99  u16 R3;
100 };
101 
102 struct SNoiseCal {
103  int cpOpt;
104  short cpNexpOfs;
105  short tdCal2k;
106  short tdCal8k;
107 };
108 
109 enum app_env {
110  APPENV_STATIC = 0,
111  APPENV_PORTABLE = 1,
112  APPENV_MOBILE = 2
113 };
114 
115 enum EIFFilter {
116  IFFILTER_SAW = 0,
117  IFFILTER_DISCRETE = 1
118 };
119 
120 struct drxd_state {
121  struct dvb_frontend frontend;
122  struct dvb_frontend_ops ops;
123  struct dtv_frontend_properties props;
124 
125  const struct firmware *fw;
126  struct device *dev;
127 
128  struct i2c_adapter *i2c;
129  void *priv;
130  struct drxd_config config;
131 
132  int i2c_access;
133  int init_done;
134  struct mutex mutex;
135 
136  u8 chip_adr;
137  u16 hi_cfg_timing_div;
138  u16 hi_cfg_bridge_delay;
139  u16 hi_cfg_wakeup_key;
140  u16 hi_cfg_ctrl;
141 
142  u16 intermediate_freq;
143  u16 osc_clock_freq;
144 
145  enum CSCDState cscd_state;
146  enum CDrxdState drxd_state;
147 
148  u16 sys_clock_freq;
149  s16 osc_clock_deviation;
150  u16 expected_sys_clock_freq;
151 
152  u16 insert_rs_byte;
153  u16 enable_parallel;
154 
155  int operation_mode;
156 
157  struct SCfgAgc if_agc_cfg;
158  struct SCfgAgc rf_agc_cfg;
159 
160  struct SNoiseCal noise_cal;
161 
162  u32 fe_fs_add_incr;
163  u32 org_fe_fs_add_incr;
164  u16 current_fe_if_incr;
165 
166  u16 m_FeAgRegAgPwd;
167  u16 m_FeAgRegAgAgcSio;
168 
169  u16 m_EcOcRegOcModeLop;
170  u16 m_EcOcRegSncSncLvl;
171  u8 *m_InitAtomicRead;
172  u8 *m_HiI2cPatch;
173 
174  u8 *m_ResetCEFR;
175  u8 *m_InitFE_1;
176  u8 *m_InitFE_2;
177  u8 *m_InitCP;
178  u8 *m_InitCE;
179  u8 *m_InitEQ;
180  u8 *m_InitSC;
181  u8 *m_InitEC;
182  u8 *m_ResetECRAM;
183  u8 *m_InitDiversityFront;
184  u8 *m_InitDiversityEnd;
185  u8 *m_DisableDiversity;
186  u8 *m_StartDiversityFront;
187  u8 *m_StartDiversityEnd;
188 
189  u8 *m_DiversityDelay8MHZ;
190  u8 *m_DiversityDelay6MHZ;
191 
192  u8 *microcode;
193  u32 microcode_length;
194 
195  int type_A;
196  int PGA;
197  int diversity;
198  int tuner_mirrors;
199 
200  enum app_env app_env_default;
201  enum app_env app_env_diversity;
202 
203 };
204 
205 /****************************************************************************/
206 /* I2C **********************************************************************/
207 /****************************************************************************/
208 
209 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
210 {
211  struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
212 
213  if (i2c_transfer(adap, &msg, 1) != 1)
214  return -1;
215  return 0;
216 }
217 
218 static int i2c_read(struct i2c_adapter *adap,
219  u8 adr, u8 *msg, int len, u8 *answ, int alen)
220 {
221  struct i2c_msg msgs[2] = {
222  {
223  .addr = adr, .flags = 0,
224  .buf = msg, .len = len
225  }, {
226  .addr = adr, .flags = I2C_M_RD,
227  .buf = answ, .len = alen
228  }
229  };
230  if (i2c_transfer(adap, msgs, 2) != 2)
231  return -1;
232  return 0;
233 }
234 
235 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
236 {
237  u64 tmp64;
238 
239  tmp64 = (u64)a * (u64)b;
240  do_div(tmp64, c);
241 
242  return (u32) tmp64;
243 }
244 
245 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
246 {
247  u8 adr = state->config.demod_address;
248  u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
249  flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
250  };
251  u8 mm2[2];
252  if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
253  return -1;
254  if (data)
255  *data = mm2[0] | (mm2[1] << 8);
256  return mm2[0] | (mm2[1] << 8);
257 }
258 
259 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
260 {
261  u8 adr = state->config.demod_address;
262  u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
263  flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
264  };
265  u8 mm2[4];
266 
267  if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
268  return -1;
269  if (data)
270  *data =
271  mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
272  return 0;
273 }
274 
275 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
276 {
277  u8 adr = state->config.demod_address;
278  u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
279  flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
280  data & 0xff, (data >> 8) & 0xff
281  };
282 
283  if (i2c_write(state->i2c, adr, mm, 6) < 0)
284  return -1;
285  return 0;
286 }
287 
288 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
289 {
290  u8 adr = state->config.demod_address;
291  u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
292  flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
293  data & 0xff, (data >> 8) & 0xff,
294  (data >> 16) & 0xff, (data >> 24) & 0xff
295  };
296 
297  if (i2c_write(state->i2c, adr, mm, 8) < 0)
298  return -1;
299  return 0;
300 }
301 
302 static int write_chunk(struct drxd_state *state,
303  u32 reg, u8 *data, u32 len, u8 flags)
304 {
305  u8 adr = state->config.demod_address;
306  u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
307  flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
308  };
309  int i;
310 
311  for (i = 0; i < len; i++)
312  mm[4 + i] = data[i];
313  if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
314  printk(KERN_ERR "error in write_chunk\n");
315  return -1;
316  }
317  return 0;
318 }
319 
320 static int WriteBlock(struct drxd_state *state,
321  u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
322 {
323  while (BlockSize > 0) {
324  u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
325 
326  if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
327  return -1;
328  pBlock += Chunk;
329  Address += (Chunk >> 1);
330  BlockSize -= Chunk;
331  }
332  return 0;
333 }
334 
335 static int WriteTable(struct drxd_state *state, u8 * pTable)
336 {
337  int status = 0;
338 
339  if (pTable == NULL)
340  return 0;
341 
342  while (!status) {
343  u16 Length;
344  u32 Address = pTable[0] | (pTable[1] << 8) |
345  (pTable[2] << 16) | (pTable[3] << 24);
346 
347  if (Address == 0xFFFFFFFF)
348  break;
349  pTable += sizeof(u32);
350 
351  Length = pTable[0] | (pTable[1] << 8);
352  pTable += sizeof(u16);
353  if (!Length)
354  break;
355  status = WriteBlock(state, Address, Length * 2, pTable, 0);
356  pTable += (Length * 2);
357  }
358  return status;
359 }
360 
361 /****************************************************************************/
362 /****************************************************************************/
363 /****************************************************************************/
364 
365 static int ResetCEFR(struct drxd_state *state)
366 {
367  return WriteTable(state, state->m_ResetCEFR);
368 }
369 
370 static int InitCP(struct drxd_state *state)
371 {
372  return WriteTable(state, state->m_InitCP);
373 }
374 
375 static int InitCE(struct drxd_state *state)
376 {
377  int status;
378  enum app_env AppEnv = state->app_env_default;
379 
380  do {
381  status = WriteTable(state, state->m_InitCE);
382  if (status < 0)
383  break;
384 
385  if (state->operation_mode == OM_DVBT_Diversity_Front ||
386  state->operation_mode == OM_DVBT_Diversity_End) {
387  AppEnv = state->app_env_diversity;
388  }
389  if (AppEnv == APPENV_STATIC) {
390  status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
391  if (status < 0)
392  break;
393  } else if (AppEnv == APPENV_PORTABLE) {
394  status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
395  if (status < 0)
396  break;
397  } else if (AppEnv == APPENV_MOBILE && state->type_A) {
398  status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
399  if (status < 0)
400  break;
401  } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
402  status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
403  if (status < 0)
404  break;
405  }
406 
407  /* start ce */
408  status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
409  if (status < 0)
410  break;
411  } while (0);
412  return status;
413 }
414 
415 static int StopOC(struct drxd_state *state)
416 {
417  int status = 0;
418  u16 ocSyncLvl = 0;
419  u16 ocModeLop = state->m_EcOcRegOcModeLop;
420  u16 dtoIncLop = 0;
421  u16 dtoIncHip = 0;
422 
423  do {
424  /* Store output configuration */
425  status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
426  if (status < 0)
427  break;
428  /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
429  state->m_EcOcRegSncSncLvl = ocSyncLvl;
430  /* m_EcOcRegOcModeLop = ocModeLop; */
431 
432  /* Flush FIFO (byte-boundary) at fixed rate */
433  status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
434  if (status < 0)
435  break;
436  status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
437  if (status < 0)
438  break;
439  status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
440  if (status < 0)
441  break;
442  status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
443  if (status < 0)
444  break;
445  ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
446  ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
447  status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
448  if (status < 0)
449  break;
450  status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
451  if (status < 0)
452  break;
453 
454  msleep(1);
455  /* Output pins to '0' */
456  status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
457  if (status < 0)
458  break;
459 
460  /* Force the OC out of sync */
461  ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
462  status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
463  if (status < 0)
464  break;
465  ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
466  ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
467  ocModeLop |= 0x2; /* Magically-out-of-sync */
468  status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
469  if (status < 0)
470  break;
471  status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
472  if (status < 0)
473  break;
474  status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
475  if (status < 0)
476  break;
477  } while (0);
478 
479  return status;
480 }
481 
482 static int StartOC(struct drxd_state *state)
483 {
484  int status = 0;
485 
486  do {
487  /* Stop OC */
488  status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
489  if (status < 0)
490  break;
491 
492  /* Restore output configuration */
493  status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
494  if (status < 0)
495  break;
496  status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
497  if (status < 0)
498  break;
499 
500  /* Output pins active again */
501  status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
502  if (status < 0)
503  break;
504 
505  /* Start OC */
506  status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
507  if (status < 0)
508  break;
509  } while (0);
510  return status;
511 }
512 
513 static int InitEQ(struct drxd_state *state)
514 {
515  return WriteTable(state, state->m_InitEQ);
516 }
517 
518 static int InitEC(struct drxd_state *state)
519 {
520  return WriteTable(state, state->m_InitEC);
521 }
522 
523 static int InitSC(struct drxd_state *state)
524 {
525  return WriteTable(state, state->m_InitSC);
526 }
527 
528 static int InitAtomicRead(struct drxd_state *state)
529 {
530  return WriteTable(state, state->m_InitAtomicRead);
531 }
532 
533 static int CorrectSysClockDeviation(struct drxd_state *state);
534 
535 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
536 {
537  u16 ScRaRamLock = 0;
538  const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
539  SC_RA_RAM_LOCK_FEC__M |
540  SC_RA_RAM_LOCK_DEMOD__M);
541  const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
542  SC_RA_RAM_LOCK_DEMOD__M);
543  const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
544 
545  int status;
546 
547  *pLockStatus = 0;
548 
549  status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
550  if (status < 0) {
551  printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
552  return status;
553  }
554 
555  if (state->drxd_state != DRXD_STARTED)
556  return 0;
557 
558  if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
559  *pLockStatus |= DRX_LOCK_MPEG;
560  CorrectSysClockDeviation(state);
561  }
562 
563  if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
564  *pLockStatus |= DRX_LOCK_FEC;
565 
566  if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
567  *pLockStatus |= DRX_LOCK_DEMOD;
568  return 0;
569 }
570 
571 /****************************************************************************/
572 
573 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
574 {
575  int status;
576 
577  if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
578  return -1;
579 
580  if (cfg->ctrlMode == AGC_CTRL_USER) {
581  do {
582  u16 FeAgRegPm1AgcWri;
583  u16 FeAgRegAgModeLop;
584 
585  status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
586  if (status < 0)
587  break;
588  FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
589  FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
590  status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
591  if (status < 0)
592  break;
593 
594  FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
595  FE_AG_REG_PM1_AGC_WRI__M);
596  status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
597  if (status < 0)
598  break;
599  } while (0);
600  } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
601  if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
602  ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
603  ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
604  ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
605  )
606  return -1;
607  do {
608  u16 FeAgRegAgModeLop;
609  u16 FeAgRegEgcSetLvl;
610  u16 slope, offset;
611 
612  /* == Mode == */
613 
614  status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
615  if (status < 0)
616  break;
617  FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
618  FeAgRegAgModeLop |=
619  FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
620  status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
621  if (status < 0)
622  break;
623 
624  /* == Settle level == */
625 
626  FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
627  FE_AG_REG_EGC_SET_LVL__M);
628  status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
629  if (status < 0)
630  break;
631 
632  /* == Min/Max == */
633 
634  slope = (u16) ((cfg->maxOutputLevel -
635  cfg->minOutputLevel) / 2);
636  offset = (u16) ((cfg->maxOutputLevel +
637  cfg->minOutputLevel) / 2 - 511);
638 
639  status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
640  if (status < 0)
641  break;
642  status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
643  if (status < 0)
644  break;
645 
646  /* == Speed == */
647  {
648  const u16 maxRur = 8;
649  const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 };
650  const u16 fastIncrDecLUT[] = { 14, 15, 15, 16,
651  17, 18, 18, 19,
652  20, 21, 22, 23,
653  24, 26, 27, 28,
654  29, 31
655  };
656 
657  u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
658  (maxRur + 1);
659  u16 fineSpeed = (u16) (cfg->speed -
660  ((cfg->speed /
661  fineSteps) *
662  fineSteps));
663  u16 invRurCount = (u16) (cfg->speed /
664  fineSteps);
665  u16 rurCount;
666  if (invRurCount > maxRur) {
667  rurCount = 0;
668  fineSpeed += fineSteps;
669  } else {
670  rurCount = maxRur - invRurCount;
671  }
672 
673  /*
674  fastInc = default *
675  (2^(fineSpeed/fineSteps))
676  => range[default...2*default>
677  slowInc = default *
678  (2^(fineSpeed/fineSteps))
679  */
680  {
681  u16 fastIncrDec =
682  fastIncrDecLUT[fineSpeed /
683  ((fineSteps /
684  (14 + 1)) + 1)];
685  u16 slowIncrDec =
686  slowIncrDecLUT[fineSpeed /
687  (fineSteps /
688  (3 + 1))];
689 
690  status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
691  if (status < 0)
692  break;
693  status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
694  if (status < 0)
695  break;
696  status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
697  if (status < 0)
698  break;
699  status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
700  if (status < 0)
701  break;
702  status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
703  if (status < 0)
704  break;
705  }
706  }
707  } while (0);
708 
709  } else {
710  /* No OFF mode for IF control */
711  return -1;
712  }
713  return status;
714 }
715 
716 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
717 {
718  int status = 0;
719 
720  if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
721  return -1;
722 
723  if (cfg->ctrlMode == AGC_CTRL_USER) {
724  do {
725  u16 AgModeLop = 0;
726  u16 level = (cfg->outputLevel);
727 
728  if (level == DRXD_FE_CTRL_MAX)
729  level++;
730 
731  status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
732  if (status < 0)
733  break;
734 
735  /*==== Mode ====*/
736 
737  /* Powerdown PD2, WRI source */
738  state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
739  state->m_FeAgRegAgPwd |=
740  FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
741  status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
742  if (status < 0)
743  break;
744 
745  status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
746  if (status < 0)
747  break;
748  AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
749  FE_AG_REG_AG_MODE_LOP_MODE_E__M));
750  AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
751  FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
752  status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
753  if (status < 0)
754  break;
755 
756  /* enable AGC2 pin */
757  {
758  u16 FeAgRegAgAgcSio = 0;
759  status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
760  if (status < 0)
761  break;
762  FeAgRegAgAgcSio &=
763  ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
764  FeAgRegAgAgcSio |=
765  FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
766  status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
767  if (status < 0)
768  break;
769  }
770 
771  } while (0);
772  } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
773  u16 AgModeLop = 0;
774 
775  do {
776  u16 level;
777  /* Automatic control */
778  /* Powerup PD2, AGC2 as output, TGC source */
779  (state->m_FeAgRegAgPwd) &=
780  ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
781  (state->m_FeAgRegAgPwd) |=
782  FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
783  status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
784  if (status < 0)
785  break;
786 
787  status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
788  if (status < 0)
789  break;
790  AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
791  FE_AG_REG_AG_MODE_LOP_MODE_E__M));
792  AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
793  FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
794  status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
795  if (status < 0)
796  break;
797  /* Settle level */
798  level = (((cfg->settleLevel) >> 4) &
799  FE_AG_REG_TGC_SET_LVL__M);
800  status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
801  if (status < 0)
802  break;
803 
804  /* Min/max: don't care */
805 
806  /* Speed: TODO */
807 
808  /* enable AGC2 pin */
809  {
810  u16 FeAgRegAgAgcSio = 0;
811  status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
812  if (status < 0)
813  break;
814  FeAgRegAgAgcSio &=
815  ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
816  FeAgRegAgAgcSio |=
817  FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
818  status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
819  if (status < 0)
820  break;
821  }
822 
823  } while (0);
824  } else {
825  u16 AgModeLop = 0;
826 
827  do {
828  /* No RF AGC control */
829  /* Powerdown PD2, AGC2 as output, WRI source */
830  (state->m_FeAgRegAgPwd) &=
831  ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
832  (state->m_FeAgRegAgPwd) |=
833  FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
834  status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
835  if (status < 0)
836  break;
837 
838  status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
839  if (status < 0)
840  break;
841  AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
842  FE_AG_REG_AG_MODE_LOP_MODE_E__M));
843  AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
844  FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
845  status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
846  if (status < 0)
847  break;
848 
849  /* set FeAgRegAgAgcSio AGC2 (RF) as input */
850  {
851  u16 FeAgRegAgAgcSio = 0;
852  status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
853  if (status < 0)
854  break;
855  FeAgRegAgAgcSio &=
856  ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
857  FeAgRegAgAgcSio |=
858  FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
859  status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
860  if (status < 0)
861  break;
862  }
863  } while (0);
864  }
865  return status;
866 }
867 
868 static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
869 {
870  int status = 0;
871 
872  *pValue = 0;
873  if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
874  u16 Value;
875  status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
876  Value &= FE_AG_REG_GC1_AGC_DAT__M;
877  if (status >= 0) {
878  /* 3.3V
879  |
880  R1
881  |
882  Vin - R3 - * -- Vout
883  |
884  R2
885  |
886  GND
887  */
888  u32 R1 = state->if_agc_cfg.R1;
889  u32 R2 = state->if_agc_cfg.R2;
890  u32 R3 = state->if_agc_cfg.R3;
891 
892  u32 Vmax, Rpar, Vmin, Vout;
893 
894  if (R2 == 0 && (R1 == 0 || R3 == 0))
895  return 0;
896 
897  Vmax = (3300 * R2) / (R1 + R2);
898  Rpar = (R2 * R3) / (R3 + R2);
899  Vmin = (3300 * Rpar) / (R1 + Rpar);
900  Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
901 
902  *pValue = Vout;
903  }
904  }
905  return status;
906 }
907 
908 static int load_firmware(struct drxd_state *state, const char *fw_name)
909 {
910  const struct firmware *fw;
911 
912  if (request_firmware(&fw, fw_name, state->dev) < 0) {
913  printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
914  return -EIO;
915  }
916 
917  state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL);
918  if (state->microcode == NULL) {
919  release_firmware(fw);
920  printk(KERN_ERR "drxd: firmware load failure: no memory\n");
921  return -ENOMEM;
922  }
923 
924  state->microcode_length = fw->size;
925  release_firmware(fw);
926  return 0;
927 }
928 
929 static int DownloadMicrocode(struct drxd_state *state,
930  const u8 *pMCImage, u32 Length)
931 {
932  u8 *pSrc;
933  u32 Address;
934  u16 nBlocks;
935  u16 BlockSize;
936  u32 offset = 0;
937  int i, status = 0;
938 
939  pSrc = (u8 *) pMCImage;
940  /* We're not using Flags */
941  /* Flags = (pSrc[0] << 8) | pSrc[1]; */
942  pSrc += sizeof(u16);
943  offset += sizeof(u16);
944  nBlocks = (pSrc[0] << 8) | pSrc[1];
945  pSrc += sizeof(u16);
946  offset += sizeof(u16);
947 
948  for (i = 0; i < nBlocks; i++) {
949  Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
950  (pSrc[2] << 8) | pSrc[3];
951  pSrc += sizeof(u32);
952  offset += sizeof(u32);
953 
954  BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
955  pSrc += sizeof(u16);
956  offset += sizeof(u16);
957 
958  /* We're not using Flags */
959  /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */
960  pSrc += sizeof(u16);
961  offset += sizeof(u16);
962 
963  /* We're not using BlockCRC */
964  /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */
965  pSrc += sizeof(u16);
966  offset += sizeof(u16);
967 
968  status = WriteBlock(state, Address, BlockSize,
969  pSrc, DRX_I2C_CLEARCRC);
970  if (status < 0)
971  break;
972  pSrc += BlockSize;
973  offset += BlockSize;
974  }
975 
976  return status;
977 }
978 
979 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
980 {
981  u32 nrRetries = 0;
982  u16 waitCmd;
983  int status;
984 
985  status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
986  if (status < 0)
987  return status;
988 
989  do {
990  nrRetries += 1;
991  if (nrRetries > DRXD_MAX_RETRIES) {
992  status = -1;
993  break;
994  }
995  status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
996  } while (waitCmd != 0);
997 
998  if (status >= 0)
999  status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
1000  return status;
1001 }
1002 
1003 static int HI_CfgCommand(struct drxd_state *state)
1004 {
1005  int status = 0;
1006 
1007  mutex_lock(&state->mutex);
1008  Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1009  Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
1010  Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
1011  Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
1012  Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
1013 
1014  Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1015 
1016  if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
1017  HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
1018  status = Write16(state, HI_RA_RAM_SRV_CMD__A,
1019  HI_RA_RAM_SRV_CMD_CONFIG, 0);
1020  else
1021  status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0);
1022  mutex_unlock(&state->mutex);
1023  return status;
1024 }
1025 
1026 static int InitHI(struct drxd_state *state)
1027 {
1028  state->hi_cfg_wakeup_key = (state->chip_adr);
1029  /* port/bridge/power down ctrl */
1030  state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
1031  return HI_CfgCommand(state);
1032 }
1033 
1034 static int HI_ResetCommand(struct drxd_state *state)
1035 {
1036  int status;
1037 
1038  mutex_lock(&state->mutex);
1039  status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1040  HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1041  if (status == 0)
1042  status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0);
1043  mutex_unlock(&state->mutex);
1044  msleep(1);
1045  return status;
1046 }
1047 
1048 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
1049 {
1050  state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
1051  if (bEnableBridge)
1052  state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
1053  else
1054  state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
1055 
1056  return HI_CfgCommand(state);
1057 }
1058 
1059 #define HI_TR_WRITE 0x9
1060 #define HI_TR_READ 0xA
1061 #define HI_TR_READ_WRITE 0xB
1062 #define HI_TR_BROADCAST 0x4
1063 
1064 #if 0
1065 static int AtomicReadBlock(struct drxd_state *state,
1066  u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
1067 {
1068  int status;
1069  int i = 0;
1070 
1071  /* Parameter check */
1072  if ((!pData) || ((DataSize & 1) != 0))
1073  return -1;
1074 
1075  mutex_lock(&state->mutex);
1076 
1077  do {
1078  /* Instruct HI to read n bytes */
1079  /* TODO use proper names forthese egisters */
1080  status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1081  if (status < 0)
1082  break;
1083  status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1084  if (status < 0)
1085  break;
1086  status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1087  if (status < 0)
1088  break;
1089  status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1090  if (status < 0)
1091  break;
1092  status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1093  if (status < 0)
1094  break;
1095 
1096  status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1097  if (status < 0)
1098  break;
1099 
1100  } while (0);
1101 
1102  if (status >= 0) {
1103  for (i = 0; i < (DataSize / 2); i += 1) {
1104  u16 word;
1105 
1106  status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1107  &word, 0);
1108  if (status < 0)
1109  break;
1110  pData[2 * i] = (u8) (word & 0xFF);
1111  pData[(2 * i) + 1] = (u8) (word >> 8);
1112  }
1113  }
1114  mutex_unlock(&state->mutex);
1115  return status;
1116 }
1117 
1118 static int AtomicReadReg32(struct drxd_state *state,
1119  u32 Addr, u32 *pData, u8 Flags)
1120 {
1121  u8 buf[sizeof(u32)];
1122  int status;
1123 
1124  if (!pData)
1125  return -1;
1126  status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1127  *pData = (((u32) buf[0]) << 0) +
1128  (((u32) buf[1]) << 8) +
1129  (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1130  return status;
1131 }
1132 #endif
1133 
1134 static int StopAllProcessors(struct drxd_state *state)
1135 {
1136  return Write16(state, HI_COMM_EXEC__A,
1137  SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
1138 }
1139 
1140 static int EnableAndResetMB(struct drxd_state *state)
1141 {
1142  if (state->type_A) {
1143  /* disable? monitor bus observe @ EC_OC */
1144  Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
1145  }
1146 
1147  /* do inverse broadcast, followed by explicit write to HI */
1148  Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
1149  Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
1150  return 0;
1151 }
1152 
1153 static int InitCC(struct drxd_state *state)
1154 {
1155  if (state->osc_clock_freq == 0 ||
1156  state->osc_clock_freq > 20000 ||
1157  (state->osc_clock_freq % 4000) != 0) {
1158  printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
1159  return -1;
1160  }
1161 
1162  Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1163  Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
1164  CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1165  Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0);
1166  Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
1167  Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1168 
1169  return 0;
1170 }
1171 
1172 static int ResetECOD(struct drxd_state *state)
1173 {
1174  int status = 0;
1175 
1176  if (state->type_A)
1177  status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1178  else
1179  status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1180 
1181  if (!(status < 0))
1182  status = WriteTable(state, state->m_ResetECRAM);
1183  if (!(status < 0))
1184  status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1185  return status;
1186 }
1187 
1188 /* Configure PGA switch */
1189 
1190 static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1191 {
1192  int status;
1193  u16 AgModeLop = 0;
1194  u16 AgModeHip = 0;
1195  do {
1196  if (pgaSwitch) {
1197  /* PGA on */
1198  /* fine gain */
1199  status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1200  if (status < 0)
1201  break;
1202  AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1203  AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
1204  status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1205  if (status < 0)
1206  break;
1207 
1208  /* coarse gain */
1209  status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1210  if (status < 0)
1211  break;
1212  AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1213  AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
1214  status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1215  if (status < 0)
1216  break;
1217 
1218  /* enable fine and coarse gain, enable AAF,
1219  no ext resistor */
1220  status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1221  if (status < 0)
1222  break;
1223  } else {
1224  /* PGA off, bypass */
1225 
1226  /* fine gain */
1227  status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1228  if (status < 0)
1229  break;
1230  AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1231  AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
1232  status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1233  if (status < 0)
1234  break;
1235 
1236  /* coarse gain */
1237  status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1238  if (status < 0)
1239  break;
1240  AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1241  AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
1242  status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1243  if (status < 0)
1244  break;
1245 
1246  /* disable fine and coarse gain, enable AAF,
1247  no ext resistor */
1248  status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1249  if (status < 0)
1250  break;
1251  }
1252  } while (0);
1253  return status;
1254 }
1255 
1256 static int InitFE(struct drxd_state *state)
1257 {
1258  int status;
1259 
1260  do {
1261  status = WriteTable(state, state->m_InitFE_1);
1262  if (status < 0)
1263  break;
1264 
1265  if (state->type_A) {
1266  status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1267  FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1268  0);
1269  } else {
1270  if (state->PGA)
1271  status = SetCfgPga(state, 0);
1272  else
1273  status =
1274  Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1275  B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1276  0);
1277  }
1278 
1279  if (status < 0)
1280  break;
1281  status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1282  if (status < 0)
1283  break;
1284  status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1285  if (status < 0)
1286  break;
1287 
1288  status = WriteTable(state, state->m_InitFE_2);
1289  if (status < 0)
1290  break;
1291 
1292  } while (0);
1293 
1294  return status;
1295 }
1296 
1297 static int InitFT(struct drxd_state *state)
1298 {
1299  /*
1300  norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1301  SC stuff
1302  */
1303  return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
1304 }
1305 
1306 static int SC_WaitForReady(struct drxd_state *state)
1307 {
1308  u16 curCmd;
1309  int i;
1310 
1311  for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
1312  int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
1313  if (status == 0 || curCmd == 0)
1314  return status;
1315  }
1316  return -1;
1317 }
1318 
1319 static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1320 {
1321  int status = 0;
1322  u16 errCode;
1323 
1324  Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1325  SC_WaitForReady(state);
1326 
1327  Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
1328 
1329  if (errCode == 0xFFFF) {
1330  printk(KERN_ERR "Command Error\n");
1331  status = -1;
1332  }
1333 
1334  return status;
1335 }
1336 
1337 static int SC_ProcStartCommand(struct drxd_state *state,
1338  u16 subCmd, u16 param0, u16 param1)
1339 {
1340  int status = 0;
1341  u16 scExec;
1342 
1343  mutex_lock(&state->mutex);
1344  do {
1345  Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1346  if (scExec != 1) {
1347  status = -1;
1348  break;
1349  }
1350  SC_WaitForReady(state);
1351  Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1352  Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1353  Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1354 
1355  SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
1356  } while (0);
1357  mutex_unlock(&state->mutex);
1358  return status;
1359 }
1360 
1361 static int SC_SetPrefParamCommand(struct drxd_state *state,
1362  u16 subCmd, u16 param0, u16 param1)
1363 {
1364  int status;
1365 
1366  mutex_lock(&state->mutex);
1367  do {
1368  status = SC_WaitForReady(state);
1369  if (status < 0)
1370  break;
1371  status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1372  if (status < 0)
1373  break;
1374  status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1375  if (status < 0)
1376  break;
1377  status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1378  if (status < 0)
1379  break;
1380 
1381  status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1382  if (status < 0)
1383  break;
1384  } while (0);
1385  mutex_unlock(&state->mutex);
1386  return status;
1387 }
1388 
1389 #if 0
1390 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1391 {
1392  int status = 0;
1393 
1394  mutex_lock(&state->mutex);
1395  do {
1396  status = SC_WaitForReady(state);
1397  if (status < 0)
1398  break;
1399  status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1400  if (status < 0)
1401  break;
1402  status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1403  if (status < 0)
1404  break;
1405  } while (0);
1406  mutex_unlock(&state->mutex);
1407  return status;
1408 }
1409 #endif
1410 
1411 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1412 {
1413  int status;
1414 
1415  do {
1416  u16 EcOcRegIprInvMpg = 0;
1417  u16 EcOcRegOcModeLop = 0;
1418  u16 EcOcRegOcModeHip = 0;
1419  u16 EcOcRegOcMpgSio = 0;
1420 
1421  /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
1422 
1423  if (state->operation_mode == OM_DVBT_Diversity_Front) {
1424  if (bEnableOutput) {
1425  EcOcRegOcModeHip |=
1426  B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1427  } else
1428  EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1429  EcOcRegOcModeLop |=
1430  EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1431  } else {
1432  EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1433 
1434  if (bEnableOutput)
1435  EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
1436  else
1437  EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1438 
1439  /* Don't Insert RS Byte */
1440  if (state->insert_rs_byte) {
1441  EcOcRegOcModeLop &=
1442  (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
1443  EcOcRegOcModeHip &=
1444  (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1445  EcOcRegOcModeHip |=
1446  EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1447  } else {
1448  EcOcRegOcModeLop |=
1449  EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1450  EcOcRegOcModeHip &=
1451  (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1452  EcOcRegOcModeHip |=
1453  EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
1454  }
1455 
1456  /* Mode = Parallel */
1457  if (state->enable_parallel)
1458  EcOcRegOcModeLop &=
1459  (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1460  else
1461  EcOcRegOcModeLop |=
1462  EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
1463  }
1464  /* Invert Data */
1465  /* EcOcRegIprInvMpg |= 0x00FF; */
1466  EcOcRegIprInvMpg &= (~(0x00FF));
1467 
1468  /* Invert Error ( we don't use the pin ) */
1469  /* EcOcRegIprInvMpg |= 0x0100; */
1470  EcOcRegIprInvMpg &= (~(0x0100));
1471 
1472  /* Invert Start ( we don't use the pin ) */
1473  /* EcOcRegIprInvMpg |= 0x0200; */
1474  EcOcRegIprInvMpg &= (~(0x0200));
1475 
1476  /* Invert Valid ( we don't use the pin ) */
1477  /* EcOcRegIprInvMpg |= 0x0400; */
1478  EcOcRegIprInvMpg &= (~(0x0400));
1479 
1480  /* Invert Clock */
1481  /* EcOcRegIprInvMpg |= 0x0800; */
1482  EcOcRegIprInvMpg &= (~(0x0800));
1483 
1484  /* EcOcRegOcModeLop =0x05; */
1485  status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1486  if (status < 0)
1487  break;
1488  status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1489  if (status < 0)
1490  break;
1491  status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1492  if (status < 0)
1493  break;
1494  status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1495  if (status < 0)
1496  break;
1497  } while (0);
1498  return status;
1499 }
1500 
1501 static int SetDeviceTypeId(struct drxd_state *state)
1502 {
1503  int status = 0;
1504  u16 deviceId = 0;
1505 
1506  do {
1507  status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1508  if (status < 0)
1509  break;
1510  /* TODO: why twice? */
1511  status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1512  if (status < 0)
1513  break;
1514  printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
1515 
1516  state->type_A = 0;
1517  state->PGA = 0;
1518  state->diversity = 0;
1519  if (deviceId == 0) { /* on A2 only 3975 available */
1520  state->type_A = 1;
1521  printk(KERN_INFO "DRX3975D-A2\n");
1522  } else {
1523  deviceId >>= 12;
1524  printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
1525  switch (deviceId) {
1526  case 4:
1527  state->diversity = 1;
1528  case 3:
1529  case 7:
1530  state->PGA = 1;
1531  break;
1532  case 6:
1533  state->diversity = 1;
1534  case 5:
1535  case 8:
1536  break;
1537  default:
1538  status = -1;
1539  break;
1540  }
1541  }
1542  } while (0);
1543 
1544  if (status < 0)
1545  return status;
1546 
1547  /* Init Table selection */
1548  state->m_InitAtomicRead = DRXD_InitAtomicRead;
1549  state->m_InitSC = DRXD_InitSC;
1550  state->m_ResetECRAM = DRXD_ResetECRAM;
1551  if (state->type_A) {
1552  state->m_ResetCEFR = DRXD_ResetCEFR;
1553  state->m_InitFE_1 = DRXD_InitFEA2_1;
1554  state->m_InitFE_2 = DRXD_InitFEA2_2;
1555  state->m_InitCP = DRXD_InitCPA2;
1556  state->m_InitCE = DRXD_InitCEA2;
1557  state->m_InitEQ = DRXD_InitEQA2;
1558  state->m_InitEC = DRXD_InitECA2;
1559  if (load_firmware(state, DRX_FW_FILENAME_A2))
1560  return -EIO;
1561  } else {
1562  state->m_ResetCEFR = NULL;
1563  state->m_InitFE_1 = DRXD_InitFEB1_1;
1564  state->m_InitFE_2 = DRXD_InitFEB1_2;
1565  state->m_InitCP = DRXD_InitCPB1;
1566  state->m_InitCE = DRXD_InitCEB1;
1567  state->m_InitEQ = DRXD_InitEQB1;
1568  state->m_InitEC = DRXD_InitECB1;
1569  if (load_firmware(state, DRX_FW_FILENAME_B1))
1570  return -EIO;
1571  }
1572  if (state->diversity) {
1573  state->m_InitDiversityFront = DRXD_InitDiversityFront;
1574  state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1575  state->m_DisableDiversity = DRXD_DisableDiversity;
1576  state->m_StartDiversityFront = DRXD_StartDiversityFront;
1577  state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1578  state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1579  state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1580  } else {
1581  state->m_InitDiversityFront = NULL;
1582  state->m_InitDiversityEnd = NULL;
1583  state->m_DisableDiversity = NULL;
1584  state->m_StartDiversityFront = NULL;
1585  state->m_StartDiversityEnd = NULL;
1586  state->m_DiversityDelay8MHZ = NULL;
1587  state->m_DiversityDelay6MHZ = NULL;
1588  }
1589 
1590  return status;
1591 }
1592 
1593 static int CorrectSysClockDeviation(struct drxd_state *state)
1594 {
1595  int status;
1596  s32 incr = 0;
1597  s32 nomincr = 0;
1598  u32 bandwidth = 0;
1599  u32 sysClockInHz = 0;
1600  u32 sysClockFreq = 0; /* in kHz */
1601  s16 oscClockDeviation;
1602  s16 Diff;
1603 
1604  do {
1605  /* Retrieve bandwidth and incr, sanity check */
1606 
1607  /* These accesses should be AtomicReadReg32, but that
1608  causes trouble (at least for diversity */
1609  status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
1610  if (status < 0)
1611  break;
1612  status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
1613  if (status < 0)
1614  break;
1615 
1616  if (state->type_A) {
1617  if ((nomincr - incr < -500) || (nomincr - incr > 500))
1618  break;
1619  } else {
1620  if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
1621  break;
1622  }
1623 
1624  switch (state->props.bandwidth_hz) {
1625  case 8000000:
1626  bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1627  break;
1628  case 7000000:
1629  bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1630  break;
1631  case 6000000:
1632  bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1633  break;
1634  default:
1635  return -1;
1636  break;
1637  }
1638 
1639  /* Compute new sysclock value
1640  sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
1641  incr += (1 << 23);
1642  sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
1643  sysClockFreq = (u32) (sysClockInHz / 1000);
1644  /* rounding */
1645  if ((sysClockInHz % 1000) > 500)
1646  sysClockFreq++;
1647 
1648  /* Compute clock deviation in ppm */
1649  oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
1650  (s32)
1651  (state->expected_sys_clock_freq)) *
1652  1000000L) /
1653  (s32)
1654  (state->expected_sys_clock_freq));
1655 
1656  Diff = oscClockDeviation - state->osc_clock_deviation;
1657  /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
1658  if (Diff >= -200 && Diff <= 200) {
1659  state->sys_clock_freq = (u16) sysClockFreq;
1660  if (oscClockDeviation != state->osc_clock_deviation) {
1661  if (state->config.osc_deviation) {
1662  state->config.osc_deviation(state->priv,
1663  oscClockDeviation,
1664  1);
1665  state->osc_clock_deviation =
1666  oscClockDeviation;
1667  }
1668  }
1669  /* switch OFF SRMM scan in SC */
1670  status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1671  if (status < 0)
1672  break;
1673  /* overrule FE_IF internal value for
1674  proper re-locking */
1675  status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1676  if (status < 0)
1677  break;
1678  state->cscd_state = CSCD_SAVED;
1679  }
1680  } while (0);
1681 
1682  return status;
1683 }
1684 
1685 static int DRX_Stop(struct drxd_state *state)
1686 {
1687  int status;
1688 
1689  if (state->drxd_state != DRXD_STARTED)
1690  return 0;
1691 
1692  do {
1693  if (state->cscd_state != CSCD_SAVED) {
1694  u32 lock;
1695  status = DRX_GetLockStatus(state, &lock);
1696  if (status < 0)
1697  break;
1698  }
1699 
1700  status = StopOC(state);
1701  if (status < 0)
1702  break;
1703 
1704  state->drxd_state = DRXD_STOPPED;
1705 
1706  status = ConfigureMPEGOutput(state, 0);
1707  if (status < 0)
1708  break;
1709 
1710  if (state->type_A) {
1711  /* Stop relevant processors off the device */
1712  status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1713  if (status < 0)
1714  break;
1715 
1716  status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1717  if (status < 0)
1718  break;
1719  status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1720  if (status < 0)
1721  break;
1722  } else {
1723  /* Stop all processors except HI & CC & FE */
1724  status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1725  if (status < 0)
1726  break;
1727  status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1728  if (status < 0)
1729  break;
1730  status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1731  if (status < 0)
1732  break;
1733  status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1734  if (status < 0)
1735  break;
1736  status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1737  if (status < 0)
1738  break;
1739  status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1740  if (status < 0)
1741  break;
1742  status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1743  if (status < 0)
1744  break;
1745  }
1746 
1747  } while (0);
1748  return status;
1749 }
1750 
1751 int SetOperationMode(struct drxd_state *state, int oMode)
1752 {
1753  int status;
1754 
1755  do {
1756  if (state->drxd_state != DRXD_STOPPED) {
1757  status = -1;
1758  break;
1759  }
1760 
1761  if (oMode == state->operation_mode) {
1762  status = 0;
1763  break;
1764  }
1765 
1766  if (oMode != OM_Default && !state->diversity) {
1767  status = -1;
1768  break;
1769  }
1770 
1771  switch (oMode) {
1772  case OM_DVBT_Diversity_Front:
1773  status = WriteTable(state, state->m_InitDiversityFront);
1774  break;
1775  case OM_DVBT_Diversity_End:
1776  status = WriteTable(state, state->m_InitDiversityEnd);
1777  break;
1778  case OM_Default:
1779  /* We need to check how to
1780  get DRXD out of diversity */
1781  default:
1782  status = WriteTable(state, state->m_DisableDiversity);
1783  break;
1784  }
1785  } while (0);
1786 
1787  if (!status)
1788  state->operation_mode = oMode;
1789  return status;
1790 }
1791 
1792 static int StartDiversity(struct drxd_state *state)
1793 {
1794  int status = 0;
1795  u16 rcControl;
1796 
1797  do {
1798  if (state->operation_mode == OM_DVBT_Diversity_Front) {
1799  status = WriteTable(state, state->m_StartDiversityFront);
1800  if (status < 0)
1801  break;
1802  } else if (state->operation_mode == OM_DVBT_Diversity_End) {
1803  status = WriteTable(state, state->m_StartDiversityEnd);
1804  if (status < 0)
1805  break;
1806  if (state->props.bandwidth_hz == 8000000) {
1807  status = WriteTable(state, state->m_DiversityDelay8MHZ);
1808  if (status < 0)
1809  break;
1810  } else {
1811  status = WriteTable(state, state->m_DiversityDelay6MHZ);
1812  if (status < 0)
1813  break;
1814  }
1815 
1816  status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1817  if (status < 0)
1818  break;
1819  rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1820  rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
1821  /* combining enabled */
1822  B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1823  B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1824  B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
1825  status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1826  if (status < 0)
1827  break;
1828  }
1829  } while (0);
1830  return status;
1831 }
1832 
1833 static int SetFrequencyShift(struct drxd_state *state,
1834  u32 offsetFreq, int channelMirrored)
1835 {
1836  int negativeShift = (state->tuner_mirrors == channelMirrored);
1837 
1838  /* Handle all mirroring
1839  *
1840  * Note: ADC mirroring (aliasing) is implictly handled by limiting
1841  * feFsRegAddInc to 28 bits below
1842  * (if the result before masking is more than 28 bits, this means
1843  * that the ADC is mirroring.
1844  * The masking is in fact the aliasing of the ADC)
1845  *
1846  */
1847 
1848  /* Compute register value, unsigned computation */
1849  state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
1850  offsetFreq,
1851  1 << 28, state->sys_clock_freq);
1852  /* Remove integer part */
1853  state->fe_fs_add_incr &= 0x0FFFFFFFL;
1854  if (negativeShift)
1855  state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
1856 
1857  /* Save the frequency shift without tunerOffset compensation
1858  for CtrlGetChannel. */
1859  state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1860  1 << 28, state->sys_clock_freq);
1861  /* Remove integer part */
1862  state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1863  if (negativeShift)
1864  state->org_fe_fs_add_incr = ((1L << 28) -
1865  state->org_fe_fs_add_incr);
1866 
1867  return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1868  state->fe_fs_add_incr, 0);
1869 }
1870 
1871 static int SetCfgNoiseCalibration(struct drxd_state *state,
1872  struct SNoiseCal *noiseCal)
1873 {
1874  u16 beOptEna;
1875  int status = 0;
1876 
1877  do {
1878  status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1879  if (status < 0)
1880  break;
1881  if (noiseCal->cpOpt) {
1882  beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1883  } else {
1884  beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1885  status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1886  if (status < 0)
1887  break;
1888  }
1889  status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1890  if (status < 0)
1891  break;
1892 
1893  if (!state->type_A) {
1894  status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1895  if (status < 0)
1896  break;
1897  status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1898  if (status < 0)
1899  break;
1900  }
1901  } while (0);
1902 
1903  return status;
1904 }
1905 
1906 static int DRX_Start(struct drxd_state *state, s32 off)
1907 {
1908  struct dtv_frontend_properties *p = &state->props;
1909  int status;
1910 
1911  u16 transmissionParams = 0;
1912  u16 operationMode = 0;
1913  u16 qpskTdTpsPwr = 0;
1914  u16 qam16TdTpsPwr = 0;
1915  u16 qam64TdTpsPwr = 0;
1916  u32 feIfIncr = 0;
1917  u32 bandwidth = 0;
1918  int mirrorFreqSpect;
1919 
1920  u16 qpskSnCeGain = 0;
1921  u16 qam16SnCeGain = 0;
1922  u16 qam64SnCeGain = 0;
1923  u16 qpskIsGainMan = 0;
1924  u16 qam16IsGainMan = 0;
1925  u16 qam64IsGainMan = 0;
1926  u16 qpskIsGainExp = 0;
1927  u16 qam16IsGainExp = 0;
1928  u16 qam64IsGainExp = 0;
1929  u16 bandwidthParam = 0;
1930 
1931  if (off < 0)
1932  off = (off - 500) / 1000;
1933  else
1934  off = (off + 500) / 1000;
1935 
1936  do {
1937  if (state->drxd_state != DRXD_STOPPED)
1938  return -1;
1939  status = ResetECOD(state);
1940  if (status < 0)
1941  break;
1942  if (state->type_A) {
1943  status = InitSC(state);
1944  if (status < 0)
1945  break;
1946  } else {
1947  status = InitFT(state);
1948  if (status < 0)
1949  break;
1950  status = InitCP(state);
1951  if (status < 0)
1952  break;
1953  status = InitCE(state);
1954  if (status < 0)
1955  break;
1956  status = InitEQ(state);
1957  if (status < 0)
1958  break;
1959  status = InitSC(state);
1960  if (status < 0)
1961  break;
1962  }
1963 
1964  /* Restore current IF & RF AGC settings */
1965 
1966  status = SetCfgIfAgc(state, &state->if_agc_cfg);
1967  if (status < 0)
1968  break;
1969  status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1970  if (status < 0)
1971  break;
1972 
1973  mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1974 
1975  switch (p->transmission_mode) {
1976  default: /* Not set, detect it automatically */
1977  operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1978  /* fall through , try first guess DRX_FFTMODE_8K */
1979  case TRANSMISSION_MODE_8K:
1980  transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1981  if (state->type_A) {
1982  status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1983  if (status < 0)
1984  break;
1985  qpskSnCeGain = 99;
1986  qam16SnCeGain = 83;
1987  qam64SnCeGain = 67;
1988  }
1989  break;
1990  case TRANSMISSION_MODE_2K:
1991  transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1992  if (state->type_A) {
1993  status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1994  if (status < 0)
1995  break;
1996  qpskSnCeGain = 97;
1997  qam16SnCeGain = 71;
1998  qam64SnCeGain = 65;
1999  }
2000  break;
2001  }
2002 
2003  switch (p->guard_interval) {
2004  case GUARD_INTERVAL_1_4:
2005  transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2006  break;
2007  case GUARD_INTERVAL_1_8:
2008  transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
2009  break;
2010  case GUARD_INTERVAL_1_16:
2011  transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
2012  break;
2013  case GUARD_INTERVAL_1_32:
2014  transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
2015  break;
2016  default: /* Not set, detect it automatically */
2017  operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
2018  /* try first guess 1/4 */
2019  transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2020  break;
2021  }
2022 
2023  switch (p->hierarchy) {
2024  case HIERARCHY_1:
2025  transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
2026  if (state->type_A) {
2027  status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2028  if (status < 0)
2029  break;
2030  status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2031  if (status < 0)
2032  break;
2033 
2034  qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2035  qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
2036  qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
2037 
2038  qpskIsGainMan =
2039  SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2040  qam16IsGainMan =
2041  SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2042  qam64IsGainMan =
2043  SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2044 
2045  qpskIsGainExp =
2046  SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2047  qam16IsGainExp =
2048  SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2049  qam64IsGainExp =
2050  SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2051  }
2052  break;
2053 
2054  case HIERARCHY_2:
2055  transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
2056  if (state->type_A) {
2057  status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2058  if (status < 0)
2059  break;
2060  status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2061  if (status < 0)
2062  break;
2063 
2064  qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2065  qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
2066  qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
2067 
2068  qpskIsGainMan =
2069  SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2070  qam16IsGainMan =
2071  SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
2072  qam64IsGainMan =
2073  SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
2074 
2075  qpskIsGainExp =
2076  SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2077  qam16IsGainExp =
2078  SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
2079  qam64IsGainExp =
2080  SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
2081  }
2082  break;
2083  case HIERARCHY_4:
2084  transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
2085  if (state->type_A) {
2086  status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2087  if (status < 0)
2088  break;
2089  status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2090  if (status < 0)
2091  break;
2092 
2093  qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2094  qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
2095  qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
2096 
2097  qpskIsGainMan =
2098  SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2099  qam16IsGainMan =
2100  SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
2101  qam64IsGainMan =
2102  SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
2103 
2104  qpskIsGainExp =
2105  SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2106  qam16IsGainExp =
2107  SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
2108  qam64IsGainExp =
2109  SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
2110  }
2111  break;
2112  case HIERARCHY_AUTO:
2113  default:
2114  /* Not set, detect it automatically, start with none */
2115  operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
2116  transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
2117  if (state->type_A) {
2118  status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2119  if (status < 0)
2120  break;
2121  status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2122  if (status < 0)
2123  break;
2124 
2125  qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
2126  qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2127  qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2128 
2129  qpskIsGainMan =
2130  SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
2131  qam16IsGainMan =
2132  SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2133  qam64IsGainMan =
2134  SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2135 
2136  qpskIsGainExp =
2137  SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
2138  qam16IsGainExp =
2139  SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2140  qam64IsGainExp =
2141  SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2142  }
2143  break;
2144  }
2145  status = status;
2146  if (status < 0)
2147  break;
2148 
2149  switch (p->modulation) {
2150  default:
2151  operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2152  /* fall through , try first guess
2153  DRX_CONSTELLATION_QAM64 */
2154  case QAM_64:
2155  transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2156  if (state->type_A) {
2157  status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2158  if (status < 0)
2159  break;
2160  status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2161  if (status < 0)
2162  break;
2163  status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2164  if (status < 0)
2165  break;
2166  status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2167  if (status < 0)
2168  break;
2169  status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2170  if (status < 0)
2171  break;
2172 
2173  status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2174  if (status < 0)
2175  break;
2176  status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2177  if (status < 0)
2178  break;
2179  status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2180  if (status < 0)
2181  break;
2182  status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2183  if (status < 0)
2184  break;
2185  }
2186  break;
2187  case QPSK:
2188  transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2189  if (state->type_A) {
2190  status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2191  if (status < 0)
2192  break;
2193  status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2194  if (status < 0)
2195  break;
2196  status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2197  if (status < 0)
2198  break;
2199  status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2200  if (status < 0)
2201  break;
2202  status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2203  if (status < 0)
2204  break;
2205 
2206  status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2207  if (status < 0)
2208  break;
2209  status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2210  if (status < 0)
2211  break;
2212  status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2213  if (status < 0)
2214  break;
2215  status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2216  if (status < 0)
2217  break;
2218  }
2219  break;
2220 
2221  case QAM_16:
2222  transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2223  if (state->type_A) {
2224  status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2225  if (status < 0)
2226  break;
2227  status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2228  if (status < 0)
2229  break;
2230  status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2231  if (status < 0)
2232  break;
2233  status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2234  if (status < 0)
2235  break;
2236  status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2237  if (status < 0)
2238  break;
2239 
2240  status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2241  if (status < 0)
2242  break;
2243  status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2244  if (status < 0)
2245  break;
2246  status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2247  if (status < 0)
2248  break;
2249  status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2250  if (status < 0)
2251  break;
2252  }
2253  break;
2254 
2255  }
2256  status = status;
2257  if (status < 0)
2258  break;
2259 
2260  switch (DRX_CHANNEL_HIGH) {
2261  default:
2262  case DRX_CHANNEL_AUTO:
2263  case DRX_CHANNEL_LOW:
2264  transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
2265  status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2266  if (status < 0)
2267  break;
2268  break;
2269  case DRX_CHANNEL_HIGH:
2270  transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
2271  status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2272  if (status < 0)
2273  break;
2274  break;
2275 
2276  }
2277 
2278  switch (p->code_rate_HP) {
2279  case FEC_1_2:
2280  transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2281  if (state->type_A) {
2282  status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2283  if (status < 0)
2284  break;
2285  }
2286  break;
2287  default:
2288  operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
2289  case FEC_2_3:
2290  transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2291  if (state->type_A) {
2292  status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2293  if (status < 0)
2294  break;
2295  }
2296  break;
2297  case FEC_3_4:
2298  transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2299  if (state->type_A) {
2300  status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2301  if (status < 0)
2302  break;
2303  }
2304  break;
2305  case FEC_5_6:
2306  transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2307  if (state->type_A) {
2308  status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2309  if (status < 0)
2310  break;
2311  }
2312  break;
2313  case FEC_7_8:
2314  transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2315  if (state->type_A) {
2316  status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2317  if (status < 0)
2318  break;
2319  }
2320  break;
2321  }
2322  status = status;
2323  if (status < 0)
2324  break;
2325 
2326  /* First determine real bandwidth (Hz) */
2327  /* Also set delay for impulse noise cruncher (only A2) */
2328  /* Also set parameters for EC_OC fix, note
2329  EC_OC_REG_TMD_HIL_MAR is changed
2330  by SC for fix for some 8K,1/8 guard but is restored by
2331  InitEC and ResetEC
2332  functions */
2333  switch (p->bandwidth_hz) {
2334  case 0:
2335  p->bandwidth_hz = 8000000;
2336  /* fall through */
2337  case 8000000:
2338  /* (64/7)*(8/8)*1000000 */
2339  bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2340 
2341  bandwidthParam = 0;
2342  status = Write16(state,
2343  FE_AG_REG_IND_DEL__A, 50, 0x0000);
2344  break;
2345  case 7000000:
2346  /* (64/7)*(7/8)*1000000 */
2347  bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2348  bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
2349  status = Write16(state,
2350  FE_AG_REG_IND_DEL__A, 59, 0x0000);
2351  break;
2352  case 6000000:
2353  /* (64/7)*(6/8)*1000000 */
2354  bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2355  bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
2356  status = Write16(state,
2357  FE_AG_REG_IND_DEL__A, 71, 0x0000);
2358  break;
2359  default:
2360  status = -EINVAL;
2361  }
2362  if (status < 0)
2363  break;
2364 
2365  status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2366  if (status < 0)
2367  break;
2368 
2369  {
2370  u16 sc_config;
2371  status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2372  if (status < 0)
2373  break;
2374 
2375  /* enable SLAVE mode in 2k 1/32 to
2376  prevent timing change glitches */
2377  if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
2378  (p->guard_interval == GUARD_INTERVAL_1_32)) {
2379  /* enable slave */
2380  sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2381  } else {
2382  /* disable slave */
2383  sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2384  }
2385  status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2386  if (status < 0)
2387  break;
2388  }
2389 
2390  status = SetCfgNoiseCalibration(state, &state->noise_cal);
2391  if (status < 0)
2392  break;
2393 
2394  if (state->cscd_state == CSCD_INIT) {
2395  /* switch on SRMM scan in SC */
2396  status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2397  if (status < 0)
2398  break;
2399 /* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
2400  state->cscd_state = CSCD_SET;
2401  }
2402 
2403  /* Now compute FE_IF_REG_INCR */
2404  /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
2405  ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2406  feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2407  (1ULL << 21), bandwidth) - (1 << 23);
2408  status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2409  if (status < 0)
2410  break;
2411  status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2412  if (status < 0)
2413  break;
2414  /* Bandwidth setting done */
2415 
2416  /* Mirror & frequency offset */
2417  SetFrequencyShift(state, off, mirrorFreqSpect);
2418 
2419  /* Start SC, write channel settings to SC */
2420 
2421  /* Enable SC after setting all other parameters */
2422  status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2423  if (status < 0)
2424  break;
2425  status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2426  if (status < 0)
2427  break;
2428 
2429  /* Write SC parameter registers, operation mode */
2430 #if 1
2431  operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
2432  SC_RA_RAM_OP_AUTO_GUARD__M |
2433  SC_RA_RAM_OP_AUTO_CONST__M |
2434  SC_RA_RAM_OP_AUTO_HIER__M |
2435  SC_RA_RAM_OP_AUTO_RATE__M);
2436 #endif
2437  status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2438  if (status < 0)
2439  break;
2440 
2441  /* Start correct processes to get in lock */
2442  status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2443  if (status < 0)
2444  break;
2445 
2446  status = StartOC(state);
2447  if (status < 0)
2448  break;
2449 
2450  if (state->operation_mode != OM_Default) {
2451  status = StartDiversity(state);
2452  if (status < 0)
2453  break;
2454  }
2455 
2456  state->drxd_state = DRXD_STARTED;
2457  } while (0);
2458 
2459  return status;
2460 }
2461 
2462 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2463 {
2464  u32 ulRfAgcOutputLevel = 0xffffffff;
2465  u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */
2466  u32 ulRfAgcMinLevel = 0; /* Currently unused */
2467  u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
2468  u32 ulRfAgcSpeed = 0; /* Currently unused */
2469  u32 ulRfAgcMode = 0; /*2; Off */
2470  u32 ulRfAgcR1 = 820;
2471  u32 ulRfAgcR2 = 2200;
2472  u32 ulRfAgcR3 = 150;
2473  u32 ulIfAgcMode = 0; /* Auto */
2474  u32 ulIfAgcOutputLevel = 0xffffffff;
2475  u32 ulIfAgcSettleLevel = 0xffffffff;
2476  u32 ulIfAgcMinLevel = 0xffffffff;
2477  u32 ulIfAgcMaxLevel = 0xffffffff;
2478  u32 ulIfAgcSpeed = 0xffffffff;
2479  u32 ulIfAgcR1 = 820;
2480  u32 ulIfAgcR2 = 2200;
2481  u32 ulIfAgcR3 = 150;
2482  u32 ulClock = state->config.clock;
2483  u32 ulSerialMode = 0;
2484  u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */
2485  u32 ulHiI2cDelay = HI_I2C_DELAY;
2486  u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2487  u32 ulHiI2cPatch = 0;
2488  u32 ulEnvironment = APPENV_PORTABLE;
2489  u32 ulEnvironmentDiversity = APPENV_MOBILE;
2490  u32 ulIFFilter = IFFILTER_SAW;
2491 
2492  state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2493  state->if_agc_cfg.outputLevel = 0;
2494  state->if_agc_cfg.settleLevel = 140;
2495  state->if_agc_cfg.minOutputLevel = 0;
2496  state->if_agc_cfg.maxOutputLevel = 1023;
2497  state->if_agc_cfg.speed = 904;
2498 
2499  if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2500  state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2501  state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
2502  }
2503 
2504  if (ulIfAgcMode == 0 &&
2505  ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2506  ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2507  ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2508  ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2509  state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2510  state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
2511  state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
2512  state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
2513  state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
2514  }
2515 
2516  state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
2517  state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
2518  state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
2519 
2520  state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
2521  state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
2522  state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
2523 
2524  state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2525  /* rest of the RFAgcCfg structure currently unused */
2526  if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2527  state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2528  state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
2529  }
2530 
2531  if (ulRfAgcMode == 0 &&
2532  ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2533  ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2534  ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2535  ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2536  state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2537  state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
2538  state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
2539  state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
2540  state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
2541  }
2542 
2543  if (ulRfAgcMode == 2)
2544  state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
2545 
2546  if (ulEnvironment <= 2)
2547  state->app_env_default = (enum app_env)
2548  (ulEnvironment);
2549  if (ulEnvironmentDiversity <= 2)
2550  state->app_env_diversity = (enum app_env)
2551  (ulEnvironmentDiversity);
2552 
2553  if (ulIFFilter == IFFILTER_DISCRETE) {
2554  /* discrete filter */
2555  state->noise_cal.cpOpt = 0;
2556  state->noise_cal.cpNexpOfs = 40;
2557  state->noise_cal.tdCal2k = -40;
2558  state->noise_cal.tdCal8k = -24;
2559  } else {
2560  /* SAW filter */
2561  state->noise_cal.cpOpt = 1;
2562  state->noise_cal.cpNexpOfs = 0;
2563  state->noise_cal.tdCal2k = -21;
2564  state->noise_cal.tdCal8k = -24;
2565  }
2566  state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
2567 
2568  state->chip_adr = (state->config.demod_address << 1) | 1;
2569  switch (ulHiI2cPatch) {
2570  case 1:
2571  state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
2572  break;
2573  case 3:
2574  state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
2575  break;
2576  default:
2577  state->m_HiI2cPatch = NULL;
2578  }
2579 
2580  /* modify tuner and clock attributes */
2581  state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
2582  /* expected system clock frequency in kHz */
2583  state->expected_sys_clock_freq = 48000;
2584  /* real system clock frequency in kHz */
2585  state->sys_clock_freq = 48000;
2586  state->osc_clock_freq = (u16) ulClock;
2587  state->osc_clock_deviation = 0;
2588  state->cscd_state = CSCD_INIT;
2589  state->drxd_state = DRXD_UNINITIALIZED;
2590 
2591  state->PGA = 0;
2592  state->type_A = 0;
2593  state->tuner_mirrors = 0;
2594 
2595  /* modify MPEG output attributes */
2596  state->insert_rs_byte = state->config.insert_rs_byte;
2597  state->enable_parallel = (ulSerialMode != 1);
2598 
2599  /* Timing div, 250ns/Psys */
2600  /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2601 
2602  state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
2603  ulHiI2cDelay) / 1000;
2604  /* Bridge delay, uses oscilator clock */
2605  /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2606  state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
2607  ulHiI2cBridgeDelay) / 1000;
2608 
2609  state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2610  /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2611  state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2612  return 0;
2613 }
2614 
2615 int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size)
2616 {
2617  int status = 0;
2618  u32 driverVersion;
2619 
2620  if (state->init_done)
2621  return 0;
2622 
2623  CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2624 
2625  do {
2626  state->operation_mode = OM_Default;
2627 
2628  status = SetDeviceTypeId(state);
2629  if (status < 0)
2630  break;
2631 
2632  /* Apply I2c address patch to B1 */
2633  if (!state->type_A && state->m_HiI2cPatch != NULL)
2634  status = WriteTable(state, state->m_HiI2cPatch);
2635  if (status < 0)
2636  break;
2637 
2638  if (state->type_A) {
2639  /* HI firmware patch for UIO readout,
2640  avoid clearing of result register */
2641  status = Write16(state, 0x43012D, 0x047f, 0);
2642  if (status < 0)
2643  break;
2644  }
2645 
2646  status = HI_ResetCommand(state);
2647  if (status < 0)
2648  break;
2649 
2650  status = StopAllProcessors(state);
2651  if (status < 0)
2652  break;
2653  status = InitCC(state);
2654  if (status < 0)
2655  break;
2656 
2657  state->osc_clock_deviation = 0;
2658 
2659  if (state->config.osc_deviation)
2660  state->osc_clock_deviation =
2661  state->config.osc_deviation(state->priv, 0, 0);
2662  {
2663  /* Handle clock deviation */
2664  s32 devB;
2665  s32 devA = (s32) (state->osc_clock_deviation) *
2666  (s32) (state->expected_sys_clock_freq);
2667  /* deviation in kHz */
2668  s32 deviation = (devA / (1000000L));
2669  /* rounding, signed */
2670  if (devA > 0)
2671  devB = (2);
2672  else
2673  devB = (-2);
2674  if ((devB * (devA % 1000000L) > 1000000L)) {
2675  /* add +1 or -1 */
2676  deviation += (devB / 2);
2677  }
2678 
2679  state->sys_clock_freq =
2680  (u16) ((state->expected_sys_clock_freq) +
2681  deviation);
2682  }
2683  status = InitHI(state);
2684  if (status < 0)
2685  break;
2686  status = InitAtomicRead(state);
2687  if (status < 0)
2688  break;
2689 
2690  status = EnableAndResetMB(state);
2691  if (status < 0)
2692  break;
2693  if (state->type_A)
2694  status = ResetCEFR(state);
2695  if (status < 0)
2696  break;
2697 
2698  if (fw) {
2699  status = DownloadMicrocode(state, fw, fw_size);
2700  if (status < 0)
2701  break;
2702  } else {
2703  status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2704  if (status < 0)
2705  break;
2706  }
2707 
2708  if (state->PGA) {
2709  state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
2710  SetCfgPga(state, 0); /* PGA = 0 dB */
2711  } else {
2712  state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2713  }
2714 
2715  state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2716 
2717  status = InitFE(state);
2718  if (status < 0)
2719  break;
2720  status = InitFT(state);
2721  if (status < 0)
2722  break;
2723  status = InitCP(state);
2724  if (status < 0)
2725  break;
2726  status = InitCE(state);
2727  if (status < 0)
2728  break;
2729  status = InitEQ(state);
2730  if (status < 0)
2731  break;
2732  status = InitEC(state);
2733  if (status < 0)
2734  break;
2735  status = InitSC(state);
2736  if (status < 0)
2737  break;
2738 
2739  status = SetCfgIfAgc(state, &state->if_agc_cfg);
2740  if (status < 0)
2741  break;
2742  status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2743  if (status < 0)
2744  break;
2745 
2746  state->cscd_state = CSCD_INIT;
2747  status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2748  if (status < 0)
2749  break;
2750  status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2751  if (status < 0)
2752  break;
2753 
2754  driverVersion = (((VERSION_MAJOR / 10) << 4) +
2755  (VERSION_MAJOR % 10)) << 24;
2756  driverVersion += (((VERSION_MINOR / 10) << 4) +
2757  (VERSION_MINOR % 10)) << 16;
2758  driverVersion += ((VERSION_PATCH / 1000) << 12) +
2759  ((VERSION_PATCH / 100) << 8) +
2760  ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
2761 
2762  status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2763  if (status < 0)
2764  break;
2765 
2766  status = StopOC(state);
2767  if (status < 0)
2768  break;
2769 
2770  state->drxd_state = DRXD_STOPPED;
2771  state->init_done = 1;
2772  status = 0;
2773  } while (0);
2774  return status;
2775 }
2776 
2777 int DRXD_status(struct drxd_state *state, u32 * pLockStatus)
2778 {
2779  DRX_GetLockStatus(state, pLockStatus);
2780 
2781  /*if (*pLockStatus&DRX_LOCK_MPEG) */
2782  if (*pLockStatus & DRX_LOCK_FEC) {
2783  ConfigureMPEGOutput(state, 1);
2784  /* Get status again, in case we have MPEG lock now */
2785  /*DRX_GetLockStatus(state, pLockStatus); */
2786  }
2787 
2788  return 0;
2789 }
2790 
2791 /****************************************************************************/
2792 /****************************************************************************/
2793 /****************************************************************************/
2794 
2795 static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2796 {
2797  struct drxd_state *state = fe->demodulator_priv;
2798  u32 value;
2799  int res;
2800 
2801  res = ReadIFAgc(state, &value);
2802  if (res < 0)
2803  *strength = 0;
2804  else
2805  *strength = 0xffff - (value << 4);
2806  return 0;
2807 }
2808 
2809 static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status)
2810 {
2811  struct drxd_state *state = fe->demodulator_priv;
2812  u32 lock;
2813 
2814  DRXD_status(state, &lock);
2815  *status = 0;
2816  /* No MPEG lock in V255 firmware, bug ? */
2817 #if 1
2818  if (lock & DRX_LOCK_MPEG)
2819  *status |= FE_HAS_LOCK;
2820 #else
2821  if (lock & DRX_LOCK_FEC)
2822  *status |= FE_HAS_LOCK;
2823 #endif
2824  if (lock & DRX_LOCK_FEC)
2825  *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2826  if (lock & DRX_LOCK_DEMOD)
2827  *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
2828 
2829  return 0;
2830 }
2831 
2832 static int drxd_init(struct dvb_frontend *fe)
2833 {
2834  struct drxd_state *state = fe->demodulator_priv;
2835  int err = 0;
2836 
2837 /* if (request_firmware(&state->fw, "drxd.fw", state->dev)<0) */
2838  return DRXD_init(state, 0, 0);
2839 
2840  err = DRXD_init(state, state->fw->data, state->fw->size);
2841  release_firmware(state->fw);
2842  return err;
2843 }
2844 
2845 int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
2846 {
2847  struct drxd_state *state = fe->demodulator_priv;
2848 
2849  if (state->config.disable_i2c_gate_ctrl == 1)
2850  return 0;
2851 
2852  return DRX_ConfigureI2CBridge(state, onoff);
2853 }
2854 EXPORT_SYMBOL(drxd_config_i2c);
2855 
2856 static int drxd_get_tune_settings(struct dvb_frontend *fe,
2857  struct dvb_frontend_tune_settings *sets)
2858 {
2859  sets->min_delay_ms = 10000;
2860  sets->max_drift = 0;
2861  sets->step_size = 0;
2862  return 0;
2863 }
2864 
2865 static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
2866 {
2867  *ber = 0;
2868  return 0;
2869 }
2870 
2871 static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
2872 {
2873  *snr = 0;
2874  return 0;
2875 }
2876 
2877 static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
2878 {
2879  *ucblocks = 0;
2880  return 0;
2881 }
2882 
2883 static int drxd_sleep(struct dvb_frontend *fe)
2884 {
2885  struct drxd_state *state = fe->demodulator_priv;
2886 
2887  ConfigureMPEGOutput(state, 0);
2888  return 0;
2889 }
2890 
2891 static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2892 {
2893  return drxd_config_i2c(fe, enable);
2894 }
2895 
2896 static int drxd_set_frontend(struct dvb_frontend *fe)
2897 {
2898  struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2899  struct drxd_state *state = fe->demodulator_priv;
2900  s32 off = 0;
2901 
2902  state->props = *p;
2903  DRX_Stop(state);
2904 
2905  if (fe->ops.tuner_ops.set_params) {
2906  fe->ops.tuner_ops.set_params(fe);
2907  if (fe->ops.i2c_gate_ctrl)
2908  fe->ops.i2c_gate_ctrl(fe, 0);
2909  }
2910 
2911  msleep(200);
2912 
2913  return DRX_Start(state, off);
2914 }
2915 
2916 static void drxd_release(struct dvb_frontend *fe)
2917 {
2918  struct drxd_state *state = fe->demodulator_priv;
2919 
2920  kfree(state);
2921 }
2922 
2923 static struct dvb_frontend_ops drxd_ops = {
2924  .delsys = { SYS_DVBT},
2925  .info = {
2926  .name = "Micronas DRXD DVB-T",
2927  .frequency_min = 47125000,
2928  .frequency_max = 855250000,
2929  .frequency_stepsize = 166667,
2930  .frequency_tolerance = 0,
2931  .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2932  FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2933  FE_CAN_FEC_AUTO |
2934  FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2935  FE_CAN_QAM_AUTO |
2936  FE_CAN_TRANSMISSION_MODE_AUTO |
2937  FE_CAN_GUARD_INTERVAL_AUTO |
2938  FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
2939 
2940  .release = drxd_release,
2941  .init = drxd_init,
2942  .sleep = drxd_sleep,
2943  .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2944 
2945  .set_frontend = drxd_set_frontend,
2946  .get_tune_settings = drxd_get_tune_settings,
2947 
2948  .read_status = drxd_read_status,
2949  .read_ber = drxd_read_ber,
2950  .read_signal_strength = drxd_read_signal_strength,
2951  .read_snr = drxd_read_snr,
2952  .read_ucblocks = drxd_read_ucblocks,
2953 };
2954 
2955 struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2956  void *priv, struct i2c_adapter *i2c,
2957  struct device *dev)
2958 {
2959  struct drxd_state *state = NULL;
2960 
2961  state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL);
2962  if (!state)
2963  return NULL;
2964  memset(state, 0, sizeof(*state));
2965 
2966  memcpy(&state->ops, &drxd_ops, sizeof(struct dvb_frontend_ops));
2967  state->dev = dev;
2968  state->config = *config;
2969  state->i2c = i2c;
2970  state->priv = priv;
2971 
2972  mutex_init(&state->mutex);
2973 
2974  if (Read16(state, 0, 0, 0) < 0)
2975  goto error;
2976 
2977  memcpy(&state->frontend.ops, &drxd_ops,
2978  sizeof(struct dvb_frontend_ops));
2979  state->frontend.demodulator_priv = state;
2980  ConfigureMPEGOutput(state, 0);
2981  return &state->frontend;
2982 
2983 error:
2984  printk(KERN_ERR "drxd: not found\n");
2985  kfree(state);
2986  return NULL;
2987 }
2988 EXPORT_SYMBOL(drxd_attach);
2989 
2990 MODULE_DESCRIPTION("DRXD driver");
2991 MODULE_AUTHOR("Micronas");
2992 MODULE_LICENSE("GPL");
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