e1000_defines.h File Reference

Go to the source code of this file.

Macros
#define	REQ_TX_DESCRIPTOR_MULTIPLE   8
#define	REQ_RX_DESCRIPTOR_MULTIPLE   8
#define	E1000_WUC_PME_EN   0x00000002 /* PME Enable */
#define	E1000_WUFC_LNKC   0x00000001 /* Link Status Change Wakeup Enable */
#define	E1000_WUFC_MAG   0x00000002 /* Magic Packet Wakeup Enable */
#define	E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
#define	E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
#define	E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
#define	E1000_CTRL_EXT_SDP3_DATA   0x00000080 /* Value of SW Defineable Pin 3 */
#define	E1000_CTRL_EXT_PFRSTD   0x00004000
#define	E1000_CTRL_EXT_LINK_MODE_MASK   0x00C00000
#define	E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES   0x00C00000
#define	E1000_CTRL_EXT_LINK_MODE_1000BASE_KX   0x00400000
#define	E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000
#define	E1000_CTRL_EXT_LINK_MODE_GMII   0x00000000
#define	E1000_CTRL_EXT_EIAME   0x01000000
#define	E1000_CTRL_EXT_IRCA   0x00000001
#define	E1000_CTRL_EXT_DRV_LOAD   0x10000000
#define	E1000_CTRL_EXT_PBA_CLR   0x80000000 /* PBA Clear */
#define	E1000_I2CCMD_REG_ADDR_SHIFT   16
#define	E1000_I2CCMD_PHY_ADDR_SHIFT   24
#define	E1000_I2CCMD_OPCODE_READ   0x08000000
#define	E1000_I2CCMD_OPCODE_WRITE   0x00000000
#define	E1000_I2CCMD_READY   0x20000000
#define	E1000_I2CCMD_ERROR   0x80000000
#define	E1000_MAX_SGMII_PHY_REG_ADDR   255
#define	E1000_I2CCMD_PHY_TIMEOUT   200
#define	E1000_IVAR_VALID   0x80
#define	E1000_GPIE_NSICR   0x00000001
#define	E1000_GPIE_MSIX_MODE   0x00000010
#define	E1000_GPIE_EIAME   0x40000000
#define	E1000_GPIE_PBA   0x80000000
#define	E1000_RXD_STAT_DD   0x01 /* Descriptor Done */
#define	E1000_RXD_STAT_EOP   0x02 /* End of Packet */
#define	E1000_RXD_STAT_IXSM   0x04 /* Ignore checksum */
#define	E1000_RXD_STAT_VP   0x08 /* IEEE VLAN Packet */
#define	E1000_RXD_STAT_UDPCS   0x10 /* UDP xsum calculated */
#define	E1000_RXD_STAT_TCPCS   0x20 /* TCP xsum calculated */
#define	E1000_RXD_STAT_TS   0x10000 /* Pkt was time stamped */
#define	E1000_RXDEXT_STATERR_LB   0x00040000
#define	E1000_RXDEXT_STATERR_CE   0x01000000
#define	E1000_RXDEXT_STATERR_SE   0x02000000
#define	E1000_RXDEXT_STATERR_SEQ   0x04000000
#define	E1000_RXDEXT_STATERR_CXE   0x10000000
#define	E1000_RXDEXT_STATERR_TCPE   0x20000000
#define	E1000_RXDEXT_STATERR_IPE   0x40000000
#define	E1000_RXDEXT_STATERR_RXE   0x80000000
#define	E1000_RXDEXT_ERR_FRAME_ERR_MASK
#define	E1000_MRQC_RSS_FIELD_IPV4_TCP   0x00010000
#define	E1000_MRQC_RSS_FIELD_IPV4   0x00020000
#define	E1000_MRQC_RSS_FIELD_IPV6_TCP_EX   0x00040000
#define	E1000_MRQC_RSS_FIELD_IPV6   0x00100000
#define	E1000_MRQC_RSS_FIELD_IPV6_TCP   0x00200000
#define	E1000_MANC_SMBUS_EN   0x00000001 /* SMBus Enabled - RO */
#define	E1000_MANC_ASF_EN   0x00000002 /* ASF Enabled - RO */
#define	E1000_MANC_EN_BMC2OS   0x10000000 /* OSBMC is Enabled or not */
#define	E1000_MANC_RCV_TCO_EN   0x00020000 /* Receive TCO Packets Enabled */
#define	E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
#define	E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
#define	E1000_RCTL_EN   0x00000002 /* enable */
#define	E1000_RCTL_SBP   0x00000004 /* store bad packet */
#define	E1000_RCTL_UPE   0x00000008 /* unicast promiscuous enable */
#define	E1000_RCTL_MPE   0x00000010 /* multicast promiscuous enab */
#define	E1000_RCTL_LPE   0x00000020 /* long packet enable */
#define	E1000_RCTL_LBM_MAC   0x00000040 /* MAC loopback mode */
#define	E1000_RCTL_LBM_TCVR   0x000000C0 /* tcvr loopback mode */
#define	E1000_RCTL_RDMTS_HALF   0x00000000 /* rx desc min threshold size */
#define	E1000_RCTL_MO_SHIFT   12 /* multicast offset shift */
#define	E1000_RCTL_BAM   0x00008000 /* broadcast enable */
#define	E1000_RCTL_SZ_512   0x00020000 /* rx buffer size 512 */
#define	E1000_RCTL_SZ_256   0x00030000 /* rx buffer size 256 */
#define	E1000_RCTL_VFE   0x00040000 /* vlan filter enable */
#define	E1000_RCTL_CFIEN   0x00080000 /* canonical form enable */
#define	E1000_RCTL_DPF   0x00400000 /* Discard Pause Frames */
#define	E1000_RCTL_PMCF   0x00800000 /* pass MAC control frames */
#define	E1000_RCTL_SECRC   0x04000000 /* Strip Ethernet CRC */
#define	E1000_PSRCTL_BSIZE0_MASK   0x0000007F
#define	E1000_PSRCTL_BSIZE1_MASK   0x00003F00
#define	E1000_PSRCTL_BSIZE2_MASK   0x003F0000
#define	E1000_PSRCTL_BSIZE3_MASK   0x3F000000
#define	E1000_PSRCTL_BSIZE0_SHIFT   7 /* Shift _right_ 7 */
#define	E1000_PSRCTL_BSIZE1_SHIFT   2 /* Shift _right_ 2 */
#define	E1000_PSRCTL_BSIZE2_SHIFT   6 /* Shift _left_ 6 */
#define	E1000_PSRCTL_BSIZE3_SHIFT   14 /* Shift _left_ 14 */
#define	E1000_SWFW_EEP_SM   0x1
#define	E1000_SWFW_PHY0_SM   0x2
#define	E1000_SWFW_PHY1_SM   0x4
#define	E1000_SWFW_PHY2_SM   0x20
#define	E1000_SWFW_PHY3_SM   0x40
#define	E1000_CTRL_FD   0x00000001 /* Full duplex.0=half; 1=full */
#define	E1000_CTRL_GIO_MASTER_DISABLE   0x00000004 /*Blocks new Master requests */
#define	E1000_CTRL_LRST   0x00000008 /* Link reset. 0=normal,1=reset */
#define	E1000_CTRL_ASDE   0x00000020 /* Auto-speed detect enable */
#define	E1000_CTRL_SLU   0x00000040 /* Set link up (Force Link) */
#define	E1000_CTRL_ILOS   0x00000080 /* Invert Loss-Of Signal */
#define	E1000_CTRL_SPD_SEL   0x00000300 /* Speed Select Mask */
#define	E1000_CTRL_SPD_100   0x00000100 /* Force 100Mb */
#define	E1000_CTRL_SPD_1000   0x00000200 /* Force 1Gb */
#define	E1000_CTRL_FRCSPD   0x00000800 /* Force Speed */
#define	E1000_CTRL_FRCDPX   0x00001000 /* Force Duplex */
#define	E1000_CTRL_SWDPIN0   0x00040000 /* SWDPIN 0 value */
#define	E1000_CTRL_SWDPIN1   0x00080000 /* SWDPIN 1 value */
#define	E1000_CTRL_SWDPIO0   0x00400000 /* SWDPIN 0 Input or output */
#define	E1000_CTRL_RST   0x04000000 /* Global reset */
#define	E1000_CTRL_RFCE   0x08000000 /* Receive Flow Control enable */
#define	E1000_CTRL_TFCE   0x10000000 /* Transmit flow control enable */
#define	E1000_CTRL_VME   0x40000000 /* IEEE VLAN mode enable */
#define	E1000_CTRL_PHY_RST   0x80000000 /* PHY Reset */
#define	E1000_CTRL_I2C_ENA   0x02000000 /* I2C enable */
#define	E1000_CONNSW_ENRGSRC   0x4
#define	E1000_PCS_CFG_PCS_EN   8
#define	E1000_PCS_LCTL_FLV_LINK_UP   1
#define	E1000_PCS_LCTL_FSV_100   2
#define	E1000_PCS_LCTL_FSV_1000   4
#define	E1000_PCS_LCTL_FDV_FULL   8
#define	E1000_PCS_LCTL_FSD   0x10
#define	E1000_PCS_LCTL_FORCE_LINK   0x20
#define	E1000_PCS_LCTL_FORCE_FCTRL   0x80
#define	E1000_PCS_LCTL_AN_ENABLE   0x10000
#define	E1000_PCS_LCTL_AN_RESTART   0x20000
#define	E1000_PCS_LCTL_AN_TIMEOUT   0x40000
#define	E1000_ENABLE_SERDES_LOOPBACK   0x0410
#define	E1000_PCS_LSTS_LINK_OK   1
#define	E1000_PCS_LSTS_SPEED_100   2
#define	E1000_PCS_LSTS_SPEED_1000   4
#define	E1000_PCS_LSTS_DUPLEX_FULL   8
#define	E1000_PCS_LSTS_SYNK_OK   0x10
#define	E1000_STATUS_FD   0x00000001 /* Full duplex.0=half,1=full */
#define	E1000_STATUS_LU   0x00000002 /* Link up.0=no,1=link */
#define	E1000_STATUS_FUNC_MASK   0x0000000C /* PCI Function Mask */
#define	E1000_STATUS_FUNC_SHIFT   2
#define	E1000_STATUS_FUNC_1   0x00000004 /* Function 1 */
#define	E1000_STATUS_TXOFF   0x00000010 /* transmission paused */
#define	E1000_STATUS_SPEED_100   0x00000040 /* Speed 100Mb/s */
#define	E1000_STATUS_SPEED_1000   0x00000080 /* Speed 1000Mb/s */
#define	E1000_STATUS_GIO_MASTER_ENABLE   0x00080000
#define	SPEED_10   10
#define	SPEED_100   100
#define	SPEED_1000   1000
#define	HALF_DUPLEX   1
#define	FULL_DUPLEX   2
#define	ADVERTISE_10_HALF   0x0001
#define	ADVERTISE_10_FULL   0x0002
#define	ADVERTISE_100_HALF   0x0004
#define	ADVERTISE_100_FULL   0x0008
#define	ADVERTISE_1000_HALF   0x0010 /* Not used, just FYI */
#define	ADVERTISE_1000_FULL   0x0020
#define	E1000_ALL_SPEED_DUPLEX
#define	E1000_ALL_NOT_GIG
#define	E1000_ALL_100_SPEED   (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
#define	E1000_ALL_10_SPEED   (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
#define	E1000_ALL_FULL_DUPLEX
#define	E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
#define	AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
#define	E1000_LEDCTL_LED0_MODE_SHIFT   0
#define	E1000_LEDCTL_LED0_BLINK   0x00000080
#define	E1000_LEDCTL_MODE_LED_ON   0xE
#define	E1000_LEDCTL_MODE_LED_OFF   0xF
#define	E1000_TXD_POPTS_IXSM   0x01 /* Insert IP checksum */
#define	E1000_TXD_POPTS_TXSM   0x02 /* Insert TCP/UDP checksum */
#define	E1000_TXD_CMD_EOP   0x01000000 /* End of Packet */
#define	E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
#define	E1000_TXD_CMD_RS   0x08000000 /* Report Status */
#define	E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
#define	E1000_TXD_STAT_DD   0x00000001 /* Descriptor Done */
#define	E1000_TCTL_EN   0x00000002 /* enable tx */
#define	E1000_TCTL_PSP   0x00000008 /* pad short packets */
#define	E1000_TCTL_CT   0x00000ff0 /* collision threshold */
#define	E1000_TCTL_COLD   0x003ff000 /* collision distance */
#define	E1000_TCTL_RTLC   0x01000000 /* Re-transmit on late collision */
#define	E1000_DMACR_DMACWT_MASK
#define	E1000_DMACR_DMACTHR_MASK
#define	E1000_DMACR_DMACTHR_SHIFT   16
#define	E1000_DMACR_DMAC_LX_MASK
#define	E1000_DMACR_DMAC_LX_SHIFT   28
#define	E1000_DMACR_DMAC_EN   0x80000000 /* Enable DMA Coalescing */
#define	E1000_DMACR_DC_BMC2OSW_EN   0x00008000
#define	E1000_DMCTXTH_DMCTTHR_MASK
#define	E1000_DMCTLX_TTLX_MASK   0x00000FFF /* Time to LX request */
#define	E1000_DMCRTRH_UTRESH_MASK
#define	E1000_DMCRTRH_LRPRCW
#define	E1000_DMCCNT_CCOUNT_MASK
#define	E1000_FCRTC_RTH_COAL_MASK
#define	E1000_FCRTC_RTH_COAL_SHIFT   4
#define	E1000_PCIEMISC_LX_DECISION   0x00000080 /* Lx power decision */
#define	E1000_RXPBS_CFG_TS_EN   0x80000000
#define	E1000_SCTL_DISABLE_SERDES_LOOPBACK   0x0400
#define	E1000_RXCSUM_IPOFL   0x00000100 /* IPv4 checksum offload */
#define	E1000_RXCSUM_TUOFL   0x00000200 /* TCP / UDP checksum offload */
#define	E1000_RXCSUM_CRCOFL   0x00000800 /* CRC32 offload enable */
#define	E1000_RXCSUM_PCSD   0x00002000 /* packet checksum disabled */
#define	E1000_RFCTL_LEF   0x00040000
#define	E1000_COLLISION_THRESHOLD   15
#define	E1000_CT_SHIFT   4
#define	E1000_COLLISION_DISTANCE   63
#define	E1000_COLD_SHIFT   12
#define	ETHERNET_IEEE_VLAN_TYPE   0x8100 /* 802.3ac packet */
#define	MAX_JUMBO_FRAME_SIZE   0x3F00
#define	E1000_PBA_34K   0x0022
#define	E1000_PBA_64K   0x0040 /* 64KB */
#define	E1000_SWSM_SMBI   0x00000001 /* Driver Semaphore bit */
#define	E1000_SWSM_SWESMBI   0x00000002 /* FW Semaphore bit */
#define	E1000_ICR_TXDW   0x00000001 /* Transmit desc written back */
#define	E1000_ICR_LSC   0x00000004 /* Link Status Change */
#define	E1000_ICR_RXSEQ   0x00000008 /* rx sequence error */
#define	E1000_ICR_RXDMT0   0x00000010 /* rx desc min. threshold (0) */
#define	E1000_ICR_RXT0   0x00000080 /* rx timer intr (ring 0) */
#define	E1000_ICR_VMMB   0x00000100 /* VM MB event */
#define	E1000_ICR_TS   0x00080000 /* Time Sync Interrupt */
#define	E1000_ICR_DRSTA   0x40000000 /* Device Reset Asserted */
#define	E1000_ICR_INT_ASSERTED   0x80000000
#define	E1000_ICR_DOUTSYNC   0x10000000 /* NIC DMA out of sync */
#define	E1000_EICR_RX_QUEUE0   0x00000001 /* Rx Queue 0 Interrupt */
#define	E1000_EICR_RX_QUEUE1   0x00000002 /* Rx Queue 1 Interrupt */
#define	E1000_EICR_RX_QUEUE2   0x00000004 /* Rx Queue 2 Interrupt */
#define	E1000_EICR_RX_QUEUE3   0x00000008 /* Rx Queue 3 Interrupt */
#define	E1000_EICR_TX_QUEUE0   0x00000100 /* Tx Queue 0 Interrupt */
#define	E1000_EICR_TX_QUEUE1   0x00000200 /* Tx Queue 1 Interrupt */
#define	E1000_EICR_TX_QUEUE2   0x00000400 /* Tx Queue 2 Interrupt */
#define	E1000_EICR_TX_QUEUE3   0x00000800 /* Tx Queue 3 Interrupt */
#define	E1000_EICR_OTHER   0x80000000 /* Interrupt Cause Active */
#define	IMS_ENABLE_MASK
#define	E1000_IMS_TXDW   E1000_ICR_TXDW /* Transmit desc written back */
#define	E1000_IMS_LSC   E1000_ICR_LSC /* Link Status Change */
#define	E1000_IMS_VMMB   E1000_ICR_VMMB /* Mail box activity */
#define	E1000_IMS_TS   E1000_ICR_TS /* Time Sync Interrupt */
#define	E1000_IMS_RXSEQ   E1000_ICR_RXSEQ /* rx sequence error */
#define	E1000_IMS_RXDMT0   E1000_ICR_RXDMT0 /* rx desc min. threshold */
#define	E1000_IMS_RXT0   E1000_ICR_RXT0 /* rx timer intr */
#define	E1000_IMS_DRSTA   E1000_ICR_DRSTA /* Device Reset Asserted */
#define	E1000_IMS_DOUTSYNC   E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
#define	E1000_EIMS_OTHER   E1000_EICR_OTHER /* Interrupt Cause Active */
#define	E1000_ICS_LSC   E1000_ICR_LSC /* Link Status Change */
#define	E1000_ICS_RXDMT0   E1000_ICR_RXDMT0 /* rx desc min. threshold */
#define	E1000_ICS_DRSTA   E1000_ICR_DRSTA /* Device Reset Aserted */
#define	E1000_EITR_CNT_IGNR   0x80000000 /* Don't reset counters on write */
#define	FLOW_CONTROL_ADDRESS_LOW   0x00C28001
#define	FLOW_CONTROL_ADDRESS_HIGH   0x00000100
#define	FLOW_CONTROL_TYPE   0x8808
#define	VLAN_TAG_SIZE   4 /* 802.3ac tag (not DMA'd) */
#define	E1000_VLAN_FILTER_TBL_SIZE   128 /* VLAN Filter Table (4096 bits) */
#define	E1000_RAH_AV   0x80000000 /* Receive descriptor valid */
#define	E1000_RAL_MAC_ADDR_LEN   4
#define	E1000_RAH_MAC_ADDR_LEN   2
#define	E1000_RAH_POOL_MASK   0x03FC0000
#define	E1000_RAH_POOL_1   0x00040000
#define	E1000_SUCCESS   0
#define	E1000_ERR_NVM   1
#define	E1000_ERR_PHY   2
#define	E1000_ERR_CONFIG   3
#define	E1000_ERR_PARAM   4
#define	E1000_ERR_MAC_INIT   5
#define	E1000_ERR_RESET   9
#define	E1000_ERR_MASTER_REQUESTS_PENDING   10
#define	E1000_BLK_PHY_RESET   12
#define	E1000_ERR_SWFW_SYNC   13
#define	E1000_NOT_IMPLEMENTED   14
#define	E1000_ERR_MBX   15
#define	E1000_ERR_INVALID_ARGUMENT   16
#define	E1000_ERR_NO_SPACE   17
#define	E1000_ERR_NVM_PBA_SECTION   18
#define	E1000_ERR_INVM_VALUE_NOT_FOUND   19
#define	COPPER_LINK_UP_LIMIT   10
#define	PHY_AUTO_NEG_LIMIT   45
#define	PHY_FORCE_LIMIT   20
#define	MASTER_DISABLE_TIMEOUT   800
#define	PHY_CFG_TIMEOUT   100
#define	AUTO_READ_DONE_TIMEOUT   10
#define	E1000_FCRTL_XONE   0x80000000 /* Enable XON frame transmission */
#define	E1000_TSYNCTXCTL_VALID   0x00000001 /* tx timestamp valid */
#define	E1000_TSYNCTXCTL_ENABLED   0x00000010 /* enable tx timestampping */
#define	E1000_TSYNCRXCTL_VALID   0x00000001 /* rx timestamp valid */
#define	E1000_TSYNCRXCTL_TYPE_MASK   0x0000000E /* rx type mask */
#define	E1000_TSYNCRXCTL_TYPE_L2_V2   0x00
#define	E1000_TSYNCRXCTL_TYPE_L4_V1   0x02
#define	E1000_TSYNCRXCTL_TYPE_L2_L4_V2   0x04
#define	E1000_TSYNCRXCTL_TYPE_ALL   0x08
#define	E1000_TSYNCRXCTL_TYPE_EVENT_V2   0x0A
#define	E1000_TSYNCRXCTL_ENABLED   0x00000010 /* enable rx timestampping */
#define	E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK   0x000000FF
#define	E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE   0x00
#define	E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE   0x01
#define	E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE   0x02
#define	E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE   0x03
#define	E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE   0x04
#define	E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK   0x00000F00
#define	E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE   0x0000
#define	E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE   0x0100
#define	E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE   0x0200
#define	E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE   0x0300
#define	E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE   0x0800
#define	E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE   0x0900
#define	E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE   0x0A00
#define	E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE   0x0B00
#define	E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE   0x0C00
#define	E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE   0x0D00
#define	E1000_TIMINCA_16NS_SHIFT   24
#define	E1000_TSICR_TXTS   0x00000002
#define	E1000_TSIM_TXTS   0x00000002
#define	E1000_MDICNFG_EXT_MDIO   0x80000000 /* MDI ext/int destination */
#define	E1000_MDICNFG_COM_MDIO   0x40000000 /* MDI shared w/ lan 0 */
#define	E1000_MDICNFG_PHY_MASK   0x03E00000
#define	E1000_MDICNFG_PHY_SHIFT   21
#define	E1000_GCR_CMPL_TMOUT_MASK   0x0000F000
#define	E1000_GCR_CMPL_TMOUT_10ms   0x00001000
#define	E1000_GCR_CMPL_TMOUT_RESEND   0x00010000
#define	E1000_GCR_CAP_VER2   0x00040000
#define	E1000_MPHY_ADDR_CTL   0x0024 /* mPHY Address Control Register */
#define	E1000_MPHY_ADDR_CTL_OFFSET_MASK   0xFFFF0000
#define	E1000_MPHY_DATA   0x0E10 /* mPHY Data Register */
#define	E1000_MPHY_PCS_CLK_REG_OFFSET   0x0004 /* mPHY PCS CLK AFE CSR Offset */
#define	E1000_MPHY_PCS_CLK_REG_DIGINELBEN   0x10
#define	MII_CR_FULL_DUPLEX   0x0100 /* FDX =1, half duplex =0 */
#define	MII_CR_RESTART_AUTO_NEG   0x0200 /* Restart auto negotiation */
#define	MII_CR_POWER_DOWN   0x0800 /* Power down */
#define	MII_CR_AUTO_NEG_EN   0x1000 /* Auto Neg Enable */
#define	MII_CR_LOOPBACK   0x4000 /* 0 = normal, 1 = loopback */
#define	MII_CR_RESET   0x8000 /* 0 = normal, 1 = PHY reset */
#define	MII_CR_SPEED_1000   0x0040
#define	MII_CR_SPEED_100   0x2000
#define	MII_CR_SPEED_10   0x0000
#define	MII_SR_LINK_STATUS   0x0004 /* Link Status 1 = link */
#define	MII_SR_AUTONEG_COMPLETE   0x0020 /* Auto Neg Complete */
#define	NWAY_AR_10T_HD_CAPS   0x0020 /* 10T Half Duplex Capable */
#define	NWAY_AR_10T_FD_CAPS   0x0040 /* 10T Full Duplex Capable */
#define	NWAY_AR_100TX_HD_CAPS   0x0080 /* 100TX Half Duplex Capable */
#define	NWAY_AR_100TX_FD_CAPS   0x0100 /* 100TX Full Duplex Capable */
#define	NWAY_AR_PAUSE   0x0400 /* Pause operation desired */
#define	NWAY_AR_ASM_DIR   0x0800 /* Asymmetric Pause Direction bit */
#define	NWAY_LPAR_PAUSE   0x0400 /* LP Pause operation desired */
#define	NWAY_LPAR_ASM_DIR   0x0800 /* LP Asymmetric Pause Direction bit */
#define	CR_1000T_HD_CAPS   0x0100 /* Advertise 1000T HD capability */
#define	CR_1000T_FD_CAPS   0x0200 /* Advertise 1000T FD capability */
#define	CR_1000T_MS_VALUE   0x0800 /* 1=Configure PHY as Master */
#define	CR_1000T_MS_ENABLE   0x1000 /* 1=Master/Slave manual config value */
#define	SR_1000T_REMOTE_RX_STATUS   0x1000 /* Remote receiver OK */
#define	SR_1000T_LOCAL_RX_STATUS   0x2000 /* Local receiver OK */
#define	PHY_CONTROL   0x00 /* Control Register */
#define	PHY_STATUS   0x01 /* Status Register */
#define	PHY_ID1   0x02 /* Phy Id Reg (word 1) */
#define	PHY_ID2   0x03 /* Phy Id Reg (word 2) */
#define	PHY_AUTONEG_ADV   0x04 /* Autoneg Advertisement */
#define	PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
#define	PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
#define	PHY_1000T_STATUS   0x0A /* 1000Base-T Status Reg */
#define	E1000_EECD_SK   0x00000001 /* NVM Clock */
#define	E1000_EECD_CS   0x00000002 /* NVM Chip Select */
#define	E1000_EECD_DI   0x00000004 /* NVM Data In */
#define	E1000_EECD_DO   0x00000008 /* NVM Data Out */
#define	E1000_EECD_REQ   0x00000040 /* NVM Access Request */
#define	E1000_EECD_GNT   0x00000080 /* NVM Access Grant */
#define	E1000_EECD_PRES   0x00000100 /* NVM Present */
#define	E1000_EECD_ADDR_BITS   0x00000400
#define	E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
#define	E1000_EECD_AUTO_RD   0x00000200 /* NVM Auto Read done */
#define	E1000_EECD_SIZE_EX_MASK   0x00007800 /* NVM Size */
#define	E1000_EECD_SIZE_EX_SHIFT   11
#define	E1000_EECD_FLUPD_I210   0x00800000 /* Update FLASH */
#define	E1000_EECD_FLUDONE_I210   0x04000000 /* Update FLASH done*/
#define	E1000_FLUDONE_ATTEMPTS   20000
#define	E1000_EERD_EEWR_MAX_COUNT   512 /* buffered EEPROM words rw */
#define	E1000_I210_FIFO_SEL_RX   0x00
#define	E1000_I210_FIFO_SEL_TX_QAV(_i)   (0x02 + (_i))
#define	E1000_I210_FIFO_SEL_TX_LEGACY   E1000_I210_FIFO_SEL_TX_QAV(0)
#define	E1000_I210_FIFO_SEL_BMC2OS_TX   0x06
#define	E1000_I210_FIFO_SEL_BMC2OS_RX   0x01
#define	E1000_EECD_FLUPD_I210   0x00800000 /* Update FLASH */
#define	E1000_EECD_FLUDONE_I210   0x04000000 /* Update FLASH done*/
#define	E1000_FLUDONE_ATTEMPTS   20000
#define	E1000_EERD_EEWR_MAX_COUNT   512 /* buffered EEPROM words rw */
#define	E1000_I210_FIFO_SEL_RX   0x00
#define	E1000_I210_FIFO_SEL_TX_QAV(_i)   (0x02 + (_i))
#define	E1000_I210_FIFO_SEL_TX_LEGACY   E1000_I210_FIFO_SEL_TX_QAV(0)
#define	E1000_I210_FIFO_SEL_BMC2OS_TX   0x06
#define	E1000_I210_FIFO_SEL_BMC2OS_RX   0x01
#define	E1000_NVM_RW_REG_DATA   16
#define	E1000_NVM_RW_REG_DONE   2 /* Offset to READ/WRITE done bit */
#define	E1000_NVM_RW_REG_START   1 /* Start operation */
#define	E1000_NVM_RW_ADDR_SHIFT   2 /* Shift to the address bits */
#define	E1000_NVM_POLL_READ   0 /* Flag for polling for read complete */
#define	NVM_COMPAT   0x0003
#define	NVM_ID_LED_SETTINGS   0x0004 /* SERDES output amplitude */
#define	NVM_INIT_CONTROL2_REG   0x000F
#define	NVM_INIT_CONTROL3_PORT_B   0x0014
#define	NVM_INIT_CONTROL3_PORT_A   0x0024
#define	NVM_ALT_MAC_ADDR_PTR   0x0037
#define	NVM_CHECKSUM_REG   0x003F
#define	NVM_COMPATIBILITY_REG_3   0x0003
#define	NVM_COMPATIBILITY_BIT_MASK   0x8000
#define	NVM_MAC_ADDR   0x0000
#define	NVM_SUB_DEV_ID   0x000B
#define	NVM_SUB_VEN_ID   0x000C
#define	NVM_DEV_ID   0x000D
#define	NVM_VEN_ID   0x000E
#define	NVM_INIT_CTRL_2   0x000F
#define	NVM_INIT_CTRL_4   0x0013
#define	NVM_LED_1_CFG   0x001C
#define	NVM_LED_0_2_CFG   0x001F
#define	E1000_NVM_CFG_DONE_PORT_0   0x040000 /* MNG config cycle done */
#define	E1000_NVM_CFG_DONE_PORT_1   0x080000 /* ...for second port */
#define	E1000_NVM_CFG_DONE_PORT_2   0x100000 /* ...for third port */
#define	E1000_NVM_CFG_DONE_PORT_3   0x200000 /* ...for fourth port */
#define	NVM_82580_LAN_FUNC_OFFSET(a)   (a ? (0x40 + (0x40 * a)) : 0)
#define	NVM_WORD24_COM_MDIO   0x0008 /* MDIO interface shared */
#define	NVM_WORD24_EXT_MDIO   0x0004 /* MDIO accesses routed external */
#define	NVM_WORD0F_PAUSE_MASK   0x3000
#define	NVM_WORD0F_ASM_DIR   0x2000
#define	E1000_PBANUM_LENGTH   11
#define	NVM_SUM   0xBABA
#define	NVM_PBA_OFFSET_0   8
#define	NVM_PBA_OFFSET_1   9
#define	NVM_RESERVED_WORD   0xFFFF
#define	NVM_PBA_PTR_GUARD   0xFAFA
#define	NVM_WORD_SIZE_BASE_SHIFT   6
#define	NVM_MAX_RETRY_SPI   5000 /* Max wait of 5ms, for RDY signal */
#define	NVM_WRITE_OPCODE_SPI   0x02 /* NVM write opcode */
#define	NVM_READ_OPCODE_SPI   0x03 /* NVM read opcode */
#define	NVM_A8_OPCODE_SPI   0x08 /* opcode bit-3 = address bit-8 */
#define	NVM_WREN_OPCODE_SPI   0x06 /* NVM set Write Enable latch */
#define	NVM_RDSR_OPCODE_SPI   0x05 /* NVM read Status register */
#define	NVM_STATUS_RDY_SPI   0x01
#define	ID_LED_RESERVED_0000   0x0000
#define	ID_LED_RESERVED_FFFF   0xFFFF
#define	ID_LED_DEFAULT
#define	ID_LED_DEF1_DEF2   0x1
#define	ID_LED_DEF1_ON2   0x2
#define	ID_LED_DEF1_OFF2   0x3
#define	ID_LED_ON1_DEF2   0x4
#define	ID_LED_ON1_ON2   0x5
#define	ID_LED_ON1_OFF2   0x6
#define	ID_LED_OFF1_DEF2   0x7
#define	ID_LED_OFF1_ON2   0x8
#define	ID_LED_OFF1_OFF2   0x9
#define	IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
#define	IGP_ACTIVITY_LED_ENABLE   0x0300
#define	IGP_LED3_MODE   0x07000000
#define	PCIE_DEVICE_CONTROL2   0x28
#define	PCIE_DEVICE_CONTROL2_16ms   0x0005
#define	PHY_REVISION_MASK   0xFFFFFFF0
#define	MAX_PHY_REG_ADDRESS   0x1F /* 5 bit address bus (0-0x1F) */
#define	MAX_PHY_MULTI_PAGE_REG   0xF
#define	M88E1111_I_PHY_ID   0x01410CC0
#define	M88E1112_E_PHY_ID   0x01410C90
#define	I347AT4_E_PHY_ID   0x01410DC0
#define	IGP03E1000_E_PHY_ID   0x02A80390
#define	I82580_I_PHY_ID   0x015403A0
#define	I350_I_PHY_ID   0x015403B0
#define	M88_VENDOR   0x0141
#define	I210_I_PHY_ID   0x01410C00
#define	M88E1000_PHY_SPEC_CTRL   0x10 /* PHY Specific Control Register */
#define	M88E1000_PHY_SPEC_STATUS   0x11 /* PHY Specific Status Register */
#define	M88E1000_EXT_PHY_SPEC_CTRL   0x14 /* Extended PHY Specific Control */
#define	M88E1000_PHY_PAGE_SELECT   0x1D /* Reg 29 for page number setting */
#define	M88E1000_PHY_GEN_CONTROL   0x1E /* Its meaning depends on reg 29 */
#define	M88E1000_PSCR_POLARITY_REVERSAL   0x0002 /* 1=Polarity Reversal enabled */
#define	M88E1000_PSCR_MDI_MANUAL_MODE   0x0000 /* MDI Crossover Mode bits 6:5 */
#define	M88E1000_PSCR_MDIX_MANUAL_MODE   0x0020 /* Manual MDIX configuration */
#define	M88E1000_PSCR_AUTO_X_1000T   0x0040
#define	M88E1000_PSCR_AUTO_X_MODE   0x0060
#define	M88E1000_PSCR_ASSERT_CRS_ON_TX   0x0800 /* 1=Assert CRS on Transmit */
#define	M88E1000_PSSR_REV_POLARITY   0x0002 /* 1=Polarity reversed */
#define	M88E1000_PSSR_DOWNSHIFT   0x0020 /* 1=Downshifted */
#define	M88E1000_PSSR_MDIX   0x0040 /* 1=MDIX; 0=MDI */
#define	M88E1000_PSSR_CABLE_LENGTH   0x0380
#define	M88E1000_PSSR_SPEED   0xC000 /* Speed, bits 14:15 */
#define	M88E1000_PSSR_1000MBS   0x8000 /* 10=1000Mbs */
#define	M88E1000_PSSR_CABLE_LENGTH_SHIFT   7
#define	M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK   0x0C00
#define	M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
#define	M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK   0x0300
#define	M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X   0x0100
#define	M88E1000_EPSCR_TX_CLK_25   0x0070 /* 25 MHz TX_CLK */
#define	I347AT4_PCDL   0x10 /* PHY Cable Diagnostics Length */
#define	I347AT4_PCDC   0x15 /* PHY Cable Diagnostics Control */
#define	I347AT4_PAGE_SELECT   0x16
#define	I347AT4_PSCR_DOWNSHIFT_ENABLE   0x0800
#define	I347AT4_PSCR_DOWNSHIFT_MASK   0x7000
#define	I347AT4_PSCR_DOWNSHIFT_1X   0x0000
#define	I347AT4_PSCR_DOWNSHIFT_2X   0x1000
#define	I347AT4_PSCR_DOWNSHIFT_3X   0x2000
#define	I347AT4_PSCR_DOWNSHIFT_4X   0x3000
#define	I347AT4_PSCR_DOWNSHIFT_5X   0x4000
#define	I347AT4_PSCR_DOWNSHIFT_6X   0x5000
#define	I347AT4_PSCR_DOWNSHIFT_7X   0x6000
#define	I347AT4_PSCR_DOWNSHIFT_8X   0x7000
#define	I347AT4_PCDC_CABLE_LENGTH_UNIT   0x0400 /* 0=cm 1=meters */
#define	M88E1112_VCT_DSP_DISTANCE   0x001A
#define	M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK   0x0E00
#define	M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X   0x0800
#define	E1000_MDIC_DATA_MASK   0x0000FFFF
#define	E1000_MDIC_REG_MASK   0x001F0000
#define	E1000_MDIC_REG_SHIFT   16
#define	E1000_MDIC_PHY_MASK   0x03E00000
#define	E1000_MDIC_PHY_SHIFT   21
#define	E1000_MDIC_OP_WRITE   0x04000000
#define	E1000_MDIC_OP_READ   0x08000000
#define	E1000_MDIC_READY   0x10000000
#define	E1000_MDIC_INT_EN   0x20000000
#define	E1000_MDIC_ERROR   0x40000000
#define	E1000_MDIC_DEST   0x80000000
#define	E1000_THSTAT_PWR_DOWN   0x00000001 /* Power Down Event */
#define	E1000_THSTAT_LINK_THROTTLE   0x00000002 /* Link Speed Throttle Event */
#define	E1000_IPCNFG_EEE_1G_AN   0x00000008 /* EEE Enable 1G AN */
#define	E1000_IPCNFG_EEE_100M_AN   0x00000004 /* EEE Enable 100M AN */
#define	E1000_EEER_TX_LPI_EN   0x00010000 /* EEE Tx LPI Enable */
#define	E1000_EEER_RX_LPI_EN   0x00020000 /* EEE Rx LPI Enable */
#define	E1000_EEER_FRC_AN   0x10000000 /* Enable EEE in loopback */
#define	E1000_EEER_LPI_FC   0x00040000 /* EEE Enable on FC */
#define	E1000_EEE_SU_LPI_CLK_STP   0X00800000 /* EEE LPI Clock Stop */
#define	E1000_GEN_CTL_READY   0x80000000
#define	E1000_GEN_CTL_ADDRESS_SHIFT   8
#define	E1000_GEN_POLL_TIMEOUT   640
#define	E1000_VFTA_ENTRY_SHIFT   5
#define	E1000_VFTA_ENTRY_MASK   0x7F
#define	E1000_VFTA_ENTRY_BIT_SHIFT_MASK   0x1F
#define	E1000_PCIEMISC_LX_DECISION
#define	E1000_RTTBCNRC_RS_ENA   0x80000000
#define	E1000_RTTBCNRC_RF_DEC_MASK   0x00003FFF
#define	E1000_RTTBCNRC_RF_INT_SHIFT   14
#define	E1000_RTTBCNRC_RF_INT_MASK   (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)

Macro Definition Documentation

#define ADVERTISE_1000_FULL   0x0020

Definition at line 254 of file e1000_defines.h.

#define ADVERTISE_1000_HALF   0x0010 /* Not used, just FYI */

Definition at line 253 of file e1000_defines.h.

#define ADVERTISE_100_FULL   0x0008

Definition at line 252 of file e1000_defines.h.

#define ADVERTISE_100_HALF   0x0004

Definition at line 251 of file e1000_defines.h.

#define ADVERTISE_10_FULL   0x0002

Definition at line 250 of file e1000_defines.h.

#define ADVERTISE_10_HALF   0x0001

Definition at line 249 of file e1000_defines.h.

#define AUTO_READ_DONE_TIMEOUT   10

Definition at line 472 of file e1000_defines.h.

#define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX

Definition at line 268 of file e1000_defines.h.

#define COPPER_LINK_UP_LIMIT   10

Definition at line 463 of file e1000_defines.h.

#define CR_1000T_FD_CAPS   0x0200 /* Advertise 1000T FD capability */

Definition at line 565 of file e1000_defines.h.

#define CR_1000T_HD_CAPS   0x0100 /* Advertise 1000T HD capability */

Definition at line 564 of file e1000_defines.h.

#define CR_1000T_MS_ENABLE   0x1000 /* 1=Master/Slave manual config value */

Definition at line 568 of file e1000_defines.h.

#define CR_1000T_MS_VALUE   0x0800 /* 1=Configure PHY as Master */

Definition at line 566 of file e1000_defines.h.

#define E1000_ALL_100_SPEED   (ADVERTISE_100_HALF | ADVERTISE_100_FULL)

Definition at line 262 of file e1000_defines.h.

#define E1000_ALL_10_SPEED   (ADVERTISE_10_HALF | ADVERTISE_10_FULL)

Definition at line 263 of file e1000_defines.h.

#define E1000_ALL_FULL_DUPLEX

Value:

(ADVERTISE_10_FULL  |  ADVERTISE_100_FULL | \
                              ADVERTISE_1000_FULL)

Definition at line 264 of file e1000_defines.h.

#define E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF | ADVERTISE_100_HALF)

Definition at line 266 of file e1000_defines.h.

#define E1000_ALL_NOT_GIG

Value:

(ADVERTISE_10_HALF  |  ADVERTISE_10_FULL | \
                ADVERTISE_100_HALF |  ADVERTISE_100_FULL)

Definition at line 260 of file e1000_defines.h.

#define E1000_ALL_SPEED_DUPLEX

Value:

(ADVERTISE_10_HALF  |  ADVERTISE_10_FULL | \
                ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
                              ADVERTISE_1000_FULL)

Definition at line 257 of file e1000_defines.h.

#define E1000_BLK_PHY_RESET   12

Definition at line 453 of file e1000_defines.h.

#define E1000_COLD_SHIFT   12

Definition at line 336 of file e1000_defines.h.

#define E1000_COLLISION_DISTANCE   63

Definition at line 335 of file e1000_defines.h.

#define E1000_COLLISION_THRESHOLD   15

Definition at line 333 of file e1000_defines.h.

#define E1000_CONNSW_ENRGSRC   0x4

Definition at line 206 of file e1000_defines.h.

#define E1000_CT_SHIFT   4

Definition at line 334 of file e1000_defines.h.

#define E1000_CTRL_ASDE   0x00000020 /* Auto-speed detect enable */

Definition at line 180 of file e1000_defines.h.

#define E1000_CTRL_EXT_DRV_LOAD   0x10000000

Definition at line 59 of file e1000_defines.h.

#define E1000_CTRL_EXT_EIAME   0x01000000

Definition at line 55 of file e1000_defines.h.

#define E1000_CTRL_EXT_IRCA   0x00000001

Definition at line 56 of file e1000_defines.h.

#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX   0x00400000

Definition at line 52 of file e1000_defines.h.

#define E1000_CTRL_EXT_LINK_MODE_GMII   0x00000000

Definition at line 54 of file e1000_defines.h.

#define E1000_CTRL_EXT_LINK_MODE_MASK   0x00C00000

Definition at line 50 of file e1000_defines.h.

#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES   0x00C00000

Definition at line 51 of file e1000_defines.h.

#define E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000

Definition at line 53 of file e1000_defines.h.

#define E1000_CTRL_EXT_PBA_CLR   0x80000000 /* PBA Clear */

Definition at line 64 of file e1000_defines.h.

#define E1000_CTRL_EXT_PFRSTD   0x00004000

Definition at line 49 of file e1000_defines.h.

#define E1000_CTRL_EXT_SDP3_DATA   0x00000080 /* Value of SW Defineable Pin 3 */

Definition at line 47 of file e1000_defines.h.

#define E1000_CTRL_FD   0x00000001 /* Full duplex.0=half; 1=full */

Definition at line 177 of file e1000_defines.h.

#define E1000_CTRL_FRCDPX   0x00001000 /* Force Duplex */

Definition at line 187 of file e1000_defines.h.

#define E1000_CTRL_FRCSPD   0x00000800 /* Force Speed */

Definition at line 186 of file e1000_defines.h.

#define E1000_CTRL_GIO_MASTER_DISABLE   0x00000004 /*Blocks new Master requests */

Definition at line 178 of file e1000_defines.h.

#define E1000_CTRL_I2C_ENA   0x02000000 /* I2C enable */

Definition at line 200 of file e1000_defines.h.

#define E1000_CTRL_ILOS   0x00000080 /* Invert Loss-Of Signal */

Definition at line 182 of file e1000_defines.h.

#define E1000_CTRL_LRST   0x00000008 /* Link reset. 0=normal,1=reset */

Definition at line 179 of file e1000_defines.h.

#define E1000_CTRL_PHY_RST   0x80000000 /* PHY Reset */

Definition at line 198 of file e1000_defines.h.

#define E1000_CTRL_RFCE   0x08000000 /* Receive Flow Control enable */

Definition at line 195 of file e1000_defines.h.

#define E1000_CTRL_RST   0x04000000 /* Global reset */

Definition at line 194 of file e1000_defines.h.

#define E1000_CTRL_SLU   0x00000040 /* Set link up (Force Link) */

Definition at line 181 of file e1000_defines.h.

#define E1000_CTRL_SPD_100   0x00000100 /* Force 100Mb */

Definition at line 184 of file e1000_defines.h.

#define E1000_CTRL_SPD_1000   0x00000200 /* Force 1Gb */

Definition at line 185 of file e1000_defines.h.

#define E1000_CTRL_SPD_SEL   0x00000300 /* Speed Select Mask */

Definition at line 183 of file e1000_defines.h.

#define E1000_CTRL_SWDPIN0   0x00040000 /* SWDPIN 0 value */

Definition at line 191 of file e1000_defines.h.

#define E1000_CTRL_SWDPIN1   0x00080000 /* SWDPIN 1 value */

Definition at line 192 of file e1000_defines.h.

#define E1000_CTRL_SWDPIO0   0x00400000 /* SWDPIN 0 Input or output */

Definition at line 193 of file e1000_defines.h.

#define E1000_CTRL_TFCE   0x10000000 /* Transmit flow control enable */

Definition at line 196 of file e1000_defines.h.

#define E1000_CTRL_VME   0x40000000 /* IEEE VLAN mode enable */

Definition at line 197 of file e1000_defines.h.

#define E1000_DMACR_DC_BMC2OSW_EN   0x00008000

Definition at line 302 of file e1000_defines.h.

#define E1000_DMACR_DMAC_EN   0x80000000 /* Enable DMA Coalescing */

Definition at line 300 of file e1000_defines.h.

#define E1000_DMACR_DMAC_LX_MASK

Value:

0x30000000 /* Lx when no PCIe
                            * transactions */

Definition at line 298 of file e1000_defines.h.

#define E1000_DMACR_DMAC_LX_SHIFT   28

Definition at line 299 of file e1000_defines.h.

#define E1000_DMACR_DMACTHR_MASK

Value:

0x00FF0000 /* DMA Coalescing Receive
                            * Threshold */

Definition at line 296 of file e1000_defines.h.

#define E1000_DMACR_DMACTHR_SHIFT   16

Definition at line 297 of file e1000_defines.h.

#define E1000_DMACR_DMACWT_MASK

Value:

0x00003FFF /* DMA Coalescing
                            * Watchdog Timer */

Definition at line 295 of file e1000_defines.h.

#define E1000_DMCCNT_CCOUNT_MASK

Value:

0x01FFFFFF /* DMA Coal Rcv Traffic
                            * Current Cnt */

Definition at line 311 of file e1000_defines.h.

#define E1000_DMCRTRH_LRPRCW

Value:

0x80000000 /* Rcv packet rate in
                            * current window */

Definition at line 309 of file e1000_defines.h.

#define E1000_DMCRTRH_UTRESH_MASK

Value:

0x0007FFFF /* Receive Traffic Rate
                            * Threshold */

Definition at line 308 of file e1000_defines.h.

#define E1000_DMCTLX_TTLX_MASK   0x00000FFF /* Time to LX request */

Definition at line 306 of file e1000_defines.h.

#define E1000_DMCTXTH_DMCTTHR_MASK

Value:

0x00000FFF /* DMA Coalescing Transmit
                            * Threshold */

Definition at line 304 of file e1000_defines.h.

#define E1000_EECD_ADDR_BITS   0x00000400

Definition at line 596 of file e1000_defines.h.

#define E1000_EECD_AUTO_RD   0x00000200 /* NVM Auto Read done */

Definition at line 598 of file e1000_defines.h.

#define E1000_EECD_CS   0x00000002 /* NVM Chip Select */

Definition at line 589 of file e1000_defines.h.

#define E1000_EECD_DI   0x00000004 /* NVM Data In */

Definition at line 590 of file e1000_defines.h.

#define E1000_EECD_DO   0x00000008 /* NVM Data Out */

Definition at line 591 of file e1000_defines.h.

#define E1000_EECD_FLUDONE_I210   0x04000000 /* Update FLASH done*/

Definition at line 611 of file e1000_defines.h.

#define E1000_EECD_FLUDONE_I210   0x04000000 /* Update FLASH done*/

Definition at line 611 of file e1000_defines.h.

#define E1000_EECD_FLUPD_I210   0x00800000 /* Update FLASH */

Definition at line 610 of file e1000_defines.h.

#define E1000_EECD_FLUPD_I210   0x00800000 /* Update FLASH */

Definition at line 610 of file e1000_defines.h.

#define E1000_EECD_GNT   0x00000080 /* NVM Access Grant */

Definition at line 593 of file e1000_defines.h.

#define E1000_EECD_PRES   0x00000100 /* NVM Present */

Definition at line 594 of file e1000_defines.h.

#define E1000_EECD_REQ   0x00000040 /* NVM Access Request */

Definition at line 592 of file e1000_defines.h.

#define E1000_EECD_SIZE_EX_MASK   0x00007800 /* NVM Size */

Definition at line 599 of file e1000_defines.h.

#define E1000_EECD_SIZE_EX_SHIFT   11

Definition at line 600 of file e1000_defines.h.

#define E1000_EECD_SK   0x00000001 /* NVM Clock */

Definition at line 588 of file e1000_defines.h.

#define E1000_EEE_SU_LPI_CLK_STP   0X00800000 /* EEE LPI Clock Stop */

Definition at line 854 of file e1000_defines.h.

#define E1000_EEER_FRC_AN   0x10000000 /* Enable EEE in loopback */

Definition at line 852 of file e1000_defines.h.

#define E1000_EEER_LPI_FC   0x00040000 /* EEE Enable on FC */

Definition at line 853 of file e1000_defines.h.

#define E1000_EEER_RX_LPI_EN   0x00020000 /* EEE Rx LPI Enable */

Definition at line 851 of file e1000_defines.h.

#define E1000_EEER_TX_LPI_EN   0x00010000 /* EEE Tx LPI Enable */

Definition at line 850 of file e1000_defines.h.

#define E1000_EERD_EEWR_MAX_COUNT   512 /* buffered EEPROM words rw */

Definition at line 613 of file e1000_defines.h.

#define E1000_EERD_EEWR_MAX_COUNT   512 /* buffered EEPROM words rw */

Definition at line 613 of file e1000_defines.h.

#define E1000_EICR_OTHER   0x80000000 /* Interrupt Cause Active */

Definition at line 374 of file e1000_defines.h.

#define E1000_EICR_RX_QUEUE0   0x00000001 /* Rx Queue 0 Interrupt */

Definition at line 366 of file e1000_defines.h.

#define E1000_EICR_RX_QUEUE1   0x00000002 /* Rx Queue 1 Interrupt */

Definition at line 367 of file e1000_defines.h.

#define E1000_EICR_RX_QUEUE2   0x00000004 /* Rx Queue 2 Interrupt */

Definition at line 368 of file e1000_defines.h.

#define E1000_EICR_RX_QUEUE3   0x00000008 /* Rx Queue 3 Interrupt */

Definition at line 369 of file e1000_defines.h.

#define E1000_EICR_TX_QUEUE0   0x00000100 /* Tx Queue 0 Interrupt */

Definition at line 370 of file e1000_defines.h.

#define E1000_EICR_TX_QUEUE1   0x00000200 /* Tx Queue 1 Interrupt */

Definition at line 371 of file e1000_defines.h.

#define E1000_EICR_TX_QUEUE2   0x00000400 /* Tx Queue 2 Interrupt */

Definition at line 372 of file e1000_defines.h.

#define E1000_EICR_TX_QUEUE3   0x00000800 /* Tx Queue 3 Interrupt */

Definition at line 373 of file e1000_defines.h.

#define E1000_EIMS_OTHER   E1000_EICR_OTHER /* Interrupt Cause Active */

Definition at line 406 of file e1000_defines.h.

#define E1000_EITR_CNT_IGNR   0x80000000 /* Don't reset counters on write */

Definition at line 415 of file e1000_defines.h.

#define E1000_ENABLE_SERDES_LOOPBACK   0x0410

Definition at line 218 of file e1000_defines.h.

#define E1000_ERR_CONFIG   3

Definition at line 448 of file e1000_defines.h.

#define E1000_ERR_INVALID_ARGUMENT   16

Definition at line 457 of file e1000_defines.h.

#define E1000_ERR_INVM_VALUE_NOT_FOUND   19

Definition at line 460 of file e1000_defines.h.

#define E1000_ERR_MAC_INIT   5

Definition at line 450 of file e1000_defines.h.

#define E1000_ERR_MASTER_REQUESTS_PENDING   10

Definition at line 452 of file e1000_defines.h.

#define E1000_ERR_MBX   15

Definition at line 456 of file e1000_defines.h.

#define E1000_ERR_NO_SPACE   17

Definition at line 458 of file e1000_defines.h.

#define E1000_ERR_NVM   1

Definition at line 446 of file e1000_defines.h.

#define E1000_ERR_NVM_PBA_SECTION   18

Definition at line 459 of file e1000_defines.h.

#define E1000_ERR_PARAM   4

Definition at line 449 of file e1000_defines.h.

#define E1000_ERR_PHY   2

Definition at line 447 of file e1000_defines.h.

#define E1000_ERR_RESET   9

Definition at line 451 of file e1000_defines.h.

#define E1000_ERR_SWFW_SYNC   13

Definition at line 454 of file e1000_defines.h.

#define E1000_FCRTC_RTH_COAL_MASK

Value:

0x0003FFF0 /* Flow ctrl Rcv Threshold
                            * High val */

Definition at line 313 of file e1000_defines.h.

#define E1000_FCRTC_RTH_COAL_SHIFT   4

Definition at line 314 of file e1000_defines.h.

#define E1000_FCRTL_XONE   0x80000000 /* Enable XON frame transmission */

Definition at line 475 of file e1000_defines.h.

#define E1000_FLUDONE_ATTEMPTS   20000

Definition at line 612 of file e1000_defines.h.

#define E1000_FLUDONE_ATTEMPTS   20000

Definition at line 612 of file e1000_defines.h.

#define E1000_GCR_CAP_VER2   0x00040000

Definition at line 522 of file e1000_defines.h.

#define E1000_GCR_CMPL_TMOUT_10ms   0x00001000

Definition at line 520 of file e1000_defines.h.

#define E1000_GCR_CMPL_TMOUT_MASK   0x0000F000

Definition at line 519 of file e1000_defines.h.

#define E1000_GCR_CMPL_TMOUT_RESEND   0x00010000

Definition at line 521 of file e1000_defines.h.

#define E1000_GEN_CTL_ADDRESS_SHIFT   8

Definition at line 858 of file e1000_defines.h.

#define E1000_GEN_CTL_READY   0x80000000

Definition at line 857 of file e1000_defines.h.

#define E1000_GEN_POLL_TIMEOUT   640

Definition at line 859 of file e1000_defines.h.

#define E1000_GPIE_EIAME   0x40000000

Definition at line 76 of file e1000_defines.h.

#define E1000_GPIE_MSIX_MODE   0x00000010

Definition at line 75 of file e1000_defines.h.

#define E1000_GPIE_NSICR   0x00000001

Definition at line 74 of file e1000_defines.h.

#define E1000_GPIE_PBA   0x80000000

Definition at line 77 of file e1000_defines.h.

#define E1000_I210_FIFO_SEL_BMC2OS_RX   0x01

Definition at line 618 of file e1000_defines.h.

#define E1000_I210_FIFO_SEL_BMC2OS_RX   0x01

Definition at line 618 of file e1000_defines.h.

#define E1000_I210_FIFO_SEL_BMC2OS_TX   0x06

Definition at line 617 of file e1000_defines.h.

#define E1000_I210_FIFO_SEL_BMC2OS_TX   0x06

Definition at line 617 of file e1000_defines.h.

#define E1000_I210_FIFO_SEL_RX   0x00

Definition at line 614 of file e1000_defines.h.

#define E1000_I210_FIFO_SEL_RX   0x00

Definition at line 614 of file e1000_defines.h.

#define E1000_I210_FIFO_SEL_TX_LEGACY   E1000_I210_FIFO_SEL_TX_QAV(0)

Definition at line 616 of file e1000_defines.h.

#define E1000_I210_FIFO_SEL_TX_LEGACY   E1000_I210_FIFO_SEL_TX_QAV(0)

Definition at line 616 of file e1000_defines.h.

#define E1000_I210_FIFO_SEL_TX_QAV

(

_i

)

(0x02 + (_i))

Definition at line 615 of file e1000_defines.h.

#define E1000_I210_FIFO_SEL_TX_QAV

(

_i

)

(0x02 + (_i))

Definition at line 615 of file e1000_defines.h.

#define E1000_I2CCMD_ERROR   0x80000000

Definition at line 70 of file e1000_defines.h.

#define E1000_I2CCMD_OPCODE_READ   0x08000000

Definition at line 67 of file e1000_defines.h.

#define E1000_I2CCMD_OPCODE_WRITE   0x00000000

Definition at line 68 of file e1000_defines.h.

#define E1000_I2CCMD_PHY_ADDR_SHIFT   24

Definition at line 66 of file e1000_defines.h.

#define E1000_I2CCMD_PHY_TIMEOUT   200

Definition at line 72 of file e1000_defines.h.

#define E1000_I2CCMD_READY   0x20000000

Definition at line 69 of file e1000_defines.h.

#define E1000_I2CCMD_REG_ADDR_SHIFT   16

Definition at line 65 of file e1000_defines.h.

#define E1000_ICR_DOUTSYNC   0x10000000 /* NIC DMA out of sync */

Definition at line 363 of file e1000_defines.h.

#define E1000_ICR_DRSTA   0x40000000 /* Device Reset Asserted */

Definition at line 359 of file e1000_defines.h.

#define E1000_ICR_INT_ASSERTED   0x80000000

Definition at line 361 of file e1000_defines.h.

#define E1000_ICR_LSC   0x00000004 /* Link Status Change */

Definition at line 353 of file e1000_defines.h.

#define E1000_ICR_RXDMT0   0x00000010 /* rx desc min. threshold (0) */

Definition at line 355 of file e1000_defines.h.

#define E1000_ICR_RXSEQ   0x00000008 /* rx sequence error */

Definition at line 354 of file e1000_defines.h.

#define E1000_ICR_RXT0   0x00000080 /* rx timer intr (ring 0) */

Definition at line 356 of file e1000_defines.h.

#define E1000_ICR_TS   0x00080000 /* Time Sync Interrupt */

Definition at line 358 of file e1000_defines.h.

#define E1000_ICR_TXDW   0x00000001 /* Transmit desc written back */

Definition at line 352 of file e1000_defines.h.

#define E1000_ICR_VMMB   0x00000100 /* VM MB event */

Definition at line 357 of file e1000_defines.h.

#define E1000_ICS_DRSTA   E1000_ICR_DRSTA /* Device Reset Aserted */

Definition at line 411 of file e1000_defines.h.

#define E1000_ICS_LSC   E1000_ICR_LSC /* Link Status Change */

Definition at line 409 of file e1000_defines.h.

#define E1000_ICS_RXDMT0   E1000_ICR_RXDMT0 /* rx desc min. threshold */

Definition at line 410 of file e1000_defines.h.

#define E1000_IMS_DOUTSYNC   E1000_ICR_DOUTSYNC /* NIC DMA out of sync */

Definition at line 403 of file e1000_defines.h.

#define E1000_IMS_DRSTA   E1000_ICR_DRSTA /* Device Reset Asserted */

Definition at line 402 of file e1000_defines.h.

#define E1000_IMS_LSC   E1000_ICR_LSC /* Link Status Change */

Definition at line 396 of file e1000_defines.h.

#define E1000_IMS_RXDMT0   E1000_ICR_RXDMT0 /* rx desc min. threshold */

Definition at line 400 of file e1000_defines.h.

#define E1000_IMS_RXSEQ   E1000_ICR_RXSEQ /* rx sequence error */

Definition at line 399 of file e1000_defines.h.

#define E1000_IMS_RXT0   E1000_ICR_RXT0 /* rx timer intr */

Definition at line 401 of file e1000_defines.h.

#define E1000_IMS_TS   E1000_ICR_TS /* Time Sync Interrupt */

Definition at line 398 of file e1000_defines.h.

#define E1000_IMS_TXDW   E1000_ICR_TXDW /* Transmit desc written back */

Definition at line 395 of file e1000_defines.h.

#define E1000_IMS_VMMB   E1000_ICR_VMMB /* Mail box activity */

Definition at line 397 of file e1000_defines.h.

#define E1000_IPCNFG_EEE_100M_AN   0x00000004 /* EEE Enable 100M AN */

Definition at line 849 of file e1000_defines.h.

#define E1000_IPCNFG_EEE_1G_AN   0x00000008 /* EEE Enable 1G AN */

Definition at line 848 of file e1000_defines.h.

#define E1000_IVAR_VALID   0x80

Definition at line 73 of file e1000_defines.h.

#define E1000_LEDCTL_LED0_BLINK   0x00000080

Definition at line 272 of file e1000_defines.h.

#define E1000_LEDCTL_LED0_MODE_SHIFT   0

Definition at line 271 of file e1000_defines.h.

#define E1000_LEDCTL_MODE_LED_OFF   0xF

Definition at line 275 of file e1000_defines.h.

#define E1000_LEDCTL_MODE_LED_ON   0xE

Definition at line 274 of file e1000_defines.h.

#define E1000_MANC_ASF_EN   0x00000002 /* ASF Enabled - RO */

Definition at line 114 of file e1000_defines.h.

#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */

Definition at line 118 of file e1000_defines.h.

#define E1000_MANC_EN_BMC2OS   0x10000000 /* OSBMC is Enabled or not */

Definition at line 115 of file e1000_defines.h.

#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000

Definition at line 120 of file e1000_defines.h.

#define E1000_MANC_RCV_TCO_EN   0x00020000 /* Receive TCO Packets Enabled */

Definition at line 117 of file e1000_defines.h.

#define E1000_MANC_SMBUS_EN   0x00000001 /* SMBus Enabled - RO */

Definition at line 113 of file e1000_defines.h.

#define E1000_MAX_SGMII_PHY_REG_ADDR   255

Definition at line 71 of file e1000_defines.h.

#define E1000_MDIC_DATA_MASK   0x0000FFFF

Definition at line 831 of file e1000_defines.h.

#define E1000_MDIC_DEST   0x80000000

Definition at line 841 of file e1000_defines.h.

#define E1000_MDIC_ERROR   0x40000000

Definition at line 840 of file e1000_defines.h.

#define E1000_MDIC_INT_EN   0x20000000

Definition at line 839 of file e1000_defines.h.

#define E1000_MDIC_OP_READ   0x08000000

Definition at line 837 of file e1000_defines.h.

#define E1000_MDIC_OP_WRITE   0x04000000

Definition at line 836 of file e1000_defines.h.

#define E1000_MDIC_PHY_MASK   0x03E00000

Definition at line 834 of file e1000_defines.h.

#define E1000_MDIC_PHY_SHIFT   21

Definition at line 835 of file e1000_defines.h.

#define E1000_MDIC_READY   0x10000000

Definition at line 838 of file e1000_defines.h.

#define E1000_MDIC_REG_MASK   0x001F0000

Definition at line 832 of file e1000_defines.h.

#define E1000_MDIC_REG_SHIFT   16

Definition at line 833 of file e1000_defines.h.

#define E1000_MDICNFG_COM_MDIO   0x40000000 /* MDI shared w/ lan 0 */

Definition at line 514 of file e1000_defines.h.

#define E1000_MDICNFG_EXT_MDIO   0x80000000 /* MDI ext/int destination */

Definition at line 513 of file e1000_defines.h.

#define E1000_MDICNFG_PHY_MASK   0x03E00000

Definition at line 515 of file e1000_defines.h.

#define E1000_MDICNFG_PHY_SHIFT   21

Definition at line 516 of file e1000_defines.h.

#define E1000_MPHY_ADDR_CTL   0x0024 /* mPHY Address Control Register */

Definition at line 525 of file e1000_defines.h.

#define E1000_MPHY_ADDR_CTL_OFFSET_MASK   0xFFFF0000

Definition at line 526 of file e1000_defines.h.

#define E1000_MPHY_DATA   0x0E10 /* mPHY Data Register */

Definition at line 527 of file e1000_defines.h.

#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN   0x10

Definition at line 532 of file e1000_defines.h.

#define E1000_MPHY_PCS_CLK_REG_OFFSET   0x0004 /* mPHY PCS CLK AFE CSR Offset */

Definition at line 530 of file e1000_defines.h.

#define E1000_MRQC_RSS_FIELD_IPV4   0x00020000

Definition at line 106 of file e1000_defines.h.

#define E1000_MRQC_RSS_FIELD_IPV4_TCP   0x00010000

Definition at line 105 of file e1000_defines.h.

#define E1000_MRQC_RSS_FIELD_IPV6   0x00100000

Definition at line 108 of file e1000_defines.h.

#define E1000_MRQC_RSS_FIELD_IPV6_TCP   0x00200000

Definition at line 109 of file e1000_defines.h.

#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX   0x00040000

Definition at line 107 of file e1000_defines.h.

#define E1000_NOT_IMPLEMENTED   14

Definition at line 455 of file e1000_defines.h.

#define E1000_NVM_CFG_DONE_PORT_0   0x040000 /* MNG config cycle done */

Definition at line 649 of file e1000_defines.h.

#define E1000_NVM_CFG_DONE_PORT_1   0x080000 /* ...for second port */

Definition at line 650 of file e1000_defines.h.

#define E1000_NVM_CFG_DONE_PORT_2   0x100000 /* ...for third port */

Definition at line 651 of file e1000_defines.h.

#define E1000_NVM_CFG_DONE_PORT_3   0x200000 /* ...for fourth port */

Definition at line 652 of file e1000_defines.h.

#define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */

Definition at line 597 of file e1000_defines.h.

#define E1000_NVM_POLL_READ   0 /* Flag for polling for read complete */

Definition at line 626 of file e1000_defines.h.

#define E1000_NVM_RW_ADDR_SHIFT   2 /* Shift to the address bits */

Definition at line 625 of file e1000_defines.h.

#define E1000_NVM_RW_REG_DATA   16

Definition at line 622 of file e1000_defines.h.

#define E1000_NVM_RW_REG_DONE   2 /* Offset to READ/WRITE done bit */

Definition at line 623 of file e1000_defines.h.

#define E1000_NVM_RW_REG_START   1 /* Start operation */

Definition at line 624 of file e1000_defines.h.

#define E1000_PBA_34K   0x0022

Definition at line 344 of file e1000_defines.h.

#define E1000_PBA_64K   0x0040 /* 64KB */

Definition at line 345 of file e1000_defines.h.

#define E1000_PBANUM_LENGTH   11

Definition at line 667 of file e1000_defines.h.

#define E1000_PCIEMISC_LX_DECISION   0x00000080 /* Lx power decision */

Definition at line 866 of file e1000_defines.h.

#define E1000_PCIEMISC_LX_DECISION

Value:

0x00000080 /* Lx power decision based
                                                      on DMA coal */

Definition at line 866 of file e1000_defines.h.

#define E1000_PCS_CFG_PCS_EN   8

Definition at line 207 of file e1000_defines.h.

#define E1000_PCS_LCTL_AN_ENABLE   0x10000

Definition at line 215 of file e1000_defines.h.

#define E1000_PCS_LCTL_AN_RESTART   0x20000

Definition at line 216 of file e1000_defines.h.

#define E1000_PCS_LCTL_AN_TIMEOUT   0x40000

Definition at line 217 of file e1000_defines.h.

#define E1000_PCS_LCTL_FDV_FULL   8

Definition at line 211 of file e1000_defines.h.

#define E1000_PCS_LCTL_FLV_LINK_UP   1

Definition at line 208 of file e1000_defines.h.

#define E1000_PCS_LCTL_FORCE_FCTRL   0x80

Definition at line 214 of file e1000_defines.h.

#define E1000_PCS_LCTL_FORCE_LINK   0x20

Definition at line 213 of file e1000_defines.h.

#define E1000_PCS_LCTL_FSD   0x10

Definition at line 212 of file e1000_defines.h.

#define E1000_PCS_LCTL_FSV_100   2

Definition at line 209 of file e1000_defines.h.

#define E1000_PCS_LCTL_FSV_1000   4

Definition at line 210 of file e1000_defines.h.

#define E1000_PCS_LSTS_DUPLEX_FULL   8

Definition at line 223 of file e1000_defines.h.

#define E1000_PCS_LSTS_LINK_OK   1

Definition at line 220 of file e1000_defines.h.

#define E1000_PCS_LSTS_SPEED_100   2

Definition at line 221 of file e1000_defines.h.

#define E1000_PCS_LSTS_SPEED_1000   4

Definition at line 222 of file e1000_defines.h.

#define E1000_PCS_LSTS_SYNK_OK   0x10

Definition at line 224 of file e1000_defines.h.

#define E1000_PSRCTL_BSIZE0_MASK   0x0000007F

Definition at line 158 of file e1000_defines.h.

#define E1000_PSRCTL_BSIZE0_SHIFT   7 /* Shift _right_ 7 */

Definition at line 163 of file e1000_defines.h.

#define E1000_PSRCTL_BSIZE1_MASK   0x00003F00

Definition at line 159 of file e1000_defines.h.

#define E1000_PSRCTL_BSIZE1_SHIFT   2 /* Shift _right_ 2 */

Definition at line 164 of file e1000_defines.h.

#define E1000_PSRCTL_BSIZE2_MASK   0x003F0000

Definition at line 160 of file e1000_defines.h.

#define E1000_PSRCTL_BSIZE2_SHIFT   6 /* Shift _left_ 6 */

Definition at line 165 of file e1000_defines.h.

#define E1000_PSRCTL_BSIZE3_MASK   0x3F000000

Definition at line 161 of file e1000_defines.h.

#define E1000_PSRCTL_BSIZE3_SHIFT   14 /* Shift _left_ 14 */

Definition at line 166 of file e1000_defines.h.

#define E1000_RAH_AV   0x80000000 /* Receive descriptor valid */

Definition at line 438 of file e1000_defines.h.

#define E1000_RAH_MAC_ADDR_LEN   2

Definition at line 440 of file e1000_defines.h.

#define E1000_RAH_POOL_1   0x00040000

Definition at line 442 of file e1000_defines.h.

#define E1000_RAH_POOL_MASK   0x03FC0000

Definition at line 441 of file e1000_defines.h.

#define E1000_RAL_MAC_ADDR_LEN   4

Definition at line 439 of file e1000_defines.h.

#define E1000_RCTL_BAM   0x00008000 /* broadcast enable */

Definition at line 132 of file e1000_defines.h.

#define E1000_RCTL_CFIEN   0x00080000 /* canonical form enable */

Definition at line 136 of file e1000_defines.h.

#define E1000_RCTL_DPF   0x00400000 /* Discard Pause Frames */

Definition at line 137 of file e1000_defines.h.

#define E1000_RCTL_EN   0x00000002 /* enable */

Definition at line 123 of file e1000_defines.h.

#define E1000_RCTL_LBM_MAC   0x00000040 /* MAC loopback mode */

Definition at line 128 of file e1000_defines.h.

#define E1000_RCTL_LBM_TCVR   0x000000C0 /* tcvr loopback mode */

Definition at line 129 of file e1000_defines.h.

#define E1000_RCTL_LPE   0x00000020 /* long packet enable */

Definition at line 127 of file e1000_defines.h.

#define E1000_RCTL_MO_SHIFT   12 /* multicast offset shift */

Definition at line 131 of file e1000_defines.h.

#define E1000_RCTL_MPE   0x00000010 /* multicast promiscuous enab */

Definition at line 126 of file e1000_defines.h.

#define E1000_RCTL_PMCF   0x00800000 /* pass MAC control frames */

Definition at line 138 of file e1000_defines.h.

#define E1000_RCTL_RDMTS_HALF   0x00000000 /* rx desc min threshold size */

Definition at line 130 of file e1000_defines.h.

#define E1000_RCTL_SBP   0x00000004 /* store bad packet */

Definition at line 124 of file e1000_defines.h.

#define E1000_RCTL_SECRC   0x04000000 /* Strip Ethernet CRC */

Definition at line 139 of file e1000_defines.h.

#define E1000_RCTL_SZ_256   0x00030000 /* rx buffer size 256 */

Definition at line 134 of file e1000_defines.h.

#define E1000_RCTL_SZ_512   0x00020000 /* rx buffer size 512 */

Definition at line 133 of file e1000_defines.h.

#define E1000_RCTL_UPE   0x00000008 /* unicast promiscuous enable */

Definition at line 125 of file e1000_defines.h.

#define E1000_RCTL_VFE   0x00040000 /* vlan filter enable */

Definition at line 135 of file e1000_defines.h.

#define E1000_RFCTL_LEF   0x00040000

Definition at line 330 of file e1000_defines.h.

#define E1000_RTTBCNRC_RF_DEC_MASK   0x00003FFF

Definition at line 870 of file e1000_defines.h.

#define E1000_RTTBCNRC_RF_INT_MASK   (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)

Definition at line 872 of file e1000_defines.h.

#define E1000_RTTBCNRC_RF_INT_SHIFT   14

Definition at line 871 of file e1000_defines.h.

#define E1000_RTTBCNRC_RS_ENA   0x80000000

Definition at line 869 of file e1000_defines.h.

#define E1000_RXCSUM_CRCOFL   0x00000800 /* CRC32 offload enable */

Definition at line 326 of file e1000_defines.h.

#define E1000_RXCSUM_IPOFL   0x00000100 /* IPv4 checksum offload */

Definition at line 324 of file e1000_defines.h.

#define E1000_RXCSUM_PCSD   0x00002000 /* packet checksum disabled */

Definition at line 327 of file e1000_defines.h.

#define E1000_RXCSUM_TUOFL   0x00000200 /* TCP / UDP checksum offload */

Definition at line 325 of file e1000_defines.h.

#define E1000_RXD_STAT_DD   0x01 /* Descriptor Done */

Definition at line 80 of file e1000_defines.h.

#define E1000_RXD_STAT_EOP   0x02 /* End of Packet */

Definition at line 81 of file e1000_defines.h.

#define E1000_RXD_STAT_IXSM   0x04 /* Ignore checksum */

Definition at line 82 of file e1000_defines.h.

#define E1000_RXD_STAT_TCPCS   0x20 /* TCP xsum calculated */

Definition at line 85 of file e1000_defines.h.

#define E1000_RXD_STAT_TS   0x10000 /* Pkt was time stamped */

Definition at line 86 of file e1000_defines.h.

#define E1000_RXD_STAT_UDPCS   0x10 /* UDP xsum calculated */

Definition at line 84 of file e1000_defines.h.

#define E1000_RXD_STAT_VP   0x08 /* IEEE VLAN Packet */

Definition at line 83 of file e1000_defines.h.

#define E1000_RXDEXT_ERR_FRAME_ERR_MASK

Value:

( \
    E1000_RXDEXT_STATERR_CE  |            \
    E1000_RXDEXT_STATERR_SE  |            \
    E1000_RXDEXT_STATERR_SEQ |            \
    E1000_RXDEXT_STATERR_CXE |            \
    E1000_RXDEXT_STATERR_RXE)

Definition at line 98 of file e1000_defines.h.

#define E1000_RXDEXT_STATERR_CE   0x01000000

Definition at line 89 of file e1000_defines.h.

#define E1000_RXDEXT_STATERR_CXE   0x10000000

Definition at line 92 of file e1000_defines.h.

#define E1000_RXDEXT_STATERR_IPE   0x40000000

Definition at line 94 of file e1000_defines.h.

#define E1000_RXDEXT_STATERR_LB   0x00040000

Definition at line 88 of file e1000_defines.h.

#define E1000_RXDEXT_STATERR_RXE   0x80000000

Definition at line 95 of file e1000_defines.h.

#define E1000_RXDEXT_STATERR_SE   0x02000000

Definition at line 90 of file e1000_defines.h.

#define E1000_RXDEXT_STATERR_SEQ   0x04000000

Definition at line 91 of file e1000_defines.h.

#define E1000_RXDEXT_STATERR_TCPE   0x20000000

Definition at line 93 of file e1000_defines.h.

#define E1000_RXPBS_CFG_TS_EN   0x80000000

Definition at line 318 of file e1000_defines.h.

#define E1000_SCTL_DISABLE_SERDES_LOOPBACK   0x0400

Definition at line 321 of file e1000_defines.h.

#define E1000_STATUS_FD   0x00000001 /* Full duplex.0=half,1=full */

Definition at line 227 of file e1000_defines.h.

#define E1000_STATUS_FUNC_1   0x00000004 /* Function 1 */

Definition at line 231 of file e1000_defines.h.

#define E1000_STATUS_FUNC_MASK   0x0000000C /* PCI Function Mask */

Definition at line 229 of file e1000_defines.h.

#define E1000_STATUS_FUNC_SHIFT   2

Definition at line 230 of file e1000_defines.h.

#define E1000_STATUS_GIO_MASTER_ENABLE   0x00080000

Definition at line 237 of file e1000_defines.h.

#define E1000_STATUS_LU   0x00000002 /* Link up.0=no,1=link */

Definition at line 228 of file e1000_defines.h.

#define E1000_STATUS_SPEED_100   0x00000040 /* Speed 100Mb/s */

Definition at line 233 of file e1000_defines.h.

#define E1000_STATUS_SPEED_1000   0x00000080 /* Speed 1000Mb/s */

Definition at line 234 of file e1000_defines.h.

#define E1000_STATUS_TXOFF   0x00000010 /* transmission paused */

Definition at line 232 of file e1000_defines.h.

#define E1000_SUCCESS   0

Definition at line 445 of file e1000_defines.h.

#define E1000_SWFW_EEP_SM   0x1

Definition at line 169 of file e1000_defines.h.

#define E1000_SWFW_PHY0_SM   0x2

Definition at line 170 of file e1000_defines.h.

#define E1000_SWFW_PHY1_SM   0x4

Definition at line 171 of file e1000_defines.h.

#define E1000_SWFW_PHY2_SM   0x20

Definition at line 172 of file e1000_defines.h.

#define E1000_SWFW_PHY3_SM   0x40

Definition at line 173 of file e1000_defines.h.

#define E1000_SWSM_SMBI   0x00000001 /* Driver Semaphore bit */

Definition at line 348 of file e1000_defines.h.

#define E1000_SWSM_SWESMBI   0x00000002 /* FW Semaphore bit */

Definition at line 349 of file e1000_defines.h.

#define E1000_TCTL_COLD   0x003ff000 /* collision distance */

Definition at line 291 of file e1000_defines.h.

#define E1000_TCTL_CT   0x00000ff0 /* collision threshold */

Definition at line 290 of file e1000_defines.h.

#define E1000_TCTL_EN   0x00000002 /* enable tx */

Definition at line 288 of file e1000_defines.h.

#define E1000_TCTL_PSP   0x00000008 /* pad short packets */

Definition at line 289 of file e1000_defines.h.

#define E1000_TCTL_RTLC   0x01000000 /* Re-transmit on late collision */

Definition at line 292 of file e1000_defines.h.

#define E1000_THSTAT_LINK_THROTTLE   0x00000002 /* Link Speed Throttle Event */

Definition at line 845 of file e1000_defines.h.

#define E1000_THSTAT_PWR_DOWN   0x00000001 /* Power Down Event */

Definition at line 844 of file e1000_defines.h.

#define E1000_TIMINCA_16NS_SHIFT   24

Definition at line 508 of file e1000_defines.h.

#define E1000_TSICR_TXTS   0x00000002

Definition at line 510 of file e1000_defines.h.

#define E1000_TSIM_TXTS   0x00000002

Definition at line 511 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK   0x000000FF

Definition at line 489 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE   0x01

Definition at line 491 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE   0x03

Definition at line 493 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE   0x02

Definition at line 492 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE   0x04

Definition at line 494 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE   0x00

Definition at line 490 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE   0x0B00

Definition at line 504 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE   0x0100

Definition at line 498 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE   0x0900

Definition at line 502 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE   0x0800

Definition at line 501 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE   0x0D00

Definition at line 506 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK   0x00000F00

Definition at line 496 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE   0x0A00

Definition at line 503 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE   0x0200

Definition at line 499 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE   0x0300

Definition at line 500 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE   0x0C00

Definition at line 505 of file e1000_defines.h.

#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE   0x0000

Definition at line 497 of file e1000_defines.h.

#define E1000_TSYNCRXCTL_ENABLED   0x00000010 /* enable rx timestampping */

Definition at line 487 of file e1000_defines.h.

#define E1000_TSYNCRXCTL_TYPE_ALL   0x08

Definition at line 485 of file e1000_defines.h.

#define E1000_TSYNCRXCTL_TYPE_EVENT_V2   0x0A

Definition at line 486 of file e1000_defines.h.

#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2   0x04

Definition at line 484 of file e1000_defines.h.

#define E1000_TSYNCRXCTL_TYPE_L2_V2   0x00

Definition at line 482 of file e1000_defines.h.

#define E1000_TSYNCRXCTL_TYPE_L4_V1   0x02

Definition at line 483 of file e1000_defines.h.

#define E1000_TSYNCRXCTL_TYPE_MASK   0x0000000E /* rx type mask */

Definition at line 481 of file e1000_defines.h.

#define E1000_TSYNCRXCTL_VALID   0x00000001 /* rx timestamp valid */

Definition at line 480 of file e1000_defines.h.

#define E1000_TSYNCTXCTL_ENABLED   0x00000010 /* enable tx timestampping */

Definition at line 478 of file e1000_defines.h.

#define E1000_TSYNCTXCTL_VALID   0x00000001 /* tx timestamp valid */

Definition at line 477 of file e1000_defines.h.

#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */

Definition at line 283 of file e1000_defines.h.

#define E1000_TXD_CMD_EOP   0x01000000 /* End of Packet */

Definition at line 280 of file e1000_defines.h.

#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */

Definition at line 281 of file e1000_defines.h.

#define E1000_TXD_CMD_RS   0x08000000 /* Report Status */

Definition at line 282 of file e1000_defines.h.

#define E1000_TXD_POPTS_IXSM   0x01 /* Insert IP checksum */

Definition at line 278 of file e1000_defines.h.

#define E1000_TXD_POPTS_TXSM   0x02 /* Insert TCP/UDP checksum */

Definition at line 279 of file e1000_defines.h.

#define E1000_TXD_STAT_DD   0x00000001 /* Descriptor Done */

Definition at line 284 of file e1000_defines.h.

#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK   0x1F

Definition at line 863 of file e1000_defines.h.

#define E1000_VFTA_ENTRY_MASK   0x7F

Definition at line 862 of file e1000_defines.h.

#define E1000_VFTA_ENTRY_SHIFT   5

Definition at line 861 of file e1000_defines.h.

#define E1000_VLAN_FILTER_TBL_SIZE   128 /* VLAN Filter Table (4096 bits) */

Definition at line 428 of file e1000_defines.h.

#define E1000_WUC_PME_EN   0x00000002 /* PME Enable */

Definition at line 37 of file e1000_defines.h.

#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */

Definition at line 44 of file e1000_defines.h.

#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */

Definition at line 42 of file e1000_defines.h.

#define E1000_WUFC_LNKC   0x00000001 /* Link Status Change Wakeup Enable */

Definition at line 40 of file e1000_defines.h.

#define E1000_WUFC_MAG   0x00000002 /* Magic Packet Wakeup Enable */

Definition at line 41 of file e1000_defines.h.

#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */

Definition at line 43 of file e1000_defines.h.

#define ETHERNET_IEEE_VLAN_TYPE   0x8100 /* 802.3ac packet */

Definition at line 339 of file e1000_defines.h.

#define FLOW_CONTROL_ADDRESS_HIGH   0x00000100

Definition at line 423 of file e1000_defines.h.

#define FLOW_CONTROL_ADDRESS_LOW   0x00C28001

Definition at line 422 of file e1000_defines.h.

#define FLOW_CONTROL_TYPE   0x8808

Definition at line 424 of file e1000_defines.h.

#define FULL_DUPLEX   2

Definition at line 246 of file e1000_defines.h.

#define HALF_DUPLEX   1

Definition at line 245 of file e1000_defines.h.

#define I210_I_PHY_ID   0x01410C00

Definition at line 732 of file e1000_defines.h.

#define I347AT4_E_PHY_ID   0x01410DC0

Definition at line 727 of file e1000_defines.h.

#define I347AT4_PAGE_SELECT   0x16

Definition at line 801 of file e1000_defines.h.

#define I347AT4_PCDC   0x15 /* PHY Cable Diagnostics Control */

Definition at line 800 of file e1000_defines.h.

#define I347AT4_PCDC_CABLE_LENGTH_UNIT   0x0400 /* 0=cm 1=meters */

Definition at line 821 of file e1000_defines.h.

#define I347AT4_PCDL   0x10 /* PHY Cable Diagnostics Length */

Definition at line 799 of file e1000_defines.h.

#define I347AT4_PSCR_DOWNSHIFT_1X   0x0000

Definition at line 811 of file e1000_defines.h.

#define I347AT4_PSCR_DOWNSHIFT_2X   0x1000

Definition at line 812 of file e1000_defines.h.

#define I347AT4_PSCR_DOWNSHIFT_3X   0x2000

Definition at line 813 of file e1000_defines.h.

#define I347AT4_PSCR_DOWNSHIFT_4X   0x3000

Definition at line 814 of file e1000_defines.h.

#define I347AT4_PSCR_DOWNSHIFT_5X   0x4000

Definition at line 815 of file e1000_defines.h.

#define I347AT4_PSCR_DOWNSHIFT_6X   0x5000

Definition at line 816 of file e1000_defines.h.

#define I347AT4_PSCR_DOWNSHIFT_7X   0x6000

Definition at line 817 of file e1000_defines.h.

#define I347AT4_PSCR_DOWNSHIFT_8X   0x7000

Definition at line 818 of file e1000_defines.h.

#define I347AT4_PSCR_DOWNSHIFT_ENABLE   0x0800

Definition at line 809 of file e1000_defines.h.

#define I347AT4_PSCR_DOWNSHIFT_MASK   0x7000

Definition at line 810 of file e1000_defines.h.

#define I350_I_PHY_ID   0x015403B0

Definition at line 730 of file e1000_defines.h.

#define I82580_I_PHY_ID   0x015403A0

Definition at line 729 of file e1000_defines.h.

#define ID_LED_DEF1_DEF2   0x1

Definition at line 698 of file e1000_defines.h.

#define ID_LED_DEF1_OFF2   0x3

Definition at line 700 of file e1000_defines.h.

#define ID_LED_DEF1_ON2   0x2

Definition at line 699 of file e1000_defines.h.

#define ID_LED_DEFAULT

Value:

((ID_LED_OFF1_ON2  << 12) | \
                  (ID_LED_OFF1_OFF2 <<  8) | \
                  (ID_LED_DEF1_DEF2 <<  4) | \
                  (ID_LED_DEF1_DEF2))

Definition at line 694 of file e1000_defines.h.

#define ID_LED_OFF1_DEF2   0x7

Definition at line 704 of file e1000_defines.h.

#define ID_LED_OFF1_OFF2   0x9

Definition at line 706 of file e1000_defines.h.

#define ID_LED_OFF1_ON2   0x8

Definition at line 705 of file e1000_defines.h.

#define ID_LED_ON1_DEF2   0x4

Definition at line 701 of file e1000_defines.h.

#define ID_LED_ON1_OFF2   0x6

Definition at line 703 of file e1000_defines.h.

#define ID_LED_ON1_ON2   0x5

Definition at line 702 of file e1000_defines.h.

#define ID_LED_RESERVED_0000   0x0000

Definition at line 692 of file e1000_defines.h.

#define ID_LED_RESERVED_FFFF   0xFFFF

Definition at line 693 of file e1000_defines.h.

#define IGP03E1000_E_PHY_ID   0x02A80390

Definition at line 728 of file e1000_defines.h.

#define IGP_ACTIVITY_LED_ENABLE   0x0300

Definition at line 709 of file e1000_defines.h.

#define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF

Definition at line 708 of file e1000_defines.h.

#define IGP_LED3_MODE   0x07000000

Definition at line 710 of file e1000_defines.h.

#define IMS_ENABLE_MASK

Value:

( \
    E1000_IMS_RXT0   |    \
    E1000_IMS_TXDW   |    \
    E1000_IMS_RXDMT0 |    \
    E1000_IMS_RXSEQ  |    \
    E1000_IMS_LSC    |    \
    E1000_IMS_DOUTSYNC)

Definition at line 386 of file e1000_defines.h.

#define M88_VENDOR   0x0141

Definition at line 731 of file e1000_defines.h.

#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000

Definition at line 788 of file e1000_defines.h.

#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK   0x0C00

Definition at line 787 of file e1000_defines.h.

#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X   0x0100

Definition at line 794 of file e1000_defines.h.

#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK   0x0300

Definition at line 793 of file e1000_defines.h.

#define M88E1000_EPSCR_TX_CLK_25   0x0070 /* 25 MHz TX_CLK */

Definition at line 795 of file e1000_defines.h.

#define M88E1000_EXT_PHY_SPEC_CTRL   0x14 /* Extended PHY Specific Control */

Definition at line 737 of file e1000_defines.h.

#define M88E1000_PHY_GEN_CONTROL   0x1E /* Its meaning depends on reg 29 */

Definition at line 740 of file e1000_defines.h.

#define M88E1000_PHY_PAGE_SELECT   0x1D /* Reg 29 for page number setting */

Definition at line 739 of file e1000_defines.h.

#define M88E1000_PHY_SPEC_CTRL   0x10 /* PHY Specific Control Register */

Definition at line 735 of file e1000_defines.h.

#define M88E1000_PHY_SPEC_STATUS   0x11 /* PHY Specific Status Register */

Definition at line 736 of file e1000_defines.h.

#define M88E1000_PSCR_ASSERT_CRS_ON_TX   0x0800 /* 1=Assert CRS on Transmit */

Definition at line 757 of file e1000_defines.h.

#define M88E1000_PSCR_AUTO_X_1000T   0x0040

Definition at line 749 of file e1000_defines.h.

#define M88E1000_PSCR_AUTO_X_MODE   0x0060

Definition at line 751 of file e1000_defines.h.

#define M88E1000_PSCR_MDI_MANUAL_MODE   0x0000 /* MDI Crossover Mode bits 6:5 */

Definition at line 745 of file e1000_defines.h.

#define M88E1000_PSCR_MDIX_MANUAL_MODE   0x0020 /* Manual MDIX configuration */

Definition at line 747 of file e1000_defines.h.

#define M88E1000_PSCR_POLARITY_REVERSAL   0x0002 /* 1=Polarity Reversal enabled */

Definition at line 743 of file e1000_defines.h.

#define M88E1000_PSSR_1000MBS   0x8000 /* 10=1000Mbs */

Definition at line 772 of file e1000_defines.h.

#define M88E1000_PSSR_CABLE_LENGTH   0x0380

Definition at line 770 of file e1000_defines.h.

#define M88E1000_PSSR_CABLE_LENGTH_SHIFT   7

Definition at line 774 of file e1000_defines.h.

#define M88E1000_PSSR_DOWNSHIFT   0x0020 /* 1=Downshifted */

Definition at line 761 of file e1000_defines.h.

#define M88E1000_PSSR_MDIX   0x0040 /* 1=MDIX; 0=MDI */

Definition at line 762 of file e1000_defines.h.

#define M88E1000_PSSR_REV_POLARITY   0x0002 /* 1=Polarity reversed */

Definition at line 760 of file e1000_defines.h.

#define M88E1000_PSSR_SPEED   0xC000 /* Speed, bits 14:15 */

Definition at line 771 of file e1000_defines.h.

#define M88E1111_I_PHY_ID   0x01410CC0

Definition at line 725 of file e1000_defines.h.

#define M88E1112_E_PHY_ID   0x01410C90

Definition at line 726 of file e1000_defines.h.

#define M88E1112_VCT_DSP_DISTANCE   0x001A

Definition at line 824 of file e1000_defines.h.

#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X   0x0800

Definition at line 828 of file e1000_defines.h.

#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK   0x0E00

Definition at line 827 of file e1000_defines.h.

#define MASTER_DISABLE_TIMEOUT   800

Definition at line 467 of file e1000_defines.h.

#define MAX_JUMBO_FRAME_SIZE   0x3F00

Definition at line 341 of file e1000_defines.h.

#define MAX_PHY_MULTI_PAGE_REG   0xF

Definition at line 718 of file e1000_defines.h.

#define MAX_PHY_REG_ADDRESS   0x1F /* 5 bit address bus (0-0x1F) */

Definition at line 717 of file e1000_defines.h.

#define MII_CR_AUTO_NEG_EN   0x1000 /* Auto Neg Enable */

Definition at line 538 of file e1000_defines.h.

#define MII_CR_FULL_DUPLEX   0x0100 /* FDX =1, half duplex =0 */

Definition at line 535 of file e1000_defines.h.

#define MII_CR_LOOPBACK   0x4000 /* 0 = normal, 1 = loopback */

Definition at line 539 of file e1000_defines.h.

#define MII_CR_POWER_DOWN   0x0800 /* Power down */

Definition at line 537 of file e1000_defines.h.

#define MII_CR_RESET   0x8000 /* 0 = normal, 1 = PHY reset */

Definition at line 540 of file e1000_defines.h.

#define MII_CR_RESTART_AUTO_NEG   0x0200 /* Restart auto negotiation */

Definition at line 536 of file e1000_defines.h.

#define MII_CR_SPEED_10   0x0000

Definition at line 543 of file e1000_defines.h.

#define MII_CR_SPEED_100   0x2000

Definition at line 542 of file e1000_defines.h.

#define MII_CR_SPEED_1000   0x0040

Definition at line 541 of file e1000_defines.h.

#define MII_SR_AUTONEG_COMPLETE   0x0020 /* Auto Neg Complete */

Definition at line 547 of file e1000_defines.h.

#define MII_SR_LINK_STATUS   0x0004 /* Link Status 1 = link */

Definition at line 546 of file e1000_defines.h.

#define NVM_82580_LAN_FUNC_OFFSET

(

a

)

(a ? (0x40 + (0x40 * a)) : 0)

Definition at line 654 of file e1000_defines.h.

#define NVM_A8_OPCODE_SPI   0x08 /* opcode bit-3 = address bit-8 */

Definition at line 684 of file e1000_defines.h.

#define NVM_ALT_MAC_ADDR_PTR   0x0037

Definition at line 634 of file e1000_defines.h.

#define NVM_CHECKSUM_REG   0x003F

Definition at line 635 of file e1000_defines.h.

#define NVM_COMPAT   0x0003

Definition at line 629 of file e1000_defines.h.

#define NVM_COMPATIBILITY_BIT_MASK   0x8000

Definition at line 637 of file e1000_defines.h.

#define NVM_COMPATIBILITY_REG_3   0x0003

Definition at line 636 of file e1000_defines.h.

#define NVM_DEV_ID   0x000D

Definition at line 641 of file e1000_defines.h.

#define NVM_ID_LED_SETTINGS   0x0004 /* SERDES output amplitude */

Definition at line 630 of file e1000_defines.h.

#define NVM_INIT_CONTROL2_REG   0x000F

Definition at line 631 of file e1000_defines.h.

#define NVM_INIT_CONTROL3_PORT_A   0x0024

Definition at line 633 of file e1000_defines.h.

#define NVM_INIT_CONTROL3_PORT_B   0x0014

Definition at line 632 of file e1000_defines.h.

#define NVM_INIT_CTRL_2   0x000F

Definition at line 643 of file e1000_defines.h.

#define NVM_INIT_CTRL_4   0x0013

Definition at line 644 of file e1000_defines.h.

#define NVM_LED_0_2_CFG   0x001F

Definition at line 646 of file e1000_defines.h.

#define NVM_LED_1_CFG   0x001C

Definition at line 645 of file e1000_defines.h.

#define NVM_MAC_ADDR   0x0000

Definition at line 638 of file e1000_defines.h.

#define NVM_MAX_RETRY_SPI   5000 /* Max wait of 5ms, for RDY signal */

Definition at line 681 of file e1000_defines.h.

#define NVM_PBA_OFFSET_0   8

Definition at line 672 of file e1000_defines.h.

#define NVM_PBA_OFFSET_1   9

Definition at line 673 of file e1000_defines.h.

#define NVM_PBA_PTR_GUARD   0xFAFA

Definition at line 675 of file e1000_defines.h.

#define NVM_RDSR_OPCODE_SPI   0x05 /* NVM read Status register */

Definition at line 686 of file e1000_defines.h.

#define NVM_READ_OPCODE_SPI   0x03 /* NVM read opcode */

Definition at line 683 of file e1000_defines.h.

#define NVM_RESERVED_WORD   0xFFFF

Definition at line 674 of file e1000_defines.h.

#define NVM_STATUS_RDY_SPI   0x01

Definition at line 689 of file e1000_defines.h.

#define NVM_SUB_DEV_ID   0x000B

Definition at line 639 of file e1000_defines.h.

#define NVM_SUB_VEN_ID   0x000C

Definition at line 640 of file e1000_defines.h.

#define NVM_SUM   0xBABA

Definition at line 670 of file e1000_defines.h.

#define NVM_VEN_ID   0x000E

Definition at line 642 of file e1000_defines.h.

#define NVM_WORD0F_ASM_DIR   0x2000

Definition at line 662 of file e1000_defines.h.

#define NVM_WORD0F_PAUSE_MASK   0x3000

Definition at line 661 of file e1000_defines.h.

#define NVM_WORD24_COM_MDIO   0x0008 /* MDIO interface shared */

Definition at line 657 of file e1000_defines.h.

#define NVM_WORD24_EXT_MDIO   0x0004 /* MDIO accesses routed external */

Definition at line 658 of file e1000_defines.h.

#define NVM_WORD_SIZE_BASE_SHIFT   6

Definition at line 676 of file e1000_defines.h.

#define NVM_WREN_OPCODE_SPI   0x06 /* NVM set Write Enable latch */

Definition at line 685 of file e1000_defines.h.

#define NVM_WRITE_OPCODE_SPI   0x02 /* NVM write opcode */

Definition at line 682 of file e1000_defines.h.

#define NWAY_AR_100TX_FD_CAPS   0x0100 /* 100TX Full Duplex Capable */

Definition at line 553 of file e1000_defines.h.

#define NWAY_AR_100TX_HD_CAPS   0x0080 /* 100TX Half Duplex Capable */

Definition at line 552 of file e1000_defines.h.

#define NWAY_AR_10T_FD_CAPS   0x0040 /* 10T Full Duplex Capable */

Definition at line 551 of file e1000_defines.h.

#define NWAY_AR_10T_HD_CAPS   0x0020 /* 10T Half Duplex Capable */

Definition at line 550 of file e1000_defines.h.

#define NWAY_AR_ASM_DIR   0x0800 /* Asymmetric Pause Direction bit */

Definition at line 555 of file e1000_defines.h.

#define NWAY_AR_PAUSE   0x0400 /* Pause operation desired */

Definition at line 554 of file e1000_defines.h.

#define NWAY_LPAR_ASM_DIR   0x0800 /* LP Asymmetric Pause Direction bit */

Definition at line 559 of file e1000_defines.h.

#define NWAY_LPAR_PAUSE   0x0400 /* LP Pause operation desired */

Definition at line 558 of file e1000_defines.h.

#define PCIE_DEVICE_CONTROL2   0x28

Definition at line 713 of file e1000_defines.h.

#define PCIE_DEVICE_CONTROL2_16ms   0x0005

Definition at line 714 of file e1000_defines.h.

#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */

Definition at line 584 of file e1000_defines.h.

#define PHY_1000T_STATUS   0x0A /* 1000Base-T Status Reg */

Definition at line 585 of file e1000_defines.h.

#define PHY_AUTO_NEG_LIMIT   45

Definition at line 464 of file e1000_defines.h.

#define PHY_AUTONEG_ADV   0x04 /* Autoneg Advertisement */

Definition at line 582 of file e1000_defines.h.

#define PHY_CFG_TIMEOUT   100

Definition at line 469 of file e1000_defines.h.

#define PHY_CONTROL   0x00 /* Control Register */

Definition at line 578 of file e1000_defines.h.

#define PHY_FORCE_LIMIT   20

Definition at line 465 of file e1000_defines.h.

#define PHY_ID1   0x02 /* Phy Id Reg (word 1) */

Definition at line 580 of file e1000_defines.h.

#define PHY_ID2   0x03 /* Phy Id Reg (word 2) */

Definition at line 581 of file e1000_defines.h.

#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */

Definition at line 583 of file e1000_defines.h.

#define PHY_REVISION_MASK   0xFFFFFFF0

Definition at line 716 of file e1000_defines.h.

#define PHY_STATUS   0x01 /* Status Register */

Definition at line 579 of file e1000_defines.h.

#define REQ_RX_DESCRIPTOR_MULTIPLE   8

Definition at line 33 of file e1000_defines.h.

#define REQ_TX_DESCRIPTOR_MULTIPLE   8

Definition at line 32 of file e1000_defines.h.

#define SPEED_10   10

Definition at line 242 of file e1000_defines.h.

#define SPEED_100   100

Definition at line 243 of file e1000_defines.h.

#define SPEED_1000   1000

Definition at line 244 of file e1000_defines.h.

#define SR_1000T_LOCAL_RX_STATUS   0x2000 /* Local receiver OK */

Definition at line 573 of file e1000_defines.h.

#define SR_1000T_REMOTE_RX_STATUS   0x1000 /* Remote receiver OK */

Definition at line 572 of file e1000_defines.h.

#define VLAN_TAG_SIZE   4 /* 802.3ac tag (not DMA'd) */

Definition at line 427 of file e1000_defines.h.