Data Structures
struct	ehci_caps

struct	ehci_regs

struct	ehci_dbg_port

Macros
#define	HC_LENGTH(ehci, p)

#define	HC_VERSION(ehci, p)

#define	HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */

#define	HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */

#define	HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */

#define	HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */

#define	HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */

#define	HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */

#define	HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */

#define	HCC_32FRAME_PERIODIC_LIST(p) ((p)&(1 << 19))

#define	HCC_PER_PORT_CHANGE_EVENT(p) ((p)&(1 << 18))

#define	HCC_LPM(p) ((p)&(1 << 17))

#define	HCC_HW_PREFETCH(p) ((p)&(1 << 16))

#define	HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */

#define	HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */

#define	HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */

#define	HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */

#define	HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/

#define	HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */

#define	CMD_HIRD (0xf<<24) /* host initiated resume duration */

#define	CMD_PPCEE (1<<15) /* per port change event enable */

#define	CMD_FSP (1<<14) /* fully synchronized prefetch */

#define	CMD_ASPE (1<<13) /* async schedule prefetch enable */

#define	CMD_PSPE (1<<12) /* periodic schedule prefetch enable */

#define	CMD_PARK (1<<11) /* enable "park" on async qh */

#define	CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */

#define	CMD_LRESET (1<<7) /* partial reset (no ports, etc) */

#define	CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */

#define	CMD_ASE (1<<5) /* async schedule enable */

#define	CMD_PSE (1<<4) /* periodic schedule enable */

#define	CMD_RESET (1<<1) /* reset HC not bus */

#define	CMD_RUN (1<<0) /* start/stop HC */

#define	STS_PPCE_MASK (0xff<<16) /* Per-Port change event 1-16 */

#define	STS_ASS (1<<15) /* Async Schedule Status */

#define	STS_PSS (1<<14) /* Periodic Schedule Status */

#define	STS_RECL (1<<13) /* Reclamation */

#define	STS_HALT (1<<12) /* Not running (any reason) */

#define	STS_IAA (1<<5) /* Interrupted on async advance */

#define	STS_FATAL (1<<4) /* such as some PCI access errors */

#define	STS_FLR (1<<3) /* frame list rolled over */

#define	STS_PCD (1<<2) /* port change detect */

#define	STS_ERR (1<<1) /* "error" completion (overflow, ...) */

#define	STS_INT (1<<0) /* "normal" completion (short, ...) */

#define	TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */

#define	FLAG_CF (1<<0) /* true: we'll support "high speed" */

#define	PORTSC_SUSPEND_STS_ACK 0

#define	PORTSC_SUSPEND_STS_NYET 1

#define	PORTSC_SUSPEND_STS_STALL 2

#define	PORTSC_SUSPEND_STS_ERR 3

#define	PORT_DEV_ADDR (0x7f<<25) /* device address */

#define	PORT_SSTS (0x3<<23) /* suspend status */

#define	PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */

#define	PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */

#define	PORT_WKCONN_E (1<<20) /* wake on connect (enable) */

#define	PORT_TEST(x) (((x)&0xf)<<16) /* Port Test Control */

#define	PORT_TEST_PKT PORT_TEST(0x4) /* Port Test Control - packet test */

#define	PORT_TEST_FORCE PORT_TEST(0x5) /* Port Test Control - force enable */

#define	PORT_LED_OFF (0<<14)

#define	PORT_LED_AMBER (1<<14)

#define	PORT_LED_GREEN (2<<14)

#define	PORT_LED_MASK (3<<14)

#define	PORT_OWNER (1<<13) /* true: companion hc owns this port */

#define	PORT_POWER (1<<12) /* true: has power (see PPC) */

#define	PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */

#define	PORT_LPM (1<<9) /* LPM transaction */

#define	PORT_RESET (1<<8) /* reset port */

#define	PORT_SUSPEND (1<<7) /* suspend port */

#define	PORT_RESUME (1<<6) /* resume it */

#define	PORT_OCC (1<<5) /* over current change */

#define	PORT_OC (1<<4) /* over current active */

#define	PORT_PEC (1<<3) /* port enable change */

#define	PORT_PE (1<<2) /* port enable */

#define	PORT_CSC (1<<1) /* connect status change */

#define	PORT_CONNECT (1<<0) /* device connected */

#define	PORT_RWC_BITS (PORT_CSC \| PORT_PEC \| PORT_OCC)

#define	USBMODE_SDIS (1<<3) /* Stream disable */

#define	USBMODE_BE (1<<2) /* BE/LE endianness select */

#define	USBMODE_CM_HC (3<<0) /* host controller mode */

#define	USBMODE_CM_IDLE (0<<0) /* idle state */

#define	HOSTPC_PHCD (1<<22) /* Phy clock disable */

#define	HOSTPC_PSPD (3<<25) /* Port speed detection */

#define	USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */

#define	USBMODE_EX_HC (3<<0) /* host controller mode */

#define	DBGP_OWNER (1<<30)

#define	DBGP_ENABLED (1<<28)

#define	DBGP_DONE (1<<16)

#define	DBGP_INUSE (1<<10)

#define	DBGP_ERRCODE(x) (((x)>>7)&0x07)

#define	DBGP_ERR_BAD 1

#define	DBGP_ERR_SIGNAL 2

#define	DBGP_ERROR (1<<6)

#define	DBGP_GO (1<<5)

#define	DBGP_OUT (1<<4)

#define	DBGP_LEN(x) (((x)>>0)&0x0f)

#define	DBGP_PID_GET(x) (((x)>>16)&0xff)

#define	DBGP_PID_SET(data, tok) (((data)<<8)\|(tok))

#define	DBGP_EPADDR(dev, ep) (((dev)<<8)\|(ep))

Macro Definition Documentation

#define CMD_ASE (1<<5) /* async schedule enable */

Definition at line 80 of file ehci_def.h.

#define CMD_ASPE (1<<13) /* async schedule prefetch enable */

Definition at line 73 of file ehci_def.h.

#define CMD_FSP (1<<14) /* fully synchronized prefetch */

Definition at line 72 of file ehci_def.h.

#define CMD_HIRD (0xf<<24) /* host initiated resume duration */

Definition at line 70 of file ehci_def.h.

#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */

Definition at line 79 of file ehci_def.h.

#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */

Definition at line 78 of file ehci_def.h.

#define CMD_PARK (1<<11) /* enable "park" on async qh */

Definition at line 76 of file ehci_def.h.

#define CMD_PARK_CNT ( c ) (((c)>>8)&3) /* how many transfers to park for */

Definition at line 77 of file ehci_def.h.

#define CMD_PPCEE (1<<15) /* per port change event enable */

Definition at line 71 of file ehci_def.h.

#define CMD_PSE (1<<4) /* periodic schedule enable */

Definition at line 81 of file ehci_def.h.

#define CMD_PSPE (1<<12) /* periodic schedule prefetch enable */

Definition at line 74 of file ehci_def.h.

#define CMD_RESET (1<<1) /* reset HC not bus */

Definition at line 83 of file ehci_def.h.

#define CMD_RUN (1<<0) /* start/stop HC */

Definition at line 84 of file ehci_def.h.

#define DBGP_DONE (1<<16)

Definition at line 200 of file ehci_def.h.

#define DBGP_ENABLED (1<<28)

Definition at line 199 of file ehci_def.h.

#define DBGP_EPADDR	(	dev,
		ep
	)	(((dev)<<8)\|(ep))

Definition at line 215 of file ehci_def.h.

#define DBGP_ERR_BAD 1

Definition at line 203 of file ehci_def.h.

#define DBGP_ERR_SIGNAL 2

Definition at line 204 of file ehci_def.h.

#define DBGP_ERRCODE ( x ) (((x)>>7)&0x07)

Definition at line 202 of file ehci_def.h.

#define DBGP_ERROR (1<<6)

Definition at line 205 of file ehci_def.h.

#define DBGP_GO (1<<5)

Definition at line 206 of file ehci_def.h.

#define DBGP_INUSE (1<<10)

Definition at line 201 of file ehci_def.h.

#define DBGP_LEN ( x ) (((x)>>0)&0x0f)

Definition at line 208 of file ehci_def.h.

#define DBGP_OUT (1<<4)

Definition at line 207 of file ehci_def.h.

#define DBGP_OWNER (1<<30)

Definition at line 198 of file ehci_def.h.

#define DBGP_PID_GET ( x ) (((x)>>16)&0xff)

Definition at line 210 of file ehci_def.h.

#define DBGP_PID_SET	(	data,
		tok
	)	(((data)<<8)\|(tok))

Definition at line 211 of file ehci_def.h.

#define FLAG_CF (1<<0) /* true: we'll support "high speed" */

Definition at line 124 of file ehci_def.h.

#define HC_LENGTH	(	ehci,
		p
	)

Value:

(0x00ff&((p) >> /* bits 7:0 / offset 00h */ \

(ehci_big_endian_capbase(ehci) ? 24 : 0)))

Definition at line 33 of file ehci_def.h.

#define HC_VERSION	(	ehci,
		p
	)

Value:

(0xffff&((p) >> /* bits 31:16 / offset 02h */ \

(ehci_big_endian_capbase(ehci) ? 0 : 16)))

Definition at line 35 of file ehci_def.h.

#define HCC_32FRAME_PERIODIC_LIST ( p ) ((p)&(1 << 19))

Definition at line 48 of file ehci_def.h.

#define HCC_64BIT_ADDR ( p ) ((p)&(1)) /* true: can use 64-bit addr */

Definition at line 58 of file ehci_def.h.

#define HCC_CANPARK ( p ) ((p)&(1 << 2)) /* true: can park on async qh */

Definition at line 56 of file ehci_def.h.

#define HCC_EXT_CAPS ( p ) (((p)>>8)&0xff) /* for pci extended caps */

Definition at line 53 of file ehci_def.h.

#define HCC_HW_PREFETCH ( p ) ((p)&(1 << 16))

Definition at line 51 of file ehci_def.h.

#define HCC_ISOC_CACHE ( p ) ((p)&(1 << 7)) /* true: can cache isoc frame */

Definition at line 54 of file ehci_def.h.

#define HCC_ISOC_THRES ( p ) (((p)>>4)&0x7) /* bits 6:4, uframes cached */

Definition at line 55 of file ehci_def.h.

#define HCC_LPM ( p ) ((p)&(1 << 17))

Definition at line 50 of file ehci_def.h.

#define HCC_PER_PORT_CHANGE_EVENT ( p ) ((p)&(1 << 18))

Definition at line 49 of file ehci_def.h.

#define HCC_PGM_FRAMELISTLEN ( p ) ((p)&(1 << 1)) /* true: periodic_size changes*/

Definition at line 57 of file ehci_def.h.

#define HCS_DEBUG_PORT ( p ) (((p)>>20)&0xf) /* bits 23:20, debug port? */

Definition at line 38 of file ehci_def.h.

#define HCS_INDICATOR ( p ) ((p)&(1 << 16)) /* true: has port indicators */

Definition at line 39 of file ehci_def.h.

#define HCS_N_CC ( p ) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */

Definition at line 40 of file ehci_def.h.

#define HCS_N_PCC ( p ) (((p)>>8)&0xf) /* bits 11:8, ports per CC */

Definition at line 41 of file ehci_def.h.

#define HCS_N_PORTS ( p ) (((p)>>0)&0xf) /* bits 3:0, ports on HC */

Definition at line 44 of file ehci_def.h.

#define HCS_PORTROUTED ( p ) ((p)&(1 << 7)) /* true: port routing */

Definition at line 42 of file ehci_def.h.

#define HCS_PPC ( p ) ((p)&(1 << 4)) /* true: port power control */

Definition at line 43 of file ehci_def.h.

#define HOSTPC_PHCD (1<<22) /* Phy clock disable */

Definition at line 182 of file ehci_def.h.

#define HOSTPC_PSPD (3<<25) /* Port speed detection */

Definition at line 183 of file ehci_def.h.

#define PORT_CONNECT (1<<0) /* device connected */

Definition at line 162 of file ehci_def.h.

#define PORT_CSC (1<<1) /* connect status change */

Definition at line 161 of file ehci_def.h.

#define PORT_DEV_ADDR (0x7f<<25) /* device address */

Definition at line 134 of file ehci_def.h.

#define PORT_LED_AMBER (1<<14)

Definition at line 145 of file ehci_def.h.

#define PORT_LED_GREEN (2<<14)

Definition at line 146 of file ehci_def.h.

#define PORT_LED_MASK (3<<14)

Definition at line 147 of file ehci_def.h.

#define PORT_LED_OFF (0<<14)

Definition at line 144 of file ehci_def.h.

#define PORT_LPM (1<<9) /* LPM transaction */

Definition at line 153 of file ehci_def.h.

#define PORT_OC (1<<4) /* over current active */

Definition at line 158 of file ehci_def.h.

#define PORT_OCC (1<<5) /* over current change */

Definition at line 157 of file ehci_def.h.

#define PORT_OWNER (1<<13) /* true: companion hc owns this port */

Definition at line 148 of file ehci_def.h.

#define PORT_PE (1<<2) /* port enable */

Definition at line 160 of file ehci_def.h.

#define PORT_PEC (1<<3) /* port enable change */

Definition at line 159 of file ehci_def.h.

#define PORT_POWER (1<<12) /* true: has power (see PPC) */

Definition at line 149 of file ehci_def.h.

#define PORT_RESET (1<<8) /* reset port */

Definition at line 154 of file ehci_def.h.

#define PORT_RESUME (1<<6) /* resume it */

Definition at line 156 of file ehci_def.h.

#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)

Definition at line 163 of file ehci_def.h.

#define PORT_SSTS (0x3<<23) /* suspend status */

Definition at line 135 of file ehci_def.h.

#define PORT_SUSPEND (1<<7) /* suspend port */

Definition at line 155 of file ehci_def.h.

#define PORT_TEST ( x ) (((x)&0xf)<<16) /* Port Test Control */

Definition at line 141 of file ehci_def.h.

#define PORT_TEST_FORCE PORT_TEST(0x5) /* Port Test Control - force enable */

Definition at line 143 of file ehci_def.h.

#define PORT_TEST_PKT PORT_TEST(0x4) /* Port Test Control - packet test */

Definition at line 142 of file ehci_def.h.

#define PORT_USB11 ( x ) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */

Definition at line 150 of file ehci_def.h.

#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */

Definition at line 139 of file ehci_def.h.

#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */

Definition at line 138 of file ehci_def.h.

#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */

Definition at line 137 of file ehci_def.h.

#define PORTSC_SUSPEND_STS_ACK 0

Definition at line 129 of file ehci_def.h.

#define PORTSC_SUSPEND_STS_ERR 3

Definition at line 132 of file ehci_def.h.

#define PORTSC_SUSPEND_STS_NYET 1

Definition at line 130 of file ehci_def.h.

#define PORTSC_SUSPEND_STS_STALL 2

Definition at line 131 of file ehci_def.h.

#define STS_ASS (1<<15) /* Async Schedule Status */

Definition at line 89 of file ehci_def.h.

#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */

Definition at line 99 of file ehci_def.h.

#define STS_FATAL (1<<4) /* such as some PCI access errors */

Definition at line 96 of file ehci_def.h.

#define STS_FLR (1<<3) /* frame list rolled over */

Definition at line 97 of file ehci_def.h.

#define STS_HALT (1<<12) /* Not running (any reason) */

Definition at line 92 of file ehci_def.h.

#define STS_IAA (1<<5) /* Interrupted on async advance */

Definition at line 95 of file ehci_def.h.

#define STS_INT (1<<0) /* "normal" completion (short, ...) */

Definition at line 100 of file ehci_def.h.

#define STS_PCD (1<<2) /* port change detect */

Definition at line 98 of file ehci_def.h.

#define STS_PPCE_MASK (0xff<<16) /* Per-Port change event 1-16 */

Definition at line 88 of file ehci_def.h.

#define STS_PSS (1<<14) /* Periodic Schedule Status */

Definition at line 90 of file ehci_def.h.

#define STS_RECL (1<<13) /* Reclamation */

Definition at line 91 of file ehci_def.h.

#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */

Definition at line 118 of file ehci_def.h.

#define USBMODE_BE (1<<2) /* BE/LE endianness select */

Definition at line 170 of file ehci_def.h.

#define USBMODE_CM_HC (3<<0) /* host controller mode */

Definition at line 171 of file ehci_def.h.

#define USBMODE_CM_IDLE (0<<0) /* idle state */

Definition at line 172 of file ehci_def.h.

#define USBMODE_EX_HC (3<<0) /* host controller mode */

Definition at line 190 of file ehci_def.h.

#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */

Definition at line 189 of file ehci_def.h.

#define USBMODE_SDIS (1<<3) /* Stream disable */

Definition at line 169 of file ehci_def.h.

Data Structures

Macros

Macro Definition Documentation