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#define | CACHE_SLINE_SIZE 128 /* Secondary cache line size on SN0 */ |
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#define | MAX_REGIONS 64 |
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#define | MD_PAGE_SIZE 4096 /* Page size in bytes */ |
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#define | MD_PAGE_NUM_SHFT 12 /* Address to page number shift */ |
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#define | MD_BASE 0x200000 |
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#define | MD_BASE_PERF 0x210000 |
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#define | MD_BASE_JUNK 0x220000 |
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#define | MD_IO_PROTECT 0x200000 /* MD and core register protection */ |
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#define | MD_IO_PROT_OVRRD 0x200008 /* Clear my bit in MD_IO_PROTECT */ |
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#define | MD_HSPEC_PROTECT 0x200010 /* BDDIR, LBOOT, RBOOT protection */ |
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#define | MD_MEMORY_CONFIG 0x200018 /* Memory/Directory DIMM control */ |
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#define | MD_REFRESH_CONTROL 0x200020 /* Memory/Directory refresh ctrl */ |
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#define | MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */ |
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#define | MD_MIG_DIFF_THRESH 0x200030 /* Page migr. count diff thresh. */ |
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#define | MD_MIG_VALUE_THRESH 0x200038 /* Page migr. count abs. thresh. */ |
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#define | MD_MIG_CANDIDATE 0x200040 /* Latest page migration candidate */ |
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#define | MD_MIG_CANDIDATE_CLR 0x200048 /* Clear page migration candidate */ |
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#define | MD_DIR_ERROR 0x200050 /* Directory DIMM error */ |
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#define | MD_DIR_ERROR_CLR 0x200058 /* Directory DIMM error clear */ |
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#define | MD_PROTOCOL_ERROR 0x200060 /* Directory protocol error */ |
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#define | MD_PROTOCOL_ERROR_CLR 0x200068 /* Directory protocol error clear */ |
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#define | MD_MEM_ERROR 0x200070 /* Memory DIMM error */ |
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#define | MD_MEM_ERROR_CLR 0x200078 /* Memory DIMM error clear */ |
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#define | MD_MISC_ERROR 0x200080 /* Miscellaneous MD error */ |
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#define | MD_MISC_ERROR_CLR 0x200088 /* Miscellaneous MD error clear */ |
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#define | MD_MEM_DIMM_INIT 0x200090 /* Memory DIMM mode initization. */ |
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#define | MD_DIR_DIMM_INIT 0x200098 /* Directory DIMM mode init. */ |
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#define | MD_MOQ_SIZE 0x2000a0 /* MD outgoing queue size */ |
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#define | MD_MLAN_CTL 0x2000a8 /* NIC (Microlan) control register */ |
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#define | MD_PERF_SEL 0x210000 /* Select perf monitor events */ |
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#define | MD_PERF_CNT0 0x210010 /* Performance counter 0 */ |
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#define | MD_PERF_CNT1 0x210018 /* Performance counter 1 */ |
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#define | MD_PERF_CNT2 0x210020 /* Performance counter 2 */ |
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#define | MD_PERF_CNT3 0x210028 /* Performance counter 3 */ |
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#define | MD_PERF_CNT4 0x210030 /* Performance counter 4 */ |
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#define | MD_PERF_CNT5 0x210038 /* Performance counter 5 */ |
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#define | MD_UREG0_0 0x220000 /* uController/UART 0 register */ |
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#define | MD_UREG0_1 0x220008 /* uController/UART 0 register */ |
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#define | MD_UREG0_2 0x220010 /* uController/UART 0 register */ |
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#define | MD_UREG0_3 0x220018 /* uController/UART 0 register */ |
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#define | MD_UREG0_4 0x220020 /* uController/UART 0 register */ |
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#define | MD_UREG0_5 0x220028 /* uController/UART 0 register */ |
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#define | MD_UREG0_6 0x220030 /* uController/UART 0 register */ |
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#define | MD_UREG0_7 0x220038 /* uController/UART 0 register */ |
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#define | MD_SLOTID_USTAT 0x220048 /* Hub slot ID & UART/uCtlr status */ |
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#define | MD_LED0 0x220050 /* Eight-bit LED for CPU A */ |
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#define | MD_LED1 0x220058 /* Eight-bit LED for CPU B */ |
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#define | MD_UREG1_0 0x220080 /* uController/UART 1 register */ |
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#define | MD_UREG1_1 0x220088 /* uController/UART 1 register */ |
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#define | MD_UREG1_2 0x220090 /* uController/UART 1 register */ |
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#define | MD_UREG1_3 0x220098 /* uController/UART 1 register */ |
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#define | MD_UREG1_4 0x2200a0 /* uController/UART 1 register */ |
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#define | MD_UREG1_5 0x2200a8 /* uController/UART 1 register */ |
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#define | MD_UREG1_6 0x2200b0 /* uController/UART 1 register */ |
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#define | MD_UREG1_7 0x2200b8 /* uController/UART 1 register */ |
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#define | MD_UREG1_8 0x2200c0 /* uController/UART 1 register */ |
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#define | MD_UREG1_9 0x2200c8 /* uController/UART 1 register */ |
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#define | MD_UREG1_10 0x2200d0 /* uController/UART 1 register */ |
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#define | MD_UREG1_11 0x2200d8 /* uController/UART 1 register */ |
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#define | MD_UREG1_12 0x2200e0 /* uController/UART 1 register */ |
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#define | MD_UREG1_13 0x2200e8 /* uController/UART 1 register */ |
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#define | MD_UREG1_14 0x2200f0 /* uController/UART 1 register */ |
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#define | MD_UREG1_15 0x2200f8 /* uController/UART 1 register */ |
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#define | MD_MEM_BANKS 8 /* 8 banks of memory max in M mode */ |
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#define | MD_SIZE_EMPTY 0 /* Valid in MEMORY_CONFIG */ |
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#define | MD_SIZE_8MB 1 |
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#define | MD_SIZE_16MB 2 |
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#define | MD_SIZE_32MB 3 /* Broken in Hub 1 */ |
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#define | MD_SIZE_64MB 4 /* Valid in MEMORY_CONFIG */ |
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#define | MD_SIZE_128MB 5 /* Valid in MEMORY_CONFIG */ |
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#define | MD_SIZE_256MB 6 |
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#define | MD_SIZE_512MB 7 /* Valid in MEMORY_CONFIG */ |
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#define | MD_SIZE_1GB 8 |
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#define | MD_SIZE_2GB 9 |
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#define | MD_SIZE_4GB 10 |
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#define | MD_SIZE_BYTES(size) ((size) == 0 ? 0 : 0x400000L << (size)) |
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#define | MD_SIZE_MBYTES(size) ((size) == 0 ? 0 : 4 << (size)) |
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#define | MMC_FPROM_CYC_SHFT 49 /* Have to use UINT64_CAST, instead */ |
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#define | MMC_FPROM_CYC_MASK (UINT64_CAST 31 << 49) /* of 'L' suffix, */ |
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#define | MMC_FPROM_WR_SHFT 44 /* for assembler */ |
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#define | MMC_FPROM_WR_MASK (UINT64_CAST 31 << 44) |
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#define | MMC_UCTLR_CYC_SHFT 39 |
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#define | MMC_UCTLR_CYC_MASK (UINT64_CAST 31 << 39) |
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#define | MMC_UCTLR_WR_SHFT 34 |
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#define | MMC_UCTLR_WR_MASK (UINT64_CAST 31 << 34) |
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#define | MMC_DIMM0_SEL_SHFT 32 |
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#define | MMC_DIMM0_SEL_MASK (UINT64_CAST 3 << 32) |
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#define | MMC_IO_PROT_EN_SHFT 31 |
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#define | MMC_IO_PROT_EN_MASK (UINT64_CAST 1 << 31) |
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#define | MMC_IO_PROT (UINT64_CAST 1 << 31) |
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#define | MMC_ARB_MLSS_SHFT 30 |
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#define | MMC_ARB_MLSS_MASK (UINT64_CAST 1 << 30) |
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#define | MMC_ARB_MLSS (UINT64_CAST 1 << 30) |
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#define | MMC_IGNORE_ECC_SHFT 29 |
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#define | MMC_IGNORE_ECC_MASK (UINT64_CAST 1 << 29) |
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#define | MMC_IGNORE_ECC (UINT64_CAST 1 << 29) |
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#define | MMC_DIR_PREMIUM_SHFT 28 |
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#define | MMC_DIR_PREMIUM_MASK (UINT64_CAST 1 << 28) |
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#define | MMC_DIR_PREMIUM (UINT64_CAST 1 << 28) |
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#define | MMC_REPLY_GUAR_SHFT 24 |
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#define | MMC_REPLY_GUAR_MASK (UINT64_CAST 15 << 24) |
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#define | MMC_BANK_SHFT(_b) ((_b) * 3) |
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#define | MMC_BANK_MASK(_b) (UINT64_CAST 7 << MMC_BANK_SHFT(_b)) |
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#define | MMC_BANK_ALL_MASK 0xffffff |
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#define | MMC_RESET_DEFAULTS |
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#define | MRC_ENABLE_SHFT 63 |
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#define | MRC_ENABLE_MASK (UINT64_CAST 1 << 63) |
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#define | MRC_ENABLE (UINT64_CAST 1 << 63) |
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#define | MRC_COUNTER_SHFT 12 |
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#define | MRC_COUNTER_MASK (UINT64_CAST 0xfff << 12) |
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#define | MRC_CNT_THRESH_MASK 0xfff |
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#define | MRC_RESET_DEFAULTS (UINT64_CAST 0x400) |
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#define | MDI_SELECT_SHFT 32 |
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#define | MDI_SELECT_MASK (UINT64_CAST 0x0f << 32) |
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#define | MDI_DIMM_MODE_MASK (UINT64_CAST 0xfff) |
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#define | MMS_RP_SIZE_SHFT 8 |
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#define | MMS_RP_SIZE_MASK (UINT64_CAST 0x3f << 8) |
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#define | MMS_RQ_SIZE_SHFT 0 |
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#define | MMS_RQ_SIZE_MASK (UINT64_CAST 0x1f) |
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#define | MMS_RESET_DEFAULTS (0x32 << 8 | 0x12) |
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#define | MFC_VALID_SHFT 63 |
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#define | MFC_VALID_MASK (UINT64_CAST 1 << 63) |
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#define | MFC_VALID (UINT64_CAST 1 << 63) |
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#define | MFC_ADDR_SHFT 6 |
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#define | MFC_ADDR_MASK (UINT64_CAST 0x3ffffff) |
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#define | MLAN_PHI1_SHFT 27 |
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#define | MLAN_PHI1_MASK (UINT64_CAST 0x7f << 27) |
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#define | MLAN_PHI0_SHFT 20 |
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#define | MLAN_PHI0_MASK (UINT64_CAST 0x7f << 27) |
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#define | MLAN_PULSE_SHFT 10 |
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#define | MLAN_PULSE_MASK (UINT64_CAST 0x3ff << 10) |
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#define | MLAN_SAMPLE_SHFT 2 |
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#define | MLAN_SAMPLE_MASK (UINT64_CAST 0xff << 2) |
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#define | MLAN_DONE_SHFT 1 |
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#define | MLAN_DONE_MASK 2 |
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#define | MLAN_DONE (UINT64_CAST 0x02) |
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#define | MLAN_RD_DATA (UINT64_CAST 0x01) |
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#define | MLAN_RESET_DEFAULTS |
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#define | MSU_CORECLK_TST_SHFT 7 /* You don't wanna know */ |
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#define | MSU_CORECLK_TST_MASK (UINT64_CAST 1 << 7) |
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#define | MSU_CORECLK_TST (UINT64_CAST 1 << 7) |
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#define | MSU_CORECLK_SHFT 6 /* You don't wanna know */ |
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#define | MSU_CORECLK_MASK (UINT64_CAST 1 << 6) |
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#define | MSU_CORECLK (UINT64_CAST 1 << 6) |
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#define | MSU_NETSYNC_SHFT 5 /* You don't wanna know */ |
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#define | MSU_NETSYNC_MASK (UINT64_CAST 1 << 5) |
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#define | MSU_NETSYNC (UINT64_CAST 1 << 5) |
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#define | MSU_FPROMRDY_SHFT 4 /* Flash PROM ready bit */ |
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#define | MSU_FPROMRDY_MASK (UINT64_CAST 1 << 4) |
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#define | MSU_FPROMRDY (UINT64_CAST 1 << 4) |
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#define | MSU_I2CINTR_SHFT 3 /* I2C interrupt bit */ |
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#define | MSU_I2CINTR_MASK (UINT64_CAST 1 << 3) |
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#define | MSU_I2CINTR (UINT64_CAST 1 << 3) |
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#define | MSU_SLOTID_MASK 0xff |
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#define | MSU_SN0_SLOTID_SHFT 0 /* Slot ID */ |
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#define | MSU_SN0_SLOTID_MASK (UINT64_CAST 7) |
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#define | MSU_SN00_SLOTID_SHFT 7 |
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#define | MSU_SN00_SLOTID_MASK (UINT64_CAST 0x80) |
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#define | MSU_PIMM_PSC_SHFT 4 |
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#define | MSU_PIMM_PSC_MASK (0xf << MSU_PIMM_PSC_SHFT) |
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#define | MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63) |
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#define | MD_MIG_DIFF_THRES_VALID_SHFT 63 |
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#define | MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff) |
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#define | MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63) |
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#define | MD_MIG_VALUE_THRES_VALID_SHFT 63 |
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#define | MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff) |
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#define | MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63) |
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#define | MD_MIG_CANDIDATE_VALID_SHFT 63 |
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#define | MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30) |
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#define | MD_MIG_CANDIDATE_TYPE_SHFT 30 |
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#define | MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29) |
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#define | MD_MIG_CANDIDATE_OVERRUN_SHFT 29 |
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#define | MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18) |
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#define | MD_MIG_CANDIDATE_INITIATOR_SHFT 18 |
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#define | MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20) |
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#define | MD_MIG_CANDIDATE_NODEID_SHFT 20 |
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#define | MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff) |
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#define | MD_MIG_CANDIDATE_ADDR_SHFT 14 /* The address starts at bit 14 */ |
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#define | MD_BANK_SHFT 29 /* log2(512 MB) */ |
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#define | MD_BANK_MASK (UINT64_CAST 7 << 29) |
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#define | MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT) /* 512 MB */ |
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#define | MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT) |
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#define | MD_DIR_SHARED (UINT64_CAST 0x0) /* 000 */ |
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#define | MD_DIR_POISONED (UINT64_CAST 0x1) /* 001 */ |
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#define | MD_DIR_EXCLUSIVE (UINT64_CAST 0x2) /* 010 */ |
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#define | MD_DIR_BUSY_SHARED (UINT64_CAST 0x3) /* 011 */ |
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#define | MD_DIR_BUSY_EXCL (UINT64_CAST 0x4) /* 100 */ |
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#define | MD_DIR_WAIT (UINT64_CAST 0x5) /* 101 */ |
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#define | MD_DIR_UNOWNED (UINT64_CAST 0x7) /* 111 */ |
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#define | MD_DIR_FORCE_ECC (UINT64_CAST 1 << 63) |
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#define | MD_PDIR_MASK 0xffffffffffff /* Whole entry */ |
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#define | MD_PDIR_ECC_SHFT 0 /* ABC low or high */ |
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#define | MD_PDIR_ECC_MASK 0x7f |
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#define | MD_PDIR_PRIO_SHFT 8 /* ABC low */ |
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#define | MD_PDIR_PRIO_MASK (0xf << 8) |
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#define | MD_PDIR_AX_SHFT 7 /* ABC low */ |
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#define | MD_PDIR_AX_MASK (1 << 7) |
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#define | MD_PDIR_AX (1 << 7) |
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#define | MD_PDIR_FINE_SHFT 12 /* ABC low */ |
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#define | MD_PDIR_FINE_MASK (1 << 12) |
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#define | MD_PDIR_FINE (1 << 12) |
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#define | MD_PDIR_OCT_SHFT 13 /* A low */ |
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#define | MD_PDIR_OCT_MASK (7 << 13) |
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#define | MD_PDIR_STATE_SHFT 13 /* BC low */ |
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#define | MD_PDIR_STATE_MASK (7 << 13) |
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#define | MD_PDIR_ONECNT_SHFT 16 /* BC low */ |
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#define | MD_PDIR_ONECNT_MASK (0x3f << 16) |
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#define | MD_PDIR_PTR_SHFT 22 /* C low */ |
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#define | MD_PDIR_PTR_MASK (UINT64_CAST 0x7ff << 22) |
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#define | MD_PDIR_VECMSB_SHFT 22 /* AB low */ |
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#define | MD_PDIR_VECMSB_BITMASK 0x3ffffff |
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#define | MD_PDIR_VECMSB_BITSHFT 27 |
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#define | MD_PDIR_VECMSB_MASK (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22) |
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#define | MD_PDIR_CWOFF_SHFT 7 /* C high */ |
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#define | MD_PDIR_CWOFF_MASK (7 << 7) |
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#define | MD_PDIR_VECLSB_SHFT 10 /* AB high */ |
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#define | MD_PDIR_VECLSB_BITMASK (UINT64_CAST 0x3fffffffff) |
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#define | MD_PDIR_VECLSB_BITSHFT 0 |
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#define | MD_PDIR_VECLSB_MASK (MD_PDIR_VECLSB_BITMASK << 10) |
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#define | MD_PDIR_INIT_LO |
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#define | MD_PDIR_INIT_HI 0 |
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#define | MD_PDIR_INIT_PROT |
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#define | MD_SDIR_MASK 0xffff /* Whole entry */ |
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#define | MD_SDIR_ECC_SHFT 0 /* AC low or high */ |
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#define | MD_SDIR_ECC_MASK 0x1f |
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#define | MD_SDIR_PRIO_SHFT 6 /* AC low */ |
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#define | MD_SDIR_PRIO_MASK (1 << 6) |
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#define | MD_SDIR_AX_SHFT 5 /* AC low */ |
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#define | MD_SDIR_AX_MASK (1 << 5) |
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#define | MD_SDIR_AX (1 << 5) |
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#define | MD_SDIR_STATE_SHFT 7 /* AC low */ |
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#define | MD_SDIR_STATE_MASK (7 << 7) |
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#define | MD_SDIR_PTR_SHFT 10 /* C low */ |
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#define | MD_SDIR_PTR_MASK (0x3f << 10) |
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#define | MD_SDIR_CWOFF_SHFT 5 /* C high */ |
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#define | MD_SDIR_CWOFF_MASK (7 << 5) |
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#define | MD_SDIR_VECMSB_SHFT 11 /* A low */ |
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#define | MD_SDIR_VECMSB_BITMASK 0x1f |
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#define | MD_SDIR_VECMSB_BITSHFT 7 |
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#define | MD_SDIR_VECMSB_MASK (MD_SDIR_VECMSB_BITMASK << 11) |
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#define | MD_SDIR_VECLSB_SHFT 5 /* A high */ |
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#define | MD_SDIR_VECLSB_BITMASK 0x7ff |
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#define | MD_SDIR_VECLSB_BITSHFT 0 |
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#define | MD_SDIR_VECLSB_MASK (MD_SDIR_VECLSB_BITMASK << 5) |
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#define | MD_SDIR_INIT_LO |
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#define | MD_SDIR_INIT_HI 0 |
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#define | MD_SDIR_INIT_PROT (MD_PROT_RW << MD_SPROT_SHFT) |
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#define | MD_PROT_RW (UINT64_CAST 0x6) |
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#define | MD_PROT_RO (UINT64_CAST 0x3) |
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#define | MD_PROT_NO (UINT64_CAST 0x0) |
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#define | MD_PROT_BAD (UINT64_CAST 0x5) |
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#define | MD_PPROT_SHFT 0 /* Prot. field */ |
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#define | MD_PPROT_MASK 7 |
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#define | MD_PPROT_MIGMD_SHFT 3 /* Migration mode */ |
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#define | MD_PPROT_MIGMD_MASK (3 << 3) |
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#define | MD_PPROT_REFCNT_SHFT 5 /* Reference count */ |
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#define | MD_PPROT_REFCNT_WIDTH 0x7ffff |
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#define | MD_PPROT_REFCNT_MASK (MD_PPROT_REFCNT_WIDTH << 5) |
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#define | MD_PPROT_IO_SHFT 45 /* I/O Prot field */ |
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#define | MD_PPROT_IO_MASK (UINT64_CAST 7 << 45) |
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#define | MD_SPROT_SHFT 0 /* Prot. field */ |
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#define | MD_SPROT_MASK 7 |
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#define | MD_SPROT_MIGMD_SHFT 3 /* Migration mode */ |
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#define | MD_SPROT_MIGMD_MASK (3 << 3) |
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#define | MD_SPROT_REFCNT_SHFT 5 /* Reference count */ |
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#define | MD_SPROT_REFCNT_WIDTH 0x7ff |
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#define | MD_SPROT_REFCNT_MASK (MD_SPROT_REFCNT_WIDTH << 5) |
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#define | MD_PROT_MIGMD_IREL (UINT64_CAST 0x3 << 3) |
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#define | MD_PROT_MIGMD_IABS (UINT64_CAST 0x2 << 3) |
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#define | MD_PROT_MIGMD_PREL (UINT64_CAST 0x1 << 3) |
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#define | MD_PROT_MIGMD_OFF (UINT64_CAST 0x0 << 3) |
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#define | CPU_LED_ADDR(_nasid, _slice) |
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#define | SET_CPU_LEDS(_nasid, _slice,_val) (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val))) |
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#define | SET_MY_LEDS(_v) SET_CPU_LEDS(get_nasid(), get_slice(), (_v)) |
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#define | DIRTYPE_PREMIUM 1 |
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#define | DIRTYPE_STANDARD 0 |
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#define | MD_MEMORY_CONFIG_DIR_TYPE_GET(region) |
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#define | MD_MIG_DIFF_THRESH_GET(region) |
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#define | MD_MIG_DIFF_THRESH_SET(region, value) |
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#define | MD_MIG_DIFF_THRESH_DISABLE(region) |
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#define | MD_MIG_DIFF_THRESH_ENABLE(region) |
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#define | MD_MIG_DIFF_THRESH_IS_ENABLED(region) |
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#define | MD_MIG_VALUE_THRESH_GET(region) |
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#define | MD_MIG_VALUE_THRESH_SET(region, value) |
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#define | MD_MIG_VALUE_THRESH_DISABLE(region) |
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#define | MD_MIG_VALUE_THRESH_ENABLE(region) |
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#define | MD_MIG_VALUE_THRESH_IS_ENABLED(region) |
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#define | MD_MIG_CANDIDATE_GET(my_region_id) |
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#define | MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK) |
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#define | MD_MIG_CANDIDATE_NODEID(value) |
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#define | MD_MIG_CANDIDATE_TYPE(value) |
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#define | MD_MIG_CANDIDATE_VALID(value) |
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#define | MD_PPROT_REFCNT_GET(value) |
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#define | MD_PPROT_MIGMD_GET(value) |
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#define | MD_SPROT_REFCNT_GET(value) |
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#define | MD_SPROT_MIGMD_GET(value) |
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#define | DIR_ERROR_VALID_MASK 0xe000000000000000 |
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#define | DIR_ERROR_VALID_SHFT 61 |
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#define | DIR_ERROR_VALID_UCE 0x8000000000000000 |
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#define | DIR_ERROR_VALID_AE 0x4000000000000000 |
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#define | DIR_ERROR_VALID_CE 0x2000000000000000 |
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#define | MEM_ERROR_VALID_MASK 0xc000000000000000 |
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#define | MEM_ERROR_VALID_SHFT 62 |
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#define | MEM_ERROR_VALID_UCE 0x8000000000000000 |
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#define | MEM_ERROR_VALID_CE 0x4000000000000000 |
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#define | PROTO_ERROR_VALID_MASK 0x8000000000000000 |
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#define | MISC_ERROR_VALID_MASK 0x3ff |
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#define | DIR_ERR_HSPEC_MASK 0x3ffffff8 |
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#define | ERROR_HSPEC_MASK 0x3ffffff8 |
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#define | ERROR_HSPEC_SHFT 3 |
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#define | ERROR_ADDR_MASK 0xfffffff8 |
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#define | ERROR_ADDR_SHFT 3 |
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#define | MMCE_VALID_MASK 0x3ff |
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#define | MMCE_ILL_MSG_SHFT 8 |
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#define | MMCE_ILL_MSG_MASK (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT) |
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#define | MMCE_ILL_REV_SHFT 6 |
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#define | MMCE_ILL_REV_MASK (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT) |
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#define | MMCE_LONG_PACK_SHFT 4 |
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#define | MMCE_LONG_PACK_MASK (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT) |
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#define | MMCE_SHORT_PACK_SHFT 2 |
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#define | MMCE_SHORT_PACK_MASK (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT) |
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#define | MMCE_BAD_DATA_SHFT 0 |
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#define | MMCE_BAD_DATA_MASK (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT) |
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#define | MD_PERF_COUNTERS 6 |
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#define | MD_PERF_SETS 6 |
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#define | MEM_DIMM_MASK 0xe0000000 |
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#define | MEM_DIMM_SHFT 29 |
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