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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/module.h>#include <linux/kernel.h>#include <linux/err.h>#include <linux/slab.h>#include <linux/stat.h>#include <linux/delay.h>#include <linux/i2c.h>#include <linux/init.h>#include <linux/pci.h>#include <linux/interrupt.h>#include <linux/pm_runtime.h>#include <linux/io.h>Go to the source code of this file.
Data Structures | |
| struct | intel_mid_i2c_private |
Macros | |
| #define | DRIVER_NAME "i2c-intel-mid" |
| #define | VERSION "Version 0.5ac2" |
| #define | PLATFORM "Moorestown/Medfield" |
| #define | NUM_PLATFORMS 2 |
| #define | NUM_SPEEDS 3 |
| #define | ACTIVE 0 |
| #define | STANDBY 1 |
| #define | IC_CON 0x00 |
| #define | SLV_DIS (1 << 6) /* Disable slave mode */ |
| #define | RESTART (1 << 5) /* Send a Restart condition */ |
| #define | ADDR_10BIT (1 << 4) /* 10-bit addressing */ |
| #define | STANDARD_MODE (1 << 1) /* standard mode */ |
| #define | FAST_MODE (2 << 1) /* fast mode */ |
| #define | HIGH_MODE (3 << 1) /* high speed mode */ |
| #define | MASTER_EN (1 << 0) /* Master mode */ |
| #define | IC_TAR 0x04 |
| #define | IC_TAR_10BIT_ADDR (1 << 12) /* 10-bit addressing */ |
| #define | IC_TAR_SPECIAL (1 << 11) /* Perform special I2C cmd */ |
| #define | IC_TAR_GC_OR_START (1 << 10) /* 0: Gerneral Call Address */ |
| #define | IC_SAR 0x08 /* Not used in Master mode */ |
| #define | IC_HS_MADDR 0x0c |
| #define | IC_DATA_CMD 0x10 |
| #define | IC_RD (1 << 8) /* 1: Read 0: Write */ |
| #define | IC_SS_SCL_HCNT 0x14 |
| #define | IC_SS_SCL_LCNT 0x18 |
| #define | IC_FS_SCL_HCNT 0x1c |
| #define | IC_FS_SCL_LCNT 0x20 |
| #define | IC_HS_SCL_HCNT 0x24 |
| #define | IC_HS_SCL_LCNT 0x28 |
| #define | IC_INTR_STAT 0x2c /* Read only */ |
| #define | R_GEN_CALL (1 << 11) |
| #define | R_START_DET (1 << 10) |
| #define | R_STOP_DET (1 << 9) |
| #define | R_ACTIVITY (1 << 8) |
| #define | R_RX_DONE (1 << 7) |
| #define | R_TX_ABRT (1 << 6) |
| #define | R_RD_REQ (1 << 5) |
| #define | R_TX_EMPTY (1 << 4) |
| #define | R_TX_OVER (1 << 3) |
| #define | R_RX_FULL (1 << 2) |
| #define | R_RX_OVER (1 << 1) |
| #define | R_RX_UNDER (1 << 0) |
| #define | IC_INTR_MASK 0x30 /* Read and Write */ |
| #define | M_GEN_CALL (1 << 11) |
| #define | M_START_DET (1 << 10) |
| #define | M_STOP_DET (1 << 9) |
| #define | M_ACTIVITY (1 << 8) |
| #define | M_RX_DONE (1 << 7) |
| #define | M_TX_ABRT (1 << 6) |
| #define | M_RD_REQ (1 << 5) |
| #define | M_TX_EMPTY (1 << 4) |
| #define | M_TX_OVER (1 << 3) |
| #define | M_RX_FULL (1 << 2) |
| #define | M_RX_OVER (1 << 1) |
| #define | M_RX_UNDER (1 << 0) |
| #define | IC_RAW_INTR_STAT 0x34 /* Read Only */ |
| #define | GEN_CALL (1 << 11) /* General call */ |
| #define | START_DET (1 << 10) /* (RE)START occurred */ |
| #define | STOP_DET (1 << 9) /* STOP occurred */ |
| #define | ACTIVITY (1 << 8) /* Bus busy */ |
| #define | RX_DONE (1 << 7) /* Not used in Master mode */ |
| #define | TX_ABRT (1 << 6) /* Transmit Abort */ |
| #define | RD_REQ (1 << 5) /* Not used in Master mode */ |
| #define | TX_EMPTY (1 << 4) /* TX FIFO <= threshold */ |
| #define | TX_OVER (1 << 3) /* TX FIFO overflow */ |
| #define | RX_FULL (1 << 2) /* RX FIFO >= threshold */ |
| #define | RX_OVER (1 << 1) /* RX FIFO overflow */ |
| #define | RX_UNDER (1 << 0) /* RX FIFO empty */ |
| #define | IC_RX_TL 0x38 |
| #define | IC_TX_TL 0x3c |
| #define | IC_CLR_INTR 0x40 |
| #define | CLR_INTR (1 << 0) |
| #define | IC_CLR_RX_UNDER 0x44 |
| #define | CLR_RX_UNDER (1 << 0) |
| #define | IC_CLR_RX_OVER 0x48 |
| #define | CLR_RX_OVER (1 << 0) |
| #define | IC_CLR_TX_OVER 0x4c |
| #define | CLR_TX_OVER (1 << 0) |
| #define | IC_CLR_RD_REQ 0x50 |
| #define | IC_CLR_TX_ABRT 0x54 |
| #define | CLR_TX_ABRT (1 << 0) |
| #define | IC_CLR_RX_DONE 0x58 |
| #define | IC_CLR_ACTIVITY 0x5c |
| #define | CLR_ACTIVITY (1 << 0) |
| #define | IC_CLR_STOP_DET 0x60 |
| #define | CLR_STOP_DET (1 << 0) |
| #define | IC_CLR_START_DET 0x64 |
| #define | CLR_START_DET (1 << 0) |
| #define | IC_CLR_GEN_CALL 0x68 |
| #define | CLR_GEN_CALL (1 << 0) |
| #define | IC_ENABLE 0x6c |
| #define | ENABLE (1 << 0) |
| #define | IC_STATUS 0x70 /* Read Only */ |
| #define | STAT_SLV_ACTIVITY (1 << 6) /* Slave not in idle */ |
| #define | STAT_MST_ACTIVITY (1 << 5) /* Master not in idle */ |
| #define | STAT_RFF (1 << 4) /* RX FIFO Full */ |
| #define | STAT_RFNE (1 << 3) /* RX FIFO Not Empty */ |
| #define | STAT_TFE (1 << 2) /* TX FIFO Empty */ |
| #define | STAT_TFNF (1 << 1) /* TX FIFO Not Full */ |
| #define | STAT_ACTIVITY (1 << 0) /* Activity Status */ |
| #define | IC_TXFLR 0x74 /* Read Only */ |
| #define | TXFLR (1 << 0) /* TX FIFO level */ |
| #define | IC_RXFLR 0x78 /* Read Only */ |
| #define | RXFLR (1 << 0) /* RX FIFO level */ |
| #define | IC_TX_ABRT_SOURCE 0x80 |
| #define | ABRT_SLVRD_INTX (1 << 15) |
| #define | ABRT_SLV_ARBLOST (1 << 14) |
| #define | ABRT_SLVFLUSH_TXFIFO (1 << 13) |
| #define | ARB_LOST (1 << 12) |
| #define | ABRT_MASTER_DIS (1 << 11) |
| #define | ABRT_10B_RD_NORSTRT (1 << 10) |
| #define | ABRT_SBYTE_NORSTRT (1 << 9) |
| #define | ABRT_HS_NORSTRT (1 << 8) |
| #define | ABRT_SBYTE_ACKDET (1 << 7) |
| #define | ABRT_HS_ACKDET (1 << 6) |
| #define | ABRT_GCALL_READ (1 << 5) |
| #define | ABRT_GCALL_NOACK (1 << 4) |
| #define | ABRT_TXDATA_NOACK (1 << 3) |
| #define | ABRT_10ADDR2_NOACK (1 << 2) |
| #define | ABRT_10ADDR1_NOACK (1 << 1) |
| #define | ABRT_7B_ADDR_NOACK (1 << 0) |
| #define | IC_ENABLE_STATUS 0x9c |
| #define | IC_EN (1 << 0) /* I2C in an enabled state */ |
| #define | IC_COMP_PARAM_1 0xf4 |
| #define | APB_DATA_WIDTH (0x3 << 0) |
| #define | SS_MIN_SCL_HIGH 4000 |
| #define | SS_MIN_SCL_LOW 4700 |
| #define | FS_MIN_SCL_HIGH 600 |
| #define | FS_MIN_SCL_LOW 1300 |
| #define | HS_MIN_SCL_HIGH_100PF 60 |
| #define | HS_MIN_SCL_LOW_100PF 120 |
| #define | STANDARD 0 |
| #define | FAST 1 |
| #define | HIGH 2 |
| #define | NUM_SPEEDS 3 |
Enumerations | |
| enum | platform_enum { MOORESTOWN = 0, MEDFIELD = 1 } |
| enum | mid_i2c_status { STATUS_IDLE = 0, STATUS_READ_START, STATUS_READ_IN_PROGRESS, STATUS_READ_SUCCESS, STATUS_WRITE_START, STATUS_WRITE_SUCCESS, STATUS_XFER_ABORT, STATUS_STANDBY } |
Functions | |
| module_param_array (speed_mode, int,&ctl_num, S_IRUGO) | |
| MODULE_PARM_DESC (speed_mode,"Set the speed of the i2c interface (0-2)") | |
| MODULE_DEVICE_TABLE (pci, intel_mid_i2c_ids) | |
| module_pci_driver (intel_mid_i2c_driver) | |
| MODULE_AUTHOR ("Ba Zheng <[email protected]>") | |
| MODULE_DESCRIPTION ("I2C driver for Moorestown Platform") | |
| MODULE_LICENSE ("GPL") | |
| MODULE_VERSION (VERSION) | |
| #define ABRT_10ADDR1_NOACK (1 << 1) |
Definition at line 268 of file i2c-intel-mid.c.
| #define ABRT_10ADDR2_NOACK (1 << 2) |
Definition at line 267 of file i2c-intel-mid.c.
| #define ABRT_10B_RD_NORSTRT (1 << 10) |
Definition at line 259 of file i2c-intel-mid.c.
| #define ABRT_7B_ADDR_NOACK (1 << 0) |
Definition at line 269 of file i2c-intel-mid.c.
| #define ABRT_GCALL_NOACK (1 << 4) |
Definition at line 265 of file i2c-intel-mid.c.
| #define ABRT_GCALL_READ (1 << 5) |
Definition at line 264 of file i2c-intel-mid.c.
| #define ABRT_HS_ACKDET (1 << 6) |
Definition at line 263 of file i2c-intel-mid.c.
| #define ABRT_HS_NORSTRT (1 << 8) |
Definition at line 261 of file i2c-intel-mid.c.
| #define ABRT_MASTER_DIS (1 << 11) |
Definition at line 258 of file i2c-intel-mid.c.
| #define ABRT_SBYTE_ACKDET (1 << 7) |
Definition at line 262 of file i2c-intel-mid.c.
| #define ABRT_SBYTE_NORSTRT (1 << 9) |
Definition at line 260 of file i2c-intel-mid.c.
| #define ABRT_SLV_ARBLOST (1 << 14) |
Definition at line 255 of file i2c-intel-mid.c.
| #define ABRT_SLVFLUSH_TXFIFO (1 << 13) |
Definition at line 256 of file i2c-intel-mid.c.
| #define ABRT_SLVRD_INTX (1 << 15) |
Definition at line 254 of file i2c-intel-mid.c.
| #define ABRT_TXDATA_NOACK (1 << 3) |
Definition at line 266 of file i2c-intel-mid.c.
| #define ACTIVE 0 |
Definition at line 92 of file i2c-intel-mid.c.
| #define ACTIVITY (1 << 8) /* Bus busy */ |
Definition at line 175 of file i2c-intel-mid.c.
| #define ADDR_10BIT (1 << 4) /* 10-bit addressing */ |
Definition at line 100 of file i2c-intel-mid.c.
| #define APB_DATA_WIDTH (0x3 << 0) |
Definition at line 277 of file i2c-intel-mid.c.
| #define ARB_LOST (1 << 12) |
Definition at line 257 of file i2c-intel-mid.c.
| #define CLR_ACTIVITY (1 << 0) |
Definition at line 216 of file i2c-intel-mid.c.
| #define CLR_GEN_CALL (1 << 0) |
Definition at line 228 of file i2c-intel-mid.c.
| #define CLR_INTR (1 << 0) |
Definition at line 193 of file i2c-intel-mid.c.
| #define CLR_RX_OVER (1 << 0) |
Definition at line 201 of file i2c-intel-mid.c.
| #define CLR_RX_UNDER (1 << 0) |
Definition at line 197 of file i2c-intel-mid.c.
| #define CLR_START_DET (1 << 0) |
Definition at line 224 of file i2c-intel-mid.c.
| #define CLR_STOP_DET (1 << 0) |
Definition at line 220 of file i2c-intel-mid.c.
| #define CLR_TX_ABRT (1 << 0) |
Definition at line 211 of file i2c-intel-mid.c.
| #define CLR_TX_OVER (1 << 0) |
Definition at line 205 of file i2c-intel-mid.c.
| #define DRIVER_NAME "i2c-intel-mid" |
Definition at line 35 of file i2c-intel-mid.c.
| #define ENABLE (1 << 0) |
Definition at line 232 of file i2c-intel-mid.c.
| #define FAST 1 |
Definition at line 288 of file i2c-intel-mid.c.
Definition at line 102 of file i2c-intel-mid.c.
| #define FS_MIN_SCL_HIGH 600 |
Definition at line 282 of file i2c-intel-mid.c.
| #define FS_MIN_SCL_LOW 1300 |
Definition at line 283 of file i2c-intel-mid.c.
| #define GEN_CALL (1 << 11) /* General call */ |
Definition at line 172 of file i2c-intel-mid.c.
| #define HIGH 2 |
Definition at line 289 of file i2c-intel-mid.c.
Definition at line 103 of file i2c-intel-mid.c.
| #define HS_MIN_SCL_HIGH_100PF 60 |
Definition at line 284 of file i2c-intel-mid.c.
| #define HS_MIN_SCL_LOW_100PF 120 |
Definition at line 285 of file i2c-intel-mid.c.
| #define IC_CLR_ACTIVITY 0x5c |
Definition at line 215 of file i2c-intel-mid.c.
| #define IC_CLR_GEN_CALL 0x68 |
Definition at line 227 of file i2c-intel-mid.c.
| #define IC_CLR_INTR 0x40 |
Definition at line 192 of file i2c-intel-mid.c.
| #define IC_CLR_RD_REQ 0x50 |
Definition at line 207 of file i2c-intel-mid.c.
| #define IC_CLR_RX_DONE 0x58 |
Definition at line 212 of file i2c-intel-mid.c.
| #define IC_CLR_RX_OVER 0x48 |
Definition at line 200 of file i2c-intel-mid.c.
| #define IC_CLR_RX_UNDER 0x44 |
Definition at line 196 of file i2c-intel-mid.c.
| #define IC_CLR_START_DET 0x64 |
Definition at line 223 of file i2c-intel-mid.c.
| #define IC_CLR_STOP_DET 0x60 |
Definition at line 219 of file i2c-intel-mid.c.
| #define IC_CLR_TX_ABRT 0x54 |
Definition at line 210 of file i2c-intel-mid.c.
| #define IC_CLR_TX_OVER 0x4c |
Definition at line 204 of file i2c-intel-mid.c.
| #define IC_COMP_PARAM_1 0xf4 |
Definition at line 276 of file i2c-intel-mid.c.
| #define IC_CON 0x00 |
Definition at line 97 of file i2c-intel-mid.c.
| #define IC_DATA_CMD 0x10 |
Definition at line 119 of file i2c-intel-mid.c.
Definition at line 273 of file i2c-intel-mid.c.
| #define IC_ENABLE 0x6c |
Definition at line 231 of file i2c-intel-mid.c.
| #define IC_ENABLE_STATUS 0x9c |
Definition at line 272 of file i2c-intel-mid.c.
| #define IC_FS_SCL_HCNT 0x1c |
Definition at line 129 of file i2c-intel-mid.c.
| #define IC_FS_SCL_LCNT 0x20 |
Definition at line 132 of file i2c-intel-mid.c.
| #define IC_HS_MADDR 0x0c |
Definition at line 116 of file i2c-intel-mid.c.
| #define IC_HS_SCL_HCNT 0x24 |
Definition at line 135 of file i2c-intel-mid.c.
| #define IC_HS_SCL_LCNT 0x28 |
Definition at line 138 of file i2c-intel-mid.c.
| #define IC_INTR_MASK 0x30 /* Read and Write */ |
Definition at line 156 of file i2c-intel-mid.c.
| #define IC_INTR_STAT 0x2c /* Read only */ |
Definition at line 141 of file i2c-intel-mid.c.
| #define IC_RAW_INTR_STAT 0x34 /* Read Only */ |
Definition at line 171 of file i2c-intel-mid.c.
Definition at line 120 of file i2c-intel-mid.c.
| #define IC_RX_TL 0x38 |
Definition at line 186 of file i2c-intel-mid.c.
| #define IC_RXFLR 0x78 /* Read Only */ |
Definition at line 249 of file i2c-intel-mid.c.
| #define IC_SAR 0x08 /* Not used in Master mode */ |
Definition at line 113 of file i2c-intel-mid.c.
| #define IC_SS_SCL_HCNT 0x14 |
Definition at line 123 of file i2c-intel-mid.c.
| #define IC_SS_SCL_LCNT 0x18 |
Definition at line 126 of file i2c-intel-mid.c.
| #define IC_STATUS 0x70 /* Read Only */ |
Definition at line 235 of file i2c-intel-mid.c.
| #define IC_TAR 0x04 |
Definition at line 107 of file i2c-intel-mid.c.
| #define IC_TAR_10BIT_ADDR (1 << 12) /* 10-bit addressing */ |
Definition at line 108 of file i2c-intel-mid.c.
| #define IC_TAR_GC_OR_START (1 << 10) /* 0: Gerneral Call Address */ |
Definition at line 110 of file i2c-intel-mid.c.
Definition at line 109 of file i2c-intel-mid.c.
| #define IC_TX_ABRT_SOURCE 0x80 |
Definition at line 253 of file i2c-intel-mid.c.
| #define IC_TX_TL 0x3c |
Definition at line 189 of file i2c-intel-mid.c.
| #define IC_TXFLR 0x74 /* Read Only */ |
Definition at line 245 of file i2c-intel-mid.c.
| #define M_ACTIVITY (1 << 8) |
Definition at line 160 of file i2c-intel-mid.c.
| #define M_GEN_CALL (1 << 11) |
Definition at line 157 of file i2c-intel-mid.c.
| #define M_RD_REQ (1 << 5) |
Definition at line 163 of file i2c-intel-mid.c.
| #define M_RX_DONE (1 << 7) |
Definition at line 161 of file i2c-intel-mid.c.
| #define M_RX_FULL (1 << 2) |
Definition at line 166 of file i2c-intel-mid.c.
| #define M_RX_OVER (1 << 1) |
Definition at line 167 of file i2c-intel-mid.c.
| #define M_RX_UNDER (1 << 0) |
Definition at line 168 of file i2c-intel-mid.c.
| #define M_START_DET (1 << 10) |
Definition at line 158 of file i2c-intel-mid.c.
| #define M_STOP_DET (1 << 9) |
Definition at line 159 of file i2c-intel-mid.c.
| #define M_TX_ABRT (1 << 6) |
Definition at line 162 of file i2c-intel-mid.c.
| #define M_TX_EMPTY (1 << 4) |
Definition at line 164 of file i2c-intel-mid.c.
| #define M_TX_OVER (1 << 3) |
Definition at line 165 of file i2c-intel-mid.c.
| #define MASTER_EN (1 << 0) /* Master mode */ |
Definition at line 104 of file i2c-intel-mid.c.
| #define NUM_PLATFORMS 2 |
Definition at line 40 of file i2c-intel-mid.c.
| #define NUM_SPEEDS 3 |
Definition at line 291 of file i2c-intel-mid.c.
| #define NUM_SPEEDS 3 |
Definition at line 291 of file i2c-intel-mid.c.
| #define PLATFORM "Moorestown/Medfield" |
Definition at line 37 of file i2c-intel-mid.c.
| #define R_ACTIVITY (1 << 8) |
Definition at line 145 of file i2c-intel-mid.c.
| #define R_GEN_CALL (1 << 11) |
Definition at line 142 of file i2c-intel-mid.c.
| #define R_RD_REQ (1 << 5) |
Definition at line 148 of file i2c-intel-mid.c.
| #define R_RX_DONE (1 << 7) |
Definition at line 146 of file i2c-intel-mid.c.
| #define R_RX_FULL (1 << 2) |
Definition at line 151 of file i2c-intel-mid.c.
| #define R_RX_OVER (1 << 1) |
Definition at line 152 of file i2c-intel-mid.c.
| #define R_RX_UNDER (1 << 0) |
Definition at line 153 of file i2c-intel-mid.c.
| #define R_START_DET (1 << 10) |
Definition at line 143 of file i2c-intel-mid.c.
| #define R_STOP_DET (1 << 9) |
Definition at line 144 of file i2c-intel-mid.c.
| #define R_TX_ABRT (1 << 6) |
Definition at line 147 of file i2c-intel-mid.c.
| #define R_TX_EMPTY (1 << 4) |
Definition at line 149 of file i2c-intel-mid.c.
| #define R_TX_OVER (1 << 3) |
Definition at line 150 of file i2c-intel-mid.c.
Definition at line 178 of file i2c-intel-mid.c.
| #define RESTART (1 << 5) /* Send a Restart condition */ |
Definition at line 99 of file i2c-intel-mid.c.
Definition at line 176 of file i2c-intel-mid.c.
Definition at line 181 of file i2c-intel-mid.c.
Definition at line 182 of file i2c-intel-mid.c.
Definition at line 183 of file i2c-intel-mid.c.
Definition at line 250 of file i2c-intel-mid.c.
Definition at line 98 of file i2c-intel-mid.c.
| #define SS_MIN_SCL_HIGH 4000 |
Definition at line 280 of file i2c-intel-mid.c.
| #define SS_MIN_SCL_LOW 4700 |
Definition at line 281 of file i2c-intel-mid.c.
| #define STANDARD 0 |
Definition at line 287 of file i2c-intel-mid.c.
| #define STANDARD_MODE (1 << 1) /* standard mode */ |
Definition at line 101 of file i2c-intel-mid.c.
| #define STANDBY 1 |
Definition at line 93 of file i2c-intel-mid.c.
Definition at line 173 of file i2c-intel-mid.c.
| #define STAT_ACTIVITY (1 << 0) /* Activity Status */ |
Definition at line 242 of file i2c-intel-mid.c.
Definition at line 237 of file i2c-intel-mid.c.
Definition at line 238 of file i2c-intel-mid.c.
Definition at line 239 of file i2c-intel-mid.c.
Definition at line 236 of file i2c-intel-mid.c.
Definition at line 240 of file i2c-intel-mid.c.
Definition at line 241 of file i2c-intel-mid.c.
| #define STOP_DET (1 << 9) /* STOP occurred */ |
Definition at line 174 of file i2c-intel-mid.c.
Definition at line 177 of file i2c-intel-mid.c.
Definition at line 179 of file i2c-intel-mid.c.
Definition at line 180 of file i2c-intel-mid.c.
Definition at line 246 of file i2c-intel-mid.c.
| #define VERSION "Version 0.5ac2" |
Definition at line 36 of file i2c-intel-mid.c.
| enum mid_i2c_status |
| STATUS_IDLE | |
| STATUS_READ_START | |
| STATUS_READ_IN_PROGRESS | |
| STATUS_READ_SUCCESS | |
| STATUS_WRITE_START | |
| STATUS_WRITE_SUCCESS | |
| STATUS_XFER_ABORT | |
| STATUS_STANDBY |
Definition at line 46 of file i2c-intel-mid.c.
| enum platform_enum |
Definition at line 41 of file i2c-intel-mid.c.
| MODULE_AUTHOR | ( | "Ba Zheng <[email protected]>" | ) |
| MODULE_DEVICE_TABLE | ( | pci | , |
| intel_mid_i2c_ids | |||
| ) |
| MODULE_LICENSE | ( | "GPL" | ) |
| module_pci_driver | ( | intel_mid_i2c_driver | ) |
| MODULE_VERSION | ( | VERSION | ) |
1.8.2