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i82443bxgx_edac.c File Reference
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include "edac_core.h"

Go to the source code of this file.

Data Structures

struct  i82443bxgx_edacmc_error_info
 

Macros

#define I82443_REVISION   "0.1"
 
#define EDAC_MOD_STR   "i82443bxgx_edac"
 
#define I82443BXGX_NR_CSROWS   8
 
#define I82443BXGX_NR_CHANS   1
 
#define I82443BXGX_NR_DIMMS   4
 
#define I82443BXGX_NBXCFG
 
#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW
 
#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ   12 /* 2 bits,00=100MHz,10=66 MHz */
 
#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY   7 /* 2 bits: */
 
#define I82443BXGX_NBXCFG_INTEGRITY_NONE   0x0 /* 00 = Non-ECC */
 
#define I82443BXGX_NBXCFG_INTEGRITY_EC   0x1 /* 01 = EC (only) */
 
#define I82443BXGX_NBXCFG_INTEGRITY_ECC   0x2 /* 10 = ECC */
 
#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB   0x3 /* 11 = ECC + HW Scrub */
 
#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE   6
 
#define I82443BXGX_EAP
 
#define I82443BXGX_EAP_OFFSET_EAP   12 /* High 20 bits of error address */
 
#define I82443BXGX_EAP_OFFSET_MBE   BIT(1) /* Err at EAP was multi-bit (W1TC) */
 
#define I82443BXGX_EAP_OFFSET_SBE   BIT(0) /* Err at EAP was single-bit (W1TC) */
 
#define I82443BXGX_ERRCMD
 
#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE   BIT(1) /* 1 = enable */
 
#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE   BIT(0) /* 1 = enable */
 
#define I82443BXGX_ERRSTS
 
#define I82443BXGX_ERRSTS_OFFSET_MBFRE   5 /* 3 bits - first err row multibit */
 
#define I82443BXGX_ERRSTS_OFFSET_MEF   BIT(4) /* 1 = MBE occurred */
 
#define I82443BXGX_ERRSTS_OFFSET_SBFRE   1 /* 3 bits - first err row singlebit */
 
#define I82443BXGX_ERRSTS_OFFSET_SEF   BIT(0) /* 1 = SBE occurred */
 
#define I82443BXGX_DRAMC
 
#define I82443BXGX_DRAMC_OFFSET_DT   3 /* 2 bits, DRAM Type */
 
#define I82443BXGX_DRAMC_DRAM_IS_EDO   0 /* 00 = EDO */
 
#define I82443BXGX_DRAMC_DRAM_IS_SDRAM   1 /* 01 = SDRAM */
 
#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM   2 /* 10 = Registered SDRAM */
 
#define I82443BXGX_DRB
 

Functions

 EXPORT_SYMBOL_GPL (i82443bxgx_edacmc_probe1)
 
 EXPORT_SYMBOL_GPL (i82443bxgx_edacmc_remove_one)
 
 MODULE_DEVICE_TABLE (pci, i82443bxgx_pci_tbl)
 
 module_init (i82443bxgx_edacmc_init)
 
 module_exit (i82443bxgx_edacmc_exit)
 
 MODULE_LICENSE ("GPL")
 
 MODULE_AUTHOR ("Tim Small <[email protected]> - WPAD")
 
 MODULE_DESCRIPTION ("EDAC MC support for Intel 82443BX/GX memory controllers")
 
 module_param (edac_op_state, int, 0444)
 
 MODULE_PARM_DESC (edac_op_state,"EDAC Error Reporting state: 0=Poll,1=NMI")
 

Variables

struct i82443bxgx_edacmc_error_info __attribute__
 

Macro Definition Documentation

#define EDAC_MOD_STR   "i82443bxgx_edac"

Definition at line 36 of file i82443bxgx_edac.c.

#define I82443_REVISION   "0.1"

Definition at line 34 of file i82443bxgx_edac.c.

#define I82443BXGX_DRAMC
Value:
0x57 /* 8bit register starting at this PCI
* config space offset. */

Definition at line 92 of file i82443bxgx_edac.c.

#define I82443BXGX_DRAMC_DRAM_IS_EDO   0 /* 00 = EDO */

Definition at line 94 of file i82443bxgx_edac.c.

#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM   2 /* 10 = Registered SDRAM */

Definition at line 96 of file i82443bxgx_edac.c.

#define I82443BXGX_DRAMC_DRAM_IS_SDRAM   1 /* 01 = SDRAM */

Definition at line 95 of file i82443bxgx_edac.c.

#define I82443BXGX_DRAMC_OFFSET_DT   3 /* 2 bits, DRAM Type */

Definition at line 93 of file i82443bxgx_edac.c.

#define I82443BXGX_DRB
Value:
0x60 /* 8x 8bit registers starting at this PCI
* config space offset. */

Definition at line 98 of file i82443bxgx_edac.c.

#define I82443BXGX_EAP
Value:
0x80 /* 32bit register starting at this PCI
* config space offset, Error Address
* Pointer Register */

Definition at line 77 of file i82443bxgx_edac.c.

#define I82443BXGX_EAP_OFFSET_EAP   12 /* High 20 bits of error address */

Definition at line 78 of file i82443bxgx_edac.c.

#define I82443BXGX_EAP_OFFSET_MBE   BIT(1) /* Err at EAP was multi-bit (W1TC) */

Definition at line 79 of file i82443bxgx_edac.c.

#define I82443BXGX_EAP_OFFSET_SBE   BIT(0) /* Err at EAP was single-bit (W1TC) */

Definition at line 80 of file i82443bxgx_edac.c.

#define I82443BXGX_ERRCMD
Value:
0x90 /* 8bit register starting at this PCI
* config space offset. */

Definition at line 82 of file i82443bxgx_edac.c.

#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE   BIT(1) /* 1 = enable */

Definition at line 83 of file i82443bxgx_edac.c.

#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE   BIT(0) /* 1 = enable */

Definition at line 84 of file i82443bxgx_edac.c.

#define I82443BXGX_ERRSTS
Value:
0x91 /* 16bit register starting at this PCI
* config space offset. */

Definition at line 86 of file i82443bxgx_edac.c.

#define I82443BXGX_ERRSTS_OFFSET_MBFRE   5 /* 3 bits - first err row multibit */

Definition at line 87 of file i82443bxgx_edac.c.

#define I82443BXGX_ERRSTS_OFFSET_MEF   BIT(4) /* 1 = MBE occurred */

Definition at line 88 of file i82443bxgx_edac.c.

#define I82443BXGX_ERRSTS_OFFSET_SBFRE   1 /* 3 bits - first err row singlebit */

Definition at line 89 of file i82443bxgx_edac.c.

#define I82443BXGX_ERRSTS_OFFSET_SEF   BIT(0) /* 1 = SBE occurred */

Definition at line 90 of file i82443bxgx_edac.c.

#define I82443BXGX_NBXCFG
Value:
0x50 /* 32bit register starting at this PCI
* config space offset */

Definition at line 64 of file i82443bxgx_edac.c.

#define I82443BXGX_NBXCFG_INTEGRITY_EC   0x1 /* 01 = EC (only) */

Definition at line 70 of file i82443bxgx_edac.c.

#define I82443BXGX_NBXCFG_INTEGRITY_ECC   0x2 /* 10 = ECC */

Definition at line 71 of file i82443bxgx_edac.c.

#define I82443BXGX_NBXCFG_INTEGRITY_NONE   0x0 /* 00 = Non-ECC */

Definition at line 69 of file i82443bxgx_edac.c.

#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB   0x3 /* 11 = ECC + HW Scrub */

Definition at line 72 of file i82443bxgx_edac.c.

#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ   12 /* 2 bits,00=100MHz,10=66 MHz */

Definition at line 66 of file i82443bxgx_edac.c.

#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY   7 /* 2 bits: */

Definition at line 68 of file i82443bxgx_edac.c.

#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE   6

Definition at line 74 of file i82443bxgx_edac.c.

#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW
Value:
24 /* Array of bits, zero if
* row is non-ECC */

Definition at line 65 of file i82443bxgx_edac.c.

#define I82443BXGX_NR_CHANS   1

Definition at line 60 of file i82443bxgx_edac.c.

#define I82443BXGX_NR_CSROWS   8

Definition at line 59 of file i82443bxgx_edac.c.

#define I82443BXGX_NR_DIMMS   4

Definition at line 61 of file i82443bxgx_edac.c.

Function Documentation

EXPORT_SYMBOL_GPL ( i82443bxgx_edacmc_probe1  )
EXPORT_SYMBOL_GPL ( i82443bxgx_edacmc_remove_one  )
MODULE_AUTHOR ( "Tim Small <[email protected]> - WPAD"  )
MODULE_DESCRIPTION ( "EDAC MC support for Intel 82443BX/GX memory controllers"  )
MODULE_DEVICE_TABLE ( pci  ,
i82443bxgx_pci_tbl   
)
module_exit ( i82443bxgx_edacmc_exit  )
module_init ( i82443bxgx_edacmc_init  )
MODULE_LICENSE ( "GPL"  )
module_param ( edac_op_state  ,
int  ,
0444   
)
MODULE_PARM_DESC ( edac_op_state  ,
"EDAC Error Reporting state:  0 = Poll 
)

Variable Documentation

struct i82443bxgx_edacmc_error_info __attribute__
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