#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/dmaengine.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/platform_data/mmp_dma.h>
#include <linux/dmapool.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include "dmaengine.h"

Data Structures
struct	mmp_pdma_desc_hw

struct	mmp_pdma_desc_sw

struct	mmp_pdma_chan

struct	mmp_pdma_phy

struct	mmp_pdma_device

Macros
#define	DCSR 0x0000

#define	DALGN 0x00a0

#define	DINT 0x00f0

#define	DDADR 0x0200

#define	DSADR 0x0204

#define	DTADR 0x0208

#define	DCMD 0x020c

#define	DCSR_RUN (1 << 31) /* Run Bit (read / write) */

#define	DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */

#define	DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */

#define	DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */

#define	DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */

#define	DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */

#define	DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */

#define	DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */

#define	DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */

#define	DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */

#define	DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */

#define	DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */

#define	DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */

#define	DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */

#define	DCSR_EORINTR (1 << 9) /* The end of Receive */

#define	DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */

#define	DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */

#define	DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */

#define	DDADR_STOP (1 << 0) /* Stop (read / write) */

#define	DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */

#define	DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */

#define	DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */

#define	DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */

#define	DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */

#define	DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */

#define	DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */

#define	DCMD_BURST8 (1 << 16) /* 8 byte burst */

#define	DCMD_BURST16 (2 << 16) /* 16 byte burst */

#define	DCMD_BURST32 (3 << 16) /* 32 byte burst */

#define	DCMD_WIDTH1 (1 << 14) /* 1 byte width */

#define	DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */

#define	DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */

#define	DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */

#define	PDMA_ALIGNMENT 3

#define	PDMA_MAX_DESC_BYTES 0x1000

#define	tx_to_mmp_pdma_desc(tx) container_of(tx, struct mmp_pdma_desc_sw, async_tx)

#define	to_mmp_pdma_desc(lh) container_of(lh, struct mmp_pdma_desc_sw, node)

#define	to_mmp_pdma_chan(dchan) container_of(dchan, struct mmp_pdma_chan, chan)

#define	to_mmp_pdma_dev(dmadev) container_of(dmadev, struct mmp_pdma_device, device)

Functions
struct mmp_pdma_desc_hw	__aligned (32)

struct mmp_pdma_desc_sw *	mmp_pdma_alloc_descriptor (struct mmp_pdma_chan *chan)

	MODULE_DEVICE_TABLE (of, mmp_pdma_dt_ids)

	module_platform_driver (mmp_pdma_driver)

	MODULE_DESCRIPTION ("MARVELL MMP Periphera DMA Driver")

	MODULE_AUTHOR ("Marvell International Ltd.")

	MODULE_LICENSE ("GPL v2")

Variables
u32	ddadr

u32	dsadr

u32	dtadr

u32	dcmd

struct mmp_pdma_desc_sw	__aligned

Macro Definition Documentation

#define DALGN 0x00a0

Definition at line 25 of file mmp_pdma.c.

#define DCMD 0x020c

Definition at line 30 of file mmp_pdma.c.

#define DCMD_BURST16 (2 << 16) /* 16 byte burst */

Definition at line 63 of file mmp_pdma.c.

#define DCMD_BURST32 (3 << 16) /* 32 byte burst */

Definition at line 64 of file mmp_pdma.c.

#define DCMD_BURST8 (1 << 16) /* 8 byte burst */

Definition at line 62 of file mmp_pdma.c.

#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */

Definition at line 61 of file mmp_pdma.c.

#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */

Definition at line 60 of file mmp_pdma.c.

#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */

Definition at line 57 of file mmp_pdma.c.

#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */

Definition at line 58 of file mmp_pdma.c.

#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */

Definition at line 55 of file mmp_pdma.c.

#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */

Definition at line 56 of file mmp_pdma.c.

#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */

Definition at line 68 of file mmp_pdma.c.

#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */

Definition at line 59 of file mmp_pdma.c.

#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */

Definition at line 65 of file mmp_pdma.c.

#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */

Definition at line 66 of file mmp_pdma.c.

#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */

Definition at line 67 of file mmp_pdma.c.

#define DCSR 0x0000

Definition at line 24 of file mmp_pdma.c.

#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */

Definition at line 39 of file mmp_pdma.c.

#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */

Definition at line 45 of file mmp_pdma.c.

#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */

Definition at line 46 of file mmp_pdma.c.

#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */

Definition at line 37 of file mmp_pdma.c.

#define DCSR_EORINTR (1 << 9) /* The end of Receive */

Definition at line 47 of file mmp_pdma.c.

#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */

Definition at line 41 of file mmp_pdma.c.

#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */

Definition at line 42 of file mmp_pdma.c.

#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */

Definition at line 43 of file mmp_pdma.c.

#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */

Definition at line 33 of file mmp_pdma.c.

#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */

Definition at line 35 of file mmp_pdma.c.

#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */

Definition at line 32 of file mmp_pdma.c.

#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */

Definition at line 44 of file mmp_pdma.c.

#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */

Definition at line 38 of file mmp_pdma.c.

#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */

Definition at line 34 of file mmp_pdma.c.

#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */

Definition at line 36 of file mmp_pdma.c.

#define DDADR 0x0200

Definition at line 27 of file mmp_pdma.c.

#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */

Definition at line 52 of file mmp_pdma.c.

#define DDADR_STOP (1 << 0) /* Stop (read / write) */

Definition at line 53 of file mmp_pdma.c.

#define DINT 0x00f0

Definition at line 26 of file mmp_pdma.c.

#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */

Definition at line 50 of file mmp_pdma.c.

#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */

Definition at line 49 of file mmp_pdma.c.

#define DSADR 0x0204

Definition at line 28 of file mmp_pdma.c.

#define DTADR 0x0208

Definition at line 29 of file mmp_pdma.c.

#define PDMA_ALIGNMENT 3

Definition at line 70 of file mmp_pdma.c.

#define PDMA_MAX_DESC_BYTES 0x1000

Definition at line 71 of file mmp_pdma.c.

#define to_mmp_pdma_chan ( dchan ) container_of(dchan, struct mmp_pdma_chan, chan)

Definition at line 127 of file mmp_pdma.c.

#define to_mmp_pdma_desc ( lh ) container_of(lh, struct mmp_pdma_desc_sw, node)

Definition at line 126 of file mmp_pdma.c.

#define to_mmp_pdma_dev ( dmadev ) container_of(dmadev, struct mmp_pdma_device, device)

Definition at line 128 of file mmp_pdma.c.

#define tx_to_mmp_pdma_desc ( tx ) container_of(tx, struct mmp_pdma_desc_sw, async_tx)

Definition at line 125 of file mmp_pdma.c.

Function Documentation

struct mmp_pdma_desc_hw __aligned ( 32 )

struct mmp_pdma_desc_sw* mmp_pdma_alloc_descriptor ( struct mmp_pdma_chan * chan )

read

Definition at line 335 of file mmp_pdma.c.

MODULE_AUTHOR ( "Marvell International Ltd." )

MODULE_DESCRIPTION ( "MARVELL MMP Periphera DMA Driver" )

MODULE_DEVICE_TABLE	(	of	,
		mmp_pdma_dt_ids
	)

MODULE_LICENSE ( "GPL v2" )

module_platform_driver ( mmp_pdma_driver )

Variable Documentation

struct mmp_pdma_desc_sw __aligned

u32 dcmd

Definition at line 82 of file mmp_pdma.c.

u32 ddadr

Definition at line 79 of file mmp_pdma.c.

u32 dsadr

Definition at line 80 of file mmp_pdma.c.

u32 dtadr

Definition at line 81 of file mmp_pdma.c.

Data Structures

Macros

Functions

Variables

Macro Definition Documentation

Function Documentation

Variable Documentation