|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
#include <linux/module.h>#include <linux/kernel.h>#include <linux/string.h>#include <linux/timer.h>#include <linux/errno.h>#include <linux/ioport.h>#include <linux/slab.h>#include <linux/interrupt.h>#include <linux/pci.h>#include <linux/netdevice.h>#include <linux/etherdevice.h>#include <linux/skbuff.h>#include <linux/init.h>#include <linux/spinlock.h>#include <linux/ethtool.h>#include <linux/delay.h>#include <linux/rtnetlink.h>#include <linux/mii.h>#include <linux/crc32.h>#include <linux/bitops.h>#include <linux/prefetch.h>#include <asm/processor.h>#include <asm/io.h>#include <asm/irq.h>#include <asm/uaccess.h>Go to the source code of this file.
Data Structures | |
| struct | netdev_desc |
| struct | netdev_private |
Macros | |
| #define | DRV_NAME "natsemi" |
| #define | DRV_VERSION "2.1" |
| #define | DRV_RELDATE "Sept 11, 2006" |
| #define | RX_OFFSET 2 |
| #define | NATSEMI_DEF_MSG |
| #define | MAX_UNITS 8 /* More are supported, limit only on options */ |
| #define | TX_RING_SIZE 16 |
| #define | TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */ |
| #define | RX_RING_SIZE 32 |
| #define | TX_TIMEOUT (2*HZ) |
| #define | NATSEMI_HW_TIMEOUT 400 |
| #define | NATSEMI_TIMER_FREQ 5*HZ |
| #define | NATSEMI_PG0_NREGS 64 |
| #define | NATSEMI_RFDR_NREGS 8 |
| #define | NATSEMI_PG1_NREGS 4 |
| #define | NATSEMI_NREGS |
| #define | NATSEMI_REGS_VER 1 /* v1 added RFDR registers */ |
| #define | NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32)) |
| #define | NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */ |
| #define | NATSEMI_PADDING 16 /* 2 bytes should be sufficient */ |
| #define | NATSEMI_LONGPKT 1518 /* limit for normal packets */ |
| #define | NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */ |
| #define | PHYID_AM79C874 0x0022561b |
| #define | PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */ |
| #define | TSTDAT_VAL 0x0 |
| #define | DSPCFG_VAL 0x5040 |
| #define | SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */ |
| #define | DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */ |
| #define | DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */ |
| #define | TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */ |
| #define | DEFAULT_INTR 0x00f1cd65 |
| #define | TX_FLTH_VAL ((512/32) << 8) |
| #define | TX_DRTH_VAL_START (64/32) |
| #define | TX_DRTH_VAL_INC 2 |
| #define | TX_DRTH_VAL_LIMIT (1472/32) |
| #define | RX_DRTH_VAL (128/8) |
| #define | PHY_ADDR_NONE 32 |
| #define | PHY_ADDR_INTERNAL 1 |
| #define | SRR_DP83815_C 0x0302 |
| #define | SRR_DP83815_D 0x0403 |
| #define | SRR_DP83816_A4 0x0504 |
| #define | SRR_DP83816_A5 0x0505 |
| #define | NATSEMI_ATTR(_name) |
| #define | NATSEMI_CREATE_FILE(_dev, _name) device_create_file(&_dev->dev, &dev_attr_##_name) |
| #define | NATSEMI_REMOVE_FILE(_dev, _name) device_remove_file(&_dev->dev, &dev_attr_##_name) |
| #define | eeprom_delay(ee_addr) readl(ee_addr) |
| #define | EE_Write0 (EE_ChipSelect) |
| #define | EE_Write1 (EE_ChipSelect | EE_DataIn) |
| #define | mii_delay(ioaddr) readl(ioaddr + EECtrl) |
| #define | CFG_RESET_SAVE 0xfde000 |
| #define | WCSR_RESET_SAVE 0x61f |
| #define | RFCR_RESET_SAVE 0xf8500000 |
| #define | HASH_TABLE 0x200 |
| #define | SWAP_BITS(x) |
Enumerations | |
| enum | { MII_MCTRL = 0x15, MII_FX_SEL = 0x0001, MII_EN_SCRM = 0x0004 } |
| enum | { NATSEMI_FLAG_IGNORE_PHY = 0x1 } |
| enum | register_offsets { PCIDeviceConfig =0x50040, GenCtrl =0x50070, IntrTimerCtrl =0x50074, IntrClear =0x50080, IntrStatus =0x50084, IntrEnable =0x50088, MIICtrl =0x52000, TxStationAddr =0x50120, EEPROMCtrl =0x51000, GPIOCtrl =0x5008C, TxDescCtrl =0x50090, TxRingPtr =0x50098, HiPriTxRingPtr =0x50094, TxRingHiAddr =0x5009C, TxProducerIdx =0x500A0, TxConsumerIdx =0x500A4, TxThreshold =0x500B0, CompletionHiAddr =0x500B4, TxCompletionAddr =0x500B8, RxCompletionAddr =0x500BC, RxCompletionQ2Addr =0x500C0, CompletionQConsumerIdx =0x500C4, RxDMACtrl =0x500D0, RxDescQCtrl =0x500D4, RxDescQHiAddr =0x500DC, RxDescQAddr =0x500E0, RxDescQIdx =0x500E8, RxDMAStatus =0x500F0, RxFilterMode =0x500F4, TxMode =0x55000, VlanType =0x55064, PerfFilterTable =0x56000, HashTable =0x56100, TxGfpMem =0x58000, RxGfpMem =0x5a000, ChipCmd = 0x00, ChipConfig = 0x04, EECtrl = 0x08, PCIBusCfg = 0x0C, IntrStatus = 0x10, IntrMask = 0x14, IntrEnable = 0x18, IntrHoldoff = 0x1C, TxRingPtr = 0x20, TxConfig = 0x24, RxRingPtr = 0x30, RxConfig = 0x34, ClkRun = 0x3C, WOLCmd = 0x40, PauseCmd = 0x44, RxFilterAddr = 0x48, RxFilterData = 0x4C, BootRomAddr = 0x50, BootRomData = 0x54, SiliconRev = 0x58, StatsCtrl = 0x5C, StatsData = 0x60, RxPktErrs = 0x60, RxMissed = 0x68, RxCRCErrs = 0x64, BasicControl = 0x80, BasicStatus = 0x84, AnegAdv = 0x90, AnegPeer = 0x94, PhyStatus = 0xC0, MIntrCtrl = 0xC4, MIntrStatus = 0xC8, PhyCtrl = 0xE4, PGSEL = 0xCC, PMDCSR = 0xE4, TSTDAT = 0xFC, DSPCFG = 0xF4, SDCFG = 0xF8, StationAddr =0x00, RxConfig =0x06, TxConfig =0x07, ChipCmd =0x08, ChipCmd1 =0x09, TQWake =0x0A, IntrStatus =0x0C, IntrEnable =0x0E, MulticastFilter0 =0x10, MulticastFilter1 =0x14, RxRingPtr =0x18, TxRingPtr =0x1C, GFIFOTest =0x54, MIIPhyAddr =0x6C, MIIStatus =0x6D, PCIBusConfig =0x6E, PCIBusConfig1 =0x6F, MIICmd =0x70, MIIRegAddr =0x71, MIIData =0x72, MACRegEEcsr =0x74, ConfigA =0x78, ConfigB =0x79, ConfigC =0x7A, ConfigD =0x7B, RxMissed =0x7C, RxCRCErrs =0x7E, MiscCmd =0x81, StickyHW =0x83, IntrStatus2 =0x84, CamMask =0x88, CamCon =0x92, CamAddr =0x93, WOLcrSet =0xA0, PwcfgSet =0xA1, WOLcgSet =0xA3, WOLcrClr =0xA4, WOLcrClr1 =0xA6, WOLcgClr =0xA7, PwrcsrSet =0xA8, PwrcsrSet1 =0xA9, PwrcsrClr =0xAC, PwrcsrClr1 =0xAD, TxBufCount = 0x20, RxBufCount = 0x21, OpModes = 0x22, TxQed = 0x23, RxQed = 0x24, MaxBurst = 0x25, RxUnit = 0x60, EthStatus = 0x61, StationAddr0 = 0x67, EthStats = 0x69, LEDCtrl = 0x81 } |
| enum | pci_register_offsets { PCIPM = 0x44 } |
| enum | ChipCmd_bits { ChipReset = 0x100, RxReset = 0x20, TxReset = 0x10, RxOff = 0x08, RxOn = 0x04, TxOff = 0x02, TxOn = 0x01 } |
| enum | ChipConfig_bits { CfgPhyDis = 0x200, CfgPhyRst = 0x400, CfgExtPhy = 0x1000, CfgAnegEnable = 0x2000, CfgAneg100 = 0x4000, CfgAnegFull = 0x8000, CfgAnegDone = 0x8000000, CfgFullDuplex = 0x20000000, CfgSpeed100 = 0x40000000, CfgLink = 0x80000000 } |
| enum | EECtrl_bits { EE_ShiftClk = 0x04, EE_DataIn = 0x01, EE_ChipSelect = 0x08, EE_DataOut = 0x02, MII_Data = 0x10, MII_Write = 0x20, MII_ShiftClk = 0x40 } |
| enum | PCIBusCfg_bits { EepromReload = 0x4 } |
| enum | IntrStatus_bits { IntrRxDone = 0x0001, IntrRxIntr = 0x0002, IntrRxErr = 0x0004, IntrRxEarly = 0x0008, IntrRxIdle = 0x0010, IntrRxOverrun = 0x0020, IntrTxDone = 0x0040, IntrTxIntr = 0x0080, IntrTxErr = 0x0100, IntrTxIdle = 0x0200, IntrTxUnderrun = 0x0400, StatsMax = 0x0800, SWInt = 0x1000, WOLPkt = 0x2000, LinkChange = 0x4000, IntrHighBits = 0x8000, RxStatusFIFOOver = 0x10000, IntrPCIErr = 0xf00000, RxResetDone = 0x1000000, TxResetDone = 0x2000000, IntrAbnormalSummary = 0xCD20 } |
| enum | TxConfig_bits { TxDrthMask = 0x3f, TxFlthMask = 0x3f00, TxMxdmaMask = 0x700000, TxMxdma_512 = 0x0, TxMxdma_4 = 0x100000, TxMxdma_8 = 0x200000, TxMxdma_16 = 0x300000, TxMxdma_32 = 0x400000, TxMxdma_64 = 0x500000, TxMxdma_128 = 0x600000, TxMxdma_256 = 0x700000, TxCollRetry = 0x800000, TxAutoPad = 0x10000000, TxMacLoop = 0x20000000, TxHeartIgn = 0x40000000, TxCarrierIgn = 0x80000000 } |
| enum | RxConfig_bits { RxDrthMask = 0x3e, RxMxdmaMask = 0x700000, RxMxdma_512 = 0x0, RxMxdma_4 = 0x100000, RxMxdma_8 = 0x200000, RxMxdma_16 = 0x300000, RxMxdma_32 = 0x400000, RxMxdma_64 = 0x500000, RxMxdma_128 = 0x600000, RxMxdma_256 = 0x700000, RxAcceptLong = 0x8000000, RxAcceptTx = 0x10000000, RxAcceptRunt = 0x40000000, RxAcceptErr = 0x80000000 } |
| enum | ClkRun_bits { PMEEnable = 0x100, PMEStatus = 0x8000 } |
| enum | WolCmd_bits { WakePhy = 0x1, WakeUnicast = 0x2, WakeMulticast = 0x4, WakeBroadcast = 0x8, WakeArp = 0x10, WakePMatch0 = 0x20, WakePMatch1 = 0x40, WakePMatch2 = 0x80, WakePMatch3 = 0x100, WakeMagic = 0x200, WakeMagicSecure = 0x400, SecureHack = 0x100000, WokePhy = 0x400000, WokeUnicast = 0x800000, WokeMulticast = 0x1000000, WokeBroadcast = 0x2000000, WokeArp = 0x4000000, WokePMatch0 = 0x8000000, WokePMatch1 = 0x10000000, WokePMatch2 = 0x20000000, WokePMatch3 = 0x40000000, WokeMagic = 0x80000000, WakeOptsSummary = 0x7ff } |
| enum | RxFilterAddr_bits { RFCRAddressMask = 0x3ff, AcceptMulticast = 0x00200000, AcceptMyPhys = 0x08000000, AcceptAllPhys = 0x10000000, AcceptAllMulticast = 0x20000000, AcceptBroadcast = 0x40000000, RxFilterEnable = 0x80000000 } |
| enum | StatsCtrl_bits { StatsWarn = 0x1, StatsFreeze = 0x2, StatsClear = 0x4, StatsStrobe = 0x8 } |
| enum | MIntrCtrl_bits { MICRIntEn = 0x2 } |
| enum | PhyCtrl_bits { PhyAddrMask = 0x1f } |
| enum | desc_status_bits { DescOwned = 0x80000000, DescWholePkt = 0x60000000, DescEndPkt = 0x40000000, DescStartPkt = 0x20000000, DescEndRing = 0x02000000, DescUseLink = 0x01000000, RxDescErrorSummary = 0x8000, RxDescCRCError = 0x0002, RxDescCollisionSeen = 0x0040, RxDescFrameTooLong = 0x0080, RxDescRunt = 0x0800, RxDescDescErr = 0x4000, RxWholePkt = 0x00000300, RxLengthOver2047 = 0x38000010, DescOwn =0x8000, DescEndPacket =0x4000, DescEndRing =0x2000, LastFrag =0x80000000, DescIntrOnTx =0x8000, DescIntrOnDMADone =0x80000000, DisableAlign = 0x00000001, DescOwn =0x80000000, DescMore =0x40000000, DescIntr =0x20000000, DescNoCRC =0x10000000, DescPktOK =0x08000000, DescSizeMask =0xfff, DescTxAbort =0x04000000, DescTxFIFO =0x02000000, DescTxCarrier =0x01000000, DescTxDefer =0x00800000, DescTxExcDefer =0x00400000, DescTxOOWCol =0x00200000, DescTxExcColl =0x00100000, DescTxCollCount =0x000f0000, DescRxAbort =0x04000000, DescRxOver =0x02000000, DescRxDest =0x01800000, DescRxLong =0x00400000, DescRxRunt =0x00200000, DescRxInvalid =0x00100000, DescRxCRC =0x00080000, DescRxAlign =0x00040000, DescRxLoop =0x00020000, DesRxColl =0x00010000, DescOwn =0x80000000, DescEndPacket =0x40000000, DescEndRing =0x20000000, DescIntr =0x10000000, RX_EOP =0x0040, DescOwn =0x8000, DescOwn =0x80000000 } |
| enum | EEPROM_Cmds { EE_WriteCmd =(5 << 6), EE_ReadCmd =(6 << 6), EE_EraseCmd =(7 << 6), EE_WriteCmd =(5 << 6), EE_ReadCmd =(6 << 6), EE_EraseCmd =(7 << 6) } |
Functions | |
| MODULE_AUTHOR ("Donald Becker <[email protected]>") | |
| MODULE_DESCRIPTION ("National Semiconductor DP8381x series PCI Ethernet driver") | |
| MODULE_LICENSE ("GPL") | |
| module_param (mtu, int, 0) | |
| module_param (debug, int, 0) | |
| module_param (rx_copybreak, int, 0) | |
| module_param (dspcfg_workaround, int, 0) | |
| module_param_array (options, int, NULL, 0) | |
| module_param_array (full_duplex, int, NULL, 0) | |
| MODULE_PARM_DESC (mtu,"DP8381x MTU (all boards)") | |
| MODULE_PARM_DESC (debug,"DP8381x default debug level") | |
| MODULE_PARM_DESC (rx_copybreak,"DP8381x copy breakpoint for copy-only-tiny-frames") | |
| MODULE_PARM_DESC (dspcfg_workaround,"DP8381x: control DspCfg workaround") | |
| MODULE_PARM_DESC (options,"DP8381x: Bits 0-3: media type, bit 17: full duplex") | |
| MODULE_PARM_DESC (full_duplex,"DP8381x full duplex setting(s) (1)") | |
| MODULE_DEVICE_TABLE (pci, natsemi_pci_tbl) | |
| NATSEMI_ATTR (dspcfg_workaround) | |
| module_init (natsemi_init_mod) | |
| module_exit (natsemi_exit_mod) | |
| #define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */ |
| #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */ |
| #define EE_Write0 (EE_ChipSelect) |
| #define EE_Write1 (EE_ChipSelect | EE_DataIn) |
| #define NATSEMI_ATTR | ( | _name | ) |
| #define NATSEMI_CREATE_FILE | ( | _dev, | |
| _name | |||
| ) | device_create_file(&_dev->dev, &dev_attr_##_name) |
| #define NATSEMI_DEF_MSG |
| #define NATSEMI_NREGS |
| #define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32)) |
| #define NATSEMI_REMOVE_FILE | ( | _dev, | |
| _name | |||
| ) | device_remove_file(&_dev->dev, &dev_attr_##_name) |
| #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */ |
| #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */ |
| #define SWAP_BITS | ( | x | ) |
| #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */ |
| anonymous enum |
| enum ChipCmd_bits |
| enum ChipConfig_bits |
| enum ClkRun_bits |
| enum desc_status_bits |
| enum EECtrl_bits |
| enum EEPROM_Cmds |
| enum IntrStatus_bits |
| enum MIntrCtrl_bits |
| enum pci_register_offsets |
| enum PCIBusCfg_bits |
| enum PhyCtrl_bits |
| enum register_offsets |
| enum RxConfig_bits |
| enum RxFilterAddr_bits |
| enum StatsCtrl_bits |
| enum TxConfig_bits |
| enum WolCmd_bits |
| MODULE_AUTHOR | ( | "Donald Becker <[email protected]>" | ) |
| MODULE_DEVICE_TABLE | ( | pci | , |
| natsemi_pci_tbl | |||
| ) |
| module_exit | ( | natsemi_exit_mod | ) |
| module_init | ( | natsemi_init_mod | ) |
| MODULE_LICENSE | ( | "GPL" | ) |
| module_param | ( | mtu | , |
| int | , | ||
| 0 | |||
| ) |
| module_param | ( | rx_copybreak | , |
| int | , | ||
| 0 | |||
| ) |
| module_param | ( | dspcfg_workaround | , |
| int | , | ||
| 0 | |||
| ) |
| MODULE_PARM_DESC | ( | mtu | , |
| "DP8381x MTU (all boards)" | |||
| ) |
| MODULE_PARM_DESC | ( | rx_copybreak | , |
| "DP8381x copy breakpoint for copy-only-tiny-frames" | |||
| ) |
| MODULE_PARM_DESC | ( | dspcfg_workaround | , |
| "DP8381x: control DspCfg workaround" | |||
| ) |
| NATSEMI_ATTR | ( | dspcfg_workaround | ) |
1.8.2