|
| enum | chip_capability_flags {
CanHaveMII =1,
CanHaveMII =1,
HasBrokenTx =2,
AlwaysFDX =4,
FDXOnNoMII =8,
HAS_MII_XCVR,
HAS_CHIP_XCVR,
MII_PWRDWN =1,
TYPE2_INTR =2,
NO_MII =4
} |
| |
| enum | chipset { CH_6915 = 0
} |
| |
| enum | register_offsets {
PCIDeviceConfig =0x50040,
GenCtrl =0x50070,
IntrTimerCtrl =0x50074,
IntrClear =0x50080,
IntrStatus =0x50084,
IntrEnable =0x50088,
MIICtrl =0x52000,
TxStationAddr =0x50120,
EEPROMCtrl =0x51000,
GPIOCtrl =0x5008C,
TxDescCtrl =0x50090,
TxRingPtr =0x50098,
HiPriTxRingPtr =0x50094,
TxRingHiAddr =0x5009C,
TxProducerIdx =0x500A0,
TxConsumerIdx =0x500A4,
TxThreshold =0x500B0,
CompletionHiAddr =0x500B4,
TxCompletionAddr =0x500B8,
RxCompletionAddr =0x500BC,
RxCompletionQ2Addr =0x500C0,
CompletionQConsumerIdx =0x500C4,
RxDMACtrl =0x500D0,
RxDescQCtrl =0x500D4,
RxDescQHiAddr =0x500DC,
RxDescQAddr =0x500E0,
RxDescQIdx =0x500E8,
RxDMAStatus =0x500F0,
RxFilterMode =0x500F4,
TxMode =0x55000,
VlanType =0x55064,
PerfFilterTable =0x56000,
HashTable =0x56100,
TxGfpMem =0x58000,
RxGfpMem =0x5a000,
ChipCmd = 0x00,
ChipConfig = 0x04,
EECtrl = 0x08,
PCIBusCfg = 0x0C,
IntrStatus = 0x10,
IntrMask = 0x14,
IntrEnable = 0x18,
IntrHoldoff = 0x1C,
TxRingPtr = 0x20,
TxConfig = 0x24,
RxRingPtr = 0x30,
RxConfig = 0x34,
ClkRun = 0x3C,
WOLCmd = 0x40,
PauseCmd = 0x44,
RxFilterAddr = 0x48,
RxFilterData = 0x4C,
BootRomAddr = 0x50,
BootRomData = 0x54,
SiliconRev = 0x58,
StatsCtrl = 0x5C,
StatsData = 0x60,
RxPktErrs = 0x60,
RxMissed = 0x68,
RxCRCErrs = 0x64,
BasicControl = 0x80,
BasicStatus = 0x84,
AnegAdv = 0x90,
AnegPeer = 0x94,
PhyStatus = 0xC0,
MIntrCtrl = 0xC4,
MIntrStatus = 0xC8,
PhyCtrl = 0xE4,
PGSEL = 0xCC,
PMDCSR = 0xE4,
TSTDAT = 0xFC,
DSPCFG = 0xF4,
SDCFG = 0xF8,
StationAddr =0x00,
RxConfig =0x06,
TxConfig =0x07,
ChipCmd =0x08,
ChipCmd1 =0x09,
TQWake =0x0A,
IntrStatus =0x0C,
IntrEnable =0x0E,
MulticastFilter0 =0x10,
MulticastFilter1 =0x14,
RxRingPtr =0x18,
TxRingPtr =0x1C,
GFIFOTest =0x54,
MIIPhyAddr =0x6C,
MIIStatus =0x6D,
PCIBusConfig =0x6E,
PCIBusConfig1 =0x6F,
MIICmd =0x70,
MIIRegAddr =0x71,
MIIData =0x72,
MACRegEEcsr =0x74,
ConfigA =0x78,
ConfigB =0x79,
ConfigC =0x7A,
ConfigD =0x7B,
RxMissed =0x7C,
RxCRCErrs =0x7E,
MiscCmd =0x81,
StickyHW =0x83,
IntrStatus2 =0x84,
CamMask =0x88,
CamCon =0x92,
CamAddr =0x93,
WOLcrSet =0xA0,
PwcfgSet =0xA1,
WOLcgSet =0xA3,
WOLcrClr =0xA4,
WOLcrClr1 =0xA6,
WOLcgClr =0xA7,
PwrcsrSet =0xA8,
PwrcsrSet1 =0xA9,
PwrcsrClr =0xAC,
PwrcsrClr1 =0xAD,
TxBufCount = 0x20,
RxBufCount = 0x21,
OpModes = 0x22,
TxQed = 0x23,
RxQed = 0x24,
MaxBurst = 0x25,
RxUnit = 0x60,
EthStatus = 0x61,
StationAddr0 = 0x67,
EthStats = 0x69,
LEDCtrl = 0x81
} |
| |
| enum | intr_status_bits {
IntrLinkChange =0xf0000000,
IntrStatsMax =0x08000000,
IntrAbnormalSummary =0x02000000,
IntrGeneralTimer =0x01000000,
IntrSoftware =0x800000,
IntrRxComplQ1Low =0x400000,
IntrTxComplQLow =0x200000,
IntrPCI =0x100000,
IntrDMAErr =0x080000,
IntrTxDataLow =0x040000,
IntrRxComplQ2Low =0x020000,
IntrRxDescQ1Low =0x010000,
IntrNormalSummary =0x8000,
IntrTxDone =0x4000,
IntrTxDMADone =0x2000,
IntrTxEmpty =0x1000,
IntrEarlyRxQ2 =0x0800,
IntrEarlyRxQ1 =0x0400,
IntrRxQ2Done =0x0200,
IntrRxQ1Done =0x0100,
IntrRxGFPDead =0x80,
IntrRxDescQ2Low =0x40,
IntrNoTxCsum =0x20,
IntrTxBadID =0x10,
IntrHiPriTxBadID =0x08,
IntrRxGfp =0x04,
IntrTxGfp =0x02,
IntrPCIPad =0x01,
IntrRxDone =IntrRxQ2Done | IntrRxQ1Done,
IntrRxEmpty =IntrRxDescQ1Low | IntrRxDescQ2Low,
IntrNormalMask =0xff00,
IntrAbnormalMask =0x3ff00fe,
IntrSummary =0x0001,
IntrPCIErr =0x0002,
IntrMACCtrl =0x0008,
IntrTxDone =0x0004,
IntrRxDone =0x0010,
IntrRxStart =0x0020,
IntrDrvRqst =0x0040,
StatsMax =0x0080,
LinkChange =0x0100,
IntrTxDMADone =0x0200,
IntrRxDMADone =0x0400,
RFCON = 0x00020000,
RFCOFF = 0x00010000,
LSCStatus = 0x00008000,
ANCStatus = 0x00004000,
FBE = 0x00002000,
FBEMask = 0x00001800,
ParityErr = 0x00000000,
TargetErr = 0x00001000,
MasterErr = 0x00000800,
TUNF = 0x00000400,
ROVF = 0x00000200,
ETI = 0x00000100,
ERI = 0x00000080,
CNTOVF = 0x00000040,
RBU = 0x00000020,
TBU = 0x00000010,
TI = 0x00000008,
RI = 0x00000004,
RxErr = 0x00000002,
IntrRxDone =0x01,
IntrRxPCIFault =0x02,
IntrRxPCIErr =0x04,
IntrTxDone =0x100,
IntrTxPCIFault =0x200,
IntrTxPCIErr =0x400,
LinkChange =0x10000,
NegotiationChange =0x20000,
StatsMax =0x40000,
IntrRxDone =0x01,
IntrRxInvalid =0x02,
IntrRxPCIFault =0x04,
IntrRxPCIErr =0x08,
IntrTxDone =0x10,
IntrTxInvalid =0x20,
IntrTxPCIFault =0x40,
IntrTxPCIErr =0x80,
IntrEarlyRx =0x100,
IntrWakeup =0x200,
IntrRxDone = 0x0001,
IntrTxDone = 0x0002,
IntrRxErr = 0x0004,
IntrTxError = 0x0008,
IntrRxEmpty = 0x0020,
IntrPCIErr = 0x0040,
IntrStatsMax = 0x0080,
IntrRxEarly = 0x0100,
IntrTxUnderrun = 0x0210,
IntrRxOverflow = 0x0400,
IntrRxDropped = 0x0800,
IntrRxNoBuf = 0x1000,
IntrTxAborted = 0x2000,
IntrLinkChange = 0x4000,
IntrRxWakeUp = 0x8000,
IntrTxDescRace = 0x080000,
IntrNormalSummary = IntrRxDone | IntrTxDone,
IntrTxErrSummary
} |
| |
| enum | rx_mode_bits {
AcceptBroadcast =0x04,
AcceptAllMulticast =0x02,
AcceptAll =0x01,
AcceptMulticast =0x10,
PerfectFilter =0x40,
HashFilter =0x30,
PerfectFilterVlan =0x80,
MinVLANPrio =0xE000,
VlanMode =0x0200,
WakeupOnGFP =0x0800,
AcceptErr =0x80,
RxAcceptBroadcast =0x20,
AcceptMulticast =0x10,
RxAcceptAllPhys =0x08,
AcceptMyPhys =0x02,
AcceptAllIPMulti =0x20,
AcceptMultiHash =0x10,
AcceptAll =0x08,
AcceptBroadcast =0x04,
AcceptMulticast =0x02,
AcceptMyPhys =0x01,
CR_W_ENH = 0x02000000,
CR_W_FD = 0x00100000,
CR_W_PS10 = 0x00080000,
CR_W_TXEN = 0x00040000,
CR_W_PS1000 = 0x00010000,
CR_W_RXMODEMASK = 0x000000e0,
CR_W_PROM = 0x00000080,
CR_W_AB = 0x00000040,
CR_W_AM = 0x00000020,
CR_W_ARP = 0x00000008,
CR_W_ALP = 0x00000004,
CR_W_SEP = 0x00000002,
CR_W_RXEN = 0x00000001,
CR_R_TXSTOP = 0x04000000,
CR_R_FD = 0x00100000,
CR_R_PS10 = 0x00080000,
CR_R_RXSTOP = 0x00008000,
AcceptErr = 0x20,
AcceptRunt = 0x10,
AcceptBroadcast = 0x08,
AcceptMulticast = 0x04,
AcceptMyPhys = 0x02,
AcceptAllPhys = 0x01
} |
| |
| enum | tx_mode_bits {
MiiSoftReset =0x8000,
MIILoopback =0x4000,
TxFlowEnable =0x0800,
RxFlowEnable =0x0400,
PadEnable =0x04,
FullDuplex =0x02,
HugeFrame =0x01
} |
| |
| enum | tx_ctrl_bits {
TxDescSpaceUnlim =0x00,
TxDescSpace32 =0x10,
TxDescSpace64 =0x20,
TxDescSpace128 =0x30,
TxDescSpace256 =0x40,
TxDescType0 =0x00,
TxDescType1 =0x01,
TxDescType2 =0x02,
TxDescType3 =0x03,
TxDescType4 =0x04,
TxNoDMACompletion =0x08,
TxDescQAddr64bit =0x80,
TxDescQAddr32bit =0,
TxHiPriFIFOThreshShift =24,
TxPadLenShift =16,
TxDMABurstSizeShift =8
} |
| |
| enum | rx_ctrl_bits {
RxBufferLenShift =16,
RxMinDescrThreshShift =0,
RxPrefetchMode =0x8000,
RxVariableQ =0x2000,
Rx2048QEntries =0x4000,
Rx256QEntries =0,
RxDescAddr64bit =0x1000,
RxDescAddr32bit =0,
RxDescQAddr64bit =0x0100,
RxDescQAddr32bit =0,
RxDescSpace4 =0x000,
RxDescSpace8 =0x100,
RxDescSpace16 =0x200,
RxDescSpace32 =0x300,
RxDescSpace64 =0x400,
RxDescSpace128 =0x500,
RxConsumerWrEn =0x80
} |
| |
| enum | rx_dmactrl_bits {
RxReportBadFrames =0x80000000,
RxDMAShortFrames =0x40000000,
RxDMABadFrames =0x20000000,
RxDMACrcErrorFrames =0x10000000,
RxDMAControlFrame =0x08000000,
RxDMAPauseFrame =0x04000000,
RxChecksumIgnore =0,
RxChecksumRejectTCPUDP =0x02000000,
RxChecksumRejectTCPOnly =0x01000000,
RxCompletionQ2Enable =0x800000,
RxDMAQ2Disable =0,
RxDMAQ2FPOnly =0x100000,
RxDMAQ2SmallPkt =0x200000,
RxDMAQ2HighPrio =0x300000,
RxDMAQ2NonIP =0x400000,
RxUseBackupQueue =0x080000,
RxDMACRC =0x040000,
RxEarlyIntThreshShift =12,
RxHighPrioThreshShift =8,
RxBurstSizeShift =0
} |
| |
| enum | rx_compl_bits {
RxComplQAddr64bit =0x80,
RxComplQAddr32bit =0,
RxComplProducerWrEn =0x40,
RxComplType0 =0x00,
RxComplType1 =0x10,
RxComplType2 =0x20,
RxComplType3 =0x30,
RxComplThreshShift =0
} |
| |
| enum | tx_compl_bits {
TxComplQAddr64bit =0x80,
TxComplQAddr32bit =0,
TxComplProducerWrEn =0x40,
TxComplIntrStatus =0x20,
CommonQueueMode =0x10,
TxComplThreshShift =0
} |
| |
| enum | gen_ctrl_bits { RxEnable =0x05,
TxEnable =0x0a,
RxGFPEnable =0x10,
TxGFPEnable =0x20
} |
| |
| enum | intr_ctrl_bits {
Timer10X =0x800,
EnableIntrMasking =0x60,
SmallFrameBypass =0x100,
SmallFrame64 =0,
SmallFrame128 =0x200,
SmallFrame256 =0x400,
SmallFrame512 =0x600,
IntrLatencyMask =0x1f
} |
| |
| enum | rx_desc_bits { RxDescValid =1,
RxDescEndRing =2
} |
| |
| enum | rx_done_bits { RxOK =0x20000000,
RxFIFOErr =0x10000000,
RxBufQ2 =0x08000000
} |
| |
| enum | tx_desc_bits {
TxDescID =0xB0000000,
TxCRCEn =0x01000000,
TxDescIntr =0x08000000,
TxRingWrap =0x04000000,
TxCalTCP =0x02000000
} |
| |
|
| | MODULE_AUTHOR ("Donald Becker <[email protected]>") |
| |
| | MODULE_DESCRIPTION ("Adaptec Starfire Ethernet driver") |
| |
| | MODULE_LICENSE ("GPL") |
| |
| | MODULE_VERSION (DRV_VERSION) |
| |
| | MODULE_FIRMWARE (FIRMWARE_RX) |
| |
| | MODULE_FIRMWARE (FIRMWARE_TX) |
| |
| | module_param (max_interrupt_work, int, 0) |
| |
| | module_param (mtu, int, 0) |
| |
| | module_param (debug, int, 0) |
| |
| | module_param (rx_copybreak, int, 0) |
| |
| | module_param (intr_latency, int, 0) |
| |
| | module_param (small_frames, int, 0) |
| |
| | module_param (enable_hw_cksum, int, 0) |
| |
| | MODULE_PARM_DESC (max_interrupt_work,"Maximum events handled per interrupt") |
| |
| | MODULE_PARM_DESC (mtu,"MTU (all boards)") |
| |
| | MODULE_PARM_DESC (debug,"Debug level (0-6)") |
| |
| | MODULE_PARM_DESC (rx_copybreak,"Copy breakpoint for copy-only-tiny-frames") |
| |
| | MODULE_PARM_DESC (intr_latency,"Maximum interrupt latency, in microseconds") |
| |
| | MODULE_PARM_DESC (small_frames,"Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)") |
| |
| | MODULE_PARM_DESC (enable_hw_cksum,"Enable/disable hardware cksum support (0/1)") |
| |
| | MODULE_DEVICE_TABLE (pci, starfire_pci_tbl) |
| |
| | module_init (starfire_init) |
| |
| | module_exit (starfire_cleanup) |
| |
1.8.2