Linux Kernel
3.7.1
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#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/init.h>
#include <linux/bitops.h>
#include <asm/uaccess.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/dma-mapping.h>
#include <linux/crc32.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
Go to the source code of this file.
Data Structures | |
struct | pci_id_info |
struct | netdev_desc |
struct | netdev_desc::desc_frag |
struct | netdev_private |
Macros | |
#define | DRV_NAME "sundance" |
#define | DRV_VERSION "1.2" |
#define | DRV_RELDATE "11-Sep-2006" |
#define | MAX_UNITS 8 |
#define | TX_RING_SIZE 32 |
#define | TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used. */ |
#define | RX_RING_SIZE 64 |
#define | RX_BUDGET 32 |
#define | TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc) |
#define | RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc) |
#define | TX_TIMEOUT (4*HZ) |
#define | PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ |
#define | USE_IO_OPS 1 |
#define | ASIC_HI_WORD(x) ((x) + 2) |
#define | PRIV_ALIGN 15 /* Required alignment mask */ |
#define | MII_CNT 4 |
#define | EEPROM_SA_OFFSET 0x10 |
#define | DEFAULT_INTR |
#define | eeprom_delay(ee_addr) ioread32(ee_addr) |
#define | mdio_delay() ioread8(mdio_addr) |
#define | MDIO_EnbIn (0) |
#define | MDIO_WRITE0 (MDIO_EnbOutput) |
#define | MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput) |
Enumerations | |
enum | { netdev_io_size = 128 } |
enum | alta_offsets { DMACtrl = 0x00, TxListPtr = 0x04, TxDMABurstThresh = 0x08, TxDMAUrgentThresh = 0x09, TxDMAPollPeriod = 0x0a, RxDMAStatus = 0x0c, RxListPtr = 0x10, DebugCtrl0 = 0x1a, DebugCtrl1 = 0x1c, RxDMABurstThresh = 0x14, RxDMAUrgentThresh = 0x15, RxDMAPollPeriod = 0x16, LEDCtrl = 0x1a, ASICCtrl = 0x30, EEData = 0x34, EECtrl = 0x36, FlashAddr = 0x40, FlashData = 0x44, TxStatus = 0x46, TxFrameId = 0x47, DownCounter = 0x18, IntrClear = 0x4a, IntrEnable = 0x4c, IntrStatus = 0x4e, MACCtrl0 = 0x50, MACCtrl1 = 0x52, StationAddr = 0x54, MaxFrameSize = 0x5A, RxMode = 0x5c, MIICtrl = 0x5e, MulticastFilter0 = 0x60, MulticastFilter1 = 0x64, RxOctetsLow = 0x68, RxOctetsHigh = 0x6a, TxOctetsLow = 0x6c, TxOctetsHigh = 0x6e, TxFramesOK = 0x70, RxFramesOK = 0x72, StatsCarrierError = 0x74, StatsLateColl = 0x75, StatsMultiColl = 0x76, StatsOneColl = 0x77, StatsTxDefer = 0x78, RxMissed = 0x79, StatsTxXSDefer = 0x7a, StatsTxAbort = 0x7b, StatsBcastTx = 0x7c, StatsBcastRx = 0x7d, StatsMcastTx = 0x7e, StatsMcastRx = 0x7f, RxStatus = 0x0c } |
enum | ASICCtrl_HiWord_bit { GlobalReset = 0x0001, RxReset = 0x0002, TxReset = 0x0004, DMAReset = 0x0008, FIFOReset = 0x0010, NetworkReset = 0x0020, HostReset = 0x0040, ResetBusy = 0x0400 } |
enum | intr_status_bits { IntrLinkChange =0xf0000000, IntrStatsMax =0x08000000, IntrAbnormalSummary =0x02000000, IntrGeneralTimer =0x01000000, IntrSoftware =0x800000, IntrRxComplQ1Low =0x400000, IntrTxComplQLow =0x200000, IntrPCI =0x100000, IntrDMAErr =0x080000, IntrTxDataLow =0x040000, IntrRxComplQ2Low =0x020000, IntrRxDescQ1Low =0x010000, IntrNormalSummary =0x8000, IntrTxDone =0x4000, IntrTxDMADone =0x2000, IntrTxEmpty =0x1000, IntrEarlyRxQ2 =0x0800, IntrEarlyRxQ1 =0x0400, IntrRxQ2Done =0x0200, IntrRxQ1Done =0x0100, IntrRxGFPDead =0x80, IntrRxDescQ2Low =0x40, IntrNoTxCsum =0x20, IntrTxBadID =0x10, IntrHiPriTxBadID =0x08, IntrRxGfp =0x04, IntrTxGfp =0x02, IntrPCIPad =0x01, IntrRxDone =IntrRxQ2Done | IntrRxQ1Done, IntrRxEmpty =IntrRxDescQ1Low | IntrRxDescQ2Low, IntrNormalMask =0xff00, IntrAbnormalMask =0x3ff00fe, IntrSummary =0x0001, IntrPCIErr =0x0002, IntrMACCtrl =0x0008, IntrTxDone =0x0004, IntrRxDone =0x0010, IntrRxStart =0x0020, IntrDrvRqst =0x0040, StatsMax =0x0080, LinkChange =0x0100, IntrTxDMADone =0x0200, IntrRxDMADone =0x0400, RFCON = 0x00020000, RFCOFF = 0x00010000, LSCStatus = 0x00008000, ANCStatus = 0x00004000, FBE = 0x00002000, FBEMask = 0x00001800, ParityErr = 0x00000000, TargetErr = 0x00001000, MasterErr = 0x00000800, TUNF = 0x00000400, ROVF = 0x00000200, ETI = 0x00000100, ERI = 0x00000080, CNTOVF = 0x00000040, RBU = 0x00000020, TBU = 0x00000010, TI = 0x00000008, RI = 0x00000004, RxErr = 0x00000002, IntrRxDone =0x01, IntrRxPCIFault =0x02, IntrRxPCIErr =0x04, IntrTxDone =0x100, IntrTxPCIFault =0x200, IntrTxPCIErr =0x400, LinkChange =0x10000, NegotiationChange =0x20000, StatsMax =0x40000, IntrRxDone =0x01, IntrRxInvalid =0x02, IntrRxPCIFault =0x04, IntrRxPCIErr =0x08, IntrTxDone =0x10, IntrTxInvalid =0x20, IntrTxPCIFault =0x40, IntrTxPCIErr =0x80, IntrEarlyRx =0x100, IntrWakeup =0x200, IntrRxDone = 0x0001, IntrTxDone = 0x0002, IntrRxErr = 0x0004, IntrTxError = 0x0008, IntrRxEmpty = 0x0020, IntrPCIErr = 0x0040, IntrStatsMax = 0x0080, IntrRxEarly = 0x0100, IntrTxUnderrun = 0x0210, IntrRxOverflow = 0x0400, IntrRxDropped = 0x0800, IntrRxNoBuf = 0x1000, IntrTxAborted = 0x2000, IntrLinkChange = 0x4000, IntrRxWakeUp = 0x8000, IntrTxDescRace = 0x080000, IntrNormalSummary = IntrRxDone | IntrTxDone, IntrTxErrSummary } |
enum | rx_mode_bits { AcceptBroadcast =0x04, AcceptAllMulticast =0x02, AcceptAll =0x01, AcceptMulticast =0x10, PerfectFilter =0x40, HashFilter =0x30, PerfectFilterVlan =0x80, MinVLANPrio =0xE000, VlanMode =0x0200, WakeupOnGFP =0x0800, AcceptErr =0x80, RxAcceptBroadcast =0x20, AcceptMulticast =0x10, RxAcceptAllPhys =0x08, AcceptMyPhys =0x02, AcceptAllIPMulti =0x20, AcceptMultiHash =0x10, AcceptAll =0x08, AcceptBroadcast =0x04, AcceptMulticast =0x02, AcceptMyPhys =0x01, CR_W_ENH = 0x02000000, CR_W_FD = 0x00100000, CR_W_PS10 = 0x00080000, CR_W_TXEN = 0x00040000, CR_W_PS1000 = 0x00010000, CR_W_RXMODEMASK = 0x000000e0, CR_W_PROM = 0x00000080, CR_W_AB = 0x00000040, CR_W_AM = 0x00000020, CR_W_ARP = 0x00000008, CR_W_ALP = 0x00000004, CR_W_SEP = 0x00000002, CR_W_RXEN = 0x00000001, CR_R_TXSTOP = 0x04000000, CR_R_FD = 0x00100000, CR_R_PS10 = 0x00080000, CR_R_RXSTOP = 0x00008000, AcceptErr = 0x20, AcceptRunt = 0x10, AcceptBroadcast = 0x08, AcceptMulticast = 0x04, AcceptMyPhys = 0x02, AcceptAllPhys = 0x01 } |
enum | mac_ctrl0_bits { EnbFullDuplex =0x20, EnbRcvLargeFrame =0x40, EnbFlowCtrl =0x100, EnbPassRxCRC =0x200 } |
enum | mac_ctrl1_bits { StatsEnable =0x0020, StatsDisable =0x0040, StatsEnabled =0x0080, TxEnable =0x0100, TxDisable =0x0200, TxEnabled =0x0400, RxEnable =0x0800, RxDisable =0x1000, RxEnabled =0x2000 } |
enum | desc_status_bits { DescOwned = 0x80000000, DescWholePkt = 0x60000000, DescEndPkt = 0x40000000, DescStartPkt = 0x20000000, DescEndRing = 0x02000000, DescUseLink = 0x01000000, RxDescErrorSummary = 0x8000, RxDescCRCError = 0x0002, RxDescCollisionSeen = 0x0040, RxDescFrameTooLong = 0x0080, RxDescRunt = 0x0800, RxDescDescErr = 0x4000, RxWholePkt = 0x00000300, RxLengthOver2047 = 0x38000010, DescOwn =0x8000, DescEndPacket =0x4000, DescEndRing =0x2000, LastFrag =0x80000000, DescIntrOnTx =0x8000, DescIntrOnDMADone =0x80000000, DisableAlign = 0x00000001, DescOwn =0x80000000, DescMore =0x40000000, DescIntr =0x20000000, DescNoCRC =0x10000000, DescPktOK =0x08000000, DescSizeMask =0xfff, DescTxAbort =0x04000000, DescTxFIFO =0x02000000, DescTxCarrier =0x01000000, DescTxDefer =0x00800000, DescTxExcDefer =0x00400000, DescTxOOWCol =0x00200000, DescTxExcColl =0x00100000, DescTxCollCount =0x000f0000, DescRxAbort =0x04000000, DescRxOver =0x02000000, DescRxDest =0x01800000, DescRxLong =0x00400000, DescRxRunt =0x00200000, DescRxInvalid =0x00100000, DescRxCRC =0x00080000, DescRxAlign =0x00040000, DescRxLoop =0x00020000, DesRxColl =0x00010000, DescOwn =0x80000000, DescEndPacket =0x40000000, DescEndRing =0x20000000, DescIntr =0x10000000, RX_EOP =0x0040, DescOwn =0x8000, DescOwn =0x80000000 } |
enum | mii_reg_bits { MDIO_ShiftClk =0x10000, MDIO_DataIn =0x80000, MDIO_DataOut =0x20000, MDIO_EnbOutput =0x40000, MDIO_EnbIn = 0x00000, MDIO_ShiftClk =0x0001, MDIO_Data =0x0002, MDIO_EnbOutput =0x0004 } |
Functions | |
MODULE_AUTHOR ("Donald Becker <[email protected]>") | |
MODULE_DESCRIPTION ("Sundance Alta Ethernet driver") | |
MODULE_LICENSE ("GPL") | |
module_param (debug, int, 0) | |
module_param (rx_copybreak, int, 0) | |
module_param_array (media, charp, NULL, 0) | |
module_param (flowctrl, int, 0) | |
MODULE_PARM_DESC (debug,"Sundance Alta debug level (0-5)") | |
MODULE_PARM_DESC (rx_copybreak,"Sundance Alta copy breakpoint for copy-only-tiny-frames") | |
MODULE_PARM_DESC (flowctrl,"Sundance Alta flow control [0|1]") | |
MODULE_DEVICE_TABLE (pci, sundance_pci_tbl) | |
module_init (sundance_init) | |
module_exit (sundance_exit) | |
Definition at line 298 of file sundance.c.
#define DEFAULT_INTR |
Definition at line 413 of file sundance.c.
#define DRV_NAME "sundance" |
Definition at line 25 of file sundance.c.
#define DRV_RELDATE "11-Sep-2006" |
Definition at line 27 of file sundance.c.
#define DRV_VERSION "1.2" |
Definition at line 26 of file sundance.c.
#define eeprom_delay | ( | ee_addr | ) | ioread32(ee_addr) |
Definition at line 702 of file sundance.c.
#define EEPROM_SA_OFFSET 0x10 |
Definition at line 412 of file sundance.c.
#define MAX_UNITS 8 |
Definition at line 56 of file sundance.c.
#define mdio_delay | ( | ) | ioread8(mdio_addr) |
Definition at line 724 of file sundance.c.
#define MDIO_EnbIn (0) |
Definition at line 729 of file sundance.c.
#define MDIO_WRITE0 (MDIO_EnbOutput) |
Definition at line 730 of file sundance.c.
#define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput) |
Definition at line 731 of file sundance.c.
#define MII_CNT 4 |
Definition at line 359 of file sundance.c.
#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ |
Definition at line 78 of file sundance.c.
Definition at line 356 of file sundance.c.
#define RX_BUDGET 32 |
Definition at line 71 of file sundance.c.
#define RX_RING_SIZE 64 |
Definition at line 70 of file sundance.c.
#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc) |
Definition at line 73 of file sundance.c.
#define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used. */ |
Definition at line 69 of file sundance.c.
#define TX_RING_SIZE 32 |
Definition at line 68 of file sundance.c.
#define TX_TIMEOUT (4*HZ) |
Definition at line 77 of file sundance.c.
#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc) |
Definition at line 72 of file sundance.c.
#define USE_IO_OPS 1 |
Definition at line 199 of file sundance.c.
anonymous enum |
Definition at line 214 of file sundance.c.
enum alta_offsets |
Definition at line 243 of file sundance.c.
enum ASICCtrl_HiWord_bit |
Definition at line 300 of file sundance.c.
enum desc_status_bits |
Definition at line 346 of file sundance.c.
enum intr_status_bits |
Definition at line 312 of file sundance.c.
enum mac_ctrl0_bits |
Definition at line 326 of file sundance.c.
enum mac_ctrl1_bits |
StatsEnable | |
StatsDisable | |
StatsEnabled | |
TxEnable | |
TxDisable | |
TxEnabled | |
RxEnable | |
RxDisable | |
RxEnabled |
Definition at line 330 of file sundance.c.
enum mii_reg_bits |
MDIO_ShiftClk | |
MDIO_DataIn | |
MDIO_DataOut | |
MDIO_EnbOutput | |
MDIO_EnbIn | |
MDIO_ShiftClk | |
MDIO_Data | |
MDIO_EnbOutput |
Definition at line 726 of file sundance.c.
enum rx_mode_bits |
Definition at line 321 of file sundance.c.
MODULE_AUTHOR | ( | "Donald Becker <[email protected]>" | ) |
MODULE_DESCRIPTION | ( | "Sundance Alta Ethernet driver" | ) |
MODULE_DEVICE_TABLE | ( | pci | , |
sundance_pci_tbl | |||
) |
module_exit | ( | sundance_exit | ) |
module_init | ( | sundance_init | ) |
MODULE_LICENSE | ( | "GPL" | ) |
module_param | ( | rx_copybreak | , |
int | , | ||
0 | |||
) |
module_param | ( | flowctrl | , |
int | , | ||
0 | |||
) |
module_param_array | ( | media | , |
charp | , | ||
NULL | , | ||
0 | |||
) |
MODULE_PARM_DESC | ( | rx_copybreak | , |
"Sundance Alta copy breakpoint for copy-only-tiny-frames" | |||
) |
MODULE_PARM_DESC | ( | flowctrl | , |
"Sundance Alta flow control " | [0|1] | ||
) |
const char name[ETH_GSTRING_LEN] |
Definition at line 1610 of file sundance.c.