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mrst.c
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1 /*
2  * mrst.c: Intel Moorestown platform specific setup code
3  *
4  * (C) Copyright 2008 Intel Corporation
5  * Author: Jacob Pan ([email protected])
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * as published by the Free Software Foundation; version 2
10  * of the License.
11  */
12 
13 #define pr_fmt(fmt) "mrst: " fmt
14 
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/interrupt.h>
18 #include <linux/scatterlist.h>
19 #include <linux/sfi.h>
20 #include <linux/intel_pmic_gpio.h>
21 #include <linux/spi/spi.h>
22 #include <linux/i2c.h>
23 #include <linux/i2c/pca953x.h>
24 #include <linux/gpio_keys.h>
25 #include <linux/input.h>
26 #include <linux/platform_device.h>
27 #include <linux/irq.h>
28 #include <linux/module.h>
29 #include <linux/notifier.h>
30 #include <linux/mfd/intel_msic.h>
31 #include <linux/gpio.h>
32 #include <linux/i2c/tc35876x.h>
33 
34 #include <asm/setup.h>
35 #include <asm/mpspec_def.h>
36 #include <asm/hw_irq.h>
37 #include <asm/apic.h>
38 #include <asm/io_apic.h>
39 #include <asm/mrst.h>
40 #include <asm/mrst-vrtc.h>
41 #include <asm/io.h>
42 #include <asm/i8259.h>
43 #include <asm/intel_scu_ipc.h>
44 #include <asm/apb_timer.h>
45 #include <asm/reboot.h>
46 
47 /*
48  * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
49  * cmdline option x86_mrst_timer can be used to override the configuration
50  * to prefer one or the other.
51  * at runtime, there are basically three timer configurations:
52  * 1. per cpu apbt clock only
53  * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
54  * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
55  *
56  * by default (without cmdline option), platform code first detects cpu type
57  * to see if we are on lincroft or penwell, then set up both lapic or apbt
58  * clocks accordingly.
59  * i.e. by default, medfield uses configuration #2, moorestown uses #1.
60  * config #3 is supported but not recommended on medfield.
61  *
62  * rating and feature summary:
63  * lapic (with C3STOP) --------- 100
64  * apbt (always-on) ------------ 110
65  * lapic (always-on,ARAT) ------ 150
66  */
67 
69 
70 static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
71 static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
74 
76 
80 
81 static void mrst_power_off(void)
82 {
83 }
84 
85 static void mrst_reboot(void)
86 {
88 }
89 
90 /* parse all the mtimer info to a static mtimer array */
91 static int __init sfi_parse_mtmr(struct sfi_table_header *table)
92 {
93  struct sfi_table_simple *sb;
94  struct sfi_timer_table_entry *pentry;
95  struct mpc_intsrc mp_irq;
96  int totallen;
97 
98  sb = (struct sfi_table_simple *)table;
99  if (!sfi_mtimer_num) {
101  struct sfi_timer_table_entry);
102  pentry = (struct sfi_timer_table_entry *) sb->pentry;
103  totallen = sfi_mtimer_num * sizeof(*pentry);
104  memcpy(sfi_mtimer_array, pentry, totallen);
105  }
106 
107  pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
108  pentry = sfi_mtimer_array;
109  for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
110  pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz,"
111  " irq = %d\n", totallen, (u32)pentry->phys_addr,
112  pentry->freq_hz, pentry->irq);
113  if (!pentry->irq)
114  continue;
115  mp_irq.type = MP_INTSRC;
116  mp_irq.irqtype = mp_INT;
117 /* triggering mode edge bit 2-3, active high polarity bit 0-1 */
118  mp_irq.irqflag = 5;
119  mp_irq.srcbus = MP_BUS_ISA;
120  mp_irq.srcbusirq = pentry->irq; /* IRQ */
121  mp_irq.dstapic = MP_APIC_ALL;
122  mp_irq.dstirq = pentry->irq;
123  mp_save_irq(&mp_irq);
124  }
125 
126  return 0;
127 }
128 
130 {
131  int i;
132  if (hint < sfi_mtimer_num) {
133  if (!sfi_mtimer_usage[hint]) {
134  pr_debug("hint taken for timer %d irq %d\n",\
135  hint, sfi_mtimer_array[hint].irq);
136  sfi_mtimer_usage[hint] = 1;
137  return &sfi_mtimer_array[hint];
138  }
139  }
140  /* take the first timer available */
141  for (i = 0; i < sfi_mtimer_num;) {
142  if (!sfi_mtimer_usage[i]) {
143  sfi_mtimer_usage[i] = 1;
144  return &sfi_mtimer_array[i];
145  }
146  i++;
147  }
148  return NULL;
149 }
150 
152 {
153  int i;
154  for (i = 0; i < sfi_mtimer_num;) {
155  if (mtmr->irq == sfi_mtimer_array[i].irq) {
156  sfi_mtimer_usage[i] = 0;
157  return;
158  }
159  i++;
160  }
161 }
162 
163 /* parse all the mrtc info to a global mrtc array */
165 {
166  struct sfi_table_simple *sb;
167  struct sfi_rtc_table_entry *pentry;
168  struct mpc_intsrc mp_irq;
169 
170  int totallen;
171 
172  sb = (struct sfi_table_simple *)table;
173  if (!sfi_mrtc_num) {
175  struct sfi_rtc_table_entry);
176  pentry = (struct sfi_rtc_table_entry *)sb->pentry;
177  totallen = sfi_mrtc_num * sizeof(*pentry);
178  memcpy(sfi_mrtc_array, pentry, totallen);
179  }
180 
181  pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
182  pentry = sfi_mrtc_array;
183  for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
184  pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
185  totallen, (u32)pentry->phys_addr, pentry->irq);
186  mp_irq.type = MP_INTSRC;
187  mp_irq.irqtype = mp_INT;
188  mp_irq.irqflag = 0xf; /* level trigger and active low */
189  mp_irq.srcbus = MP_BUS_ISA;
190  mp_irq.srcbusirq = pentry->irq; /* IRQ */
191  mp_irq.dstapic = MP_APIC_ALL;
192  mp_irq.dstirq = pentry->irq;
193  mp_save_irq(&mp_irq);
194  }
195  return 0;
196 }
197 
198 static unsigned long __init mrst_calibrate_tsc(void)
199 {
200  unsigned long fast_calibrate;
201  u32 lo, hi, ratio, fsb;
202 
203  rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
204  pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);
205  ratio = (hi >> 8) & 0x1f;
206  pr_debug("ratio is %d\n", ratio);
207  if (!ratio) {
208  pr_err("read a zero ratio, should be incorrect!\n");
209  pr_err("force tsc ratio to 16 ...\n");
210  ratio = 16;
211  }
212  rdmsr(MSR_FSB_FREQ, lo, hi);
213  if ((lo & 0x7) == 0x7)
215  else
217  fast_calibrate = ratio * fsb;
218  pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
219  lapic_timer_frequency = fsb * 1000 / HZ;
220  /* mark tsc clocksource as reliable */
222 
223  if (fast_calibrate)
224  return fast_calibrate;
225 
226  return 0;
227 }
228 
229 static void __init mrst_time_init(void)
230 {
231  sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
232  switch (mrst_timer_options) {
234  break;
236  x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
237  x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
238  break;
239  default:
240  if (!boot_cpu_has(X86_FEATURE_ARAT))
241  break;
242  x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
243  x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
244  return;
245  }
246  /* we need at least one APB timer */
248  apbt_time_init();
249 }
250 
251 static void __cpuinit mrst_arch_setup(void)
252 {
253  if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
255  else {
256  pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n",
257  boot_cpu_data.x86, boot_cpu_data.x86_model);
259  }
260 }
261 
262 /* MID systems don't have i8042 controller */
263 static int mrst_i8042_detect(void)
264 {
265  return 0;
266 }
267 
268 /*
269  * Moorestown does not have external NMI source nor port 0x61 to report
270  * NMI status. The possible NMI sources are from pmu as a result of NMI
271  * watchdog or lock debug. Reading io port 0x61 results in 0xff which
272  * misled NMI handler.
273  */
274 static unsigned char mrst_get_nmi_reason(void)
275 {
276  return 0;
277 }
278 
279 /*
280  * Moorestown specific x86_init function overrides and early setup
281  * calls.
282  */
284 {
285  x86_init.resources.probe_roms = x86_init_noop;
286  x86_init.resources.reserve_resources = x86_init_noop;
287 
288  x86_init.timers.timer_init = mrst_time_init;
289  x86_init.timers.setup_percpu_clockev = x86_init_noop;
290 
291  x86_init.irqs.pre_vector_init = x86_init_noop;
292 
293  x86_init.oem.arch_setup = mrst_arch_setup;
294 
295  x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
296 
297  x86_platform.calibrate_tsc = mrst_calibrate_tsc;
298  x86_platform.i8042_detect = mrst_i8042_detect;
299  x86_init.timers.wallclock_init = mrst_rtc_init;
300  x86_platform.get_nmi_reason = mrst_get_nmi_reason;
301 
302  x86_init.pci.init = pci_mrst_init;
303  x86_init.pci.fixup_irqs = x86_init_noop;
304 
306 
307  /* Moorestown specific power_off/restart method */
308  pm_power_off = mrst_power_off;
309  machine_ops.emergency_restart = mrst_reboot;
310 
311  /* Avoid searching for BIOS MP tables */
312  x86_init.mpparse.find_smp_config = x86_init_noop;
313  x86_init.mpparse.get_smp_config = x86_init_uint_noop;
314  set_bit(MP_BUS_ISA, mp_bus_not_pci);
315 }
316 
317 /*
318  * if user does not want to use per CPU apb timer, just give it a lower rating
319  * than local apic timer and skip the late per cpu timer init.
320  */
321 static inline int __init setup_x86_mrst_timer(char *arg)
322 {
323  if (!arg)
324  return -EINVAL;
325 
326  if (strcmp("apbt_only", arg) == 0)
328  else if (strcmp("lapic_and_apbt", arg) == 0)
330  else {
331  pr_warning("X86 MRST timer option %s not recognised"
332  " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
333  arg);
334  return -EINVAL;
335  }
336  return 0;
337 }
338 __setup("x86_mrst_timer=", setup_x86_mrst_timer);
339 
340 /*
341  * Parsing GPIO table first, since the DEVS table will need this table
342  * to map the pin name to the actual pin.
343  */
344 static struct sfi_gpio_table_entry *gpio_table;
345 static int gpio_num_entry;
346 
347 static int __init sfi_parse_gpio(struct sfi_table_header *table)
348 {
349  struct sfi_table_simple *sb;
350  struct sfi_gpio_table_entry *pentry;
351  int num, i;
352 
353  if (gpio_table)
354  return 0;
355  sb = (struct sfi_table_simple *)table;
356  num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
357  pentry = (struct sfi_gpio_table_entry *)sb->pentry;
358 
359  gpio_table = (struct sfi_gpio_table_entry *)
360  kmalloc(num * sizeof(*pentry), GFP_KERNEL);
361  if (!gpio_table)
362  return -1;
363  memcpy(gpio_table, pentry, num * sizeof(*pentry));
364  gpio_num_entry = num;
365 
366  pr_debug("GPIO pin info:\n");
367  for (i = 0; i < num; i++, pentry++)
368  pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
369  " pin = %d\n", i,
370  pentry->controller_name,
371  pentry->pin_name,
372  pentry->pin_no);
373  return 0;
374 }
375 
376 static int get_gpio_by_name(const char *name)
377 {
378  struct sfi_gpio_table_entry *pentry = gpio_table;
379  int i;
380 
381  if (!pentry)
382  return -1;
383  for (i = 0; i < gpio_num_entry; i++, pentry++) {
384  if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
385  return pentry->pin_no;
386  }
387  return -1;
388 }
389 
390 /*
391  * Here defines the array of devices platform data that IAFW would export
392  * through SFI "DEVS" table, we use name and type to match the device and
393  * its platform data.
394  */
395 struct devs_id {
396  char name[SFI_NAME_LEN + 1];
399  void *(*get_platform_data)(void *info);
400 };
401 
402 /* the offset for the mapping of global gpio pin to irq */
403 #define MRST_IRQ_OFFSET 0x100
404 
405 static void __init *pmic_gpio_platform_data(void *info)
406 {
407  static struct intel_pmic_gpio_platform_data pmic_gpio_pdata;
408  int gpio_base = get_gpio_by_name("pmic_gpio_base");
409 
410  if (gpio_base == -1)
411  gpio_base = 64;
412  pmic_gpio_pdata.gpio_base = gpio_base;
413  pmic_gpio_pdata.irq_base = gpio_base + MRST_IRQ_OFFSET;
414  pmic_gpio_pdata.gpiointr = 0xffffeff8;
415 
416  return &pmic_gpio_pdata;
417 }
418 
419 static void __init *max3111_platform_data(void *info)
420 {
421  struct spi_board_info *spi_info = info;
422  int intr = get_gpio_by_name("max3111_int");
423 
424  spi_info->mode = SPI_MODE_0;
425  if (intr == -1)
426  return NULL;
427  spi_info->irq = intr + MRST_IRQ_OFFSET;
428  return NULL;
429 }
430 
431 /* we have multiple max7315 on the board ... */
432 #define MAX7315_NUM 2
433 static void __init *max7315_platform_data(void *info)
434 {
435  static struct pca953x_platform_data max7315_pdata[MAX7315_NUM];
436  static int nr;
437  struct pca953x_platform_data *max7315 = &max7315_pdata[nr];
438  struct i2c_board_info *i2c_info = info;
439  int gpio_base, intr;
440  char base_pin_name[SFI_NAME_LEN + 1];
441  char intr_pin_name[SFI_NAME_LEN + 1];
442 
443  if (nr == MAX7315_NUM) {
444  pr_err("too many max7315s, we only support %d\n",
445  MAX7315_NUM);
446  return NULL;
447  }
448  /* we have several max7315 on the board, we only need load several
449  * instances of the same pca953x driver to cover them
450  */
451  strcpy(i2c_info->type, "max7315");
452  if (nr++) {
453  sprintf(base_pin_name, "max7315_%d_base", nr);
454  sprintf(intr_pin_name, "max7315_%d_int", nr);
455  } else {
456  strcpy(base_pin_name, "max7315_base");
457  strcpy(intr_pin_name, "max7315_int");
458  }
459 
460  gpio_base = get_gpio_by_name(base_pin_name);
461  intr = get_gpio_by_name(intr_pin_name);
462 
463  if (gpio_base == -1)
464  return NULL;
465  max7315->gpio_base = gpio_base;
466  if (intr != -1) {
467  i2c_info->irq = intr + MRST_IRQ_OFFSET;
468  max7315->irq_base = gpio_base + MRST_IRQ_OFFSET;
469  } else {
470  i2c_info->irq = -1;
471  max7315->irq_base = -1;
472  }
473  return max7315;
474 }
475 
476 static void *tca6416_platform_data(void *info)
477 {
478  static struct pca953x_platform_data tca6416;
479  struct i2c_board_info *i2c_info = info;
480  int gpio_base, intr;
481  char base_pin_name[SFI_NAME_LEN + 1];
482  char intr_pin_name[SFI_NAME_LEN + 1];
483 
484  strcpy(i2c_info->type, "tca6416");
485  strcpy(base_pin_name, "tca6416_base");
486  strcpy(intr_pin_name, "tca6416_int");
487 
488  gpio_base = get_gpio_by_name(base_pin_name);
489  intr = get_gpio_by_name(intr_pin_name);
490 
491  if (gpio_base == -1)
492  return NULL;
493  tca6416.gpio_base = gpio_base;
494  if (intr != -1) {
495  i2c_info->irq = intr + MRST_IRQ_OFFSET;
496  tca6416.irq_base = gpio_base + MRST_IRQ_OFFSET;
497  } else {
498  i2c_info->irq = -1;
499  tca6416.irq_base = -1;
500  }
501  return &tca6416;
502 }
503 
504 static void *mpu3050_platform_data(void *info)
505 {
506  struct i2c_board_info *i2c_info = info;
507  int intr = get_gpio_by_name("mpu3050_int");
508 
509  if (intr == -1)
510  return NULL;
511 
512  i2c_info->irq = intr + MRST_IRQ_OFFSET;
513  return NULL;
514 }
515 
516 static void __init *emc1403_platform_data(void *info)
517 {
518  static short intr2nd_pdata;
519  struct i2c_board_info *i2c_info = info;
520  int intr = get_gpio_by_name("thermal_int");
521  int intr2nd = get_gpio_by_name("thermal_alert");
522 
523  if (intr == -1 || intr2nd == -1)
524  return NULL;
525 
526  i2c_info->irq = intr + MRST_IRQ_OFFSET;
527  intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
528 
529  return &intr2nd_pdata;
530 }
531 
532 static void __init *lis331dl_platform_data(void *info)
533 {
534  static short intr2nd_pdata;
535  struct i2c_board_info *i2c_info = info;
536  int intr = get_gpio_by_name("accel_int");
537  int intr2nd = get_gpio_by_name("accel_2");
538 
539  if (intr == -1 || intr2nd == -1)
540  return NULL;
541 
542  i2c_info->irq = intr + MRST_IRQ_OFFSET;
543  intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
544 
545  return &intr2nd_pdata;
546 }
547 
548 static void __init *no_platform_data(void *info)
549 {
550  return NULL;
551 }
552 
553 static struct resource msic_resources[] = {
554  {
555  .start = INTEL_MSIC_IRQ_PHYS_BASE,
556  .end = INTEL_MSIC_IRQ_PHYS_BASE + 64 - 1,
557  .flags = IORESOURCE_MEM,
558  },
559 };
560 
561 static struct intel_msic_platform_data msic_pdata;
562 
563 static struct platform_device msic_device = {
564  .name = "intel_msic",
565  .id = -1,
566  .dev = {
567  .platform_data = &msic_pdata,
568  },
569  .num_resources = ARRAY_SIZE(msic_resources),
570  .resource = msic_resources,
571 };
572 
573 static inline bool mrst_has_msic(void)
574 {
576 }
577 
578 static int msic_scu_status_change(struct notifier_block *nb,
579  unsigned long code, void *data)
580 {
581  if (code == SCU_DOWN) {
582  platform_device_unregister(&msic_device);
583  return 0;
584  }
585 
586  return platform_device_register(&msic_device);
587 }
588 
589 static int __init msic_init(void)
590 {
591  static struct notifier_block msic_scu_notifier = {
592  .notifier_call = msic_scu_status_change,
593  };
594 
595  /*
596  * We need to be sure that the SCU IPC is ready before MSIC device
597  * can be registered.
598  */
599  if (mrst_has_msic())
600  intel_scu_notifier_add(&msic_scu_notifier);
601 
602  return 0;
603 }
604 arch_initcall(msic_init);
605 
606 /*
607  * msic_generic_platform_data - sets generic platform data for the block
608  * @info: pointer to the SFI device table entry for this block
609  * @block: MSIC block
610  *
611  * Function sets IRQ number from the SFI table entry for given device to
612  * the MSIC platform data.
613  */
614 static void *msic_generic_platform_data(void *info, enum intel_msic_block block)
615 {
617 
619  msic_pdata.irq[block] = entry->irq;
620 
621  return no_platform_data(info);
622 }
623 
624 static void *msic_battery_platform_data(void *info)
625 {
626  return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_BATTERY);
627 }
628 
629 static void *msic_gpio_platform_data(void *info)
630 {
631  static struct intel_msic_gpio_pdata pdata;
632  int gpio = get_gpio_by_name("msic_gpio_base");
633 
634  if (gpio < 0)
635  return NULL;
636 
637  pdata.gpio_base = gpio;
638  msic_pdata.gpio = &pdata;
639 
640  return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_GPIO);
641 }
642 
643 static void *msic_audio_platform_data(void *info)
644 {
645  struct platform_device *pdev;
646 
647  pdev = platform_device_register_simple("sst-platform", -1, NULL, 0);
648  if (IS_ERR(pdev)) {
649  pr_err("failed to create audio platform device\n");
650  return NULL;
651  }
652 
653  return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_AUDIO);
654 }
655 
656 static void *msic_power_btn_platform_data(void *info)
657 {
658  return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_POWER_BTN);
659 }
660 
661 static void *msic_ocd_platform_data(void *info)
662 {
663  static struct intel_msic_ocd_pdata pdata;
664  int gpio = get_gpio_by_name("ocd_gpio");
665 
666  if (gpio < 0)
667  return NULL;
668 
669  pdata.gpio = gpio;
670  msic_pdata.ocd = &pdata;
671 
672  return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_OCD);
673 }
674 
675 static void *msic_thermal_platform_data(void *info)
676 {
677  return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_THERMAL);
678 }
679 
680 /* tc35876x DSI-LVDS bridge chip and panel platform data */
681 static void *tc35876x_platform_data(void *data)
682 {
683  static struct tc35876x_platform_data pdata;
684 
685  /* gpio pins set to -1 will not be used by the driver */
686  pdata.gpio_bridge_reset = get_gpio_by_name("LCMB_RXEN");
687  pdata.gpio_panel_bl_en = get_gpio_by_name("6S6P_BL_EN");
688  pdata.gpio_panel_vadd = get_gpio_by_name("EN_VREG_LCD_V3P3");
689 
690  return &pdata;
691 }
692 
693 static const struct devs_id __initconst device_ids[] = {
694  {"bma023", SFI_DEV_TYPE_I2C, 1, &no_platform_data},
695  {"pmic_gpio", SFI_DEV_TYPE_SPI, 1, &pmic_gpio_platform_data},
696  {"pmic_gpio", SFI_DEV_TYPE_IPC, 1, &pmic_gpio_platform_data},
697  {"spi_max3111", SFI_DEV_TYPE_SPI, 0, &max3111_platform_data},
698  {"i2c_max7315", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
699  {"i2c_max7315_2", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
700  {"tca6416", SFI_DEV_TYPE_I2C, 1, &tca6416_platform_data},
701  {"emc1403", SFI_DEV_TYPE_I2C, 1, &emc1403_platform_data},
702  {"i2c_accel", SFI_DEV_TYPE_I2C, 0, &lis331dl_platform_data},
703  {"pmic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
704  {"mpu3050", SFI_DEV_TYPE_I2C, 1, &mpu3050_platform_data},
705  {"i2c_disp_brig", SFI_DEV_TYPE_I2C, 0, &tc35876x_platform_data},
706 
707  /* MSIC subdevices */
708  {"msic_battery", SFI_DEV_TYPE_IPC, 1, &msic_battery_platform_data},
709  {"msic_gpio", SFI_DEV_TYPE_IPC, 1, &msic_gpio_platform_data},
710  {"msic_audio", SFI_DEV_TYPE_IPC, 1, &msic_audio_platform_data},
711  {"msic_power_btn", SFI_DEV_TYPE_IPC, 1, &msic_power_btn_platform_data},
712  {"msic_ocd", SFI_DEV_TYPE_IPC, 1, &msic_ocd_platform_data},
713  {"msic_thermal", SFI_DEV_TYPE_IPC, 1, &msic_thermal_platform_data},
714 
715  {},
716 };
717 
718 #define MAX_IPCDEVS 24
719 static struct platform_device *ipc_devs[MAX_IPCDEVS];
720 static int ipc_next_dev;
721 
722 #define MAX_SCU_SPI 24
723 static struct spi_board_info *spi_devs[MAX_SCU_SPI];
724 static int spi_next_dev;
725 
726 #define MAX_SCU_I2C 24
727 static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
728 static int i2c_bus[MAX_SCU_I2C];
729 static int i2c_next_dev;
730 
731 static void __init intel_scu_device_register(struct platform_device *pdev)
732 {
733  if(ipc_next_dev == MAX_IPCDEVS)
734  pr_err("too many SCU IPC devices");
735  else
736  ipc_devs[ipc_next_dev++] = pdev;
737 }
738 
739 static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
740 {
741  struct spi_board_info *new_dev;
742 
743  if (spi_next_dev == MAX_SCU_SPI) {
744  pr_err("too many SCU SPI devices");
745  return;
746  }
747 
748  new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
749  if (!new_dev) {
750  pr_err("failed to alloc mem for delayed spi dev %s\n",
751  sdev->modalias);
752  return;
753  }
754  memcpy(new_dev, sdev, sizeof(*sdev));
755 
756  spi_devs[spi_next_dev++] = new_dev;
757 }
758 
759 static void __init intel_scu_i2c_device_register(int bus,
760  struct i2c_board_info *idev)
761 {
762  struct i2c_board_info *new_dev;
763 
764  if (i2c_next_dev == MAX_SCU_I2C) {
765  pr_err("too many SCU I2C devices");
766  return;
767  }
768 
769  new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
770  if (!new_dev) {
771  pr_err("failed to alloc mem for delayed i2c dev %s\n",
772  idev->type);
773  return;
774  }
775  memcpy(new_dev, idev, sizeof(*idev));
776 
777  i2c_bus[i2c_next_dev] = bus;
778  i2c_devs[i2c_next_dev++] = new_dev;
779 }
780 
781 BLOCKING_NOTIFIER_HEAD(intel_scu_notifier);
782 EXPORT_SYMBOL_GPL(intel_scu_notifier);
783 
784 /* Called by IPC driver */
786 {
787  int i;
788 
789  for (i = 0; i < ipc_next_dev; i++)
790  platform_device_add(ipc_devs[i]);
791 
792  for (i = 0; i < spi_next_dev; i++)
793  spi_register_board_info(spi_devs[i], 1);
794 
795  for (i = 0; i < i2c_next_dev; i++) {
796  struct i2c_adapter *adapter;
797  struct i2c_client *client;
798 
799  adapter = i2c_get_adapter(i2c_bus[i]);
800  if (adapter) {
801  client = i2c_new_device(adapter, i2c_devs[i]);
802  if (!client)
803  pr_err("can't create i2c device %s\n",
804  i2c_devs[i]->type);
805  } else
806  i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
807  }
808  intel_scu_notifier_post(SCU_AVAILABLE, NULL);
809 }
811 
812 /* Called by IPC driver */
814 {
815  int i;
816 
817  intel_scu_notifier_post(SCU_DOWN, NULL);
818 
819  for (i = 0; i < ipc_next_dev; i++)
820  platform_device_del(ipc_devs[i]);
821 }
823 
824 static void __init install_irq_resource(struct platform_device *pdev, int irq)
825 {
826  /* Single threaded */
827  static struct resource __initdata res = {
828  .name = "IRQ",
829  .flags = IORESOURCE_IRQ,
830  };
831  res.start = irq;
832  platform_device_add_resources(pdev, &res, 1);
833 }
834 
835 static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *entry)
836 {
837  const struct devs_id *dev = device_ids;
838  struct platform_device *pdev;
839  void *pdata = NULL;
840 
841  while (dev->name[0]) {
842  if (dev->type == SFI_DEV_TYPE_IPC &&
843  !strncmp(dev->name, entry->name, SFI_NAME_LEN)) {
844  pdata = dev->get_platform_data(entry);
845  break;
846  }
847  dev++;
848  }
849 
850  /*
851  * On Medfield the platform device creation is handled by the MSIC
852  * MFD driver so we don't need to do it here.
853  */
854  if (mrst_has_msic())
855  return;
856 
857  pdev = platform_device_alloc(entry->name, 0);
858  if (pdev == NULL) {
859  pr_err("out of memory for SFI platform device '%s'.\n",
860  entry->name);
861  return;
862  }
863  install_irq_resource(pdev, entry->irq);
864 
865  pdev->dev.platform_data = pdata;
866  intel_scu_device_register(pdev);
867 }
868 
869 static void __init sfi_handle_spi_dev(struct spi_board_info *spi_info)
870 {
871  const struct devs_id *dev = device_ids;
872  void *pdata = NULL;
873 
874  while (dev->name[0]) {
875  if (dev->type == SFI_DEV_TYPE_SPI &&
876  !strncmp(dev->name, spi_info->modalias, SFI_NAME_LEN)) {
877  pdata = dev->get_platform_data(spi_info);
878  break;
879  }
880  dev++;
881  }
882  spi_info->platform_data = pdata;
883  if (dev->delay)
884  intel_scu_spi_device_register(spi_info);
885  else
886  spi_register_board_info(spi_info, 1);
887 }
888 
889 static void __init sfi_handle_i2c_dev(int bus, struct i2c_board_info *i2c_info)
890 {
891  const struct devs_id *dev = device_ids;
892  void *pdata = NULL;
893 
894  while (dev->name[0]) {
895  if (dev->type == SFI_DEV_TYPE_I2C &&
896  !strncmp(dev->name, i2c_info->type, SFI_NAME_LEN)) {
897  pdata = dev->get_platform_data(i2c_info);
898  break;
899  }
900  dev++;
901  }
902  i2c_info->platform_data = pdata;
903 
904  if (dev->delay)
905  intel_scu_i2c_device_register(bus, i2c_info);
906  else
907  i2c_register_board_info(bus, i2c_info, 1);
908  }
909 
910 
911 static int __init sfi_parse_devs(struct sfi_table_header *table)
912 {
913  struct sfi_table_simple *sb;
914  struct sfi_device_table_entry *pentry;
915  struct spi_board_info spi_info;
916  struct i2c_board_info i2c_info;
917  int num, i, bus;
918  int ioapic;
919  struct io_apic_irq_attr irq_attr;
920 
921  sb = (struct sfi_table_simple *)table;
923  pentry = (struct sfi_device_table_entry *)sb->pentry;
924 
925  for (i = 0; i < num; i++, pentry++) {
926  int irq = pentry->irq;
927 
928  if (irq != (u8)0xff) { /* native RTE case */
929  /* these SPI2 devices are not exposed to system as PCI
930  * devices, but they have separate RTE entry in IOAPIC
931  * so we have to enable them one by one here
932  */
933  ioapic = mp_find_ioapic(irq);
934  irq_attr.ioapic = ioapic;
935  irq_attr.ioapic_pin = irq;
936  irq_attr.trigger = 1;
937  irq_attr.polarity = 1;
938  io_apic_set_pci_routing(NULL, irq, &irq_attr);
939  } else
940  irq = 0; /* No irq */
941 
942  switch (pentry->type) {
943  case SFI_DEV_TYPE_IPC:
944  pr_debug("info[%2d]: IPC bus, name = %16.16s, "
945  "irq = 0x%2x\n", i, pentry->name, pentry->irq);
946  sfi_handle_ipc_dev(pentry);
947  break;
948  case SFI_DEV_TYPE_SPI:
949  memset(&spi_info, 0, sizeof(spi_info));
950  strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
951  spi_info.irq = irq;
952  spi_info.bus_num = pentry->host_num;
953  spi_info.chip_select = pentry->addr;
954  spi_info.max_speed_hz = pentry->max_freq;
955  pr_debug("info[%2d]: SPI bus = %d, name = %16.16s, "
956  "irq = 0x%2x, max_freq = %d, cs = %d\n", i,
957  spi_info.bus_num,
958  spi_info.modalias,
959  spi_info.irq,
960  spi_info.max_speed_hz,
961  spi_info.chip_select);
962  sfi_handle_spi_dev(&spi_info);
963  break;
964  case SFI_DEV_TYPE_I2C:
965  memset(&i2c_info, 0, sizeof(i2c_info));
966  bus = pentry->host_num;
967  strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
968  i2c_info.irq = irq;
969  i2c_info.addr = pentry->addr;
970  pr_debug("info[%2d]: I2C bus = %d, name = %16.16s, "
971  "irq = 0x%2x, addr = 0x%x\n", i, bus,
972  i2c_info.type,
973  i2c_info.irq,
974  i2c_info.addr);
975  sfi_handle_i2c_dev(bus, &i2c_info);
976  break;
977  case SFI_DEV_TYPE_UART:
978  case SFI_DEV_TYPE_HSI:
979  default:
980  ;
981  }
982  }
983  return 0;
984 }
985 
986 static int __init mrst_platform_init(void)
987 {
988  sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
989  sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
990  return 0;
991 }
992 arch_initcall(mrst_platform_init);
993 
994 /*
995  * we will search these buttons in SFI GPIO table (by name)
996  * and register them dynamically. Please add all possible
997  * buttons here, we will shrink them if no GPIO found.
998  */
999 static struct gpio_keys_button gpio_button[] = {
1000  {KEY_POWER, -1, 1, "power_btn", EV_KEY, 0, 3000},
1001  {KEY_PROG1, -1, 1, "prog_btn1", EV_KEY, 0, 20},
1002  {KEY_PROG2, -1, 1, "prog_btn2", EV_KEY, 0, 20},
1003  {SW_LID, -1, 1, "lid_switch", EV_SW, 0, 20},
1004  {KEY_VOLUMEUP, -1, 1, "vol_up", EV_KEY, 0, 20},
1005  {KEY_VOLUMEDOWN, -1, 1, "vol_down", EV_KEY, 0, 20},
1006  {KEY_CAMERA, -1, 1, "camera_full", EV_KEY, 0, 20},
1007  {KEY_CAMERA_FOCUS, -1, 1, "camera_half", EV_KEY, 0, 20},
1008  {SW_KEYPAD_SLIDE, -1, 1, "MagSw1", EV_SW, 0, 20},
1009  {SW_KEYPAD_SLIDE, -1, 1, "MagSw2", EV_SW, 0, 20},
1010 };
1011 
1012 static struct gpio_keys_platform_data mrst_gpio_keys = {
1013  .buttons = gpio_button,
1014  .rep = 1,
1015  .nbuttons = -1, /* will fill it after search */
1016 };
1017 
1018 static struct platform_device pb_device = {
1019  .name = "gpio-keys",
1020  .id = -1,
1021  .dev = {
1022  .platform_data = &mrst_gpio_keys,
1023  },
1024 };
1025 
1026 /*
1027  * Shrink the non-existent buttons, register the gpio button
1028  * device if there is some
1029  */
1030 static int __init pb_keys_init(void)
1031 {
1032  struct gpio_keys_button *gb = gpio_button;
1033  int i, num, good = 0;
1034 
1035  num = sizeof(gpio_button) / sizeof(struct gpio_keys_button);
1036  for (i = 0; i < num; i++) {
1037  gb[i].gpio = get_gpio_by_name(gb[i].desc);
1038  pr_debug("info[%2d]: name = %s, gpio = %d\n", i, gb[i].desc, gb[i].gpio);
1039  if (gb[i].gpio == -1)
1040  continue;
1041 
1042  if (i != good)
1043  gb[good] = gb[i];
1044  good++;
1045  }
1046 
1047  if (good) {
1048  mrst_gpio_keys.nbuttons = good;
1049  return platform_device_register(&pb_device);
1050  }
1051  return 0;
1052 }
1053 late_initcall(pb_keys_init);