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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
Data Structures | |
| struct | srb |
| struct | device_reg |
| struct | nvram |
| struct | cmd_entry |
| struct | cont_entry |
| struct | response |
| struct | mrk_entry |
| struct | ecmd_entry |
| struct | cmd_a64_entry_t |
| struct | cont_a64_entry |
| struct | elun_entry |
| struct | modify_lun_entry |
| struct | notify_entry |
| struct | nack_entry |
| struct | atio_entry |
| struct | ctio_entry |
| struct | ctio_ret_entry |
| struct | ctio_a64_entry |
| struct | ctio_a64_ret_entry |
| struct | bus_param |
| struct | qla_driver_setup |
| struct | scsi_qla_host |
Macros | |
| #define | BIT_0 0x1 |
| #define | BIT_1 0x2 |
| #define | BIT_2 0x4 |
| #define | BIT_3 0x8 |
| #define | BIT_4 0x10 |
| #define | BIT_5 0x20 |
| #define | BIT_6 0x40 |
| #define | BIT_7 0x80 |
| #define | BIT_8 0x100 |
| #define | BIT_9 0x200 |
| #define | BIT_10 0x400 |
| #define | BIT_11 0x800 |
| #define | BIT_12 0x1000 |
| #define | BIT_13 0x2000 |
| #define | BIT_14 0x4000 |
| #define | BIT_15 0x8000 |
| #define | BIT_16 0x10000 |
| #define | BIT_17 0x20000 |
| #define | BIT_18 0x40000 |
| #define | BIT_19 0x80000 |
| #define | BIT_20 0x100000 |
| #define | BIT_21 0x200000 |
| #define | BIT_22 0x400000 |
| #define | BIT_23 0x800000 |
| #define | BIT_24 0x1000000 |
| #define | BIT_25 0x2000000 |
| #define | BIT_26 0x4000000 |
| #define | BIT_27 0x8000000 |
| #define | BIT_28 0x10000000 |
| #define | BIT_29 0x20000000 |
| #define | BIT_30 0x40000000 |
| #define | BIT_31 0x80000000 |
| #define | RD_REG_WORD(addr) inw((unsigned long)addr) |
| #define | RD_REG_WORD_dmasync(addr) RD_REG_WORD(addr) |
| #define | WRT_REG_WORD(addr, data) outw(data, (unsigned long)addr) |
| #define | MAX_BUSES 2 /* 2 */ |
| #define | MAX_B_BITS 1 |
| #define | MAX_TARGETS 16 /* 16 */ |
| #define | MAX_T_BITS 4 /* 4 */ |
| #define | MAX_LUNS 8 /* 32 */ |
| #define | MAX_L_BITS 3 /* 5 */ |
| #define | QLA1280_WDG_TIME_QUANTUM 5 /* In seconds */ |
| #define | COMMAND_RETRY_COUNT 255 |
| #define | MAX_OUTSTANDING_COMMANDS 512 |
| #define | COMPLETED_HANDLE |
| #define | REQUEST_ENTRY_CNT 255 /* Number of request entries. */ |
| #define | RESPONSE_ENTRY_CNT 63 /* Number of response entries. */ |
| #define | SRB_TIMEOUT (1 << 0) /* Command timed out */ |
| #define | SRB_SENT (1 << 1) /* Command sent to ISP */ |
| #define | SRB_ABORT_PENDING (1 << 2) /* Command abort sent to device */ |
| #define | SRB_ABORTED (1 << 3) /* Command aborted command already */ |
| #define | ISP_CFG0_HWMSK 0x000f /* Hardware revision mask */ |
| #define | ISP_CFG0_1020 BIT_0 /* ISP1020 */ |
| #define | ISP_CFG0_1020A BIT_1 /* ISP1020A */ |
| #define | ISP_CFG0_1040 BIT_2 /* ISP1040 */ |
| #define | ISP_CFG0_1040A BIT_3 /* ISP1040A */ |
| #define | ISP_CFG0_1040B BIT_4 /* ISP1040B */ |
| #define | ISP_CFG0_1040C BIT_5 /* ISP1040C */ |
| #define | ISP_CFG1_F128 BIT_6 /* 128-byte FIFO threshold */ |
| #define | ISP_CFG1_F64 BIT_4|BIT_5 /* 128-byte FIFO threshold */ |
| #define | ISP_CFG1_F32 BIT_5 /* 128-byte FIFO threshold */ |
| #define | ISP_CFG1_F16 BIT_4 /* 128-byte FIFO threshold */ |
| #define | ISP_CFG1_BENAB BIT_2 /* Global Bus burst enable */ |
| #define | ISP_CFG1_SXP BIT_0 /* SXP register select */ |
| #define | ISP_RESET BIT_0 /* ISP soft reset */ |
| #define | ISP_EN_INT BIT_1 /* ISP enable interrupts. */ |
| #define | ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */ |
| #define | ISP_FLASH_ENABLE BIT_8 /* Flash BIOS Read/Write enable */ |
| #define | ISP_FLASH_UPPER BIT_9 /* Flash upper bank select */ |
| #define | PCI_64BIT_SLOT BIT_14 /* PCI 64-bit slot indicator. */ |
| #define | RISC_INT BIT_2 /* RISC interrupt */ |
| #define | PCI_INT BIT_1 /* PCI interrupt */ |
| #define | NV_DESELECT 0 |
| #define | NV_CLOCK BIT_0 |
| #define | NV_SELECT BIT_1 |
| #define | NV_DATA_OUT BIT_2 |
| #define | NV_DATA_IN BIT_3 |
| #define | CDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */ |
| #define | CDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */ |
| #define | CDMA_CONF_BENAB BIT_1 /* Bus burst enable */ |
| #define | CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */ |
| #define | DDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */ |
| #define | DDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */ |
| #define | DDMA_CONF_BENAB BIT_1 /* Bus burst enable */ |
| #define | DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */ |
| #define | HOST_INT BIT_7 /* host interrupt bit */ |
| #define | BIOS_ENABLE BIT_0 |
| #define | MAILBOX_REGISTER_COUNT 8 |
| #define | PROD_ID_1 0x4953 |
| #define | PROD_ID_2 0x0000 |
| #define | PROD_ID_2a 0x5020 |
| #define | PROD_ID_3 0x2020 |
| #define | PROD_ID_4 0x1 |
| #define | HC_RESET_RISC 0x1000 /* Reset RISC */ |
| #define | HC_PAUSE_RISC 0x2000 /* Pause RISC */ |
| #define | HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */ |
| #define | HC_SET_HOST_INT 0x5000 /* Set host interrupt */ |
| #define | HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ |
| #define | HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ |
| #define | HC_DISABLE_BIOS 0x9000 /* Disable BIOS. */ |
| #define | MBS_FRM_ALIVE 0 /* Firmware Alive. */ |
| #define | MBS_CHKSUM_ERR 1 /* Checksum Error. */ |
| #define | MBS_SHADOW_LD_ERR 2 /* Shadow Load Error. */ |
| #define | MBS_BUSY 4 /* Busy. */ |
| #define | MBS_CMD_CMP 0x4000 /* Command Complete. */ |
| #define | MBS_INV_CMD 0x4001 /* Invalid Command. */ |
| #define | MBS_HOST_INF_ERR 0x4002 /* Host Interface Error. */ |
| #define | MBS_TEST_FAILED 0x4003 /* Test Failed. */ |
| #define | MBS_CMD_ERR 0x4005 /* Command Error. */ |
| #define | MBS_CMD_PARAM_ERR 0x4006 /* Command Parameter Error. */ |
| #define | MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ |
| #define | MBA_BUS_RESET 0x8001 /* SCSI Bus Reset. */ |
| #define | MBA_SYSTEM_ERR 0x8002 /* System Error. */ |
| #define | MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ |
| #define | MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ |
| #define | MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ |
| #define | MBA_TIMEOUT_RESET 0x8006 /* Execution Timeout Reset. */ |
| #define | MBA_DEVICE_RESET 0x8007 /* Bus Device Reset. */ |
| #define | MBA_BUS_MODE_CHANGE 0x800E /* SCSI bus mode transition. */ |
| #define | MBA_SCSI_COMPLETION 0x8020 /* Completion response. */ |
| #define | MBC_NOP 0 /* No Operation */ |
| #define | MBC_LOAD_RAM 1 /* Load RAM */ |
| #define | MBC_EXECUTE_FIRMWARE 2 /* Execute firmware */ |
| #define | MBC_DUMP_RAM 3 /* Dump RAM contents */ |
| #define | MBC_WRITE_RAM_WORD 4 /* Write ram word */ |
| #define | MBC_READ_RAM_WORD 5 /* Read ram word */ |
| #define | MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ |
| #define | MBC_VERIFY_CHECKSUM 7 /* Verify checksum */ |
| #define | MBC_ABOUT_FIRMWARE 8 /* Get firmware revision */ |
| #define | MBC_INIT_REQUEST_QUEUE 0x10 /* Initialize request queue */ |
| #define | MBC_INIT_RESPONSE_QUEUE 0x11 /* Initialize response queue */ |
| #define | MBC_EXECUTE_IOCB 0x12 /* Execute IOCB command */ |
| #define | MBC_ABORT_COMMAND 0x15 /* Abort IOCB command */ |
| #define | MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN) */ |
| #define | MBC_ABORT_TARGET 0x17 /* Abort target (ID) */ |
| #define | MBC_BUS_RESET 0x18 /* SCSI bus reset */ |
| #define | MBC_GET_RETRY_COUNT 0x22 /* Get retry count and delay */ |
| #define | MBC_GET_TARGET_PARAMETERS 0x28 /* Get target parameters */ |
| #define | MBC_SET_INITIATOR_ID 0x30 /* Set initiator SCSI ID */ |
| #define | MBC_SET_SELECTION_TIMEOUT 0x31 /* Set selection timeout */ |
| #define | MBC_SET_RETRY_COUNT 0x32 /* Set retry count and delay */ |
| #define | MBC_SET_TAG_AGE_LIMIT 0x33 /* Set tag age limit */ |
| #define | MBC_SET_CLOCK_RATE 0x34 /* Set clock rate */ |
| #define | MBC_SET_ACTIVE_NEGATION 0x35 /* Set active negation state */ |
| #define | MBC_SET_ASYNC_DATA_SETUP 0x36 /* Set async data setup time */ |
| #define | MBC_SET_PCI_CONTROL 0x37 /* Set BUS control parameters */ |
| #define | MBC_SET_TARGET_PARAMETERS 0x38 /* Set target parameters */ |
| #define | MBC_SET_DEVICE_QUEUE 0x39 /* Set device queue parameters */ |
| #define | MBC_SET_RESET_DELAY_PARAMETERS 0x3A /* Set reset delay parameters */ |
| #define | MBC_SET_SYSTEM_PARAMETER 0x45 /* Set system parameter word */ |
| #define | MBC_SET_FIRMWARE_FEATURES 0x4A /* Set firmware feature word */ |
| #define | MBC_INIT_REQUEST_QUEUE_A64 0x52 /* Initialize request queue A64 */ |
| #define | MBC_INIT_RESPONSE_QUEUE_A64 0x53 /* Initialize response q A64 */ |
| #define | MBC_ENABLE_TARGET_MODE 0x55 /* Enable target mode */ |
| #define | MBC_SET_DATA_OVERRUN_RECOVERY 0x5A /* Set data overrun recovery mode */ |
| #define | TP_PPR BIT_5 /* PPR */ |
| #define | TP_RENEGOTIATE BIT_8 /* Renegotiate on error. */ |
| #define | TP_STOP_QUEUE BIT_9 /* Stop que on check condition */ |
| #define | TP_AUTO_REQUEST_SENSE BIT_10 /* Automatic request sense. */ |
| #define | TP_TAGGED_QUEUE BIT_11 /* Tagged queuing. */ |
| #define | TP_SYNC BIT_12 /* Synchronous data transfers. */ |
| #define | TP_WIDE BIT_13 /* Wide data transfers. */ |
| #define | TP_PARITY BIT_14 /* Parity checking. */ |
| #define | TP_DISCONNECT BIT_15 /* Disconnect privilege. */ |
| #define | NV_START_BIT BIT_2 |
| #define | NV_WRITE_OP (BIT_26 | BIT_24) |
| #define | NV_READ_OP (BIT_26 | BIT_25) |
| #define | NV_ERASE_OP (BIT_26 | BIT_25 | BIT_24) |
| #define | NV_MASK_OP (BIT_26 | BIT_25 | BIT_24) |
| #define | NV_DELAY_COUNT 10 |
| #define | MAX_CMDSZ 12 /* SCSI maximum CDB size. */ |
| #define | COMMAND_TYPE 1 /* Command entry */ |
| #define | CONTINUE_TYPE 2 /* Continuation entry. */ |
| #define | STATUS_TYPE 3 /* Status entry. */ |
| #define | RF_CONT BIT_0 /* Continuation. */ |
| #define | RF_FULL BIT_1 /* Full */ |
| #define | RF_BAD_HEADER BIT_2 /* Bad header. */ |
| #define | RF_BAD_PAYLOAD BIT_3 /* Bad payload. */ |
| #define | SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */ |
| #define | SF_GOT_SENSE BIT_13 /* Got Sense */ |
| #define | SF_GOT_STATUS BIT_12 /* Got Status */ |
| #define | SF_TRANSFERRED_DATA BIT_11 /* Transferred data */ |
| #define | SF_SENT_CDB BIT_10 /* Send CDB */ |
| #define | SF_GOT_TARGET BIT_9 /* */ |
| #define | SF_GOT_BUS BIT_8 /* */ |
| #define | MARKER_TYPE 4 /* Marker entry. */ |
| #define | MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ |
| #define | MK_SYNC_ID 1 /* Synchronize ID */ |
| #define | MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ |
| #define | EXTENDED_CMD_TYPE 5 /* Extended command entry. */ |
| #define | COMMAND_A64_TYPE 9 /* Command A64 entry */ |
| #define | CONTINUE_A64_TYPE 0xA /* Continuation A64 entry. */ |
| #define | ENABLE_LUN_TYPE 0xB /* Enable LUN entry. */ |
| #define | MODIFY_LUN_TYPE 0xC /* Modify LUN entry. */ |
| #define | IMMED_NOTIFY_TYPE 0xD /* Immediate notify entry. */ |
| #define | NOTIFY_ACK_TYPE 0xE /* Notify acknowledge entry. */ |
| #define | ACCEPT_TGT_IO_TYPE 6 /* Accept target I/O entry. */ |
| #define | CONTINUE_TGT_IO_TYPE 7 /* CTIO entry */ |
| #define | CTIO_RET_TYPE 7 /* CTIO return entry */ |
| #define | CTIO_A64_TYPE 0xF /* CTIO A64 entry */ |
| #define | CTIO_A64_RET_TYPE 0xF /* CTIO A64 returned entry */ |
| #define | RESPONSE_ENTRY_SIZE (sizeof(struct response)) |
| #define | REQUEST_ENTRY_SIZE (sizeof(request_t)) |
| #define | CS_COMPLETE 0x0 /* No errors */ |
| #define | CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ |
| #define | CS_DMA 0x2 /* A DMA direction error. */ |
| #define | CS_TRANSPORT 0x3 /* Transport error. */ |
| #define | CS_RESET 0x4 /* SCSI bus reset occurred */ |
| #define | CS_ABORTED 0x5 /* System aborted command. */ |
| #define | CS_TIMEOUT 0x6 /* Timeout error. */ |
| #define | CS_DATA_OVERRUN 0x7 /* Data overrun. */ |
| #define | CS_COMMAND_OVERRUN 0x8 /* Command Overrun. */ |
| #define | CS_STATUS_OVERRUN 0x9 /* Status Overrun. */ |
| #define | CS_BAD_MSG 0xA /* Bad msg after status phase. */ |
| #define | CS_NO_MSG_OUT 0xB /* No msg out after selection. */ |
| #define | CS_EXTENDED_ID 0xC /* Extended ID failed. */ |
| #define | CS_IDE_MSG 0xD /* Target rejected IDE msg. */ |
| #define | CS_ABORT_MSG 0xE /* Target rejected abort msg. */ |
| #define | CS_REJECT_MSG 0xF /* Target rejected reject msg. */ |
| #define | CS_NOP_MSG 0x10 /* Target rejected NOP msg. */ |
| #define | CS_PARITY_MSG 0x11 /* Target rejected parity msg. */ |
| #define | CS_DEV_RESET_MSG 0x12 /* Target rejected dev rst msg. */ |
| #define | CS_ID_MSG 0x13 /* Target rejected ID msg. */ |
| #define | CS_FREE 0x14 /* Unexpected bus free. */ |
| #define | CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ |
| #define | CS_TRANACTION_1 0x18 /* Transaction error 1 */ |
| #define | CS_TRANACTION_2 0x19 /* Transaction error 2 */ |
| #define | CS_TRANACTION_3 0x1a /* Transaction error 3 */ |
| #define | CS_INV_ENTRY_TYPE 0x1b /* Invalid entry type */ |
| #define | CS_DEV_QUEUE_FULL 0x1c /* Device queue full */ |
| #define | CS_PHASED_SKIPPED 0x1d /* SCSI phase skipped */ |
| #define | CS_ARS_FAILED 0x1e /* ARS failed */ |
| #define | CS_LVD_BUS_ERROR 0x21 /* LVD bus error */ |
| #define | CS_BAD_PAYLOAD 0x80 /* Driver defined */ |
| #define | CS_UNKNOWN 0x81 /* Driver defined */ |
| #define | CS_RETRY 0x82 /* Driver defined */ |
| #define | OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */ |
| #define | OF_DATA_IN BIT_6 /* Data in to initiator */ |
| #define | OF_DATA_OUT BIT_7 /* Data out from initiator */ |
| #define | OF_NO_DATA (BIT_7 | BIT_6) |
| #define | OF_DISC_DISABLED BIT_15 /* Disconnects disabled */ |
| #define | OF_DISABLE_SDP BIT_24 /* Disable sending save data ptr */ |
| #define | OF_SEND_RDP BIT_26 /* Send restore data pointers msg */ |
| #define | OF_FORCE_DISC BIT_30 /* Disconnects mandatory */ |
| #define | OF_SSTS BIT_31 /* Send SCSI status */ |
Typedefs | |
| typedef struct cmd_a64_entry_t | request_t |
| #define COMPLETED_HANDLE |
| #define CONTINUE_A64_TYPE 0xA /* Continuation A64 entry. */ |
| #define CS_DEV_RESET_MSG 0x12 /* Target rejected dev rst msg. */ |
| #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ |
| #define CS_NO_MSG_OUT 0xB /* No msg out after selection. */ |
| #define CS_PARITY_MSG 0x11 /* Target rejected parity msg. */ |
| #define CS_REJECT_MSG 0xF /* Target rejected reject msg. */ |
| #define CTIO_A64_RET_TYPE 0xF /* CTIO A64 returned entry */ |
| #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */ |
| #define IMMED_NOTIFY_TYPE 0xD /* Immediate notify entry. */ |
| #define ISP_CFG0_HWMSK 0x000f /* Hardware revision mask */ |
| #define MBA_BUS_MODE_CHANGE 0x800E /* SCSI bus mode transition. */ |
| #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ |
| #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ |
| #define MBA_SCSI_COMPLETION 0x8020 /* Completion response. */ |
| #define MBA_TIMEOUT_RESET 0x8006 /* Execution Timeout Reset. */ |
| #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ |
| #define MBC_ENABLE_TARGET_MODE 0x55 /* Enable target mode */ |
| #define MBC_GET_RETRY_COUNT 0x22 /* Get retry count and delay */ |
| #define MBC_GET_TARGET_PARAMETERS 0x28 /* Get target parameters */ |
| #define MBC_INIT_REQUEST_QUEUE 0x10 /* Initialize request queue */ |
| #define MBC_INIT_REQUEST_QUEUE_A64 0x52 /* Initialize request queue A64 */ |
| #define MBC_INIT_RESPONSE_QUEUE 0x11 /* Initialize response queue */ |
| #define MBC_INIT_RESPONSE_QUEUE_A64 0x53 /* Initialize response q A64 */ |
| #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ |
| #define MBC_SET_ACTIVE_NEGATION 0x35 /* Set active negation state */ |
| #define MBC_SET_ASYNC_DATA_SETUP 0x36 /* Set async data setup time */ |
| #define MBC_SET_DATA_OVERRUN_RECOVERY 0x5A /* Set data overrun recovery mode */ |
| #define MBC_SET_DEVICE_QUEUE 0x39 /* Set device queue parameters */ |
| #define MBC_SET_FIRMWARE_FEATURES 0x4A /* Set firmware feature word */ |
| #define MBC_SET_INITIATOR_ID 0x30 /* Set initiator SCSI ID */ |
| #define MBC_SET_PCI_CONTROL 0x37 /* Set BUS control parameters */ |
| #define MBC_SET_RESET_DELAY_PARAMETERS 0x3A /* Set reset delay parameters */ |
| #define MBC_SET_RETRY_COUNT 0x32 /* Set retry count and delay */ |
| #define MBC_SET_SELECTION_TIMEOUT 0x31 /* Set selection timeout */ |
| #define MBC_SET_SYSTEM_PARAMETER 0x45 /* Set system parameter word */ |
| #define MBC_SET_TAG_AGE_LIMIT 0x33 /* Set tag age limit */ |
| #define MBC_SET_TARGET_PARAMETERS 0x38 /* Set target parameters */ |
| #define MBS_CMD_PARAM_ERR 0x4006 /* Command Parameter Error. */ |
| #define MBS_HOST_INF_ERR 0x4002 /* Host Interface Error. */ |
| #define NOTIFY_ACK_TYPE 0xE /* Notify acknowledge entry. */ |
| #define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */ |
| #define RD_REG_WORD_dmasync | ( | addr | ) | RD_REG_WORD(addr) |
| #define REQUEST_ENTRY_CNT 255 /* Number of request entries. */ |
| #define RESPONSE_ENTRY_CNT 63 /* Number of response entries. */ |
| typedef struct cmd_a64_entry_t request_t |
1.8.2