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#define | QLA2XXX_DRIVER_NAME "qla2xxx" |
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#define | QLA2XXX_APIDEV "ql2xapidev" |
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#define | MAILBOX_REGISTER_COUNT_2100 8 |
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#define | MAILBOX_REGISTER_COUNT_2200 24 |
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#define | MAILBOX_REGISTER_COUNT 32 |
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#define | QLA2200A_RISC_ROM_VER 4 |
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#define | FPM_2300 6 |
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#define | FPM_2310 7 |
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#define | BIT_0 0x1 |
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#define | BIT_1 0x2 |
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#define | BIT_2 0x4 |
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#define | BIT_3 0x8 |
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#define | BIT_4 0x10 |
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#define | BIT_5 0x20 |
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#define | BIT_6 0x40 |
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#define | BIT_7 0x80 |
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#define | BIT_8 0x100 |
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#define | BIT_9 0x200 |
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#define | BIT_10 0x400 |
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#define | BIT_11 0x800 |
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#define | BIT_12 0x1000 |
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#define | BIT_13 0x2000 |
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#define | BIT_14 0x4000 |
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#define | BIT_15 0x8000 |
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#define | BIT_16 0x10000 |
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#define | BIT_17 0x20000 |
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#define | BIT_18 0x40000 |
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#define | BIT_19 0x80000 |
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#define | BIT_20 0x100000 |
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#define | BIT_21 0x200000 |
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#define | BIT_22 0x400000 |
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#define | BIT_23 0x800000 |
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#define | BIT_24 0x1000000 |
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#define | BIT_25 0x2000000 |
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#define | BIT_26 0x4000000 |
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#define | BIT_27 0x8000000 |
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#define | BIT_28 0x10000000 |
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#define | BIT_29 0x20000000 |
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#define | BIT_30 0x40000000 |
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#define | BIT_31 0x80000000 |
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#define | LSB(x) ((uint8_t)(x)) |
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#define | MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) |
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#define | LSW(x) ((uint16_t)(x)) |
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#define | MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) |
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#define | LSD(x) ((uint32_t)((uint64_t)(x))) |
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#define | MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) |
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#define | MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) |
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#define | RD_REG_BYTE(addr) readb(addr) |
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#define | RD_REG_WORD(addr) readw(addr) |
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#define | RD_REG_DWORD(addr) readl(addr) |
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#define | RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) |
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#define | RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) |
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#define | RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) |
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#define | WRT_REG_BYTE(addr, data) writeb(data,addr) |
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#define | WRT_REG_WORD(addr, data) writew(data,addr) |
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#define | WRT_REG_DWORD(addr, data) writel(data,addr) |
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#define | QLA83XX_LED_PORT0 0x00201320 |
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#define | QLA83XX_LED_PORT1 0x00201328 |
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#define | QLA83XX_IDC_DEV_STATE 0x22102384 |
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#define | QLA83XX_IDC_MAJOR_VERSION 0x22102380 |
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#define | QLA83XX_IDC_MINOR_VERSION 0x22102398 |
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#define | QLA83XX_IDC_DRV_PRESENCE 0x22102388 |
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#define | QLA83XX_IDC_DRIVER_ACK 0x2210238c |
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#define | QLA83XX_IDC_CONTROL 0x22102390 |
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#define | QLA83XX_IDC_AUDIT 0x22102394 |
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#define | QLA83XX_IDC_LOCK_RECOVERY 0x2210239c |
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#define | QLA83XX_DRIVER_LOCKID 0x22102104 |
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#define | QLA83XX_DRIVER_LOCK 0x8111c028 |
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#define | QLA83XX_DRIVER_UNLOCK 0x8111c02c |
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#define | QLA83XX_FLASH_LOCKID 0x22102100 |
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#define | QLA83XX_FLASH_LOCK 0x8111c010 |
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#define | QLA83XX_FLASH_UNLOCK 0x8111c014 |
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#define | QLA83XX_DEV_PARTINFO1 0x221023e0 |
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#define | QLA83XX_DEV_PARTINFO2 0x221023e4 |
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#define | QLA83XX_FW_HEARTBEAT 0x221020b0 |
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#define | QLA83XX_PEG_HALT_STATUS1 0x221020a8 |
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#define | QLA83XX_PEG_HALT_STATUS2 0x221020ac |
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#define | IDC_DEVICE_STATE_CHANGE BIT_0 |
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#define | IDC_PEG_HALT_STATUS_CHANGE BIT_1 |
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#define | IDC_NIC_FW_REPORTED_FAILURE BIT_2 |
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#define | IDC_HEARTBEAT_FAILURE BIT_3 |
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#define | ERR_LEVEL_NON_FATAL 0x1 |
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#define | ERR_LEVEL_RECOVERABLE_FATAL 0x2 |
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#define | ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 |
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#define | QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 |
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#define | QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 |
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#define | QLA83XX_NIC_CORE_RESET 0x1 |
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#define | QLA83XX_IDC_STATE_HANDLER 0x2 |
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#define | QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 |
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#define | QLA83XX_IDC_RESET_DISABLED BIT_0 |
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#define | QLA83XX_IDC_GRACEFUL_RESET BIT_1 |
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#define | QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 |
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#define | QLA83XX_IDC_RESET_ACK_TIMEOUT 10 |
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#define | QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) |
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#define | QLA83XX_CLASS_TYPE_NONE 0x0 |
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#define | QLA83XX_CLASS_TYPE_NIC 0x1 |
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#define | QLA83XX_CLASS_TYPE_FCOE 0x2 |
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#define | QLA83XX_CLASS_TYPE_ISCSI 0x3 |
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#define | IDC_LOCK_RECOVERY_STAGE1 |
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#define | IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ |
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#define | IDC_AUDIT_TIMESTAMP |
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#define | IDC_AUDIT_COMPLETION |
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#define | RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) |
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#define | WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) |
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#define | WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ |
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#define | MAX_FIBRE_DEVICES_2100 512 |
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#define | MAX_FIBRE_DEVICES_2400 2048 |
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#define | MAX_FIBRE_DEVICES_LOOP 128 |
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#define | MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 |
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#define | LOOPID_MAP_SIZE (ha->max_fibre_devices) |
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#define | MAX_FIBRE_LUNS 0xFFFF |
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#define | MAX_HOST_COUNT 16 |
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#define | MAX_BUSES 1 /* We only have one bus today */ |
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#define | MIN_LUNS 8 |
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#define | MAX_LUNS MAX_FIBRE_LUNS |
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#define | MAX_CMDS_PER_LUN 255 |
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#define | SNS_LAST_LOOP_ID_2100 0xfe |
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#define | SNS_LAST_LOOP_ID_2300 0x7ff |
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#define | LAST_LOCAL_LOOP_ID 0x7d |
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#define | SNS_FL_PORT 0x7e |
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#define | FABRIC_CONTROLLER 0x7f |
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#define | SIMPLE_NAME_SERVER 0x80 |
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#define | SNS_FIRST_LOOP_ID 0x81 |
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#define | MANAGEMENT_SERVER 0xfe |
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#define | BROADCAST 0xff |
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#define | NPH_LAST_HANDLE 0x7ef |
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#define | NPH_MGMT_SERVER 0x7fa /* FFFFFA */ |
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#define | NPH_SNS 0x7fc /* FFFFFC */ |
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#define | NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ |
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#define | NPH_F_PORT 0x7fe /* FFFFFE */ |
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#define | NPH_IP_BROADCAST 0x7ff /* FFFFFF */ |
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#define | MAX_CMDSZ 16 /* SCSI maximum CDB size. */ |
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#define | PORT_RETRY_TIME 1 |
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#define | LOOP_DOWN_TIMEOUT 60 |
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#define | LOOP_DOWN_TIME 255 /* 240 */ |
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#define | LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) |
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#define | MAX_OUTSTANDING_COMMANDS 1024 |
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#define | REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ |
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#define | REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ |
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#define | REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ |
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#define | RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ |
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#define | RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ |
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#define | RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ |
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#define | ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ |
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#define | SRB_DMA_VALID BIT_0 /* Command sent to ISP */ |
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#define | SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ |
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#define | SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ |
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#define | SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ |
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#define | SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ |
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#define | IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) |
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#define | SRB_LOGIN_RETRIED BIT_0 |
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#define | SRB_LOGIN_COND_PLOGI BIT_1 |
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#define | SRB_LOGIN_SKIP_PRLI BIT_2 |
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#define | SRB_LOGIN_CMD 1 |
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#define | SRB_LOGOUT_CMD 2 |
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#define | SRB_ELS_CMD_RPT 3 |
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#define | SRB_ELS_CMD_HST 4 |
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#define | SRB_CT_CMD 5 |
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#define | SRB_ADISC_CMD 6 |
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#define | SRB_TM_CMD 7 |
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#define | SRB_SCSI_CMD 8 |
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#define | SRB_BIDI_CMD 9 |
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#define | GET_CMD_SP(sp) (sp->u.scmd.cmd) |
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#define | SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd) |
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#define | GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx) |
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#define | GET_CMD_SENSE_LEN(sp) (sp->u.scmd.request_sense_length) |
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#define | SET_CMD_SENSE_LEN(sp, len) (sp->u.scmd.request_sense_length = len) |
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#define | GET_CMD_SENSE_PTR(sp) (sp->u.scmd.request_sense_ptr) |
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#define | SET_CMD_SENSE_PTR(sp, ptr) (sp->u.scmd.request_sense_ptr = ptr) |
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#define | CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ |
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#define | CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ |
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#define | CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ |
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#define | ICR_EN_INT BIT_15 /* ISP enable interrupts. */ |
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#define | ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ |
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#define | ISR_RISC_INT BIT_3 /* RISC interrupt */ |
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#define | NVR_DESELECT 0 |
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#define | NVR_BUSY BIT_15 |
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#define | NVR_WRT_ENABLE BIT_14 /* Write enable */ |
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#define | NVR_PR_ENABLE BIT_13 /* Protection register enable */ |
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#define | NVR_DATA_IN BIT_3 |
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#define | NVR_DATA_OUT BIT_2 |
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#define | NVR_SELECT BIT_1 |
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#define | NVR_CLOCK BIT_0 |
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#define | NVR_WAIT_CNT 20000 |
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#define | HSR_RISC_INT BIT_15 /* RISC interrupt */ |
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#define | HSR_RISC_PAUSED BIT_8 /* RISC Paused */ |
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#define | HCCR_HOST_INT BIT_7 /* Host interrupt bit */ |
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#define | HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ |
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#define | HCCR_RESET_RISC 0x1000 /* Reset RISC */ |
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#define | HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ |
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#define | HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ |
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#define | HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ |
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#define | HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ |
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#define | HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ |
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#define | HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ |
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#define | HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ |
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#define | GPIO_LED_MASK 0x00C0 |
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#define | GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 |
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#define | GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 |
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#define | GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 |
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#define | GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 |
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#define | GPIO_LED_ALL_OFF 0x0000 |
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#define | GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ |
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#define | GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ |
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#define | ISP_REQ_Q_IN(ha, reg) |
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#define | ISP_REQ_Q_OUT(ha, reg) |
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#define | ISP_RSP_Q_IN(ha, reg) |
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#define | ISP_RSP_Q_OUT(ha, reg) |
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#define | MAILBOX_REG(ha, reg, num) |
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#define | RD_MAILBOX_REG(ha, reg, num) RD_REG_WORD(MAILBOX_REG(ha, reg, num)) |
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#define | WRT_MAILBOX_REG(ha, reg, num, data) WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) |
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#define | FB_CMD_REG(ha, reg) |
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#define | RD_FB_CMD_REG(ha, reg) RD_REG_WORD(FB_CMD_REG(ha, reg)) |
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#define | WRT_FB_CMD_REG(ha, reg, data) WRT_REG_WORD(FB_CMD_REG(ha, reg), data) |
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#define | MBX_DMA_IN BIT_0 |
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#define | MBX_DMA_OUT BIT_1 |
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#define | IOCTL_CMD BIT_2 |
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#define | MBX_TOV_SECONDS 30 |
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#define | PROD_ID_1 0x4953 |
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#define | PROD_ID_2 0x0000 |
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#define | PROD_ID_2a 0x5020 |
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#define | PROD_ID_3 0x2020 |
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#define | MBS_FRM_ALIVE 0 /* Firmware Alive. */ |
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#define | MBS_CHKSUM_ERR 1 /* Checksum Error. */ |
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#define | MBS_BUSY 4 /* Busy. */ |
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#define | MBS_COMMAND_COMPLETE 0x4000 |
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#define | MBS_INVALID_COMMAND 0x4001 |
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#define | MBS_HOST_INTERFACE_ERROR 0x4002 |
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#define | MBS_TEST_FAILED 0x4003 |
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#define | MBS_COMMAND_ERROR 0x4005 |
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#define | MBS_COMMAND_PARAMETER_ERROR 0x4006 |
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#define | MBS_PORT_ID_USED 0x4007 |
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#define | MBS_LOOP_ID_USED 0x4008 |
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#define | MBS_ALL_IDS_IN_USE 0x4009 |
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#define | MBS_NOT_LOGGED_IN 0x400A |
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#define | MBS_LINK_DOWN_ERROR 0x400B |
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#define | MBS_DIAG_ECHO_TEST_ERROR 0x400C |
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#define | MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ |
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#define | MBA_RESET 0x8001 /* Reset Detected. */ |
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#define | MBA_SYSTEM_ERR 0x8002 /* System Error. */ |
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#define | MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ |
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#define | MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ |
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#define | MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ |
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#define | MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ |
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#define | MBA_LOOP_UP 0x8011 /* FC Loop UP. */ |
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#define | MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ |
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#define | MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ |
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#define | MBA_PORT_UPDATE 0x8014 /* Port Database update. */ |
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#define | MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ |
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#define | MBA_LIP_F8 0x8016 /* Received a LIP F8. */ |
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#define | MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ |
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#define | MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ |
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#define | MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ |
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#define | MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ |
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#define | MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ |
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#define | MBA_IP_RECEIVE 0x8023 /* IP Received. */ |
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#define | MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ |
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#define | MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ |
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#define | MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ |
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#define | MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ |
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#define | MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ |
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#define | MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ |
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#define | MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ |
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#define | MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ |
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#define | MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ |
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#define | MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ |
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#define | MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ |
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#define | MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ |
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#define | MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ |
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#define | MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ |
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#define | MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ |
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#define | MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ |
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#define | MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ |
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#define | MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ |
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#define | MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ |
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#define | INTR_ROM_MB_SUCCESS 0x1 |
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#define | INTR_ROM_MB_FAILED 0x2 |
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#define | INTR_MB_SUCCESS 0x10 |
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#define | INTR_MB_FAILED 0x11 |
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#define | INTR_ASYNC_EVENT 0x12 |
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#define | INTR_RSP_QUE_UPDATE 0x13 |
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#define | INTR_RSP_QUE_UPDATE_83XX 0x14 |
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#define | INTR_ATIO_QUE_UPDATE 0x1C |
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#define | INTR_ATIO_RSP_QUE_UPDATE 0x1D |
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#define | MBS_LB_RESET 0x17 |
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#define | FO1_AE_ON_LIPF8 BIT_0 |
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#define | FO1_AE_ALL_LIP_RESET BIT_1 |
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#define | FO1_CTIO_RETRY BIT_3 |
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#define | FO1_DISABLE_LIP_F7_SW BIT_4 |
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#define | FO1_DISABLE_100MS_LOS_WAIT BIT_5 |
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#define | FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ |
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#define | FO1_AE_ON_LOOP_INIT_ERR BIT_7 |
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#define | FO1_SET_EMPHASIS_SWING BIT_8 |
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#define | FO1_AE_AUTO_BYPASS BIT_9 |
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#define | FO1_ENABLE_PURE_IOCB BIT_10 |
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#define | FO1_AE_PLOGI_RJT BIT_11 |
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#define | FO1_ENABLE_ABORT_SEQUENCE BIT_12 |
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#define | FO1_AE_QUEUE_FULL BIT_13 |
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#define | FO2_ENABLE_ATIO_TYPE_3 BIT_0 |
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#define | FO2_REV_LOOPBACK BIT_1 |
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#define | FO3_ENABLE_EMERG_IOCB BIT_0 |
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#define | FO3_AE_RND_ERROR BIT_1 |
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#define | ADD_FO_COUNT 3 |
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#define | ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ |
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#define | ADD_FO1_ENABLE_PUREX_IOCB BIT_10 |
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#define | ADD_FO2_ENABLE_SEL_CLS2 BIT_5 |
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#define | ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 |
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#define | MBC_LOAD_RAM 1 /* Load RAM. */ |
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#define | MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ |
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#define | MBC_WRITE_RAM_WORD 4 /* Write RAM word. */ |
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#define | MBC_READ_RAM_WORD 5 /* Read RAM word. */ |
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#define | MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ |
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#define | MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ |
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#define | MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ |
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#define | MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ |
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#define | MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ |
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#define | MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ |
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#define | MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ |
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#define | MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ |
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#define | MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ |
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#define | MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ |
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#define | MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ |
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#define | MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ |
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#define | MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ |
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#define | MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ |
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#define | MBC_RESET 0x18 /* Reset. */ |
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#define | MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ |
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#define | MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ |
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#define | MBC_DISABLE_VI 0x24 /* Disable VI operation. */ |
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#define | MBC_ENABLE_VI 0x25 /* Enable VI operation. */ |
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#define | MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ |
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#define | MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ |
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#define | MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ |
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#define | MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ |
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#define | MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ |
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#define | MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ |
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#define | MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ |
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#define | MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ |
|
#define | MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ |
|
#define | MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ |
|
#define | MBC_CONFIGURE_VF 0x4b /* Configure VFs */ |
|
#define | MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ |
|
#define | MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ |
|
#define | MBC_PORT_LOGOUT 0x56 /* Port Logout request */ |
|
#define | MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ |
|
#define | MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ |
|
#define | MBC_GET_RNID_PARAMS 0x5a /* Data Rate */ |
|
#define | MBC_DATA_RATE 0x5d /* Get RNID parameters */ |
|
#define | MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ |
|
#define | MBC_INITIATE_LIP 0x62 /* Initiate Loop */ |
|
#define | MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ |
|
#define | MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ |
|
#define | MBC_CLEAR_ACA 0x65 /* Clear ACA. */ |
|
#define | MBC_TARGET_RESET 0x66 /* Target Reset. */ |
|
#define | MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ |
|
#define | MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ |
|
#define | MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ |
|
#define | MBC_GET_PORT_NAME 0x6a /* Get port name. */ |
|
#define | MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ |
|
#define | MBC_LIP_RESET 0x6c /* LIP reset. */ |
|
#define | MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ |
|
#define | MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ |
|
#define | MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ |
|
#define | MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ |
|
#define | MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ |
|
#define | MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ |
|
#define | MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ |
|
#define | MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ |
|
#define | MBC_UNLOAD_IP 0x79 /* Shutdown IP */ |
|
#define | MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ |
|
#define | MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ |
|
#define | MBC_LUN_RESET 0x7E /* Send LUN reset */ |
|
#define | MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ |
|
#define | MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ |
|
#define | MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ |
|
#define | MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ |
|
#define | MBC_TRACE_CONTROL 0x27 /* Trace control command. */ |
|
#define | MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ |
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#define | MBC_WRITE_SFP 0x30 /* Write SFP Data. */ |
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#define | MBC_READ_SFP 0x31 /* Read SFP Data. */ |
|
#define | MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ |
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#define | MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ |
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#define | MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ |
|
#define | MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ |
|
#define | MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ |
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#define | MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ |
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#define | MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ |
|
#define | MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ |
|
#define | MBC_PORT_RESET 0x120 /* Port Reset */ |
|
#define | MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ |
|
#define | MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ |
|
#define | MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ |
|
#define | FCAL_MAP_SIZE 128 |
|
#define | MBX_31 BIT_31 |
|
#define | MBX_30 BIT_30 |
|
#define | MBX_29 BIT_29 |
|
#define | MBX_28 BIT_28 |
|
#define | MBX_27 BIT_27 |
|
#define | MBX_26 BIT_26 |
|
#define | MBX_25 BIT_25 |
|
#define | MBX_24 BIT_24 |
|
#define | MBX_23 BIT_23 |
|
#define | MBX_22 BIT_22 |
|
#define | MBX_21 BIT_21 |
|
#define | MBX_20 BIT_20 |
|
#define | MBX_19 BIT_19 |
|
#define | MBX_18 BIT_18 |
|
#define | MBX_17 BIT_17 |
|
#define | MBX_16 BIT_16 |
|
#define | MBX_15 BIT_15 |
|
#define | MBX_14 BIT_14 |
|
#define | MBX_13 BIT_13 |
|
#define | MBX_12 BIT_12 |
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#define | MBX_11 BIT_11 |
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#define | MBX_10 BIT_10 |
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#define | MBX_9 BIT_9 |
|
#define | MBX_8 BIT_8 |
|
#define | MBX_7 BIT_7 |
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#define | MBX_6 BIT_6 |
|
#define | MBX_5 BIT_5 |
|
#define | MBX_4 BIT_4 |
|
#define | MBX_3 BIT_3 |
|
#define | MBX_2 BIT_2 |
|
#define | MBX_1 BIT_1 |
|
#define | MBX_0 BIT_0 |
|
#define | FSTATE_CONFIG_WAIT 0 |
|
#define | FSTATE_WAIT_AL_PA 1 |
|
#define | FSTATE_WAIT_LOGIN 2 |
|
#define | FSTATE_READY 3 |
|
#define | FSTATE_LOSS_OF_SYNC 4 |
|
#define | FSTATE_ERROR 5 |
|
#define | FSTATE_REINIT 6 |
|
#define | FSTATE_NON_PART 7 |
|
#define | FSTATE_CONFIG_CORRECT 0 |
|
#define | FSTATE_P2P_RCV_LIP 1 |
|
#define | FSTATE_P2P_CHOOSE_LOOP 2 |
|
#define | FSTATE_P2P_RCV_UNIDEN_LIP 3 |
|
#define | FSTATE_FATAL_ERROR 4 |
|
#define | FSTATE_LOOP_BACK_CONN 5 |
|
#define | PORT_DATABASE_SIZE 128 /* bytes */ |
|
#define | PD_STATE_DISCOVERY 0 |
|
#define | PD_STATE_WAIT_DISCOVERY_ACK 1 |
|
#define | PD_STATE_PORT_LOGIN 2 |
|
#define | PD_STATE_WAIT_PORT_LOGIN_ACK 3 |
|
#define | PD_STATE_PROCESS_LOGIN 4 |
|
#define | PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 |
|
#define | PD_STATE_PORT_LOGGED_IN 6 |
|
#define | PD_STATE_PORT_UNAVAILABLE 7 |
|
#define | PD_STATE_PROCESS_LOGOUT 8 |
|
#define | PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 |
|
#define | PD_STATE_PORT_LOGOUT 10 |
|
#define | PD_STATE_WAIT_PORT_LOGOUT_ACK 11 |
|
#define | QLA_ZIO_MODE_6 (BIT_2 | BIT_1) |
|
#define | QLA_ZIO_DISABLED 0 |
|
#define | QLA_ZIO_DEFAULT_TIMER 2 |
|
#define | ICB_VERSION 1 |
|
#define | GLSO_SEND_RPS BIT_0 |
|
#define | GLSO_USE_DID BIT_3 |
|
#define | NV_START_BIT BIT_2 |
|
#define | NV_WRITE_OP (BIT_26+BIT_24) |
|
#define | NV_READ_OP (BIT_26+BIT_25) |
|
#define | NV_ERASE_OP (BIT_26+BIT_25+BIT_24) |
|
#define | NV_MASK_OP (BIT_26+BIT_25+BIT_24) |
|
#define | NV_DELAY_COUNT 10 |
|
#define | RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ |
|
#define | ATIO_PROCESSED 0xDEADDEAD /* Signature */ |
|
#define | SET_TARGET_ID(ha, to, from) |
|
#define | COMMAND_TYPE 0x11 /* Command entry */ |
|
#define | CF_WRITE BIT_6 |
|
#define | CF_READ BIT_5 |
|
#define | CF_SIMPLE_TAG BIT_3 |
|
#define | CF_ORDERED_TAG BIT_2 |
|
#define | CF_HEAD_TAG BIT_1 |
|
#define | COMMAND_A64_TYPE 0x19 /* Command A64 entry */ |
|
#define | CONTINUE_TYPE 0x02 /* Continuation entry. */ |
|
#define | CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ |
|
#define | PO_MODE_DIF_INSERT 0 |
|
#define | PO_MODE_DIF_REMOVE 1 |
|
#define | PO_MODE_DIF_PASS 2 |
|
#define | PO_MODE_DIF_REPLACE 3 |
|
#define | PO_MODE_DIF_TCP_CKSUM 6 |
|
#define | PO_ENABLE_DIF_BUNDLING BIT_8 |
|
#define | PO_ENABLE_INCR_GUARD_SEED BIT_3 |
|
#define | PO_DISABLE_INCR_REF_TAG BIT_5 |
|
#define | PO_DISABLE_GUARD_CHECK BIT_4 |
|
#define | CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) |
|
#define | CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) |
|
#define | STATUS_TYPE 0x03 /* Status entry. */ |
|
#define | RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ |
|
#define | RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ |
|
#define | RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ |
|
#define | RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ |
|
#define | RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ |
|
#define | RF_BUSY BIT_1 /* Busy */ |
|
#define | RF_MASK |
|
#define | RF_MASK_24XX |
|
#define | SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ |
|
#define | SS_RESIDUAL_UNDER BIT_11 |
|
#define | SS_RESIDUAL_OVER BIT_10 |
|
#define | SS_SENSE_LEN_VALID BIT_9 |
|
#define | SS_RESPONSE_INFO_LEN_VALID BIT_8 |
|
#define | SS_RESERVE_CONFLICT (BIT_4 | BIT_3) |
|
#define | SS_BUSY_CONDITION BIT_3 |
|
#define | SS_CONDITION_MET BIT_2 |
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#define | SS_CHECK_CONDITION BIT_1 |
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#define | CS_COMPLETE 0x0 /* No errors */ |
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#define | CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ |
|
#define | CS_DMA 0x2 /* A DMA direction error. */ |
|
#define | CS_TRANSPORT 0x3 /* Transport error. */ |
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#define | CS_RESET 0x4 /* SCSI bus reset occurred */ |
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#define | CS_ABORTED 0x5 /* System aborted command. */ |
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#define | CS_TIMEOUT 0x6 /* Timeout error. */ |
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#define | CS_DATA_OVERRUN 0x7 /* Data overrun. */ |
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#define | CS_DIF_ERROR 0xC /* DIF error detected */ |
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#define | CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ |
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#define | CS_QUEUE_FULL 0x1C /* Queue Full. */ |
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#define | CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ |
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#define | CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ |
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#define | CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ |
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#define | CS_PORT_BUSY 0x2B /* Port Busy */ |
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#define | CS_COMPLETE_CHKCOND 0x30 /* Error? */ |
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#define | CS_BAD_PAYLOAD 0x80 /* Driver defined */ |
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#define | CS_UNKNOWN 0x81 /* Driver defined */ |
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#define | CS_RETRY 0x82 /* Driver defined */ |
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#define | CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ |
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#define | CS_BIDIR_RD_OVERRUN 0x700 |
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#define | CS_BIDIR_RD_WR_OVERRUN 0x707 |
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#define | CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 |
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#define | CS_BIDIR_RD_UNDERRUN 0x1500 |
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#define | CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 |
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#define | CS_BIDIR_RD_WR_UNDERRUN 0x1515 |
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#define | CS_BIDIR_DMA 0x200 |
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#define | SF_ABTS_TERMINATED BIT_10 |
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#define | SF_LOGOUT_SENT BIT_13 |
|
#define | STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ |
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#define | STATUS_TYPE_21 0x21 /* Status entry. */ |
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#define | STATUS_TYPE_22 0x22 /* Status entry. */ |
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#define | MARKER_TYPE 0x04 /* Marker entry. */ |
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#define | MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ |
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#define | MK_SYNC_ID 1 /* Synchronize ID */ |
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#define | MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ |
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#define | MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ |
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#define | MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ |
|
#define | MBX_IOCB_TYPE 0x39 |
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#define | SOURCE_SCSI 0x00 |
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#define | SOURCE_IP 0x01 |
|
#define | SOURCE_VI 0x02 |
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#define | SOURCE_SCTP 0x03 |
|
#define | SOURCE_MP 0x04 |
|
#define | SOURCE_MPIOCTL 0x05 |
|
#define | SOURCE_ASYNC_IOCB 0x07 |
|
#define | RESPONSE_ENTRY_SIZE (sizeof(response_t)) |
|
#define | REQUEST_ENTRY_SIZE (sizeof(request_t)) |
|
#define | INVALID_PORT_ID 0xFFFFFF |
|
#define | FC4_TYPE_FCP_SCSI 0x08 |
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#define | FC4_TYPE_OTHER 0x0 |
|
#define | FC4_TYPE_UNKNOWN 0xff |
|
#define | QLA_FCPORT_SCAN_NONE 0 |
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#define | QLA_FCPORT_SCAN_FOUND 1 |
|
#define | FCS_UNCONFIGURED 1 |
|
#define | FCS_DEVICE_DEAD 2 |
|
#define | FCS_DEVICE_LOST 3 |
|
#define | FCS_ONLINE 4 |
|
#define | FCF_FABRIC_DEVICE BIT_0 |
|
#define | FCF_LOGIN_NEEDED BIT_1 |
|
#define | FCF_FCP2_DEVICE BIT_2 |
|
#define | FCF_ASYNC_SENT BIT_3 |
|
#define | FCF_CONF_COMP_SUPPORTED BIT_4 |
|
#define | FC_NO_LOOP_ID 0x1000 |
|
#define | CT_REJECT_RESPONSE 0x8001 |
|
#define | CT_ACCEPT_RESPONSE 0x8002 |
|
#define | CT_REASON_INVALID_COMMAND_CODE 0x01 |
|
#define | CT_REASON_CANNOT_PERFORM 0x09 |
|
#define | CT_REASON_COMMAND_UNSUPPORTED 0x0b |
|
#define | CT_EXPL_ALREADY_REGISTERED 0x10 |
|
#define | NS_N_PORT_TYPE 0x01 |
|
#define | NS_NL_PORT_TYPE 0x02 |
|
#define | NS_NX_PORT_TYPE 0x7F |
|
#define | GA_NXT_CMD 0x100 |
|
#define | GA_NXT_REQ_SIZE (16 + 4) |
|
#define | GA_NXT_RSP_SIZE (16 + 620) |
|
#define | GID_PT_CMD 0x1A1 |
|
#define | GID_PT_REQ_SIZE (16 + 4) |
|
#define | GPN_ID_CMD 0x112 |
|
#define | GPN_ID_REQ_SIZE (16 + 4) |
|
#define | GPN_ID_RSP_SIZE (16 + 8) |
|
#define | GNN_ID_CMD 0x113 |
|
#define | GNN_ID_REQ_SIZE (16 + 4) |
|
#define | GNN_ID_RSP_SIZE (16 + 8) |
|
#define | GFT_ID_CMD 0x117 |
|
#define | GFT_ID_REQ_SIZE (16 + 4) |
|
#define | GFT_ID_RSP_SIZE (16 + 32) |
|
#define | RFT_ID_CMD 0x217 |
|
#define | RFT_ID_REQ_SIZE (16 + 4 + 32) |
|
#define | RFT_ID_RSP_SIZE 16 |
|
#define | RFF_ID_CMD 0x21F |
|
#define | RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) |
|
#define | RFF_ID_RSP_SIZE 16 |
|
#define | RNN_ID_CMD 0x213 |
|
#define | RNN_ID_REQ_SIZE (16 + 4 + 8) |
|
#define | RNN_ID_RSP_SIZE 16 |
|
#define | RSNN_NN_CMD 0x239 |
|
#define | RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) |
|
#define | RSNN_NN_RSP_SIZE 16 |
|
#define | GFPN_ID_CMD 0x11C |
|
#define | GFPN_ID_REQ_SIZE (16 + 4) |
|
#define | GFPN_ID_RSP_SIZE (16 + 8) |
|
#define | GPSC_CMD 0x127 |
|
#define | GPSC_REQ_SIZE (16 + 8) |
|
#define | GPSC_RSP_SIZE (16 + 2 + 2) |
|
#define | GFF_ID_CMD 0x011F |
|
#define | GFF_ID_REQ_SIZE (16 + 4) |
|
#define | GFF_ID_RSP_SIZE (16 + 128) |
|
#define | FDMI_HBA_ATTR_COUNT 9 |
|
#define | FDMI_HBA_NODE_NAME 1 |
|
#define | FDMI_HBA_MANUFACTURER 2 |
|
#define | FDMI_HBA_SERIAL_NUMBER 3 |
|
#define | FDMI_HBA_MODEL 4 |
|
#define | FDMI_HBA_MODEL_DESCRIPTION 5 |
|
#define | FDMI_HBA_HARDWARE_VERSION 6 |
|
#define | FDMI_HBA_DRIVER_VERSION 7 |
|
#define | FDMI_HBA_OPTION_ROM_VERSION 8 |
|
#define | FDMI_HBA_FIRMWARE_VERSION 9 |
|
#define | FDMI_HBA_OS_NAME_AND_VERSION 0xa |
|
#define | FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb |
|
#define | FDMI_PORT_ATTR_COUNT 6 |
|
#define | FDMI_PORT_FC4_TYPES 1 |
|
#define | FDMI_PORT_SUPPORT_SPEED 2 |
|
#define | FDMI_PORT_CURRENT_SPEED 3 |
|
#define | FDMI_PORT_MAX_FRAME_SIZE 4 |
|
#define | FDMI_PORT_OS_DEVICE_NAME 5 |
|
#define | FDMI_PORT_HOST_NAME 6 |
|
#define | FDMI_PORT_SPEED_1GB 0x1 |
|
#define | FDMI_PORT_SPEED_2GB 0x2 |
|
#define | FDMI_PORT_SPEED_10GB 0x4 |
|
#define | FDMI_PORT_SPEED_4GB 0x8 |
|
#define | FDMI_PORT_SPEED_8GB 0x10 |
|
#define | FDMI_PORT_SPEED_16GB 0x20 |
|
#define | FDMI_PORT_SPEED_UNKNOWN 0x8000 |
|
#define | GRHL_CMD 0x100 |
|
#define | GHAT_CMD 0x101 |
|
#define | GRPL_CMD 0x102 |
|
#define | GPAT_CMD 0x110 |
|
#define | RHBA_CMD 0x200 |
|
#define | RHBA_RSP_SIZE 16 |
|
#define | RHAT_CMD 0x201 |
|
#define | RPRT_CMD 0x210 |
|
#define | RPA_CMD 0x211 |
|
#define | RPA_RSP_SIZE 16 |
|
#define | DHBA_CMD 0x300 |
|
#define | DHBA_REQ_SIZE (16 + 8) |
|
#define | DHBA_RSP_SIZE 16 |
|
#define | DHAT_CMD 0x301 |
|
#define | DPRT_CMD 0x310 |
|
#define | DPA_CMD 0x311 |
|
#define | GFF_FCP_SCSI_OFFSET 7 |
|
#define | RFT_ID_SNS_SCMD_LEN 22 |
|
#define | RFT_ID_SNS_CMD_SIZE 60 |
|
#define | RFT_ID_SNS_DATA_SIZE 16 |
|
#define | RNN_ID_SNS_SCMD_LEN 10 |
|
#define | RNN_ID_SNS_CMD_SIZE 36 |
|
#define | RNN_ID_SNS_DATA_SIZE 16 |
|
#define | GA_NXT_SNS_SCMD_LEN 6 |
|
#define | GA_NXT_SNS_CMD_SIZE 28 |
|
#define | GA_NXT_SNS_DATA_SIZE (620 + 16) |
|
#define | GID_PT_SNS_SCMD_LEN 6 |
|
#define | GID_PT_SNS_CMD_SIZE 28 |
|
#define | GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) |
|
#define | GPN_ID_SNS_SCMD_LEN 6 |
|
#define | GPN_ID_SNS_CMD_SIZE 28 |
|
#define | GPN_ID_SNS_DATA_SIZE (8 + 16) |
|
#define | GNN_ID_SNS_SCMD_LEN 6 |
|
#define | GNN_ID_SNS_CMD_SIZE 28 |
|
#define | GNN_ID_SNS_DATA_SIZE (8 + 16) |
|
#define | VP_OPTS_RETRY_ENABLE BIT_0 |
|
#define | VP_OPTS_VP_DISABLE BIT_1 |
|
#define | VP_RET_CODE_OK 0 |
|
#define | VP_RET_CODE_FATAL 1 |
|
#define | VP_RET_CODE_WRONG_ID 2 |
|
#define | VP_RET_CODE_WWPN 3 |
|
#define | VP_RET_CODE_RESOURCES 4 |
|
#define | VP_RET_CODE_NO_MEM 5 |
|
#define | VP_RET_CODE_NOT_FOUND 6 |
|
#define | QLA_MSIX_CHIP_REV_24XX 3 |
|
#define | QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) |
|
#define | QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) |
|
#define | QLA_MSIX_DEFAULT 0x00 |
|
#define | QLA_MSIX_RSP_Q 0x01 |
|
#define | QLA_MIDX_DEFAULT 0 |
|
#define | QLA_MIDX_RSP_Q 1 |
|
#define | QLA_PCI_MSIX_CONTROL 0xa2 |
|
#define | QLA_83XX_PCI_MSIX_CONTROL 0x92 |
|
#define | WATCH_INTERVAL 1 /* number of seconds */ |
|
#define | QLA_EVT_FLAG_FREE 0x1 |
|
#define | QLA_IDC_ACK_REGS 7 |
|
#define | QLA_LOGIO_LOGIN_RETRIED BIT_0 |
|
#define | QLA_UEVENT_CODE_FW_DUMP 0 |
|
#define | MBC_INITIALIZE_MULTIQ 0x1f |
|
#define | QLA_QUE_PAGE 0X1000 |
|
#define | QLA_MQ_SIZE 32 |
|
#define | QLA_MAX_QUEUES 256 |
|
#define | ISP_QUE_REG(ha, id) |
|
#define | QLA_REQ_QUE_ID(tag) ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) |
|
#define | QLA_DEFAULT_QUE_QOS 5 |
|
#define | QLA_PRECONFIG_VPORTS 32 |
|
#define | QLA_MAX_VPORTS_QLA24XX 128 |
|
#define | QLA_MAX_VPORTS_QLA25XX 256 |
|
#define | SRB_MIN_REQ 128 |
|
#define | MIN_IOBASE_LEN 0x100 |
|
#define | FLOGI_SEQ_DEL BIT_8 |
|
#define | FLOGI_MID_SUPPORT BIT_10 |
|
#define | FLOGI_VSAN_SUPPORT BIT_12 |
|
#define | FLOGI_SP_SUPPORT BIT_13 |
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#define | PORT_SPEED_UNKNOWN 0xFFFF |
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#define | PORT_SPEED_1GB 0x00 |
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#define | PORT_SPEED_2GB 0x01 |
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#define | PORT_SPEED_4GB 0x03 |
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#define | PORT_SPEED_8GB 0x04 |
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#define | PORT_SPEED_16GB 0x05 |
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#define | PORT_SPEED_10GB 0x13 |
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#define | ISP_CFG_NL 1 |
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#define | ISP_CFG_N 2 |
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#define | ISP_CFG_FL 4 |
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#define | ISP_CFG_F 8 |
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#define | LOOP 0 |
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#define | P2P 1 |
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#define | LOOP_P2P 2 |
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#define | P2P_LOOP 3 |
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#define | PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 |
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#define | PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 |
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#define | PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 |
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#define | PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 |
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#define | PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 |
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#define | DT_ISP2100 BIT_0 |
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#define | DT_ISP2200 BIT_1 |
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#define | DT_ISP2300 BIT_2 |
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#define | DT_ISP2312 BIT_3 |
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#define | DT_ISP2322 BIT_4 |
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#define | DT_ISP6312 BIT_5 |
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#define | DT_ISP6322 BIT_6 |
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#define | DT_ISP2422 BIT_7 |
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#define | DT_ISP2432 BIT_8 |
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#define | DT_ISP5422 BIT_9 |
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#define | DT_ISP5432 BIT_10 |
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#define | DT_ISP2532 BIT_11 |
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#define | DT_ISP8432 BIT_12 |
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#define | DT_ISP8001 BIT_13 |
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#define | DT_ISP8021 BIT_14 |
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#define | DT_ISP2031 BIT_15 |
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#define | DT_ISP8031 BIT_16 |
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#define | DT_ISP_LAST (DT_ISP8031 << 1) |
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#define | DT_T10_PI BIT_25 |
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#define | DT_IIDMA BIT_26 |
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#define | DT_FWI2 BIT_27 |
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#define | DT_ZIO_SUPPORTED BIT_28 |
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#define | DT_OEM_001 BIT_29 |
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#define | DT_ISP2200A BIT_30 |
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#define | DT_EXTENDED_IDS BIT_31 |
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#define | DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1)) |
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#define | IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) |
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#define | IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) |
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#define | IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) |
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#define | IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) |
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#define | IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) |
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#define | IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) |
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#define | IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) |
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#define | IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) |
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#define | IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) |
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#define | IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) |
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#define | IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) |
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#define | IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) |
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#define | IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) |
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#define | IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) |
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#define | IS_QLA81XX(ha) (IS_QLA8001(ha)) |
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#define | IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) |
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#define | IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) |
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#define | IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) |
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#define | IS_QLA23XX(ha) |
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#define | IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) |
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#define | IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) |
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#define | IS_QLA25XX(ha) (IS_QLA2532(ha)) |
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#define | IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) |
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#define | IS_QLA84XX(ha) (IS_QLA8432(ha)) |
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#define | IS_QLA24XX_TYPE(ha) |
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#define | IS_CNA_CAPABLE(ha) |
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#define | IS_QLA2XXX_MIDTYPE(ha) |
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#define | IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) |
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#define | IS_NOPOLLING_TYPE(ha) |
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#define | IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) |
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#define | IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) |
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#define | IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) |
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#define | IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) |
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#define | IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) |
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#define | IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) |
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#define | IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) |
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#define | IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) |
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#define | HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) |
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#define | IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) |
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#define | IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha)) |
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#define | IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha))) |
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#define | IS_MCTP_CAPABLE(ha) |
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#define | IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha)) |
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#define | IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha)) |
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#define | IS_PI_DIFB_DIX0_CAPABLE(ha) (0) |
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#define | IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha)) |
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#define | IS_PI_SPLIT_DET_CAPABLE(ha) |
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#define | MAX_NVRAM_SIZE 4096 |
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#define | VPD_OFFSET MAX_NVRAM_SIZE / 2 |
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#define | SFP_DEV_SIZE 256 |
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#define | SFP_BLOCK_SIZE 64 |
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#define | XGMAC_DATA_SIZE 4096 |
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#define | DCBX_TLV_DATA_SIZE 4096 |
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#define | DMA_POOL_SIZE 256 |
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#define | MBX_INTERRUPT 1 |
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#define | MBX_INTR_WAIT 2 |
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#define | MBX_UPDATE_FLASH_ACTIVE 3 |
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#define | RISC_START_ADDRESS_2100 0x1000 |
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#define | RISC_START_ADDRESS_2300 0x800 |
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#define | RISC_START_ADDRESS_2400 0x100000 |
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#define | MCTP_DUMP_SIZE 0x086064 |
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#define | BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" |
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#define | QLA_SWAITING 0 |
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#define | QLA_SREADING 1 |
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#define | QLA_SWRITING 2 |
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#define | ROM_CODE_TYPE_BIOS 0 |
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#define | ROM_CODE_TYPE_FCODE 1 |
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#define | ROM_CODE_TYPE_EFI 3 |
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#define | QLA_LED_GRN_ON 0x01 |
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#define | QLA_LED_YLW_ON 0x02 |
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#define | QLA_LED_ABR_ON 0x04 |
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#define | QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ |
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#define | DSD_LIST_DMA_POOL_SIZE 512 |
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#define | FCP_CMND_DMA_POOL_SIZE 512 |
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#define | NUM_DSD_CHAIN 4096 |
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#define | LOOP_TIMEOUT 1 |
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#define | LOOP_DOWN 2 |
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#define | LOOP_UP 3 |
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#define | LOOP_UPDATE 4 |
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#define | LOOP_READY 5 |
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#define | LOOP_DEAD 6 |
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#define | RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ |
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#define | RESET_ACTIVE 1 |
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#define | ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ |
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#define | ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ |
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#define | LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ |
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#define | LOOP_RESYNC_ACTIVE 5 |
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#define | LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ |
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#define | RSCN_UPDATE 7 /* Perform an RSCN update. */ |
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#define | RELOGIN_NEEDED 8 |
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#define | REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ |
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#define | ISP_ABORT_RETRY 10 /* ISP aborted. */ |
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#define | BEACON_BLINK_NEEDED 11 |
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#define | REGISTER_FDMI_NEEDED 12 |
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#define | FCPORT_UPDATE_NEEDED 13 |
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#define | VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ |
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#define | UNLOADING 15 |
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#define | NPIV_CONFIG_NEEDED 16 |
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#define | ISP_UNRECOVERABLE 17 |
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#define | FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ |
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#define | MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ |
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#define | ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ |
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#define | SCR_PENDING 21 /* SCR in target mode */ |
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#define | SWITCH_FOUND BIT_0 |
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#define | DFLG_NO_CABLE BIT_1 |
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#define | DFLG_DEV_FAILED BIT_5 |
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#define | VP_IDX_ACQUIRED 0 /* bit no 0 */ |
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#define | VP_CREATE_NEEDED 1 |
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#define | VP_BIND_NEEDED 2 |
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#define | VP_DELETE_NEEDED 3 |
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#define | VP_SCR_NEEDED 4 /* State Change Request registration */ |
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#define | VP_OFFLINE 0 |
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#define | VP_ACTIVE 1 |
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#define | VP_FAILED 2 |
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#define | VP_ERR_UNKWN 0 |
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#define | VP_ERR_PORTDWN 1 |
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#define | VP_ERR_FAB_UNSUPPORTED 2 |
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#define | VP_ERR_FAB_NORESOURCES 3 |
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#define | VP_ERR_FAB_LOGOUT 4 |
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#define | VP_ERR_ADAP_NORESOURCES 5 |
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#define | SET_VP_IDX 1 |
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#define | SET_AL_PA 2 |
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#define | RESET_VP_IDX 3 |
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#define | RESET_AL_PA 4 |
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#define | LOOP_TRANSITION(ha) |
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#define | QLA_VHA_MARK_BUSY(__vha, __bail) |
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#define | QLA_VHA_MARK_NOT_BUSY(__vha) |
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#define | MBS_MASK 0x3fff |
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#define | QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) |
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#define | QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) |
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#define | QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) |
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#define | QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) |
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#define | QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) |
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#define | QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) |
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#define | QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) |
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#define | QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) |
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#define | QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) |
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#define | QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) |
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#define | QLA_FUNCTION_TIMEOUT 0x100 |
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#define | QLA_FUNCTION_PARAMETER_ERROR 0x101 |
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#define | QLA_FUNCTION_FAILED 0x102 |
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#define | QLA_MEMORY_ALLOC_FAILED 0x103 |
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#define | QLA_LOCK_TIMEOUT 0x104 |
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#define | QLA_ABORTED 0x105 |
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#define | QLA_SUSPENDED 0x106 |
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#define | QLA_BUSY 0x107 |
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#define | QLA_ALREADY_REGISTERED 0x109 |
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#define | NVRAM_DELAY() udelay(10) |
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#define | INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1) |
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#define | OPTROM_SIZE_2300 0x20000 |
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#define | OPTROM_SIZE_2322 0x100000 |
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#define | OPTROM_SIZE_24XX 0x100000 |
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#define | OPTROM_SIZE_25XX 0x200000 |
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#define | OPTROM_SIZE_81XX 0x400000 |
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#define | OPTROM_SIZE_82XX 0x800000 |
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#define | OPTROM_SIZE_83XX 0x1000000 |
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#define | OPTROM_BURST_SIZE 0x1000 |
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#define | OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) |
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#define | QLA_DSDS_PER_IOCB 37 |
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#define | CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) |
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#define | QLA_SG_ALL 1024 |
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