Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
r8180_rtl8225z2.c
Go to the documentation of this file.
1 /*
2  * This is part of the rtl8180-sa2400 driver
3  * released under the GPL (See file COPYING for details).
4  * Copyright (c) 2005 Andrea Merello <[email protected]>
5  *
6  * This files contains programming code for the rtl8225
7  * radio frontend.
8  *
9  * *Many* thanks to Realtek Corp. for their great support!
10  */
11 
12 #include "r8180_hw.h"
13 #include "r8180_rtl8225.h"
14 #include "r8180_93cx6.h"
15 
16 #include "ieee80211/dot11d.h"
17 
18 
19 static void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
20 {
21  int i;
22  u16 out, select;
23  u8 bit;
24  u32 bangdata = (data << 4) | (adr & 0xf);
25 
26  out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
27 
28  write_nic_word(dev, RFPinsEnable,
29  (read_nic_word(dev, RFPinsEnable) | 0x7));
30 
31  select = read_nic_word(dev, RFPinsSelect);
32 
33  write_nic_word(dev, RFPinsSelect, select | 0x7 |
34  SW_CONTROL_GPIO);
35 
36  force_pci_posting(dev);
37  udelay(10);
38 
39  write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
40 
41  force_pci_posting(dev);
42  udelay(2);
43 
44  write_nic_word(dev, RFPinsOutput, out);
45 
46  force_pci_posting(dev);
47  udelay(10);
48 
49  for (i = 15; i >= 0; i--) {
50  bit = (bangdata & (1 << i)) >> i;
51 
52  write_nic_word(dev, RFPinsOutput, bit | out);
53 
54  write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
55  write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
56 
57  i--;
58  bit = (bangdata & (1 << i)) >> i;
59 
60  write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
61  write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
62 
63  write_nic_word(dev, RFPinsOutput, bit | out);
64 
65  }
66 
67  write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
68 
69  force_pci_posting(dev);
70  udelay(10);
71 
72  write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
73 
74  write_nic_word(dev, RFPinsSelect, select | SW_CONTROL_GPIO);
75 
76  rtl8185_rf_pins_enable(dev);
77 }
78 
79 static const u16 rtl8225bcd_rxgain[] = {
80  0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
81  0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
82  0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
83  0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
84  0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
85  0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
86  0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
87  0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
88  0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
89  0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
90  0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
91  0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
92 
93 };
94 
95 static const u8 rtl8225_agc[] = {
96  0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e,
97  0x9d, 0x9c, 0x9b, 0x9a, 0x99, 0x98, 0x97, 0x96,
98  0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 0x8f, 0x8e,
99  0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86,
100  0x85, 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e,
101  0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36,
102  0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 0x2e,
103  0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26,
104  0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e,
105  0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16,
106  0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
107  0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06,
108  0x05, 0x04, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01,
109  0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
110  0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
111  0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
112 };
113 
114 static const u8 rtl8225_gain[] = {
115  0x23, 0x88, 0x7c, 0xa5, /* -82dBm */
116  0x23, 0x88, 0x7c, 0xb5, /* -82dBm */
117  0x23, 0x88, 0x7c, 0xc5, /* -82dBm */
118  0x33, 0x80, 0x79, 0xc5, /* -78dBm */
119  0x43, 0x78, 0x76, 0xc5, /* -74dBm */
120  0x53, 0x60, 0x73, 0xc5, /* -70dBm */
121  0x63, 0x58, 0x70, 0xc5, /* -66dBm */
122 };
123 
124 static const u8 rtl8225_tx_gain_cck_ofdm[] = {
125  0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
126 };
127 
128 static const u8 rtl8225_tx_power_cck[] = {
129  0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
130  0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
131  0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
132  0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
133  0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
134  0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
135 };
136 
137 static const u8 rtl8225_tx_power_cck_ch14[] = {
138  0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
139  0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
140  0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
141  0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
142  0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
143  0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
144 };
145 
146 static const u8 rtl8225_tx_power_ofdm[] = {
147  0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
148 };
149 
150 static const u32 rtl8225_chan[] = {
151  0,
152  0x0080, 0x0100, 0x0180, 0x0200, 0x0280, 0x0300, 0x0380,
153  0x0400, 0x0480, 0x0500, 0x0580, 0x0600, 0x0680, 0x074A,
154 };
155 
156 static void rtl8225_SetTXPowerLevel(struct net_device *dev, short ch)
157 {
158  struct r8180_priv *priv = ieee80211_priv(dev);
159  int GainIdx;
160  int GainSetting;
161  int i;
162  u8 power;
163  const u8 *cck_power_table;
164  u8 max_cck_power_level;
165  u8 max_ofdm_power_level;
166  u8 min_ofdm_power_level;
167  u8 cck_power_level = 0xff & priv->chtxpwr[ch];
168  u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch];
169 
170  max_cck_power_level = 35;
171  max_ofdm_power_level = 35;
172  min_ofdm_power_level = 0;
173 
174  if (cck_power_level > max_cck_power_level)
175  cck_power_level = max_cck_power_level;
176 
177  GainIdx = cck_power_level % 6;
178  GainSetting = cck_power_level / 6;
179 
180  if (ch == 14)
181  cck_power_table = rtl8225_tx_power_cck_ch14;
182  else
183  cck_power_table = rtl8225_tx_power_cck;
184 
185  write_nic_byte(dev, TX_GAIN_CCK,
186  rtl8225_tx_gain_cck_ofdm[GainSetting] >> 1);
187 
188  for (i = 0; i < 8; i++) {
189  power = cck_power_table[GainIdx * 8 + i];
190  write_phy_cck(dev, 0x44 + i, power);
191  }
192 
193  /* FIXME Is this delay really needed ? */
194  force_pci_posting(dev);
195  mdelay(1);
196 
197  if (ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level))
198  ofdm_power_level = max_ofdm_power_level;
199  else
200  ofdm_power_level += min_ofdm_power_level;
201 
202  if (ofdm_power_level > 35)
203  ofdm_power_level = 35;
204 
205  GainIdx = ofdm_power_level % 6;
206  GainSetting = ofdm_power_level / 6;
207 
208  rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
209 
210  write_phy_ofdm(dev, 2, 0x42);
211  write_phy_ofdm(dev, 6, 0x00);
212  write_phy_ofdm(dev, 8, 0x00);
213 
214  write_nic_byte(dev, TX_GAIN_OFDM,
215  rtl8225_tx_gain_cck_ofdm[GainSetting] >> 1);
216 
217  power = rtl8225_tx_power_ofdm[GainIdx];
218 
219  write_phy_ofdm(dev, 5, power);
220  write_phy_ofdm(dev, 7, power);
221 
222  force_pci_posting(dev);
223  mdelay(1);
224 }
225 
226 static const u8 rtl8225z2_threshold[] = {
227  0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
228 };
229 
230 static const u8 rtl8225z2_gain_bg[] = {
231  0x23, 0x15, 0xa5, /* -82-1dBm */
232  0x23, 0x15, 0xb5, /* -82-2dBm */
233  0x23, 0x15, 0xc5, /* -82-3dBm */
234  0x33, 0x15, 0xc5, /* -78dBm */
235  0x43, 0x15, 0xc5, /* -74dBm */
236  0x53, 0x15, 0xc5, /* -70dBm */
237  0x63, 0x15, 0xc5, /* -66dBm */
238 };
239 
240 static const u8 rtl8225z2_gain_a[] = {
241  0x13, 0x27, 0x5a, /* -82dBm */
242  0x23, 0x23, 0x58, /* -82dBm */
243  0x33, 0x1f, 0x56, /* -82dBm */
244  0x43, 0x1b, 0x54, /* -78dBm */
245  0x53, 0x17, 0x51, /* -74dBm */
246  0x63, 0x24, 0x4f, /* -70dBm */
247  0x73, 0x0f, 0x4c, /* -66dBm */
248 };
249 
250 static const u16 rtl8225z2_rxgain[] = {
251  0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
252  0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
253  0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
254  0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
255  0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
256  0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
257  0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
258  0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
259  0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
260  0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
261  0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
262  0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
263 
264 };
265 
266 static const u8 ZEBRA2_CCK_OFDM_GAIN_SETTING[] = {
267  0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
268  0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
269  0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
270  0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
271  0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
272  0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
273 };
274 
275 static const u8 rtl8225z2_tx_power_ofdm[] = {
276  0x42, 0x00, 0x40, 0x00, 0x40
277 };
278 
279 static const u8 rtl8225z2_tx_power_cck_ch14[] = {
280  0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
281 };
282 
283 static const u8 rtl8225z2_tx_power_cck[] = {
284  0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
285 };
286 
287 void rtl8225z2_set_gain(struct net_device *dev, short gain)
288 {
289  const u8 *rtl8225_gain;
290  struct r8180_priv *priv = ieee80211_priv(dev);
291  u8 mode = priv->ieee80211->mode;
292 
293  if (mode == IEEE_B || mode == IEEE_G)
294  rtl8225_gain = rtl8225z2_gain_bg;
295  else
296  rtl8225_gain = rtl8225z2_gain_a;
297 
298  write_phy_ofdm(dev, 0x0b, rtl8225_gain[gain * 3]);
299  write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 3 + 1]);
300  write_phy_ofdm(dev, 0x1d, rtl8225_gain[gain * 3 + 2]);
301  write_phy_ofdm(dev, 0x21, 0x37);
302 }
303 
304 static u32 read_rtl8225(struct net_device *dev, u8 adr)
305 {
306  u32 data2Write = ((u32)(adr & 0x1f)) << 27;
307  u32 dataRead;
308  u32 mask;
309  u16 oval, oval2, oval3, tmp;
310  int i;
311  short bit, rw;
312  u8 wLength = 6;
313  u8 rLength = 12;
314  u8 low2high = 0;
315 
316  oval = read_nic_word(dev, RFPinsOutput);
317  oval2 = read_nic_word(dev, RFPinsEnable);
318  oval3 = read_nic_word(dev, RFPinsSelect);
319 
320  write_nic_word(dev, RFPinsEnable, (oval2|0xf));
321  write_nic_word(dev, RFPinsSelect, (oval3|0xf));
322 
323  dataRead = 0;
324 
325  oval &= ~0xf;
326 
327  write_nic_word(dev, RFPinsOutput, oval | BB_HOST_BANG_EN);
328  udelay(4);
329 
330  write_nic_word(dev, RFPinsOutput, oval);
331  udelay(5);
332 
333  rw = 0;
334 
335  mask = (low2high) ? 0x01 : (((u32)0x01)<<(32-1));
336 
337  for (i = 0; i < wLength/2; i++) {
338  bit = ((data2Write&mask) != 0) ? 1 : 0;
339  write_nic_word(dev, RFPinsOutput, bit | oval | rw);
340  udelay(1);
341 
342  write_nic_word(dev, RFPinsOutput,
343  bit | oval | BB_HOST_BANG_CLK | rw);
344  udelay(2);
345  write_nic_word(dev, RFPinsOutput,
346  bit | oval | BB_HOST_BANG_CLK | rw);
347  udelay(2);
348 
349  mask = (low2high) ? (mask<<1) : (mask>>1);
350 
351  if (i == 2) {
352  rw = BB_HOST_BANG_RW;
353  write_nic_word(dev, RFPinsOutput,
354  bit | oval | BB_HOST_BANG_CLK | rw);
355  udelay(2);
356  write_nic_word(dev, RFPinsOutput, bit | oval | rw);
357  udelay(2);
358  break;
359  }
360 
361  bit = ((data2Write&mask) != 0) ? 1 : 0;
362 
363  write_nic_word(dev, RFPinsOutput,
364  oval | bit | rw | BB_HOST_BANG_CLK);
365  udelay(2);
366  write_nic_word(dev, RFPinsOutput,
367  oval | bit | rw | BB_HOST_BANG_CLK);
368  udelay(2);
369 
370  write_nic_word(dev, RFPinsOutput, oval | bit | rw);
371  udelay(1);
372 
373  mask = (low2high) ? (mask<<1) : (mask>>1);
374  }
375 
376  write_nic_word(dev, RFPinsOutput, rw|oval);
377  udelay(2);
378  mask = (low2high) ? 0x01 : (((u32)0x01) << (12-1));
379 
380  /*
381  * We must set data pin to HW controlled, otherwise RF can't driver it
382  * and value RF register won't be able to read back properly.
383  */
384  write_nic_word(dev, RFPinsEnable, (oval2 & (~0x01)));
385 
386  for (i = 0; i < rLength; i++) {
387  write_nic_word(dev, RFPinsOutput, rw|oval); udelay(1);
388 
389  write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK);
390  udelay(2);
391  write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK);
392  udelay(2);
393  write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK);
394  udelay(2);
395  tmp = read_nic_word(dev, RFPinsInput);
396 
397  dataRead |= (tmp & BB_HOST_BANG_CLK ? mask : 0);
398 
399  write_nic_word(dev, RFPinsOutput, (rw|oval)); udelay(2);
400 
401  mask = (low2high) ? (mask<<1) : (mask>>1);
402  }
403 
404  write_nic_word(dev, RFPinsOutput,
405  BB_HOST_BANG_EN | BB_HOST_BANG_RW | oval);
406  udelay(2);
407 
408  write_nic_word(dev, RFPinsEnable, oval2);
409  write_nic_word(dev, RFPinsSelect, oval3); /* Set To SW Switch */
410  write_nic_word(dev, RFPinsOutput, 0x3a0);
411 
412  return dataRead;
413 }
414 
415 short rtl8225_is_V_z2(struct net_device *dev)
416 {
417  short vz2 = 1;
418 
419  if (read_rtl8225(dev, 8) != 0x588)
420  vz2 = 0;
421  else /* reg 9 pg 1 = 24 */
422  if (read_rtl8225(dev, 9) != 0x700)
423  vz2 = 0;
424 
425  /* sw back to pg 0 */
426  write_rtl8225(dev, 0, 0xb7);
427 
428  return vz2;
429 }
430 
431 void rtl8225z2_rf_close(struct net_device *dev)
432 {
433  RF_WriteReg(dev, 0x4, 0x1f);
434 
435  force_pci_posting(dev);
436  mdelay(1);
437 
438  rtl8180_set_anaparam(dev, RTL8225z2_ANAPARAM_OFF);
439  rtl8185_set_anaparam2(dev, RTL8225z2_ANAPARAM2_OFF);
440 }
441 
442 /*
443  * Map dBm into Tx power index according to current HW model, for example,
444  * RF and PA, and current wireless mode.
445  */
446 s8 DbmToTxPwrIdx(struct r8180_priv *priv, WIRELESS_MODE WirelessMode,
447  s32 PowerInDbm)
448 {
449  bool bUseDefault = true;
450  s8 TxPwrIdx = 0;
451 
452  /*
453  * OFDM Power in dBm = Index * 0.5 + 0
454  * CCK Power in dBm = Index * 0.25 + 13
455  */
456  s32 tmp = 0;
457 
458  if (WirelessMode == WIRELESS_MODE_G) {
459  bUseDefault = false;
460  tmp = (2 * PowerInDbm);
461 
462  if (tmp < 0)
463  TxPwrIdx = 0;
464  else if (tmp > 40) /* 40 means 20 dBm. */
465  TxPwrIdx = 40;
466  else
467  TxPwrIdx = (s8)tmp;
468  } else if (WirelessMode == WIRELESS_MODE_B) {
469  bUseDefault = false;
470  tmp = (4 * PowerInDbm) - 52;
471 
472  if (tmp < 0)
473  TxPwrIdx = 0;
474  else if (tmp > 28) /* 28 means 20 dBm. */
475  TxPwrIdx = 28;
476  else
477  TxPwrIdx = (s8)tmp;
478  }
479 
480  /*
481  * TRUE if we want to use a default implementation.
482  * We shall set it to FALSE when we have exact translation formula
483  * for target IC. 070622, by rcnjko.
484  */
485  if (bUseDefault) {
486  if (PowerInDbm < 0)
487  TxPwrIdx = 0;
488  else if (PowerInDbm > 35)
489  TxPwrIdx = 35;
490  else
491  TxPwrIdx = (u8)PowerInDbm;
492  }
493 
494  return TxPwrIdx;
495 }
496 
497 void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
498 {
499  struct r8180_priv *priv = ieee80211_priv(dev);
500  u8 max_cck_power_level;
501  u8 max_ofdm_power_level;
502  u8 min_ofdm_power_level;
503  char cck_power_level = (char)(0xff & priv->chtxpwr[ch]);
504  char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]);
505 
506  if (IS_DOT11D_ENABLE(priv->ieee80211) &&
507  IS_DOT11D_STATE_DONE(priv->ieee80211)) {
508  u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch);
509  u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B,
510  MaxTxPwrInDbm);
511  u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G,
512  MaxTxPwrInDbm);
513 
514  if (cck_power_level > CckMaxPwrIdx)
515  cck_power_level = CckMaxPwrIdx;
516  if (ofdm_power_level > OfdmMaxPwrIdx)
517  ofdm_power_level = OfdmMaxPwrIdx;
518  }
519 
520  max_cck_power_level = 15;
521  max_ofdm_power_level = 25;
522  min_ofdm_power_level = 10;
523 
524  if (cck_power_level > 35)
525  cck_power_level = 35;
526 
527  write_nic_byte(dev, CCK_TXAGC,
528  (ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]));
529  force_pci_posting(dev);
530  mdelay(1);
531 
532  if (ofdm_power_level > 35)
533  ofdm_power_level = 35;
534 
535  if (priv->up == 0) {
536  write_phy_ofdm(dev, 2, 0x42);
537  write_phy_ofdm(dev, 5, 0x00);
538  write_phy_ofdm(dev, 6, 0x40);
539  write_phy_ofdm(dev, 7, 0x00);
540  write_phy_ofdm(dev, 8, 0x40);
541  }
542 
543  write_nic_byte(dev, OFDM_TXAGC,
544  ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]);
545 
546  if (ofdm_power_level <= 11) {
547  write_phy_ofdm(dev, 0x07, 0x5c);
548  write_phy_ofdm(dev, 0x09, 0x5c);
549  }
550 
551  if (ofdm_power_level <= 17) {
552  write_phy_ofdm(dev, 0x07, 0x54);
553  write_phy_ofdm(dev, 0x09, 0x54);
554  } else {
555  write_phy_ofdm(dev, 0x07, 0x50);
556  write_phy_ofdm(dev, 0x09, 0x50);
557  }
558 
559  force_pci_posting(dev);
560  mdelay(1);
561 }
562 
563 void rtl8225z2_rf_set_chan(struct net_device *dev, short ch)
564 {
565  rtl8225z2_SetTXPowerLevel(dev, ch);
566 
567  RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
568 
569  if ((RF_ReadReg(dev, 0x7) & 0x0F80) != rtl8225_chan[ch])
570  RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
571 
572  mdelay(1);
573 
574  force_pci_posting(dev);
575  mdelay(10);
576 }
577 
578 static void rtl8225_host_pci_init(struct net_device *dev)
579 {
580  write_nic_word(dev, RFPinsOutput, 0x480);
581 
582  rtl8185_rf_pins_enable(dev);
583 
584  write_nic_word(dev, RFPinsSelect, 0x88 | SW_CONTROL_GPIO);
585 
586  write_nic_byte(dev, GP_ENABLE, 0);
587 
588  force_pci_posting(dev);
589  mdelay(200);
590 
591  /* bit 6 is for RF on/off detection */
592  write_nic_word(dev, GP_ENABLE, 0xff & (~(1 << 6)));
593 }
594 
595 static void rtl8225_rf_set_chan(struct net_device *dev, short ch)
596 {
597  struct r8180_priv *priv = ieee80211_priv(dev);
598  short gset = (priv->ieee80211->state == IEEE80211_LINKED &&
599  ieee80211_is_54g(&priv->ieee80211->current_network)) ||
600  priv->ieee80211->iw_mode == IW_MODE_MONITOR;
601 
602  rtl8225_SetTXPowerLevel(dev, ch);
603 
604  write_rtl8225(dev, 0x7, rtl8225_chan[ch]);
605 
606  force_pci_posting(dev);
607  mdelay(10);
608 
609  if (gset) {
610  write_nic_byte(dev, SIFS, 0x22);
611  write_nic_byte(dev, DIFS, 0x14);
612  } else {
613  write_nic_byte(dev, SIFS, 0x44);
614  write_nic_byte(dev, DIFS, 0x24);
615  }
616 
617  if (priv->ieee80211->state == IEEE80211_LINKED &&
618  ieee80211_is_shortslot(&priv->ieee80211->current_network))
619  write_nic_byte(dev, SLOT, 0x9);
620  else
621  write_nic_byte(dev, SLOT, 0x14);
622 
623  if (gset) {
624  write_nic_byte(dev, EIFS, 81);
625  write_nic_byte(dev, CW_VAL, 0x73);
626  } else {
627  write_nic_byte(dev, EIFS, 81);
628  write_nic_byte(dev, CW_VAL, 0xa5);
629  }
630 }
631 
632 void rtl8225z2_rf_init(struct net_device *dev)
633 {
634  struct r8180_priv *priv = ieee80211_priv(dev);
635  int i;
636  short channel = 1;
637  u16 brsr;
638  u32 data, addr;
639 
640  priv->chan = channel;
641 
642  rtl8225_host_pci_init(dev);
643 
644  write_nic_dword(dev, RF_TIMING, 0x000a8008);
645 
646  brsr = read_nic_word(dev, BRSR);
647 
648  write_nic_word(dev, BRSR, 0xffff);
649 
650  write_nic_dword(dev, RF_PARA, 0x100044);
651 
652  rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
653  write_nic_byte(dev, CONFIG3, 0x44);
654  rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
655 
656  rtl8185_rf_pins_enable(dev);
657 
658  write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
659  write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
660  write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
661  write_rtl8225(dev, 0x3, 0x441); mdelay(1);
662  write_rtl8225(dev, 0x4, 0x8c3); mdelay(1);
663  write_rtl8225(dev, 0x5, 0xc72); mdelay(1);
664  write_rtl8225(dev, 0x6, 0xe6); mdelay(1);
665  write_rtl8225(dev, 0x7, rtl8225_chan[channel]); mdelay(1);
666  write_rtl8225(dev, 0x8, 0x3f); mdelay(1);
667  write_rtl8225(dev, 0x9, 0x335); mdelay(1);
668  write_rtl8225(dev, 0xa, 0x9d4); mdelay(1);
669  write_rtl8225(dev, 0xb, 0x7bb); mdelay(1);
670  write_rtl8225(dev, 0xc, 0x850); mdelay(1);
671  write_rtl8225(dev, 0xd, 0xcdf); mdelay(1);
672  write_rtl8225(dev, 0xe, 0x2b); mdelay(1);
673  write_rtl8225(dev, 0xf, 0x114);
674 
675  mdelay(100);
676 
677  write_rtl8225(dev, 0x0, 0x1b7);
678 
679  for (i = 0; i < 95; i++) {
680  write_rtl8225(dev, 0x1, (u8)(i + 1));
681  write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
682  }
683 
684  write_rtl8225(dev, 0x3, 0x80);
685  write_rtl8225(dev, 0x5, 0x4);
686 
687  write_rtl8225(dev, 0x0, 0xb7);
688 
689  write_rtl8225(dev, 0x2, 0xc4d);
690 
691  /* FIXME!! rtl8187 we have to check if calibrarion
692  * is successful and eventually cal. again (repeat
693  * the two write on reg 2)
694  */
695  data = read_rtl8225(dev, 6);
696  if (!(data & 0x00000080)) {
697  write_rtl8225(dev, 0x02, 0x0c4d);
698  force_pci_posting(dev); mdelay(200);
699  write_rtl8225(dev, 0x02, 0x044d);
700  force_pci_posting(dev); mdelay(100);
701  data = read_rtl8225(dev, 6);
702  if (!(data & 0x00000080))
703  DMESGW("RF Calibration Failed!!!!\n");
704  }
705 
706  mdelay(200);
707 
708  write_rtl8225(dev, 0x0, 0x2bf);
709 
710  for (i = 0; i < 128; i++) {
711  data = rtl8225_agc[i];
712 
713  addr = i + 0x80; /* enable writing AGC table */
714  write_phy_ofdm(dev, 0xb, data);
715  mdelay(1);
716 
717  write_phy_ofdm(dev, 0xa, addr);
718  mdelay(1);
719  }
720 
721  force_pci_posting(dev);
722  mdelay(1);
723 
724  write_phy_ofdm(dev, 0x00, 0x01); mdelay(1);
725  write_phy_ofdm(dev, 0x01, 0x02); mdelay(1);
726  write_phy_ofdm(dev, 0x02, 0x62); mdelay(1);
727  write_phy_ofdm(dev, 0x03, 0x00); mdelay(1);
728  write_phy_ofdm(dev, 0x04, 0x00); mdelay(1);
729  write_phy_ofdm(dev, 0x05, 0x00); mdelay(1);
730  write_phy_ofdm(dev, 0x06, 0x40); mdelay(1);
731  write_phy_ofdm(dev, 0x07, 0x00); mdelay(1);
732  write_phy_ofdm(dev, 0x08, 0x40); mdelay(1);
733  write_phy_ofdm(dev, 0x09, 0xfe); mdelay(1);
734  write_phy_ofdm(dev, 0x0a, 0x08); mdelay(1);
735  write_phy_ofdm(dev, 0x0b, 0x80); mdelay(1);
736  write_phy_ofdm(dev, 0x0c, 0x01); mdelay(1);
737  write_phy_ofdm(dev, 0x0d, 0x43);
738  write_phy_ofdm(dev, 0x0e, 0xd3); mdelay(1);
739  write_phy_ofdm(dev, 0x0f, 0x38); mdelay(1);
740  write_phy_ofdm(dev, 0x10, 0x84); mdelay(1);
741  write_phy_ofdm(dev, 0x11, 0x07); mdelay(1);
742  write_phy_ofdm(dev, 0x12, 0x20); mdelay(1);
743  write_phy_ofdm(dev, 0x13, 0x20); mdelay(1);
744  write_phy_ofdm(dev, 0x14, 0x00); mdelay(1);
745  write_phy_ofdm(dev, 0x15, 0x40); mdelay(1);
746  write_phy_ofdm(dev, 0x16, 0x00); mdelay(1);
747  write_phy_ofdm(dev, 0x17, 0x40); mdelay(1);
748  write_phy_ofdm(dev, 0x18, 0xef); mdelay(1);
749  write_phy_ofdm(dev, 0x19, 0x19); mdelay(1);
750  write_phy_ofdm(dev, 0x1a, 0x20); mdelay(1);
751  write_phy_ofdm(dev, 0x1b, 0x15); mdelay(1);
752  write_phy_ofdm(dev, 0x1c, 0x04); mdelay(1);
753  write_phy_ofdm(dev, 0x1d, 0xc5); mdelay(1);
754  write_phy_ofdm(dev, 0x1e, 0x95); mdelay(1);
755  write_phy_ofdm(dev, 0x1f, 0x75); mdelay(1);
756  write_phy_ofdm(dev, 0x20, 0x1f); mdelay(1);
757  write_phy_ofdm(dev, 0x21, 0x17); mdelay(1);
758  write_phy_ofdm(dev, 0x22, 0x16); mdelay(1);
759  write_phy_ofdm(dev, 0x23, 0x80); mdelay(1); /* FIXME maybe not needed */
760  write_phy_ofdm(dev, 0x24, 0x46); mdelay(1);
761  write_phy_ofdm(dev, 0x25, 0x00); mdelay(1);
762  write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);
763  write_phy_ofdm(dev, 0x27, 0x88); mdelay(1);
764 
765  rtl8225z2_set_gain(dev, 4);
766 
767  write_phy_cck(dev, 0x0, 0x98); mdelay(1);
768  write_phy_cck(dev, 0x3, 0x20); mdelay(1);
769  write_phy_cck(dev, 0x4, 0x7e); mdelay(1);
770  write_phy_cck(dev, 0x5, 0x12); mdelay(1);
771  write_phy_cck(dev, 0x6, 0xfc); mdelay(1);
772  write_phy_cck(dev, 0x7, 0x78); mdelay(1);
773  write_phy_cck(dev, 0x8, 0x2e); mdelay(1);
774  write_phy_cck(dev, 0x10, 0x93); mdelay(1);
775  write_phy_cck(dev, 0x11, 0x88); mdelay(1);
776  write_phy_cck(dev, 0x12, 0x47); mdelay(1);
777  write_phy_cck(dev, 0x13, 0xd0);
778  write_phy_cck(dev, 0x19, 0x00);
779  write_phy_cck(dev, 0x1a, 0xa0);
780  write_phy_cck(dev, 0x1b, 0x08);
781  write_phy_cck(dev, 0x40, 0x86); /* CCK Carrier Sense Threshold */
782  write_phy_cck(dev, 0x41, 0x8d); mdelay(1);
783  write_phy_cck(dev, 0x42, 0x15); mdelay(1);
784  write_phy_cck(dev, 0x43, 0x18); mdelay(1);
785  write_phy_cck(dev, 0x44, 0x36); mdelay(1);
786  write_phy_cck(dev, 0x45, 0x35); mdelay(1);
787  write_phy_cck(dev, 0x46, 0x2e); mdelay(1);
788  write_phy_cck(dev, 0x47, 0x25); mdelay(1);
789  write_phy_cck(dev, 0x48, 0x1c); mdelay(1);
790  write_phy_cck(dev, 0x49, 0x12); mdelay(1);
791  write_phy_cck(dev, 0x4a, 0x09); mdelay(1);
792  write_phy_cck(dev, 0x4b, 0x04); mdelay(1);
793  write_phy_cck(dev, 0x4c, 0x05); mdelay(1);
794 
795  write_nic_byte(dev, 0x5b, 0x0d); mdelay(1);
796 
797  rtl8225z2_SetTXPowerLevel(dev, channel);
798 
799  /* RX antenna default to A */
800  write_phy_cck(dev, 0x11, 0x9b); mdelay(1); /* B: 0xDB */
801  write_phy_ofdm(dev, 0x26, 0x90); mdelay(1); /* B: 0x10 */
802 
803  rtl8185_tx_antenna(dev, 0x03); /* B: 0x00 */
804 
805  /* switch to high-speed 3-wire
806  * last digit. 2 for both cck and ofdm
807  */
808  write_nic_dword(dev, 0x94, 0x15c00002);
809  rtl8185_rf_pins_enable(dev);
810 
811  rtl8225_rf_set_chan(dev, priv->chan);
812 }
813 
814 void rtl8225z2_rf_set_mode(struct net_device *dev)
815 {
816  struct r8180_priv *priv = ieee80211_priv(dev);
817 
818  if (priv->ieee80211->mode == IEEE_A) {
819  write_rtl8225(dev, 0x5, 0x1865);
820  write_nic_dword(dev, RF_PARA, 0x10084);
821  write_nic_dword(dev, RF_TIMING, 0xa8008);
822  write_phy_ofdm(dev, 0x0, 0x0);
823  write_phy_ofdm(dev, 0xa, 0x6);
824  write_phy_ofdm(dev, 0xb, 0x99);
825  write_phy_ofdm(dev, 0xf, 0x20);
826  write_phy_ofdm(dev, 0x11, 0x7);
827 
828  rtl8225z2_set_gain(dev, 4);
829 
830  write_phy_ofdm(dev, 0x15, 0x40);
831  write_phy_ofdm(dev, 0x17, 0x40);
832 
833  write_nic_dword(dev, 0x94, 0x10000000);
834  } else {
835  write_rtl8225(dev, 0x5, 0x1864);
836  write_nic_dword(dev, RF_PARA, 0x10044);
837  write_nic_dword(dev, RF_TIMING, 0xa8008);
838  write_phy_ofdm(dev, 0x0, 0x1);
839  write_phy_ofdm(dev, 0xa, 0x6);
840  write_phy_ofdm(dev, 0xb, 0x99);
841  write_phy_ofdm(dev, 0xf, 0x20);
842  write_phy_ofdm(dev, 0x11, 0x7);
843 
844  rtl8225z2_set_gain(dev, 4);
845 
846  write_phy_ofdm(dev, 0x15, 0x40);
847  write_phy_ofdm(dev, 0x17, 0x40);
848 
849  write_nic_dword(dev, 0x94, 0x04000002);
850  }
851 }
852 
853 #define MAX_DOZE_WAITING_TIMES_85B 20
854 #define MAX_POLLING_24F_TIMES_87SE 10
855 #define LPS_MAX_SLEEP_WAITING_TIMES_87SE 5
856 
857 bool SetZebraRFPowerState8185(struct net_device *dev,
858  RT_RF_POWER_STATE eRFPowerState)
859 {
860  struct r8180_priv *priv = ieee80211_priv(dev);
861  u8 btCR9346, btConfig3;
862  bool bActionAllowed = true, bTurnOffBB = true;
863  u8 u1bTmp;
864  int i;
865  bool bResult = true;
866  u8 QueueID;
867 
868  if (priv->SetRFPowerStateInProgress == true)
869  return false;
870 
871  priv->SetRFPowerStateInProgress = true;
872 
873  btCR9346 = read_nic_byte(dev, CR9346);
874  write_nic_byte(dev, CR9346, (btCR9346 | 0xC0));
875 
876  btConfig3 = read_nic_byte(dev, CONFIG3);
877  write_nic_byte(dev, CONFIG3, (btConfig3 | CONFIG3_PARM_En));
878 
879  switch (eRFPowerState) {
880  case eRfOn:
881  write_nic_word(dev, 0x37C, 0x00EC);
882 
883  /* turn on AFE */
884  write_nic_byte(dev, 0x54, 0x00);
885  write_nic_byte(dev, 0x62, 0x00);
886 
887  /* turn on RF */
888  RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
889  RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
890 
891  /* turn on RF again */
892  RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
893  RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
894 
895  /* turn on BB */
896  write_phy_ofdm(dev, 0x10, 0x40);
897  write_phy_ofdm(dev, 0x12, 0x40);
898 
899  /* Avoid power down at init time. */
900  write_nic_byte(dev, CONFIG4, priv->RFProgType);
901 
902  u1bTmp = read_nic_byte(dev, 0x24E);
903  write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6))));
904  break;
905  case eRfSleep:
906  for (QueueID = 0, i = 0; QueueID < 6;) {
907  if (get_curr_tx_free_desc(dev, QueueID) ==
908  priv->txringcount) {
909  QueueID++;
910  continue;
911  } else {
912  priv->TxPollingTimes++;
913  if (priv->TxPollingTimes >=
914  LPS_MAX_SLEEP_WAITING_TIMES_87SE) {
915  bActionAllowed = false;
916  break;
917  } else
918  udelay(10);
919  }
920  }
921 
922  if (bActionAllowed) {
923  /* turn off BB RXIQ matrix to cut off rx signal */
924  write_phy_ofdm(dev, 0x10, 0x00);
925  write_phy_ofdm(dev, 0x12, 0x00);
926 
927  /* turn off RF */
928  RF_WriteReg(dev, 0x4, 0x0000);
929  RF_WriteReg(dev, 0x0, 0x0000);
930 
931  /* turn off AFE except PLL */
932  write_nic_byte(dev, 0x62, 0xff);
933  write_nic_byte(dev, 0x54, 0xec);
934 
935  mdelay(1);
936 
937  {
938  int i = 0;
939  while (true) {
940  u8 tmp24F = read_nic_byte(dev, 0x24f);
941 
942  if ((tmp24F == 0x01) ||
943  (tmp24F == 0x09)) {
944  bTurnOffBB = true;
945  break;
946  } else {
947  udelay(10);
948  i++;
949  priv->TxPollingTimes++;
950 
951  if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) {
952  bTurnOffBB = false;
953  break;
954  } else
955  udelay(10);
956  }
957  }
958  }
959 
960  if (bTurnOffBB) {
961  /* turn off BB */
962  u1bTmp = read_nic_byte(dev, 0x24E);
963  write_nic_byte(dev, 0x24E,
964  (u1bTmp | BIT5 | BIT6));
965 
966  /* turn off AFE PLL */
967  write_nic_byte(dev, 0x54, 0xFC);
968  write_nic_word(dev, 0x37C, 0x00FC);
969  }
970  }
971  break;
972  case eRfOff:
973  for (QueueID = 0, i = 0; QueueID < 6;) {
974  if (get_curr_tx_free_desc(dev, QueueID) ==
975  priv->txringcount) {
976  QueueID++;
977  continue;
978  } else {
979  udelay(10);
980  i++;
981  }
982 
983  if (i >= MAX_DOZE_WAITING_TIMES_85B)
984  break;
985  }
986 
987  /* turn off BB RXIQ matrix to cut off rx signal */
988  write_phy_ofdm(dev, 0x10, 0x00);
989  write_phy_ofdm(dev, 0x12, 0x00);
990 
991  /* turn off RF */
992  RF_WriteReg(dev, 0x4, 0x0000);
993  RF_WriteReg(dev, 0x0, 0x0000);
994 
995  /* turn off AFE except PLL */
996  write_nic_byte(dev, 0x62, 0xff);
997  write_nic_byte(dev, 0x54, 0xec);
998 
999  mdelay(1);
1000 
1001  {
1002  int i = 0;
1003 
1004  while (true) {
1005  u8 tmp24F = read_nic_byte(dev, 0x24f);
1006 
1007  if ((tmp24F == 0x01) || (tmp24F == 0x09)) {
1008  bTurnOffBB = true;
1009  break;
1010  } else {
1011  bTurnOffBB = false;
1012  udelay(10);
1013  i++;
1014  }
1015 
1016  if (i > MAX_POLLING_24F_TIMES_87SE)
1017  break;
1018  }
1019  }
1020 
1021  if (bTurnOffBB) {
1022  /* turn off BB */
1023  u1bTmp = read_nic_byte(dev, 0x24E);
1024  write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6));
1025 
1026  /* turn off AFE PLL (80M) */
1027  write_nic_byte(dev, 0x54, 0xFC);
1028  write_nic_word(dev, 0x37C, 0x00FC);
1029  }
1030  break;
1031  }
1032 
1033  btConfig3 &= ~(CONFIG3_PARM_En);
1034  write_nic_byte(dev, CONFIG3, btConfig3);
1035 
1036  btCR9346 &= ~(0xC0);
1037  write_nic_byte(dev, CR9346, btCR9346);
1038 
1039  if (bResult && bActionAllowed)
1040  priv->eRFPowerState = eRFPowerState;
1041 
1042  priv->SetRFPowerStateInProgress = false;
1043 
1044  return bResult && bActionAllowed;
1045 }
1046 
1047 void rtl8225z4_rf_sleep(struct net_device *dev)
1048 {
1049  MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
1050 }
1051 
1052 void rtl8225z4_rf_wakeup(struct net_device *dev)
1053 {
1054  MgntActSet_RF_State(dev, eRfOn, RF_CHANGE_BY_PS);
1055 }
Generated on Thu Jan 10 2013 14:30:38 for Linux Kernel by   doxygen 1.8.2