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rtl8192u
r8192U.h
Go to the documentation of this file.
1
/*
2
This is part of rtl8187 OpenSource driver.
3
Copyright (C) Andrea Merello 2004-2005 <
[email protected]
>
4
Released under the terms of GPL (General Public Licence)
5
6
Parts of this driver are based on the GPL part of the
7
official realtek driver
8
9
Parts of this driver are based on the rtl8192 driver skeleton
10
from Patric Schenke & Andres Salomon
11
12
Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
13
14
We want to thank the Authors of those projects and the Ndiswrapper
15
project Authors.
16
*/
17
18
#ifndef R819xU_H
19
#define R819xU_H
20
21
#include <linux/module.h>
22
#include <linux/kernel.h>
23
//#include <linux/config.h>
24
#include <
linux/init.h
>
25
#include <
linux/ioport.h
>
26
#include <linux/sched.h>
27
#include <linux/types.h>
28
#include <linux/slab.h>
29
#include <linux/netdevice.h>
30
//#include <linux/pci.h>
31
#include <
linux/usb.h
>
32
#include <
linux/etherdevice.h
>
33
#include <
linux/delay.h
>
34
#include <linux/rtnetlink.h>
//for rtnl_lock()
35
#include <linux/wireless.h>
36
#include <
linux/timer.h
>
37
#include <
linux/proc_fs.h
>
// Necessary because we use the proc fs
38
#include <linux/if_arp.h>
39
#include <linux/random.h>
40
#include <asm/io.h>
41
#include "ieee80211/ieee80211.h"
42
43
#define RTL8192U
44
#define RTL819xU_MODULE_NAME "rtl819xU"
45
//added for HW security, john.0629
46
#define FALSE 0
47
#define TRUE 1
48
#define MAX_KEY_LEN 61
49
#define KEY_BUF_SIZE 5
50
51
#define BIT0 0x00000001
52
#define BIT1 0x00000002
53
#define BIT2 0x00000004
54
#define BIT3 0x00000008
55
#define BIT4 0x00000010
56
#define BIT5 0x00000020
57
#define BIT6 0x00000040
58
#define BIT7 0x00000080
59
#define BIT8 0x00000100
60
#define BIT9 0x00000200
61
#define BIT10 0x00000400
62
#define BIT11 0x00000800
63
#define BIT12 0x00001000
64
#define BIT13 0x00002000
65
#define BIT14 0x00004000
66
#define BIT15 0x00008000
67
#define BIT16 0x00010000
68
#define BIT17 0x00020000
69
#define BIT18 0x00040000
70
#define BIT19 0x00080000
71
#define BIT20 0x00100000
72
#define BIT21 0x00200000
73
#define BIT22 0x00400000
74
#define BIT23 0x00800000
75
#define BIT24 0x01000000
76
#define BIT25 0x02000000
77
#define BIT26 0x04000000
78
#define BIT27 0x08000000
79
#define BIT28 0x10000000
80
#define BIT29 0x20000000
81
#define BIT30 0x40000000
82
#define BIT31 0x80000000
83
84
// Rx smooth factor
85
#define Rx_Smooth_Factor 20
86
#define DMESG(x,a...)
87
#define DMESGW(x,a...)
88
#define DMESGE(x,a...)
89
extern
u32
rt_global_debug_component
;
90
#define RT_TRACE(component, x, args...) \
91
do { if(rt_global_debug_component & component) \
92
printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \
93
##args);\
94
}while(0);
95
96
#define COMP_TRACE BIT0 // For function call tracing.
97
#define COMP_DBG BIT1 // Only for temporary debug message.
98
#define COMP_INIT BIT2 // during driver initialization / halt / reset.
99
100
101
#define COMP_RECV BIT3 // Receive data path.
102
#define COMP_SEND BIT4 // Send part path.
103
#define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
104
#define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related.
105
#define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS.
106
#define COMP_SWBW BIT8 // For bandwidth switch.
107
#define COMP_POWER_TRACKING BIT9 //FOR 8190 TX POWER TRACKING
108
#define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
109
#define COMP_QOS BIT11 // For QoS.
110
#define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
111
#define COMP_RM BIT13 // For Radio Measurement.
112
#define COMP_DIG BIT14 // For DIG, 2006.09.25, by rcnjko.
113
#define COMP_PHY BIT15
114
#define COMP_CH BIT16 //channel setting debug
115
#define COMP_TXAGC BIT17 // For Tx power, 060928, by rcnjko.
116
#define COMP_HIPWR BIT18 // For High Power Mechanism, 060928, by rcnjko.
117
#define COMP_HALDM BIT19 // For HW Dynamic Mechanism, 061010, by rcnjko.
118
#define COMP_SEC BIT20 // Event handling
119
#define COMP_LED BIT21 // For LED.
120
#define COMP_RF BIT22 // For RF.
121
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
122
#define COMP_RXDESC BIT23 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
123
//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
124
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
125
126
#define COMP_FIRMWARE BIT24 //for firmware downloading
127
#define COMP_HT BIT25 // For 802.11n HT related information. by Emily 2006-8-11
128
#define COMP_AMSDU BIT26 // For A-MSDU Debugging
129
130
#define COMP_SCAN BIT27
131
//#define COMP_RESET BIT28
132
#define COMP_DOWN BIT29 //for rm driver module
133
#define COMP_RESET BIT30 //for silent reset
134
#define COMP_ERR BIT31 //for error out, always on
135
136
#define RTL819x_DEBUG
137
#ifdef RTL819x_DEBUG
138
#define assert(expr) \
139
if (!(expr)) { \
140
printk( "Assertion failed! %s,%s,%s,line=%d\n", \
141
#expr,__FILE__,__FUNCTION__,__LINE__); \
142
}
143
//wb added to debug out data buf
144
//if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
145
#define RT_DEBUG_DATA(level, data, datalen) \
146
do{ if ((rt_global_debug_component & (level)) == (level)) \
147
{ \
148
int i; \
149
u8* pdata = (u8*) data; \
150
printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__); \
151
for(i=0; i<(int)(datalen); i++) \
152
{ \
153
printk("%2x ", pdata[i]); \
154
if ((i+1)%16 == 0) printk("\n"); \
155
} \
156
printk("\n"); \
157
} \
158
} while (0)
159
#else
160
#define assert(expr) do {} while (0)
161
#define RT_DEBUG_DATA(level, data, datalen) do {} while(0)
162
#endif
/* RTL8169_DEBUG */
163
164
165
//
166
// Queue Select Value in TxDesc
167
//
168
#define QSLT_BK 0x1
169
#define QSLT_BE 0x0
170
#define QSLT_VI 0x4
171
#define QSLT_VO 0x6
172
#define QSLT_BEACON 0x10
173
#define QSLT_HIGH 0x11
174
#define QSLT_MGNT 0x12
175
#define QSLT_CMD 0x13
176
177
#define DESC90_RATE1M 0x00
178
#define DESC90_RATE2M 0x01
179
#define DESC90_RATE5_5M 0x02
180
#define DESC90_RATE11M 0x03
181
#define DESC90_RATE6M 0x04
182
#define DESC90_RATE9M 0x05
183
#define DESC90_RATE12M 0x06
184
#define DESC90_RATE18M 0x07
185
#define DESC90_RATE24M 0x08
186
#define DESC90_RATE36M 0x09
187
#define DESC90_RATE48M 0x0a
188
#define DESC90_RATE54M 0x0b
189
#define DESC90_RATEMCS0 0x00
190
#define DESC90_RATEMCS1 0x01
191
#define DESC90_RATEMCS2 0x02
192
#define DESC90_RATEMCS3 0x03
193
#define DESC90_RATEMCS4 0x04
194
#define DESC90_RATEMCS5 0x05
195
#define DESC90_RATEMCS6 0x06
196
#define DESC90_RATEMCS7 0x07
197
#define DESC90_RATEMCS8 0x08
198
#define DESC90_RATEMCS9 0x09
199
#define DESC90_RATEMCS10 0x0a
200
#define DESC90_RATEMCS11 0x0b
201
#define DESC90_RATEMCS12 0x0c
202
#define DESC90_RATEMCS13 0x0d
203
#define DESC90_RATEMCS14 0x0e
204
#define DESC90_RATEMCS15 0x0f
205
#define DESC90_RATEMCS32 0x20
206
207
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
208
209
#define IEEE80211_WATCH_DOG_TIME 2000
210
#define PHY_Beacon_RSSI_SLID_WIN_MAX 10
211
//for txpowertracking by amy
212
#define OFDM_Table_Length 19
213
#define CCK_Table_length 12
214
215
/* for rtl819x */
216
typedef
struct
_tx_desc_819x_usb
{
217
//DWORD 0
218
u16
PktSize
;
219
u8
Offset
;
220
u8
Reserved0
:3;
221
u8
CmdInit
:1;
222
u8
LastSeg
:1;
223
u8
FirstSeg
:1;
224
u8
LINIP
:1;
225
u8
OWN
:1;
226
227
//DWORD 1
228
u8
TxFWInfoSize
;
229
u8
RATid
:3;
230
u8
DISFB
:1;
231
u8
USERATE
:1;
232
u8
MOREFRAG
:1;
233
u8
NoEnc
:1;
234
u8
PIFS
:1;
235
u8
QueueSelect
:5;
236
u8
NoACM
:1;
237
u8
Reserved1
:2;
238
u8
SecCAMID
:5;
239
u8
SecDescAssign
:1;
240
u8
SecType
:2;
241
242
//DWORD 2
243
u16
TxBufferSize
;
244
//u16 Reserved2;
245
u8
ResvForPaddingLen
:7;
246
u8
Reserved3
:1;
247
u8
Reserved4
;
248
249
//DWORD 3, 4, 5
250
u32
Reserved5
;
251
u32
Reserved6
;
252
u32
Reserved7
;
253
}
tx_desc_819x_usb
, *
ptx_desc_819x_usb
;
254
255
#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
256
typedef
struct
_tx_desc_819x_usb_aggr_subframe {
257
//DWORD 0
258
u16
PktSize;
259
u8
Offset;
260
u8
TxFWInfoSize;
261
262
//DWORD 1
263
u8
RATid:3;
264
u8
DISFB
:1;
265
u8
USERATE:1;
266
u8
MOREFRAG:1;
267
u8
NoEnc:1;
268
u8
PIFS
:1;
269
u8
QueueSelect:5;
270
u8
NoACM:1;
271
u8
Reserved1
:2;
272
u8
SecCAMID:5;
273
u8
SecDescAssign:1;
274
u8
SecType:2;
275
u8
PacketID:7;
276
u8
OWN
:1;
277
}tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
278
#endif
279
280
281
282
typedef
struct
_tx_desc_cmd_819x_usb
{
283
//DWORD 0
284
u16
Reserved0
;
285
u8
Reserved1
;
286
u8
Reserved2
:3;
287
u8
CmdInit
:1;
288
u8
LastSeg
:1;
289
u8
FirstSeg
:1;
290
u8
LINIP
:1;
291
u8
OWN
:1;
292
293
//DOWRD 1
294
//u32 Reserved3;
295
u8
TxFWInfoSize
;
296
u8
Reserved3
;
297
u8
QueueSelect
;
298
u8
Reserved4
;
299
300
//DOWRD 2
301
u16
TxBufferSize
;
302
u16
Reserved5
;
303
304
//DWORD 3,4,5
305
//u32 TxBufferAddr;
306
//u32 NextDescAddress;
307
u32
Reserved6
;
308
u32
Reserved7
;
309
u32
Reserved8
;
310
}
tx_desc_cmd_819x_usb
, *
ptx_desc_cmd_819x_usb
;
311
312
313
typedef
struct
_tx_fwinfo_819x_usb
{
314
//DOWRD 0
315
u8
TxRate
:7;
316
u8
CtsEnable
:1;
317
u8
RtsRate
:7;
318
u8
RtsEnable
:1;
319
u8
TxHT
:1;
320
u8
Short
:1;
//Short PLCP for CCK, or short GI for 11n MCS
321
u8
TxBandwidth
:1;
// This is used for HT MCS rate only.
322
u8
TxSubCarrier
:2;
// This is used for legacy OFDM rate only.
323
u8
STBC
:2;
324
u8
AllowAggregation
:1;
325
u8
RtsHT
:1;
//Interpret RtsRate field as high throughput data rate
326
u8
RtsShort
:1;
//Short PLCP for CCK, or short GI for 11n MCS
327
u8
RtsBandwidth
:1;
// This is used for HT MCS rate only.
328
u8
RtsSubcarrier
:2;
// This is used for legacy OFDM rate only.
329
u8
RtsSTBC
:2;
330
u8
EnableCPUDur
:1;
//Enable firmware to recalculate and assign packet duration
331
332
//DWORD 1
333
u32
RxMF
:2;
334
u32
RxAMD
:3;
335
u32
TxPerPktInfoFeedback
:1;
//1 indicate Tx info gathtered by firmware and returned by Rx Cmd
336
u32
Reserved1
:2;
337
u32
TxAGCOffSet
:4;
338
u32
TxAGCSign
:1;
339
u32
Tx_INFO_RSVD
:6;
340
u32
PacketID
:13;
341
//u32 Reserved;
342
}
tx_fwinfo_819x_usb
, *
ptx_fwinfo_819x_usb
;
343
344
typedef
struct
rtl8192_rx_info
{
345
struct
urb
*
urb
;
346
struct
net_device
*
dev
;
347
u8
out_pipe
;
348
}
rtl8192_rx_info
;
349
350
typedef
struct
rx_desc_819x_usb
{
351
//DOWRD 0
352
u16
Length
:14;
353
u16
CRC32
:1;
354
u16
ICV
:1;
355
u8
RxDrvInfoSize
;
356
u8
Shift
:2;
357
u8
PHYStatus
:1;
358
u8
SWDec
:1;
359
//u8 LastSeg:1;
360
//u8 FirstSeg:1;
361
//u8 EOR:1;
362
//u8 OWN:1;
363
u8
Reserved1
:4;
364
365
//DWORD 1
366
u32
Reserved2
;
367
368
//DWORD 2
369
//u32 Reserved3;
370
371
//DWORD 3
372
//u32 BufferAddress;
373
374
}
rx_desc_819x_usb
, *
prx_desc_819x_usb
;
375
376
#ifdef USB_RX_AGGREGATION_SUPPORT
377
typedef
struct
_rx_desc_819x_usb_aggr_subframe{
378
//DOWRD 0
379
u16
Length
:14;
380
u16
CRC32
:1;
381
u16
ICV
:1;
382
u8
Offset;
383
u8
RxDrvInfoSize;
384
//DOWRD 1
385
u8
Shift:2;
386
u8
PHYStatus:1;
387
u8
SWDec:1;
388
u8
Reserved1
:4;
389
u8
Reserved2
;
390
u16
Reserved3
;
391
//DWORD 2
392
//u4Byte Reserved3;
393
//DWORD 3
394
//u4Byte BufferAddress;
395
}rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
396
#endif
397
398
typedef
struct
rx_drvinfo_819x_usb
{
399
//DWORD 0
400
u16
Reserved1
:12;
401
u16
PartAggr
:1;
402
u16
FirstAGGR
:1;
403
u16
Reserved2
:2;
404
405
u8
RxRate
:7;
406
u8
RxHT
:1;
407
408
u8
BW
:1;
409
u8
SPLCP
:1;
410
u8
Reserved3
:2;
411
u8
PAM
:1;
412
u8
Mcast
:1;
413
u8
Bcast
:1;
414
u8
Reserved4
:1;
415
416
//DWORD 1
417
u32
TSFL
;
418
419
}
rx_drvinfo_819x_usb
, *
prx_drvinfo_819x_usb
;
420
421
422
#define MAX_DEV_ADDR_SIZE 8
/* support till 64 bit bus width OS */
423
#define MAX_FIRMWARE_INFORMATION_SIZE 32
/*2006/04/30 by Emily forRTL8190*/
424
#define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
425
#define ENCRYPTION_MAX_OVERHEAD 128
426
#define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb)
427
#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
428
#define MAX_FRAGMENT_COUNT 8
429
#ifdef RTL8192U
430
#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
431
#define MAX_TRANSMIT_BUFFER_SIZE 32000
432
#else
433
#define MAX_TRANSMIT_BUFFER_SIZE 8000
434
#endif
435
#else
436
#define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
437
#endif
438
#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
439
#define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb))
440
#endif
441
#define scrclng 4 // octets for crc32 (FCS, ICV)
442
443
typedef
enum
rf_optype
444
{
445
RF_OP_By_SW_3wire
= 0,
446
RF_OP_By_FW
,
447
RF_OP_MAX
448
}
rf_op_type
;
449
/* 8190 Loopback Mode definition */
450
typedef
enum
_rtl819xUsb_loopback
{
451
RTL819xU_NO_LOOPBACK
= 0,
452
RTL819xU_MAC_LOOPBACK
= 1,
453
RTL819xU_DMA_LOOPBACK
= 2,
454
RTL819xU_CCK_LOOPBACK
= 3,
455
}
rtl819xUsb_loopback_e
;
456
457
/* due to rtl8192 firmware */
458
typedef
enum
_desc_packet_type_e
{
459
DESC_PACKET_TYPE_INIT
= 0,
460
DESC_PACKET_TYPE_NORMAL
= 1,
461
}
desc_packet_type_e
;
462
463
typedef
enum
_firmware_status
{
464
FW_STATUS_0_INIT
= 0,
465
FW_STATUS_1_MOVE_BOOT_CODE
= 1,
466
FW_STATUS_2_MOVE_MAIN_CODE
= 2,
467
FW_STATUS_3_TURNON_CPU
= 3,
468
FW_STATUS_4_MOVE_DATA_CODE
= 4,
469
FW_STATUS_5_READY
= 5,
470
}
firmware_status_e
;
471
472
typedef
struct
_rt_firmare_seg_container
{
473
u16
seg_size
;
474
u8
*
seg_ptr
;
475
}
fw_seg_container
, *
pfw_seg_container
;
476
typedef
struct
_rt_firmware
{
477
firmware_status_e
firmware_status
;
478
u16
cmdpacket_frag_thresold
;
479
#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
480
u8
firmware_buf
[
RTL8190_MAX_FIRMWARE_CODE_SIZE
];
481
u16
firmware_buf_size
;
482
}
rt_firmware
, *
prt_firmware
;
483
484
//+by amy 080507
485
#define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
486
487
typedef
struct
_rt_firmware_info_819xUsb
{
488
u8
sz_info
[16];
489
}
rt_firmware_info_819xUsb
, *
prt_firmware_info_819xUsb
;
490
491
/* Firmware Queue Layout */
492
#define NUM_OF_FIRMWARE_QUEUE 10
493
#define NUM_OF_PAGES_IN_FW 0x100
494
495
#ifdef USE_ONE_PIPE
496
#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x000
497
#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x000
498
#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x0ff
499
#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x000
500
#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
501
#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
502
#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x00
503
#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
504
#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x0
505
#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x00
506
#else
507
508
#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x020
509
#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x020
510
#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x040
511
#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x040
512
#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
513
#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4
514
#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x20
515
#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
516
#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
517
#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18
518
519
#endif
520
521
#define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
522
#define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
523
#define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
524
#define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
525
#define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
526
#define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
527
#define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
528
#define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
529
#define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
530
//=================================================================
531
//=================================================================
532
533
#define EPROM_93c46 0
534
#define EPROM_93c56 1
535
536
#define DEFAULT_FRAG_THRESHOLD 2342U
537
#define MIN_FRAG_THRESHOLD 256U
538
#define DEFAULT_BEACONINTERVAL 0x64U
539
#define DEFAULT_BEACON_ESSID "Rtl819xU"
540
541
#define DEFAULT_SSID ""
542
#define DEFAULT_RETRY_RTS 7
543
#define DEFAULT_RETRY_DATA 7
544
#define PRISM_HDR_SIZE 64
545
546
#define PHY_RSSI_SLID_WIN_MAX 100
547
548
549
typedef
enum
_WIRELESS_MODE
{
550
WIRELESS_MODE_UNKNOWN
= 0x00,
551
WIRELESS_MODE_A
= 0x01,
552
WIRELESS_MODE_B
= 0x02,
553
WIRELESS_MODE_G
= 0x04,
554
WIRELESS_MODE_AUTO
= 0x08,
555
WIRELESS_MODE_N_24G
= 0x10,
556
WIRELESS_MODE_N_5G
= 0x20
557
}
WIRELESS_MODE
;
558
559
560
#define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30
561
562
typedef
struct
buffer
563
{
564
struct
buffer
*
next
;
565
u32
*
buf
;
566
567
}
buffer
;
568
569
typedef
struct
rtl_reg_debug
{
570
unsigned
int
cmd
;
571
struct
{
572
unsigned
char
type
;
573
unsigned
char
addr
;
574
unsigned
char
page
;
575
unsigned
char
length
;
576
}
head
;
577
unsigned
char
buf
[0xff];
578
}
rtl_reg_debug
;
579
580
581
582
583
584
585
typedef
struct
_rt_9x_tx_rate_history
{
586
u32
cck
[4];
587
u32
ofdm
[8];
588
// HT_MCS[0][]: BW=0 SG=0
589
// HT_MCS[1][]: BW=1 SG=0
590
// HT_MCS[2][]: BW=0 SG=1
591
// HT_MCS[3][]: BW=1 SG=1
592
u32
ht_mcs
[4][16];
593
}
rt_tx_rahis_t
, *
prt_tx_rahis_t
;
594
typedef
struct
_RT_SMOOTH_DATA_4RF
{
595
char
elements
[4][100];
//array to store values
596
u32
index
;
//index to current array to store
597
u32
TotalNum
;
//num of valid elements
598
u32
TotalVal
[4];
//sum of valid elements
599
}
RT_SMOOTH_DATA_4RF
, *
PRT_SMOOTH_DATA_4RF
;
600
601
#define MAX_8192U_RX_SIZE 8192 // This maybe changed for D-cut larger aggregation size
602
//stats seems messed up, clean it ASAP
603
typedef
struct
Stats
604
{
605
unsigned
long
txrdu
;
606
// unsigned long rxrdu;
607
//unsigned long rxnolast;
608
//unsigned long rxnodata;
609
// unsigned long rxreset;
610
// unsigned long rxnopointer;
611
unsigned
long
rxok
;
612
unsigned
long
rxframgment
;
613
unsigned
long
rxurberr
;
614
unsigned
long
rxstaterr
;
615
unsigned
long
received_rate_histogram
[4][32];
//0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
616
unsigned
long
received_preamble_GI
[2][32];
//0: Long preamble/GI, 1:Short preamble/GI
617
unsigned
long
rx_AMPDUsize_histogram
[5];
// level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
618
unsigned
long
rx_AMPDUnum_histogram
[5];
// level: (<5), (5~10), (10~20), (20~40), (>40)
619
unsigned
long
numpacket_matchbssid
;
// debug use only.
620
unsigned
long
numpacket_toself
;
// debug use only.
621
unsigned
long
num_process_phyinfo
;
// debug use only.
622
unsigned
long
numqry_phystatus
;
623
unsigned
long
numqry_phystatusCCK
;
624
unsigned
long
numqry_phystatusHT
;
625
unsigned
long
received_bwtype
[5];
//0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
626
unsigned
long
txnperr
;
627
unsigned
long
txnpdrop
;
628
unsigned
long
txresumed
;
629
// unsigned long rxerr;
630
// unsigned long rxoverflow;
631
// unsigned long rxint;
632
unsigned
long
txnpokint
;
633
// unsigned long txhpokint;
634
// unsigned long txhperr;
635
// unsigned long ints;
636
// unsigned long shints;
637
unsigned
long
txoverflow
;
638
// unsigned long rxdmafail;
639
// unsigned long txbeacon;
640
// unsigned long txbeaconerr;
641
unsigned
long
txlpokint
;
642
unsigned
long
txlpdrop
;
643
unsigned
long
txlperr
;
644
unsigned
long
txbeokint
;
645
unsigned
long
txbedrop
;
646
unsigned
long
txbeerr
;
647
unsigned
long
txbkokint
;
648
unsigned
long
txbkdrop
;
649
unsigned
long
txbkerr
;
650
unsigned
long
txviokint
;
651
unsigned
long
txvidrop
;
652
unsigned
long
txvierr
;
653
unsigned
long
txvookint
;
654
unsigned
long
txvodrop
;
655
unsigned
long
txvoerr
;
656
unsigned
long
txbeaconokint
;
657
unsigned
long
txbeacondrop
;
658
unsigned
long
txbeaconerr
;
659
unsigned
long
txmanageokint
;
660
unsigned
long
txmanagedrop
;
661
unsigned
long
txmanageerr
;
662
unsigned
long
txdatapkt
;
663
unsigned
long
txfeedback
;
664
unsigned
long
txfeedbackok
;
665
666
unsigned
long
txoktotal
;
667
unsigned
long
txokbytestotal
;
668
unsigned
long
txokinperiod
;
669
unsigned
long
txmulticast
;
670
unsigned
long
txbytesmulticast
;
671
unsigned
long
txbroadcast
;
672
unsigned
long
txbytesbroadcast
;
673
unsigned
long
txunicast
;
674
unsigned
long
txbytesunicast
;
675
676
unsigned
long
rxoktotal
;
677
unsigned
long
rxbytesunicast
;
678
unsigned
long
txfeedbackfail
;
679
unsigned
long
txerrtotal
;
680
unsigned
long
txerrbytestotal
;
681
unsigned
long
txerrmulticast
;
682
unsigned
long
txerrbroadcast
;
683
unsigned
long
txerrunicast
;
684
unsigned
long
txretrycount
;
685
unsigned
long
txfeedbackretry
;
686
u8
last_packet_rate
;
687
unsigned
long
slide_signal_strength
[100];
688
unsigned
long
slide_evm
[100];
689
unsigned
long
slide_rssi_total
;
// For recording sliding window's RSSI value
690
unsigned
long
slide_evm_total
;
// For recording sliding window's EVM value
691
long
signal_strength
;
// Transformed, in dbm. Beautified signal strength for UI, not correct.
692
long
signal_quality
;
693
long
last_signal_strength_inpercent
;
694
long
recv_signal_power
;
// Correct smoothed ss in Dbm, only used in driver to report real power now.
695
u8
rx_rssi_percentage
[4];
696
u8
rx_evm_percentage
[2];
697
long
rxSNRdB
[4];
698
rt_tx_rahis_t
txrate
;
699
u32
Slide_Beacon_pwdb
[100];
//cosa add for beacon rssi
700
u32
Slide_Beacon_Total
;
//cosa add for beacon rssi
701
RT_SMOOTH_DATA_4RF
cck_adc_pwdb
;
702
703
u32
CurrentShowTxate
;
704
}
Stats
;
705
706
707
// Bandwidth Offset
708
#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
709
#define HAL_PRIME_CHNL_OFFSET_LOWER 1
710
#define HAL_PRIME_CHNL_OFFSET_UPPER 2
711
712
//+by amy 080507
713
714
typedef
struct
ChnlAccessSetting
{
715
u16
SIFS_Timer
;
716
u16
DIFS_Timer
;
717
u16
SlotTimeTimer
;
718
u16
EIFS_Timer
;
719
u16
CWminIndex
;
720
u16
CWmaxIndex
;
721
}*
PCHANNEL_ACCESS_SETTING
,
CHANNEL_ACCESS_SETTING
;
722
723
typedef
struct
_BB_REGISTER_DEFINITION
{
724
u32
rfintfs
;
// set software control: // 0x870~0x877[8 bytes]
725
u32
rfintfi
;
// readback data: // 0x8e0~0x8e7[8 bytes]
726
u32
rfintfo
;
// output data: // 0x860~0x86f [16 bytes]
727
u32
rfintfe
;
// output enable: // 0x860~0x86f [16 bytes]
728
u32
rf3wireOffset
;
// LSSI data: // 0x840~0x84f [16 bytes]
729
u32
rfLSSI_Select
;
// BB Band Select: // 0x878~0x87f [8 bytes]
730
u32
rfTxGainStage
;
// Tx gain stage: // 0x80c~0x80f [4 bytes]
731
u32
rfHSSIPara1
;
// wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
732
u32
rfHSSIPara2
;
// wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
733
u32
rfSwitchControl
;
//Tx Rx antenna control : // 0x858~0x85f [16 bytes]
734
u32
rfAGCControl1
;
//AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
735
u32
rfAGCControl2
;
//AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
736
u32
rfRxIQImbalance
;
//OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
737
u32
rfRxAFE
;
//Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
738
u32
rfTxIQImbalance
;
//OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
739
u32
rfTxAFE
;
//Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
740
u32
rfLSSIReadBack
;
//LSSI RF readback data // 0x8a0~0x8af [16 bytes]
741
}
BB_REGISTER_DEFINITION_T
, *
PBB_REGISTER_DEFINITION_T
;
742
743
typedef
enum
_RT_RF_TYPE_819xU
{
744
RF_TYPE_MIN
= 0,
745
RF_8225
,
746
RF_8256
,
747
RF_8258
,
748
RF_PSEUDO_11N
= 4,
749
}
RT_RF_TYPE_819xU
, *
PRT_RF_TYPE_819xU
;
750
751
typedef
struct
_rate_adaptive
752
{
753
u8
rate_adaptive_disabled
;
754
u8
ratr_state
;
755
u16
reserve
;
756
757
u32
high_rssi_thresh_for_ra
;
758
u32
high2low_rssi_thresh_for_ra
;
759
u8
low2high_rssi_thresh_for_ra40M
;
760
u32
low_rssi_thresh_for_ra40M
;
761
u8
low2high_rssi_thresh_for_ra20M
;
762
u32
low_rssi_thresh_for_ra20M
;
763
u32
upper_rssi_threshold_ratr
;
764
u32
middle_rssi_threshold_ratr
;
765
u32
low_rssi_threshold_ratr
;
766
u32
low_rssi_threshold_ratr_40M
;
767
u32
low_rssi_threshold_ratr_20M
;
768
u8
ping_rssi_enable
;
//cosa add for test
769
u32
ping_rssi_ratr
;
//cosa add for test
770
u32
ping_rssi_thresh_for_ra
;
//cosa add for test
771
u32
last_ratr
;
772
773
}
rate_adaptive
, *
prate_adaptive
;
774
775
#define TxBBGainTableLength 37
776
#define CCKTxBBGainTableLength 23
777
778
typedef
struct
_txbbgain_struct
779
{
780
long
txbb_iq_amplifygain
;
781
u32
txbbgain_value
;
782
}
txbbgain_struct
, *
ptxbbgain_struct
;
783
784
typedef
struct
_ccktxbbgain_struct
785
{
786
//The Value is from a22 to a29 one Byte one time is much Safer
787
u8
ccktxbb_valuearray
[8];
788
}
ccktxbbgain_struct
,*
pccktxbbgain_struct
;
789
790
791
typedef
struct
_init_gain
792
{
793
u8
xaagccore1
;
794
u8
xbagccore1
;
795
u8
xcagccore1
;
796
u8
xdagccore1
;
797
u8
cca
;
798
799
}
init_gain
, *
pinit_gain
;
800
//by amy 0606
801
802
typedef
struct
_phy_ofdm_rx_status_report_819xusb
803
{
804
u8
trsw_gain_X
[4];
805
u8
pwdb_all
;
806
u8
cfosho_X
[4];
807
u8
cfotail_X
[4];
808
u8
rxevm_X
[2];
809
u8
rxsnr_X
[4];
810
u8
pdsnr_X
[2];
811
u8
csi_current_X
[2];
812
u8
csi_target_X
[2];
813
u8
sigevm
;
814
u8
max_ex_pwr
;
815
u8
sgi_en
;
816
u8
rxsc_sgien_exflg
;
817
}
phy_sts_ofdm_819xusb_t
;
818
819
typedef
struct
_phy_cck_rx_status_report_819xusb
820
{
821
/* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
822
0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
823
u8
adc_pwdb_X
[4];
824
u8
sq_rpt
;
825
u8
cck_agc_rpt
;
826
}
phy_sts_cck_819xusb_t
;
827
828
829
typedef
struct
_phy_ofdm_rx_status_rxsc_sgien_exintfflag
{
830
u8
reserved
:4;
831
u8
rxsc
:2;
832
u8
sgi_en
:1;
833
u8
ex_intf_flag
:1;
834
}
phy_ofdm_rx_status_rxsc_sgien_exintfflag
;
835
836
typedef
enum
_RT_CUSTOMER_ID
837
{
838
RT_CID_DEFAULT
= 0,
839
RT_CID_8187_ALPHA0
= 1,
840
RT_CID_8187_SERCOMM_PS
= 2,
841
RT_CID_8187_HW_LED
= 3,
842
RT_CID_8187_NETGEAR
= 4,
843
RT_CID_WHQL
= 5,
844
RT_CID_819x_CAMEO
= 6,
845
RT_CID_819x_RUNTOP
= 7,
846
RT_CID_819x_Senao
= 8,
847
RT_CID_TOSHIBA
= 9,
// Merge by Jacken, 2008/01/31.
848
RT_CID_819x_Netcore
= 10,
849
RT_CID_Nettronix
= 11,
850
RT_CID_DLINK
= 12,
851
RT_CID_PRONET
= 13,
852
}
RT_CUSTOMER_ID
, *
PRT_CUSTOMER_ID
;
853
854
//================================================================================
855
// LED customization.
856
//================================================================================
857
858
typedef
enum
_LED_STRATEGY_8190
{
859
SW_LED_MODE0
,
// SW control 1 LED via GPIO0. It is default option.
860
SW_LED_MODE1
,
// SW control for PCI Express
861
SW_LED_MODE2
,
// SW control for Cameo.
862
SW_LED_MODE3
,
// SW contorl for RunTop.
863
SW_LED_MODE4
,
// SW control for Netcore
864
HW_LED
,
// HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
865
}
LED_STRATEGY_8190
, *
PLED_STRATEGY_8190
;
866
867
typedef
enum
_RESET_TYPE
{
868
RESET_TYPE_NORESET
= 0x00,
869
RESET_TYPE_NORMAL
= 0x01,
870
RESET_TYPE_SILENT
= 0x02
871
}
RESET_TYPE
;
872
873
/* The simple tx command OP code. */
874
typedef
enum
_tag_TxCmd_Config_Index
{
875
TXCMD_TXRA_HISTORY_CTRL
= 0xFF900000,
876
TXCMD_RESET_TX_PKT_BUFF
= 0xFF900001,
877
TXCMD_RESET_RX_PKT_BUFF
= 0xFF900002,
878
TXCMD_SET_TX_DURATION
= 0xFF900003,
879
TXCMD_SET_RX_RSSI
= 0xFF900004,
880
TXCMD_SET_TX_PWR_TRACKING
= 0xFF900005,
881
TXCMD_XXXX_CTRL
,
882
}
DCMD_TXCMD_OP
;
883
884
typedef
struct
r8192_priv
885
{
886
struct
usb_device *
udev
;
887
//added for maintain info from eeprom
888
short
epromtype
;
889
u16
eeprom_vid
;
890
u16
eeprom_pid
;
891
u8
eeprom_CustomerID
;
892
u8
eeprom_ChannelPlan
;
893
RT_CUSTOMER_ID
CustomerID
;
894
LED_STRATEGY_8190
LedStrategy
;
895
u8
txqueue_to_outpipemap
[9];
896
int
irq
;
897
struct
ieee80211_device
*
ieee80211
;
898
899
short
card_8192
;
/* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
900
u8
card_8192_version
;
/* if TCR reports card V B/C this discriminates */
901
// short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */
902
short
enable_gpio0
;
903
enum
card_type
{
PCI
,
MINIPCI
,
CARDBUS
,
USB
}
card_type
;
904
short
hw_plcp_len
;
905
short
plcp_preamble_mode
;
906
907
spinlock_t
irq_lock
;
908
// spinlock_t irq_th_lock;
909
spinlock_t
tx_lock
;
910
struct
mutex
mutex
;
911
//spinlock_t rf_lock; //used to lock rf write operation added by wb
912
913
u16
irq_mask
;
914
// short irq_enabled;
915
// struct net_device *dev; //comment this out.
916
short
chan
;
917
short
sens
;
918
short
max_sens
;
919
920
921
// u8 chtxpwr[15]; //channels from 1 to 14, 0 not used
922
// u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used
923
// u8 cck_txpwr_base;
924
// u8 ofdm_txpwr_base;
925
// u8 challow[15]; //channels from 1 to 14, 0 not used
926
short
up
;
927
short
crcmon
;
//if 1 allow bad crc frame reception in monitor mode
928
// short prism_hdr;
929
930
// struct timer_list scan_timer;
931
/*short scanpending;
932
short stopscan;*/
933
// spinlock_t scan_lock;
934
// u8 active_probe;
935
//u8 active_scan_num;
936
struct
semaphore
wx_sem
;
937
struct
semaphore
rf_sem
;
//used to lock rf write operation added by wb, modified by david
938
// short hw_wep;
939
940
// short digphy;
941
// short antb;
942
// short diversity;
943
// u8 cs_treshold;
944
// short rcr_csense;
945
u8
rf_type
;
//0 means 1T2R, 1 means 2T4R
946
RT_RF_TYPE_819xU
rf_chip
;
947
948
// u32 key0[4];
949
short
(*
rf_set_sens
)(
struct
net_device
*
dev
,
short
sens
);
950
u8
(*
rf_set_chan
)(
struct
net_device
*
dev
,
u8
ch);
951
void
(*
rf_close
)(
struct
net_device
*
dev
);
952
void
(*
rf_init
)(
struct
net_device
*
dev
);
953
//short rate;
954
short
promisc
;
955
/*stats*/
956
struct
Stats
stats
;
957
struct
iw_statistics
wstats
;
958
struct
proc_dir_entry
*
dir_dev
;
959
960
/*RX stuff*/
961
// u32 *rxring;
962
// u32 *rxringtail;
963
// dma_addr_t rxringdma;
964
struct
urb
**
rx_urb
;
965
struct
urb
**
rx_cmd_urb
;
966
#ifdef THOMAS_BEACON
967
u32
*oldaddr;
968
#endif
969
#ifdef THOMAS_TASKLET
970
atomic_t
irt_counter;
//count for irq_rx_tasklet
971
#endif
972
#ifdef JACKSON_NEW_RX
973
struct
sk_buff
**pp_rxskb;
974
int
rx_inx;
975
#endif
976
977
/* modified by davad for Rx process */
978
struct
sk_buff_head
rx_queue
;
979
struct
sk_buff_head
skb_queue
;
980
struct
work_struct
qos_activate
;
981
short
tx_urb_index
;
982
atomic_t
tx_pending
[0x10];
//UART_PRIORITY+1
983
984
985
struct
tasklet_struct
irq_rx_tasklet
;
986
struct
urb
*
rxurb_task
;
987
988
//2 Tx Related variables
989
u16
ShortRetryLimit
;
990
u16
LongRetryLimit
;
991
u32
TransmitConfig
;
992
u8
RegCWinMin
;
// For turbo mode CW adaptive. Added by Annie, 2005-10-27.
993
994
u32
LastRxDescTSFHigh
;
995
u32
LastRxDescTSFLow
;
996
997
998
//2 Rx Related variables
999
u16
EarlyRxThreshold
;
1000
u32
ReceiveConfig
;
1001
u8
AcmControl
;
1002
1003
u8
RFProgType
;
1004
1005
u8
retry_data
;
1006
u8
retry_rts
;
1007
u16
rts
;
1008
1009
struct
ChnlAccessSetting
ChannelAccessSetting
;
1010
struct
work_struct
reset_wq
;
1011
1012
/**********************************************************/
1013
//for rtl819xUsb
1014
u16
basic_rate
;
1015
u8
short_preamble
;
1016
u8
slot_time
;
1017
bool
bDcut
;
1018
bool
bCurrentRxAggrEnable
;
1019
u8
Rf_Mode
;
//add for Firmware RF -R/W switch
1020
prt_firmware
pFirmware
;
1021
rtl819xUsb_loopback_e
LoopbackMode
;
1022
u16
EEPROMTxPowerDiff
;
1023
u8
EEPROMThermalMeter
;
1024
u8
EEPROMPwDiff
;
1025
u8
EEPROMCrystalCap
;
1026
u8
EEPROM_Def_Ver
;
1027
u8
EEPROMTxPowerLevelCCK
;
// CCK channel 1~14
1028
u8
EEPROMTxPowerLevelCCK_V1
[3];
1029
u8
EEPROMTxPowerLevelOFDM24G
[3];
// OFDM 2.4G channel 1~14
1030
u8
EEPROMTxPowerLevelOFDM5G
[24];
// OFDM 5G
1031
1032
/*PHY related*/
1033
BB_REGISTER_DEFINITION_T
PHYRegDef
[4];
//Radio A/B/C/D
1034
// Read/write are allow for following hardware information variables
1035
u32
MCSTxPowerLevelOriginalOffset
[6];
1036
u32
CCKTxPowerLevelOriginalOffset
;
1037
u8
TxPowerLevelCCK
[14];
// CCK channel 1~14
1038
u8
TxPowerLevelOFDM24G
[14];
// OFDM 2.4G channel 1~14
1039
u8
TxPowerLevelOFDM5G
[14];
// OFDM 5G
1040
u32
Pwr_Track
;
1041
u8
TxPowerDiff
;
1042
u8
AntennaTxPwDiff
[2];
// Antenna gain offset, index 0 for B, 1 for C, and 2 for D
1043
u8
CrystalCap
;
// CrystalCap.
1044
u8
ThermalMeter
[2];
// ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
1045
1046
u8
CckPwEnl
;
1047
// Use to calculate PWBD.
1048
u8
bCckHighPower
;
1049
long
undecorated_smoothed_pwdb
;
1050
1051
//for set channel
1052
u8
SwChnlInProgress
;
1053
u8
SwChnlStage
;
1054
u8
SwChnlStep
;
1055
u8
SetBWModeInProgress
;
1056
HT_CHANNEL_WIDTH
CurrentChannelBW
;
1057
u8
ChannelPlan
;
1058
// 8190 40MHz mode
1059
//
1060
u8
nCur40MhzPrimeSC
;
// Control channel sub-carrier
1061
// Joseph test for shorten RF configuration time.
1062
// We save RF reg0 in this variable to reduce RF reading.
1063
//
1064
u32
RfReg0Value
[4];
1065
u8
NumTotalRFPath
;
1066
bool
brfpath_rxenable
[4];
1067
//RF set related
1068
bool
SetRFPowerStateInProgress
;
1069
//+by amy 080507
1070
struct
timer_list
watch_dog_timer
;
1071
1072
//+by amy 080515 for dynamic mechenism
1073
//Add by amy Tx Power Control for Near/Far Range 2008/05/15
1074
bool
bdynamic_txpower
;
//bDynamicTxPower
1075
bool
bDynamicTxHighPower
;
// Tx high power state
1076
bool
bDynamicTxLowPower
;
// Tx low power state
1077
bool
bLastDTPFlag_High
;
1078
bool
bLastDTPFlag_Low
;
1079
1080
bool
bstore_last_dtpflag
;
1081
bool
bstart_txctrl_bydtp
;
//Define to discriminate on High power State or on sitesuvey to change Tx gain index
1082
//Add by amy for Rate Adaptive
1083
rate_adaptive
rate_adaptive
;
1084
//Add by amy for TX power tracking
1085
//2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING
1086
txbbgain_struct
txbbgain_table
[
TxBBGainTableLength
];
1087
u8
txpower_count
;
//For 6 sec do tracking again
1088
bool
btxpower_trackingInit
;
1089
u8
OFDM_index
;
1090
u8
CCK_index
;
1091
//2007/09/10 Mars Add CCK TX Power Tracking
1092
ccktxbbgain_struct
cck_txbbgain_table
[
CCKTxBBGainTableLength
];
1093
ccktxbbgain_struct
cck_txbbgain_ch14_table
[
CCKTxBBGainTableLength
];
1094
u8
rfa_txpowertrackingindex
;
1095
u8
rfa_txpowertrackingindex_real
;
1096
u8
rfa_txpowertracking_default
;
1097
u8
rfc_txpowertrackingindex
;
1098
u8
rfc_txpowertrackingindex_real
;
1099
1100
s8
cck_present_attentuation
;
1101
u8
cck_present_attentuation_20Mdefault
;
1102
u8
cck_present_attentuation_40Mdefault
;
1103
char
cck_present_attentuation_difference
;
1104
bool
btxpower_tracking
;
1105
bool
bcck_in_ch14
;
1106
bool
btxpowerdata_readfromEEPORM
;
1107
u16
TSSI_13dBm
;
1108
//For Backup Initial Gain
1109
init_gain
initgain_backup
;
1110
u8
DefaultInitialGain
[4];
1111
// For EDCA Turbo mode, Added by amy 080515.
1112
bool
bis_any_nonbepkts
;
1113
bool
bcurrent_turbo_EDCA
;
1114
bool
bis_cur_rdlstate
;
1115
struct
timer_list
fsync_timer
;
1116
bool
bfsync_processing
;
// 500ms Fsync timer is active or not
1117
u32
rate_record
;
1118
u32
rateCountDiffRecord
;
1119
u32
ContinueDiffCount
;
1120
bool
bswitch_fsync
;
1121
1122
u8
framesync
;
1123
u32
framesyncC34
;
1124
u8
framesyncMonitor
;
1125
//Added by amy 080516 for RX related
1126
u16
nrxAMPDU_size
;
1127
u8
nrxAMPDU_aggr_num
;
1128
1129
//by amy for gpio
1130
bool
bHwRadioOff
;
1131
1132
//by amy for reset_count
1133
u32
reset_count
;
1134
bool
bpbc_pressed
;
1135
//by amy for debug
1136
u32
txpower_checkcnt
;
1137
u32
txpower_tracking_callback_cnt
;
1138
u8
thermal_read_val
[40];
1139
u8
thermal_readback_index
;
1140
u32
ccktxpower_adjustcnt_not_ch14
;
1141
u32
ccktxpower_adjustcnt_ch14
;
1142
u8
tx_fwinfo_force_subcarriermode
;
1143
u8
tx_fwinfo_force_subcarrierval
;
1144
//by amy for silent reset
1145
RESET_TYPE
ResetProgress
;
1146
bool
bForcedSilentReset
;
1147
bool
bDisableNormalResetCheck
;
1148
u16
TxCounter
;
1149
u16
RxCounter
;
1150
int
IrpPendingCount
;
1151
bool
bResetInProgress
;
1152
bool
force_reset
;
1153
u8
InitialGainOperateType
;
1154
1155
u16
SifsTime
;
1156
1157
//define work item by amy 080526
1158
1159
struct
delayed_work
update_beacon_wq
;
1160
struct
delayed_work
watch_dog_wq
;
1161
struct
delayed_work
txpower_tracking_wq
;
1162
struct
delayed_work
rfpath_check_wq
;
1163
struct
delayed_work
gpio_change_rf_wq
;
1164
struct
delayed_work
initialgain_operate_wq
;
1165
struct
workqueue_struct
*
priv_wq
;
1166
}
r8192_priv
;
1167
1168
// for rtl8187
1169
// now mirging to rtl8187B
1170
/*
1171
typedef enum{
1172
LOW_PRIORITY = 0x02,
1173
NORM_PRIORITY
1174
} priority_t;
1175
*/
1176
//for rtl8187B
1177
typedef
enum
{
1178
BULK_PRIORITY
= 0x01,
1179
//RSVD0,
1180
//RSVD1,
1181
LOW_PRIORITY
,
1182
NORM_PRIORITY
,
1183
VO_PRIORITY
,
1184
VI_PRIORITY
,
//0x05
1185
BE_PRIORITY
,
1186
BK_PRIORITY
,
1187
RSVD2
,
1188
RSVD3
,
1189
BEACON_PRIORITY
,
//0x0A
1190
HIGH_PRIORITY
,
1191
MANAGE_PRIORITY
,
1192
RSVD4
,
1193
RSVD5
,
1194
UART_PRIORITY
//0x0F
1195
}
priority_t
;
1196
1197
typedef
enum
{
1198
NIC_8192U
= 1,
1199
NIC_8190P
= 2,
1200
NIC_8192E
= 3,
1201
}
nic_t
;
1202
1203
1204
#ifdef JOHN_HWSEC
1205
struct
ssid_thread {
1206
struct
net_device
*
dev
;
1207
u8
name
[
IW_ESSID_MAX_SIZE
+ 1];
1208
};
1209
#endif
1210
1211
bool
init_firmware
(
struct
net_device
*
dev
);
1212
short
rtl819xU_tx_cmd
(
struct
net_device
*
dev
,
struct
sk_buff
*
skb
);
1213
short
rtl8192_tx
(
struct
net_device
*
dev
,
struct
sk_buff
*
skb
);
1214
1215
u32
read_cam
(
struct
net_device
*
dev
,
u8
addr
);
1216
void
write_cam
(
struct
net_device
*
dev
,
u8
addr
,
u32
data
);
1217
1218
u8
read_nic_byte
(
struct
net_device
*
dev
,
int
x
);
1219
u8
read_nic_byte_E
(
struct
net_device
*
dev
,
int
x
);
1220
u32
read_nic_dword
(
struct
net_device
*
dev
,
int
x
);
1221
u16
read_nic_word
(
struct
net_device
*
dev
,
int
x
) ;
1222
void
write_nic_byte
(
struct
net_device
*
dev
,
int
x
,
u8
y
);
1223
void
write_nic_byte_E
(
struct
net_device
*
dev
,
int
x
,
u8
y
);
1224
void
write_nic_word
(
struct
net_device
*
dev
,
int
x
,
u16
y
);
1225
void
write_nic_dword
(
struct
net_device
*
dev
,
int
x
,
u32
y
);
1226
void
force_pci_posting
(
struct
net_device
*
dev
);
1227
1228
void
rtl8192_rtx_disable
(
struct
net_device
*);
1229
void
rtl8192_rx_enable
(
struct
net_device
*);
1230
void
rtl8192_tx_enable
(
struct
net_device
*);
1231
1232
void
rtl8192_disassociate
(
struct
net_device
*
dev
);
1233
//void fix_rx_fifo(struct net_device *dev);
1234
void
rtl8185_set_rf_pins_enable
(
struct
net_device
*
dev
,
u32
a
);
1235
1236
void
rtl8192_set_anaparam
(
struct
net_device
*
dev
,
u32
a
);
1237
void
rtl8185_set_anaparam2
(
struct
net_device
*
dev
,
u32
a
);
1238
void
rtl8192_update_msr
(
struct
net_device
*
dev
);
1239
int
rtl8192_down
(
struct
net_device
*
dev
);
1240
int
rtl8192_up
(
struct
net_device
*
dev
);
1241
void
rtl8192_commit
(
struct
net_device
*
dev
);
1242
void
rtl8192_set_chan
(
struct
net_device
*
dev
,
short
ch);
1243
void
write_phy
(
struct
net_device
*
dev
,
u8
adr,
u8
data
);
1244
void
write_phy_cck
(
struct
net_device
*
dev
,
u8
adr,
u32
data
);
1245
void
write_phy_ofdm
(
struct
net_device
*
dev
,
u8
adr,
u32
data
);
1246
void
rtl8185_tx_antenna
(
struct
net_device
*
dev
,
u8
ant);
1247
void
rtl8192_set_rxconf
(
struct
net_device
*
dev
);
1248
//short check_nic_enough_desc(struct net_device *dev, priority_t priority);
1249
extern
void
rtl819xusb_beacon_tx
(
struct
net_device
*
dev
,
u16
tx_rate);
1250
1251
void
EnableHWSecurityConfig8192
(
struct
net_device
*
dev
);
1252
void
setKey
(
struct
net_device
*
dev
,
u8
EntryNo,
u8
KeyIndex,
u16
KeyType,
u8
*MacAddr,
u8
DefaultKey,
u32
*KeyContent );
1253
1254
1255
#endif
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1.8.2