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s3c244x.c
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1 /* linux/arch/arm/plat-s3c24xx/s3c244x.c
2  *
3  * Copyright (c) 2004-2006 Simtec Electronics
4  * Ben Dooks <[email protected]>
5  *
6  * Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11 */
12 
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/serial_core.h>
20 #include <linux/platform_device.h>
21 #include <linux/device.h>
22 #include <linux/syscore_ops.h>
23 #include <linux/clk.h>
24 #include <linux/io.h>
25 
26 #include <asm/system_misc.h>
27 #include <asm/mach/arch.h>
28 #include <asm/mach/map.h>
29 #include <asm/mach/irq.h>
30 
31 #include <mach/hardware.h>
32 #include <asm/irq.h>
33 
34 #include <plat/cpu-freq.h>
35 
36 #include <mach/regs-clock.h>
37 #include <plat/regs-serial.h>
38 #include <mach/regs-gpio.h>
39 #include <mach/regs-dsc.h>
40 
41 #include <plat/s3c2410.h>
42 #include <plat/s3c244x.h>
43 #include <plat/clock.h>
44 #include <plat/devs.h>
45 #include <plat/cpu.h>
46 #include <plat/pm.h>
47 #include <plat/pll.h>
48 #include <plat/nand-core.h>
49 #include <plat/watchdog-reset.h>
50 
51 static struct map_desc s3c244x_iodesc[] __initdata = {
52  IODESC_ENT(CLKPWR),
55 };
56 
57 /* uart initialisation */
58 
60 {
61  s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
62 }
63 
65 {
66  /* register our io-tables */
67 
68  iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
69 
70  /* rename any peripherals used differing from the s3c2410 */
71 
72  s3c_device_sdi.name = "s3c2440-sdi";
73  s3c_device_i2c0.name = "s3c2440-i2c";
74  s3c_nand_setname("s3c2440-nand");
75  s3c_device_ts.name = "s3c2440-ts";
76  s3c_device_usbgadget.name = "s3c2440-usbgadget";
77 }
78 
80 {
81  struct clk *xtal_clk;
82  unsigned long clkdiv;
83  unsigned long camdiv;
84  unsigned long xtal;
85  unsigned long hclk, fclk, pclk;
86  int hdiv = 1;
87 
88  xtal_clk = clk_get(NULL, "xtal");
89  xtal = clk_get_rate(xtal_clk);
90  clk_put(xtal_clk);
91 
92  fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
93 
94  clkdiv = __raw_readl(S3C2410_CLKDIVN);
95  camdiv = __raw_readl(S3C2440_CAMDIVN);
96 
97  /* work out clock scalings */
98 
99  switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
100  case S3C2440_CLKDIVN_HDIVN_1:
101  hdiv = 1;
102  break;
103 
104  case S3C2440_CLKDIVN_HDIVN_2:
105  hdiv = 2;
106  break;
107 
108  case S3C2440_CLKDIVN_HDIVN_4_8:
109  hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
110  break;
111 
112  case S3C2440_CLKDIVN_HDIVN_3_6:
113  hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
114  break;
115  }
116 
117  hclk = fclk / hdiv;
118  pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
119 
120  /* print brief summary of clocks, etc */
121 
122  printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
123  print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
124 
125  s3c24xx_setup_clocks(fclk, hclk, pclk);
126 }
127 
129 {
130  /* initialise the clocks here, to allow other things like the
131  * console to use them, and to add new ones after the initialisation
132  */
133 
137 }
138 
139 /* Since the S3C2442 and S3C2440 share items, put both subsystems here */
140 
142  .name = "s3c2440-core",
143  .dev_name = "s3c2440-core",
144 };
145 
147  .name = "s3c2442-core",
148  .dev_name = "s3c2442-core",
149 };
150 
151 /* need to register the subsystem before we actually register the device, and
152  * we also need to ensure that it has been initialised before any of the
153  * drivers even try to use it (even if not on an s3c2440 based system)
154  * as a driver which may support both 2410 and 2440 may try and use it.
155 */
156 
157 static int __init s3c2440_core_init(void)
158 {
159  return subsys_system_register(&s3c2440_subsys, NULL);
160 }
161 
162 core_initcall(s3c2440_core_init);
163 
164 static int __init s3c2442_core_init(void)
165 {
166  return subsys_system_register(&s3c2442_subsys, NULL);
167 }
168 
169 core_initcall(s3c2442_core_init);
170 
171 
172 #ifdef CONFIG_PM
173 static struct sleep_save s3c244x_sleep[] = {
174  SAVE_ITEM(S3C2440_DSC0),
175  SAVE_ITEM(S3C2440_DSC1),
179 };
180 
181 static int s3c244x_suspend(void)
182 {
183  s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
184  return 0;
185 }
186 
187 static void s3c244x_resume(void)
188 {
189  s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
190 }
191 #else
192 #define s3c244x_suspend NULL
193 #define s3c244x_resume NULL
194 #endif
195 
197  .suspend = s3c244x_suspend,
198  .resume = s3c244x_resume,
199 };
200 
201 void s3c244x_restart(char mode, const char *cmd)
202 {
203  if (mode == 's')
204  soft_restart(0);
205 
206  arch_wdt_reset();
207 
208  /* we'll take a jump through zero as a poor second */
209  soft_restart(0);
210 }