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sun4d_smp.c
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1 /* Sparc SS1000/SC2000 SMP support.
2  *
3  * Copyright (C) 1998 Jakub Jelinek ([email protected])
4  *
5  * Based on sun4m's smp.c, which is:
6  * Copyright (C) 1996 David S. Miller ([email protected])
7  */
8 
9 #include <linux/clockchips.h>
10 #include <linux/interrupt.h>
11 #include <linux/profile.h>
12 #include <linux/delay.h>
13 #include <linux/sched.h>
14 #include <linux/cpu.h>
15 
16 #include <asm/cacheflush.h>
17 #include <asm/switch_to.h>
18 #include <asm/tlbflush.h>
19 #include <asm/timer.h>
20 #include <asm/oplib.h>
21 #include <asm/sbi.h>
22 #include <asm/mmu.h>
23 
24 #include "kernel.h"
25 #include "irq.h"
26 
27 #define IRQ_CROSS_CALL 15
28 
29 static volatile int smp_processors_ready;
30 static int smp_highest_cpu;
31 
32 static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
33 {
34  __asm__ __volatile__("swap [%1], %0\n\t" :
35  "=&r" (val), "=&r" (ptr) :
36  "0" (val), "1" (ptr));
37  return val;
38 }
39 
40 static void smp4d_ipi_init(void);
41 
42 static unsigned char cpu_leds[32];
43 
44 static inline void show_leds(int cpuid)
45 {
46  cpuid &= 0x1e;
47  __asm__ __volatile__ ("stba %0, [%1] %2" : :
48  "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
49  "r" (ECSR_BASE(cpuid) | BB_LEDS),
50  "i" (ASI_M_CTL));
51 }
52 
54 {
55  int cpuid = hard_smp_processor_id();
56  unsigned long flags;
57 
58  /* Show we are alive */
59  cpu_leds[cpuid] = 0x6;
60  show_leds(cpuid);
61 
62  /* Enable level15 interrupt, disable level14 interrupt for now */
63  cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000);
64 
65  local_ops->cache_all();
66  local_ops->tlb_all();
67 
68  notify_cpu_starting(cpuid);
69  /*
70  * Unblock the master CPU _only_ when the scheduler state
71  * of all secondary CPUs will be up-to-date, so after
72  * the SMP initialization the master will be just allowed
73  * to call the scheduler code.
74  */
75  /* Get our local ticker going. */
76  register_percpu_ce(cpuid);
77 
79  smp_store_cpu_info(cpuid);
80  local_ops->cache_all();
81  local_ops->tlb_all();
82 
83  /* Allow master to continue. */
84  sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
85  local_ops->cache_all();
86  local_ops->tlb_all();
87 
88  while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
89  barrier();
90 
91  while (current_set[cpuid]->cpu != cpuid)
92  barrier();
93 
94  /* Fix idle thread fields. */
95  __asm__ __volatile__("ld [%0], %%g6\n\t"
96  : : "r" (&current_set[cpuid])
97  : "memory" /* paranoid */);
98 
99  cpu_leds[cpuid] = 0x9;
100  show_leds(cpuid);
101 
102  /* Attach to the address space of init_task. */
103  atomic_inc(&init_mm.mm_count);
104  current->active_mm = &init_mm;
105 
106  local_ops->cache_all();
107  local_ops->tlb_all();
108 
109  local_irq_enable(); /* We don't allow PIL 14 yet */
110 
111  while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
112  barrier();
113 
114  spin_lock_irqsave(&sun4d_imsk_lock, flags);
115  cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
116  spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
117  set_cpu_online(cpuid, true);
118 
119 }
120 
121 /*
122  * Cycle through the processors asking the PROM to start each one.
123  */
125 {
126  smp4d_ipi_init();
127  if (boot_cpu_id)
128  current_set[0] = NULL;
129  local_ops->cache_all();
130 }
131 
133 {
134  unsigned long *entry = &sun4d_cpu_startup;
135  int timeout;
136  int cpu_node;
137 
138  cpu_find_by_instance(i, &cpu_node, NULL);
139  current_set[i] = task_thread_info(idle);
140  /*
141  * Initialize the contexts table
142  * Since the call to prom_startcpu() trashes the structure,
143  * we need to re-initialize it for each cpu
144  */
145  smp_penguin_ctable.which_io = 0;
146  smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
147  smp_penguin_ctable.reg_size = 0;
148 
149  /* whirrr, whirrr, whirrrrrrrrr... */
150  printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
151  local_ops->cache_all();
152  prom_startcpu(cpu_node,
153  &smp_penguin_ctable, 0, (char *)entry);
154 
155  printk(KERN_INFO "prom_startcpu returned :)\n");
156 
157  /* wheee... it's going... */
158  for (timeout = 0; timeout < 10000; timeout++) {
159  if (cpu_callin_map[i])
160  break;
161  udelay(200);
162  }
163 
164  if (!(cpu_callin_map[i])) {
165  printk(KERN_ERR "Processor %d is stuck.\n", i);
166  return -ENODEV;
167 
168  }
169  local_ops->cache_all();
170  return 0;
171 }
172 
174 {
175  int i, first;
176  int *prev;
177 
178  /* setup cpu list for irq rotation */
179  first = 0;
180  prev = &first;
182  *prev = i;
183  prev = &cpu_data(i).next;
184  }
185  *prev = first;
186  local_ops->cache_all();
187 
188  /* Ok, they are spinning and ready to go. */
189  smp_processors_ready = 1;
190  sun4d_distribute_irqs();
191 }
192 
193 /* Memory structure giving interrupt handler information about IPI generated */
195  int single;
196  int msk;
197  int resched;
198 };
199 
201 
202 /* Initialize IPIs on the SUN4D SMP machine */
203 static void __init smp4d_ipi_init(void)
204 {
205  int cpu;
206  struct sun4d_ipi_work *work;
207 
208  printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ);
209 
210  for_each_possible_cpu(cpu) {
211  work = &per_cpu(sun4d_ipi_work, cpu);
212  work->single = work->msk = work->resched = 0;
213  }
214 }
215 
217 {
219 
220  if (work->single) {
221  work->single = 0;
223  }
224  if (work->msk) {
225  work->msk = 0;
227  }
228  if (work->resched) {
229  work->resched = 0;
231  }
232 }
233 
234 /* +-------+-------------+-----------+------------------------------------+
235  * | bcast | devid | sid | levels mask |
236  * +-------+-------------+-----------+------------------------------------+
237  * 31 30 23 22 15 14 0
238  */
239 #define IGEN_MESSAGE(bcast, devid, sid, levels) \
240  (((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))
241 
242 static void sun4d_send_ipi(int cpu, int level)
243 {
244  cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1)));
245 }
246 
247 static void sun4d_ipi_single(int cpu)
248 {
249  struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
250 
251  /* Mark work */
252  work->single = 1;
253 
254  /* Generate IRQ on the CPU */
255  sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
256 }
257 
258 static void sun4d_ipi_mask_one(int cpu)
259 {
260  struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
261 
262  /* Mark work */
263  work->msk = 1;
264 
265  /* Generate IRQ on the CPU */
266  sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
267 }
268 
269 static void sun4d_ipi_resched(int cpu)
270 {
271  struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
272 
273  /* Mark work */
274  work->resched = 1;
275 
276  /* Generate IRQ on the CPU (any IRQ will cause resched) */
277  sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
278 }
279 
280 static struct smp_funcall {
281  smpfunc_t func;
282  unsigned long arg1;
283  unsigned long arg2;
284  unsigned long arg3;
285  unsigned long arg4;
286  unsigned long arg5;
287  unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */
288  unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
289 } ccall_info __attribute__((aligned(8)));
291 static DEFINE_SPINLOCK(cross_call_lock);
293 /* Cross calls must be serialized, at least currently. */
294 static void sun4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
295  unsigned long arg2, unsigned long arg3,
296  unsigned long arg4)
297 {
298  if (smp_processors_ready) {
299  register int high = smp_highest_cpu;
300  unsigned long flags;
301 
302  spin_lock_irqsave(&cross_call_lock, flags);
303 
304  {
305  /*
306  * If you make changes here, make sure
307  * gcc generates proper code...
308  */
309  register smpfunc_t f asm("i0") = func;
310  register unsigned long a1 asm("i1") = arg1;
311  register unsigned long a2 asm("i2") = arg2;
312  register unsigned long a3 asm("i3") = arg3;
313  register unsigned long a4 asm("i4") = arg4;
314  register unsigned long a5 asm("i5") = 0;
315 
316  __asm__ __volatile__(
317  "std %0, [%6]\n\t"
318  "std %2, [%6 + 8]\n\t"
319  "std %4, [%6 + 16]\n\t" : :
320  "r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
321  "r" (&ccall_info.func));
322  }
323 
324  /* Init receive/complete mapping, plus fire the IPI's off. */
325  {
326  register int i;
327 
328  cpumask_clear_cpu(smp_processor_id(), &mask);
329  cpumask_and(&mask, cpu_online_mask, &mask);
330  for (i = 0; i <= high; i++) {
331  if (cpumask_test_cpu(i, &mask)) {
332  ccall_info.processors_in[i] = 0;
333  ccall_info.processors_out[i] = 0;
334  sun4d_send_ipi(i, IRQ_CROSS_CALL);
335  }
336  }
337  }
338 
339  {
340  register int i;
341 
342  i = 0;
343  do {
344  if (!cpumask_test_cpu(i, &mask))
345  continue;
346  while (!ccall_info.processors_in[i])
347  barrier();
348  } while (++i <= high);
349 
350  i = 0;
351  do {
352  if (!cpumask_test_cpu(i, &mask))
353  continue;
354  while (!ccall_info.processors_out[i])
355  barrier();
356  } while (++i <= high);
357  }
358 
359  spin_unlock_irqrestore(&cross_call_lock, flags);
360  }
361 }
362 
363 /* Running cross calls. */
365 {
366  int i = hard_smp_processor_id();
367 
368  ccall_info.processors_in[i] = 1;
369  ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
370  ccall_info.arg4, ccall_info.arg5);
371  ccall_info.processors_out[i] = 1;
372 }
373 
375 {
376  struct pt_regs *old_regs;
377  int cpu = hard_smp_processor_id();
378  struct clock_event_device *ce;
379  static int cpu_tick[NR_CPUS];
380  static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };
381 
382  old_regs = set_irq_regs(regs);
383  bw_get_prof_limit(cpu);
384  bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */
385 
386  cpu_tick[cpu]++;
387  if (!(cpu_tick[cpu] & 15)) {
388  if (cpu_tick[cpu] == 0x60)
389  cpu_tick[cpu] = 0;
390  cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
391  show_leds(cpu);
392  }
393 
394  ce = &per_cpu(sparc32_clockevent, cpu);
395 
396  irq_enter();
397  ce->event_handler(ce);
398  irq_exit();
399 
400  set_irq_regs(old_regs);
401 }
402 
403 static const struct sparc32_ipi_ops sun4d_ipi_ops = {
404  .cross_call = sun4d_cross_call,
405  .resched = sun4d_ipi_resched,
406  .single = sun4d_ipi_single,
407  .mask_one = sun4d_ipi_mask_one,
408 };
409 
411 {
412  int i;
413 
414  /* Patch ipi15 trap table */
415  t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);
416 
417  sparc32_ipi_ops = &sun4d_ipi_ops;
418 
419  for (i = 0; i < NR_CPUS; i++) {
420  ccall_info.processors_in[i] = 1;
421  ccall_info.processors_out[i] = 1;
422  }
423 }