tegra20_clocks_data.c File Reference

#include <linux/clk-private.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <mach/iomap.h>
#include "clock.h"
#include "fuse.h"
#include "tegra2_emc.h"
#include "tegra20_clocks.h"
#include "tegra_cpu_car.h"

Go to the source code of this file.

Data Structures
struct	audio_sources

Macros
#define	DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,_parent_names, _parents, _parent)
#define	DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, _input_max, _cf_min, _cf_max, _vco_min, _vco_max, _freq_table, _lock_delay, _ops, _fixed_rate, _parent)
#define	DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift,_max_rate, _ops, _parent, _clk_flags)
#define	PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags)
#define	CLK_DUPLICATE(_name, _dev, _con)
#define	CLK(dev, con, ck)

Functions
	DEFINE_PLL (pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0, 0, 12000000, 26000000, tegra_pll_s_freq_table, 300, tegra_pll_ops, 0, clk_32k)
	DEFINE_PLL (pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300, tegra_pll_ops, 0, clk_m)
	DEFINE_PLL_OUT (pll_c_out1, DIV_U71, 0x84, 0, 600000000, tegra_pll_div_ops, pll_c, 0)
	DEFINE_PLL (pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300, tegra_pll_ops, 0, clk_m)
	DEFINE_PLL_OUT (pll_m_out1, DIV_U71, 0x94, 0, 600000000, tegra_pll_div_ops, pll_m, 0)
	DEFINE_PLL (pll_p, ENABLE_ON_INIT|PLL_FIXED|PLL_HAS_CPCON, 0xa0, 432000000, 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000, tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m)
	DEFINE_PLL_OUT (pll_p_out1, ENABLE_ON_INIT|DIV_U71|DIV_U71_FIXED, 0xa4, 0, 432000000, tegra_pll_div_ops, pll_p, 0)
	DEFINE_PLL_OUT (pll_p_out2, ENABLE_ON_INIT|DIV_U71|DIV_U71_FIXED, 0xa4, 16, 432000000, tegra_pll_div_ops, pll_p, 0)
	DEFINE_PLL_OUT (pll_p_out3, ENABLE_ON_INIT|DIV_U71|DIV_U71_FIXED, 0xa8, 0, 432000000, tegra_pll_div_ops, pll_p, 0)
	DEFINE_PLL_OUT (pll_p_out4, ENABLE_ON_INIT|DIV_U71|DIV_U71_FIXED, 0xa8, 16, 432000000, tegra_pll_div_ops, pll_p, 0)
	DEFINE_PLL (pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300, tegra_pll_ops, 0, pll_p_out1)
	DEFINE_PLL_OUT (pll_a_out0, DIV_U71, 0xb4, 0, 73728000, tegra_pll_div_ops, pll_a, 0)
	DEFINE_PLL (pll_d, PLL_HAS_CPCON|PLLD, 0xd0, 1000000000, 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table, 1000, tegra_pll_ops, 0, clk_m)
	DEFINE_PLL_OUT (pll_d_out0, DIV_2|PLLD, 0, 0, 500000000, tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT)
	DEFINE_PLL (pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table, 1000, tegra_pll_ops, 0, clk_m)
	DEFINE_PLL (pll_x, PLL_HAS_CPCON|PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000, 31000000, 1000000, 6000000, 20000000, 1200000000, tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m)
	DEFINE_PLL (pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0, 0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m)
	DEFINE_CLK_TEGRA (audio, 0,&tegra_audio_sync_clk_ops, 0, audio_parent_names, audio_parents, NULL)
	DEFINE_CLK_TEGRA (audio_2x, 0,&tegra_clk_double_ops, 0, audio_2x_parent_names, audio_2x_parents,&tegra_audio)
	DEFINE_CLK_TEGRA (cclk, 0,&tegra_super_ops, 0, mux_cclk, mux_cclk_p, NULL)
	DEFINE_CLK_TEGRA (sclk, 0,&tegra_super_ops, 0, mux_sclk, mux_sclk_p, NULL)
	DEFINE_CLK_TEGRA (cop, 0,&tegra_cop_ops, CLK_SET_RATE_PARENT, tegra_cop_parent_names, tegra_cop_parents,&tegra_sclk)
	DEFINE_CLK_TEGRA (hclk, 0,&tegra_bus_ops, 0, tegra_hclk_parent_names, tegra_hclk_parents,&tegra_sclk)
	DEFINE_CLK_TEGRA (pclk, 0,&tegra_bus_ops, 0, tegra_pclk_parent_names, tegra_pclk_parents,&tegra_hclk)
	DEFINE_CLK_TEGRA (blink, 0,&tegra_blink_clk_ops, 0, tegra_blink_parent_names, tegra_blink_parents,&tegra_clk_32k)
	DEFINE_CLK_TEGRA (emc, 0,&tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm, mux_pllm_pllc_pllp_clkm_p, NULL)
	PERIPH_CLK (apbdma,"tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0)
	PERIPH_CLK (rtc,"rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET)
	PERIPH_CLK (timer,"timer", NULL, 5, 0, 26000000, mux_clk_m, 0)
	PERIPH_CLK (i2s1,"tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX|DIV_U71)
	PERIPH_CLK (i2s2,"tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX|DIV_U71)
	PERIPH_CLK (spdif_out,"spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX|DIV_U71)
	PERIPH_CLK (spdif_in,"spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX|DIV_U71)
	PERIPH_CLK (pwm,"tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX|DIV_U71|MUX_PWM)
	PERIPH_CLK (spi,"spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (xio,"xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (twc,"twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (sbc1,"spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (sbc2,"spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (sbc3,"spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (sbc4,"spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (ide,"ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (ndflash,"tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (vfir,"vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (sdmmc1,"sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (sdmmc2,"sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (sdmmc3,"sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (sdmmc4,"sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (vcp,"tegra-avp","vcp", 29, 0, 250000000, mux_clk_m, 0)
	PERIPH_CLK (bsea,"tegra-avp","bsea", 62, 0, 250000000, mux_clk_m, 0)
	PERIPH_CLK (bsev,"tegra-aes","bsev", 63, 0, 250000000, mux_clk_m, 0)
	PERIPH_CLK (vde,"tegra-avp","vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (csite,"csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (la,"la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (owr,"tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (nor,"nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (mipi,"mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
	PERIPH_CLK (i2c1,"tegra-i2c.0","div-clk", 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U16)
	PERIPH_CLK (i2c2,"tegra-i2c.1","div-clk", 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U16)
	PERIPH_CLK (i2c3,"tegra-i2c.2","div-clk", 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U16)
	PERIPH_CLK (dvc,"tegra-i2c.3","div-clk", 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U16)
	PERIPH_CLK (uarta,"tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX)
	PERIPH_CLK (uartb,"tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX)
	PERIPH_CLK (uartc,"tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX)
	PERIPH_CLK (uartd,"tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX)
	PERIPH_CLK (uarte,"tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX)
	PERIPH_CLK (3d,"3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71|PERIPH_MANUAL_RESET)
	PERIPH_CLK (2d,"2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71)
	PERIPH_CLK (vi,"tegra_camera","vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71)
	PERIPH_CLK (vi_sensor,"tegra_camera","vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71|PERIPH_NO_RESET)
	PERIPH_CLK (epp,"epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71)
	PERIPH_CLK (mpe,"mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71)
	PERIPH_CLK (host1x,"host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71)
	PERIPH_CLK (cve,"cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX|DIV_U71)
	PERIPH_CLK (tvo,"tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX|DIV_U71)
	PERIPH_CLK (hdmi,"hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX|DIV_U71)
	PERIPH_CLK (tvdac,"tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX|DIV_U71)
	PERIPH_CLK (disp1,"tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX)
	PERIPH_CLK (disp2,"tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX)
	PERIPH_CLK (usbd,"fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0)
	PERIPH_CLK (usb2,"tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0)
	PERIPH_CLK (usb3,"tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0)
	PERIPH_CLK (dsi,"dsi", NULL, 48, 0, 500000000, mux_plld, 0)
	PERIPH_CLK (csi,"tegra_camera","csi", 52, 0, 72000000, mux_pllp_out3, 0)
	PERIPH_CLK (isp,"tegra_camera","isp", 23, 0, 150000000, mux_clk_m, 0)
	PERIPH_CLK (csus,"tegra_camera","csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET)
	PERIPH_CLK (pex, NULL,"pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET)
	PERIPH_CLK (afi, NULL,"afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET)
	PERIPH_CLK (pcie_xclk, NULL,"pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET)
void __init	tegra2_init_clocks (void)

Macro Definition Documentation

#define CLK	(		dev,
			con,
			ck
	)

Value:

{           \
        .dev_id = dev,  \
        .con_id = con,  \
        .clk    = ck,   \
    }

Definition at line 1058 of file tegra20_clocks_data.c.

#define CLK_DUPLICATE	(		_name,
			_dev,
			_con
	)

Value:

{                   \
        .name   = _name,        \
        .lookup = {         \
            .dev_id = _dev,     \
            .con_id = _con,     \
        },              \
    }

Definition at line 1019 of file tegra20_clocks_data.c.

#define DEFINE_CLK_TEGRA	(		_name,
			_rate,
			_ops,
			_flags,
			_parent_names,
			_parents,
			_parent
	)

Value:

static struct clk tegra_##_name = {         \
        .hw = &tegra_##_name##_hw.hw,           \
        .name = #_name,                 \
        .rate = _rate,                  \
        .ops = _ops,                    \
        .flags = _flags,                \
        .parent_names = _parent_names,          \
        .parents = _parents,                \
        .num_parents = ARRAY_SIZE(_parent_names),   \
        .parent = _parent,              \
    };

Definition at line 40 of file tegra20_clocks_data.c.

#define DEFINE_PLL	(		_name,
			_flags,
			_reg,
			_max_rate,
			_input_min,
			_input_max,
			_cf_min,
			_cf_max,
			_vco_min,
			_vco_max,
			_freq_table,
			_lock_delay,
			_ops,
			_fixed_rate,
			_parent
	)

Definition at line 89 of file tegra20_clocks_data.c.

#define DEFINE_PLL_OUT	(		_name,
			_flags,
			_reg,
			_reg_shift,
			_max_rate,
			_ops,
			_parent,
			_clk_flags
	)

Value:

static const char *tegra_##_name##_parent_names[] = {   \
        #_parent,                   \
    };                          \
    static struct clk *tegra_##_name##_parents[] = {    \
        &tegra_##_parent,               \
    };                          \
    static struct clk tegra_##_name;            \
    static struct clk_tegra tegra_##_name##_hw = {      \
        .hw = {                     \
            .clk = &tegra_##_name,          \
        },                      \
        .flags = _flags,                \
        .reg = _reg,                    \
        .max_rate = _max_rate,              \
        .reg_shift = _reg_shift,            \
    };                          \
    static struct clk tegra_##_name = {         \
        .name = #_name,                 \
        .ops = &tegra_pll_div_ops,          \
        .hw = &tegra_##_name##_hw.hw,           \
        .parent = &tegra_##_parent,         \
        .parent_names = tegra_##_name##_parent_names,   \
        .parents = tegra_##_name##_parents,     \
        .num_parents = 1,               \
        .flags = _clk_flags,                \
    };

Definition at line 129 of file tegra20_clocks_data.c.

#define PERIPH_CLK	(		_name,
			_dev,
			_con,
			_clk_num,
			_reg,
			_max,
			_inputs,
			_flags
	)

Value:

static struct clk tegra_##_name;        \
    static struct clk_tegra tegra_##_name##_hw = {  \
        .hw = {                 \
            .clk = &tegra_##_name,      \
        },                  \
        .lookup = {             \
            .dev_id = _dev,         \
            .con_id = _con,         \
        },                  \
        .reg = _reg,                \
        .flags = _flags,            \
        .max_rate = _max,           \
        .u.periph = {               \
            .clk_num = _clk_num,        \
        },                  \
        .reset = tegra2_periph_clk_reset,   \
    };                      \
    static struct clk tegra_##_name = {     \
        .name = #_name,             \
        .ops = &tegra_periph_clk_ops,       \
        .hw = &tegra_##_name##_hw.hw,       \
        .parent_names = _inputs,        \
        .parents = _inputs##_p,         \
        .num_parents = ARRAY_SIZE(_inputs), \
    };

Definition at line 860 of file tegra20_clocks_data.c.

Function Documentation

DEFINE_CLK_TEGRA	(	audio	,
		0	,
		&	tegra_audio_sync_clk_ops,
		0	,
		audio_parent_names	,
		audio_parents	,
		NULL
	)

DEFINE_CLK_TEGRA	(	audio_2x	,
		0	,
		&	tegra_clk_double_ops,
		0	,
		audio_2x_parent_names	,
		audio_2x_parents	,
		&	tegra_audio
	)

DEFINE_CLK_TEGRA	(	cclk	,
		0	,
		&	tegra_super_ops,
		0	,
		mux_cclk	,
		mux_cclk_p	,
		NULL
	)

DEFINE_CLK_TEGRA	(	sclk	,
		0	,
		&	tegra_super_ops,
		0	,
		mux_sclk	,
		mux_sclk_p	,
		NULL
	)

DEFINE_CLK_TEGRA	(	cop	,
		0	,
		&	tegra_cop_ops,
		CLK_SET_RATE_PARENT	,
		tegra_cop_parent_names	,
		tegra_cop_parents	,
		&	tegra_sclk
	)

DEFINE_CLK_TEGRA	(	hclk	,
		0	,
		&	tegra_bus_ops,
		0	,
		tegra_hclk_parent_names	,
		tegra_hclk_parents	,
		&	tegra_sclk
	)

DEFINE_CLK_TEGRA	(	pclk	,
		0	,
		&	tegra_bus_ops,
		0	,
		tegra_pclk_parent_names	,
		tegra_pclk_parents	,
		&	tegra_hclk
	)

DEFINE_CLK_TEGRA	(	blink	,
		0	,
		&	tegra_blink_clk_ops,
		0	,
		tegra_blink_parent_names	,
		tegra_blink_parents	,
		&	tegra_clk_32k
	)

DEFINE_CLK_TEGRA	(	emc	,
		0	,
		&	tegra_emc_clk_ops,
		0	,
		mux_pllm_pllc_pllp_clkm	,
		mux_pllm_pllc_pllp_clkm_p	,
		NULL
	)

DEFINE_PLL	(	pll_s	,
		PLL_ALT_MISC_REG	,
		0xf0	,
		26000000	,
		32768	,
		32768	,
		0	,
		0	,
		12000000	,
		26000000	,
		tegra_pll_s_freq_table	,
		300	,
		tegra_pll_ops	,
		0	,
		clk_32k
	)

DEFINE_PLL	(	pll_c	,
		PLL_HAS_CPCON	,
		0x80	,
		600000000	,
		2000000	,
		31000000	,
		1000000	,
		6000000	,
		20000000	,
		1400000000	,
		tegra_pll_c_freq_table	,
		300	,
		tegra_pll_ops	,
		0	,
		clk_m
	)

DEFINE_PLL	(	pll_m	,
		PLL_HAS_CPCON	,
		0x90	,
		800000000	,
		2000000	,
		31000000	,
		1000000	,
		6000000	,
		20000000	,
		1200000000	,
		tegra_pll_m_freq_table	,
		300	,
		tegra_pll_ops	,
		0	,
		clk_m
	)

DEFINE_PLL	(	pll_p	,
		ENABLE_ON_INIT|PLL_FIXED|	PLL_HAS_CPCON,
		0xa0	,
		432000000	,
		2000000	,
		31000000	,
		1000000	,
		6000000	,
		20000000	,
		1400000000	,
		tegra_pll_p_freq_table	,
		300	,
		tegra_pll_ops	,
		216000000	,
		clk_m
	)

DEFINE_PLL	(	pll_a	,
		PLL_HAS_CPCON	,
		0xb0	,
		73728000	,
		2000000	,
		31000000	,
		1000000	,
		6000000	,
		20000000	,
		1400000000	,
		tegra_pll_a_freq_table	,
		300	,
		tegra_pll_ops	,
		0	,
		pll_p_out1
	)

DEFINE_PLL	(	pll_d	,
		PLL_HAS_CPCON|	PLLD,
		0xd0	,
		1000000000	,
		2000000	,
		40000000	,
		1000000	,
		6000000	,
		40000000	,
		1000000000	,
		tegra_pll_d_freq_table	,
		1000	,
		tegra_pll_ops	,
		0	,
		clk_m
	)

DEFINE_PLL	(	pll_u	,
		PLLU	,
		0xc0	,
		480000000	,
		2000000	,
		40000000	,
		1000000	,
		6000000	,
		48000000	,
		960000000	,
		tegra_pll_u_freq_table	,
		1000	,
		tegra_pll_ops	,
		0	,
		clk_m
	)

DEFINE_PLL	(	pll_x	,
		PLL_HAS_CPCON|	PLL_ALT_MISC_REG,
		0xe0	,
		1000000000	,
		2000000	,
		31000000	,
		1000000	,
		6000000	,
		20000000	,
		1200000000	,
		tegra_pll_x_freq_table	,
		300	,
		tegra_pllx_ops	,
		0	,
		clk_m
	)

DEFINE_PLL	(	pll_e	,
		PLL_ALT_MISC_REG	,
		0xe8	,
		100000000	,
		12000000	,
		12000000	,
		0	,
		0	,
		0	,
		0	,
		tegra_pll_e_freq_table	,
		0	,
		tegra_plle_ops	,
		0	,
		clk_m
	)

DEFINE_PLL_OUT	(	pll_c_out1	,
		DIV_U71	,
		0x84	,
		0	,
		600000000	,
		tegra_pll_div_ops	,
		pll_c	,
		0
	)

DEFINE_PLL_OUT	(	pll_m_out1	,
		DIV_U71	,
		0x94	,
		0	,
		600000000	,
		tegra_pll_div_ops	,
		pll_m	,
		0
	)

DEFINE_PLL_OUT	(	pll_p_out1	,
		ENABLE_ON_INIT|DIV_U71|	DIV_U71_FIXED,
		0xa4	,
		0	,
		432000000	,
		tegra_pll_div_ops	,
		pll_p	,
		0
	)

DEFINE_PLL_OUT	(	pll_p_out2	,
		ENABLE_ON_INIT|DIV_U71|	DIV_U71_FIXED,
		0xa4	,
		16	,
		432000000	,
		tegra_pll_div_ops	,
		pll_p	,
		0
	)

DEFINE_PLL_OUT	(	pll_p_out3	,
		ENABLE_ON_INIT|DIV_U71|	DIV_U71_FIXED,
		0xa8	,
		0	,
		432000000	,
		tegra_pll_div_ops	,
		pll_p	,
		0
	)

DEFINE_PLL_OUT	(	pll_p_out4	,
		ENABLE_ON_INIT|DIV_U71|	DIV_U71_FIXED,
		0xa8	,
		16	,
		432000000	,
		tegra_pll_div_ops	,
		pll_p	,
		0
	)

DEFINE_PLL_OUT	(	pll_a_out0	,
		DIV_U71	,
		0xb4	,
		0	,
		73728000	,
		tegra_pll_div_ops	,
		pll_a	,
		0
	)

DEFINE_PLL_OUT	(	pll_d_out0	,
		DIV_2|	PLLD,
		0	,
		0	,
		500000000	,
		tegra_pll_div_ops	,
		pll_d	,
		CLK_SET_RATE_PARENT
	)

PERIPH_CLK	(	apbdma	,
		"tegra-apbdma"	,
		NULL	,
		34	,
		0	,
		108000000	,
		mux_pclk	,
		0
	)

PERIPH_CLK	(	rtc	,
		"rtc-tegra"	,
		NULL	,
		4	,
		0	,
		32768	,
		mux_clk_32k	,
		PERIPH_NO_RESET
	)

PERIPH_CLK	(	timer	,
		"timer"	,
		NULL	,
		5	,
		0	,
		26000000	,
		mux_clk_m	,
		0
	)

PERIPH_CLK	(	i2s1	,
		"tegra20-i2s.0"	,
		NULL	,
		11	,
		0x100	,
		26000000	,
		mux_pllaout0_audio2x_pllp_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	i2s2	,
		"tegra20-i2s.1"	,
		NULL	,
		18	,
		0x104	,
		26000000	,
		mux_pllaout0_audio2x_pllp_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	spdif_out	,
		"spdif_out"	,
		NULL	,
		10	,
		0x108	,
		100000000	,
		mux_pllaout0_audio2x_pllp_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	spdif_in	,
		"spdif_in"	,
		NULL	,
		10	,
		0x10c	,
		100000000	,
		mux_pllp_pllc_pllm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	pwm	,
		"tegra-pwm"	,
		NULL	,
		17	,
		0x110	,
		432000000	,
		mux_pllp_pllc_audio_clkm_clk32	,
		MUX|DIV_U71|	MUX_PWM
	)

PERIPH_CLK	(	spi	,
		"spi"	,
		NULL	,
		43	,
		0x114	,
		40000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	xio	,
		"xio"	,
		NULL	,
		45	,
		0x120	,
		150000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	twc	,
		"twc"	,
		NULL	,
		16	,
		0x12c	,
		150000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	sbc1	,
		"spi_tegra.0"	,
		NULL	,
		41	,
		0x134	,
		160000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	sbc2	,
		"spi_tegra.1"	,
		NULL	,
		44	,
		0x118	,
		160000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	sbc3	,
		"spi_tegra.2"	,
		NULL	,
		46	,
		0x11c	,
		160000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	sbc4	,
		"spi_tegra.3"	,
		NULL	,
		68	,
		0x1b4	,
		160000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	ide	,
		"ide"	,
		NULL	,
		25	,
		0x144	,
		100000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	ndflash	,
		"tegra_nand"	,
		NULL	,
		13	,
		0x160	,
		164000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	vfir	,
		"vfir"	,
		NULL	,
		7	,
		0x168	,
		72000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	sdmmc1	,
		"sdhci-tegra.0"	,
		NULL	,
		14	,
		0x150	,
		52000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	sdmmc2	,
		"sdhci-tegra.1"	,
		NULL	,
		9	,
		0x154	,
		52000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	sdmmc3	,
		"sdhci-tegra.2"	,
		NULL	,
		69	,
		0x1bc	,
		52000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	sdmmc4	,
		"sdhci-tegra.3"	,
		NULL	,
		15	,
		0x164	,
		52000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	vcp	,
		"tegra-avp"	,
		"vcp"	,
		29	,
		0	,
		250000000	,
		mux_clk_m	,
		0
	)

PERIPH_CLK	(	bsea	,
		"tegra-avp"	,
		"bsea"	,
		62	,
		0	,
		250000000	,
		mux_clk_m	,
		0
	)

PERIPH_CLK	(	bsev	,
		"tegra-aes"	,
		"bsev"	,
		63	,
		0	,
		250000000	,
		mux_clk_m	,
		0
	)

PERIPH_CLK	(	vde	,
		"tegra-avp"	,
		"vde"	,
		61	,
		0x1c8	,
		250000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	csite	,
		"csite"	,
		NULL	,
		73	,
		0x1d4	,
		144000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	la	,
		"la"	,
		NULL	,
		76	,
		0x1f8	,
		26000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	owr	,
		"tegra_w1"	,
		NULL	,
		71	,
		0x1cc	,
		26000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	nor	,
		"nor"	,
		NULL	,
		42	,
		0x1d0	,
		92000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	mipi	,
		"mipi"	,
		NULL	,
		50	,
		0x174	,
		60000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	i2c1	,
		"tegra-i2c.0"	,
		"div-clk"	,
		12	,
		0x124	,
		26000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U16
	)

PERIPH_CLK	(	i2c2	,
		"tegra-i2c.1"	,
		"div-clk"	,
		54	,
		0x198	,
		26000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U16
	)

PERIPH_CLK	(	i2c3	,
		"tegra-i2c.2"	,
		"div-clk"	,
		67	,
		0x1b8	,
		26000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U16
	)

PERIPH_CLK	(	dvc	,
		"tegra-i2c.3"	,
		"div-clk"	,
		47	,
		0x128	,
		26000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX|	DIV_U16
	)

PERIPH_CLK	(	uarta	,
		"tegra-uart.0"	,
		NULL	,
		6	,
		0x178	,
		600000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX
	)

PERIPH_CLK	(	uartb	,
		"tegra-uart.1"	,
		NULL	,
		7	,
		0x17c	,
		600000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX
	)

PERIPH_CLK	(	uartc	,
		"tegra-uart.2"	,
		NULL	,
		55	,
		0x1a0	,
		600000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX
	)

PERIPH_CLK	(	uartd	,
		"tegra-uart.3"	,
		NULL	,
		65	,
		0x1c0	,
		600000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX
	)

PERIPH_CLK	(	uarte	,
		"tegra-uart.4"	,
		NULL	,
		66	,
		0x1c4	,
		600000000	,
		mux_pllp_pllc_pllm_clkm	,
		MUX
	)

PERIPH_CLK	(	3d	,
		"3d"	,
		NULL	,
		24	,
		0x158	,
		300000000	,
		mux_pllm_pllc_pllp_plla	,
		MUX|DIV_U71|	PERIPH_MANUAL_RESET
	)

PERIPH_CLK	(	2d	,
		"2d"	,
		NULL	,
		21	,
		0x15c	,
		300000000	,
		mux_pllm_pllc_pllp_plla	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	vi	,
		"tegra_camera"	,
		"vi"	,
		20	,
		0x148	,
		150000000	,
		mux_pllm_pllc_pllp_plla	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	vi_sensor	,
		"tegra_camera"	,
		"vi_sensor"	,
		20	,
		0x1a8	,
		150000000	,
		mux_pllm_pllc_pllp_plla	,
		MUX|DIV_U71|	PERIPH_NO_RESET
	)

PERIPH_CLK	(	epp	,
		"epp"	,
		NULL	,
		19	,
		0x16c	,
		300000000	,
		mux_pllm_pllc_pllp_plla	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	mpe	,
		"mpe"	,
		NULL	,
		60	,
		0x170	,
		250000000	,
		mux_pllm_pllc_pllp_plla	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	host1x	,
		"host1x"	,
		NULL	,
		28	,
		0x180	,
		166000000	,
		mux_pllm_pllc_pllp_plla	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	cve	,
		"cve"	,
		NULL	,
		49	,
		0x140	,
		250000000	,
		mux_pllp_plld_pllc_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	tvo	,
		"tvo"	,
		NULL	,
		49	,
		0x188	,
		250000000	,
		mux_pllp_plld_pllc_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	hdmi	,
		"hdmi"	,
		NULL	,
		51	,
		0x18c	,
		600000000	,
		mux_pllp_plld_pllc_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	tvdac	,
		"tvdac"	,
		NULL	,
		53	,
		0x194	,
		250000000	,
		mux_pllp_plld_pllc_clkm	,
		MUX|	DIV_U71
	)

PERIPH_CLK	(	disp1	,
		"tegradc.0"	,
		NULL	,
		27	,
		0x138	,
		600000000	,
		mux_pllp_plld_pllc_clkm	,
		MUX
	)

PERIPH_CLK	(	disp2	,
		"tegradc.1"	,
		NULL	,
		26	,
		0x13c	,
		600000000	,
		mux_pllp_plld_pllc_clkm	,
		MUX
	)

PERIPH_CLK	(	usbd	,
		"fsl-tegra-udc"	,
		NULL	,
		22	,
		0	,
		480000000	,
		mux_clk_m	,
		0
	)

PERIPH_CLK	(	usb2	,
		"tegra-ehci.1"	,
		NULL	,
		58	,
		0	,
		480000000	,
		mux_clk_m	,
		0
	)

PERIPH_CLK	(	usb3	,
		"tegra-ehci.2"	,
		NULL	,
		59	,
		0	,
		480000000	,
		mux_clk_m	,
		0
	)

PERIPH_CLK	(	dsi	,
		"dsi"	,
		NULL	,
		48	,
		0	,
		500000000	,
		mux_plld	,
		0
	)

PERIPH_CLK	(	csi	,
		"tegra_camera"	,
		"csi"	,
		52	,
		0	,
		72000000	,
		mux_pllp_out3	,
		0
	)

PERIPH_CLK	(	isp	,
		"tegra_camera"	,
		"isp"	,
		23	,
		0	,
		150000000	,
		mux_clk_m	,
		0
	)

PERIPH_CLK	(	csus	,
		"tegra_camera"	,
		"csus"	,
		92	,
		0	,
		150000000	,
		mux_clk_m	,
		PERIPH_NO_RESET
	)

PERIPH_CLK	(	pex	,
		NULL	,
		"pex"	,
		70	,
		0	,
		26000000	,
		mux_clk_m	,
		PERIPH_MANUAL_RESET
	)

PERIPH_CLK	(	afi	,
		NULL	,
		"afi"	,
		72	,
		0	,
		26000000	,
		mux_clk_m	,
		PERIPH_MANUAL_RESET
	)

PERIPH_CLK	(	pcie_xclk	,
		NULL	,
		"pcie_xclk"	,
		74	,
		0	,
		26000000	,
		mux_clk_m	,
		PERIPH_MANUAL_RESET
	)

void __init tegra2_init_clocks

(

void

)

Definition at line 1115 of file tegra20_clocks_data.c.