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Macros | Functions | Variables
tegra30_clocks_data.c File Reference
#include <linux/clk-private.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include "clock.h"
#include "fuse.h"
#include "tegra30_clocks.h"
#include "tegra_cpu_car.h"

Go to the source code of this file.

Macros

#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,_parent_names, _parents, _parent)
 
#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, _input_max, _cf_min, _cf_max, _vco_min, _vco_max, _freq_table, _lock_delay, _ops, _fixed_rate, _clk_cfg_ex, _parent)
 
#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift,_max_rate, _ops, _parent, _clk_flags)
 
#define SYNC_SOURCE(_name)
 
#define AUDIO_SYNC_CLK(_name, _index)
 
#define AUDIO_SYNC_2X_CLK(_name, _index)
 
#define MUX_I2S_SPDIF(_id)
 
#define MUX_EXTERN_OUT(_id)
 
#define CLK_OUT_CLK(_name, _index)
 
#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags)
 
#define CLK_DUPLICATE(_name, _dev, _con)
 

Functions

 DEFINE_CLK_TEGRA (clk_m_div2, 0,&tegra_clk_m_div_ops, 0, clk_m_div_parent_names, clk_m_div_parents,&tegra_clk_m)
 
 DEFINE_CLK_TEGRA (clk_m_div4, 0,&tegra_clk_m_div_ops, 0, clk_m_div_parent_names, clk_m_div_parents,&tegra_clk_m)
 
 DEFINE_CLK_TEGRA (pll_ref, 0,&tegra_pll_ref_ops, 0, clk_m_div_parent_names, clk_m_div_parents,&tegra_clk_m)
 
 DEFINE_PLL (pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref)
 
 DEFINE_PLL_OUT (pll_c_out1, DIV_U71, 0x84, 0, 700000000, tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED)
 
 DEFINE_PLL (pll_m, PLL_HAS_CPCON|PLLM, 0x90, 800000000, 2000000, 31000000, 1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref)
 
 DEFINE_PLL_OUT (pll_m_out1, DIV_U71, 0x94, 0, 600000000, tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED)
 
 DEFINE_PLL (pll_p, ENABLE_ON_INIT|PLL_FIXED|PLL_HAS_CPCON, 0xa0, 432000000, 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000, tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL, pll_ref)
 
 DEFINE_PLL_OUT (pll_p_out1, ENABLE_ON_INIT|DIV_U71|DIV_U71_FIXED, 0xa4, 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED)
 
 DEFINE_PLL_OUT (pll_p_out2, ENABLE_ON_INIT|DIV_U71|DIV_U71_FIXED, 0xa4, 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED)
 
 DEFINE_PLL_OUT (pll_p_out3, ENABLE_ON_INIT|DIV_U71|DIV_U71_FIXED, 0xa8, 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED)
 
 DEFINE_PLL_OUT (pll_p_out4, ENABLE_ON_INIT|DIV_U71|DIV_U71_FIXED, 0xa8, 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED)
 
 DEFINE_PLL (pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_p_out1)
 
 DEFINE_PLL_OUT (pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops, pll_a, CLK_IGNORE_UNUSED)
 
 DEFINE_PLL (pll_d, PLL_HAS_CPCON|PLLD, 0xd0, 1000000000, 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref)
 
 DEFINE_PLL_OUT (pll_d_out0, DIV_2|PLLD, 0, 0, 500000000, tegra30_pll_div_ops, pll_d, CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED)
 
 DEFINE_PLL (pll_d2, PLL_HAS_CPCON|PLL_ALT_MISC_REG|PLLD, 0x4b8, 1000000000, 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL, pll_ref)
 
 DEFINE_PLL_OUT (pll_d2_out0, DIV_2|PLLD, 0, 0, 500000000, tegra30_pll_div_ops, pll_d2, CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED)
 
 DEFINE_PLL (pll_u, PLL_HAS_CPCON|PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table, 1000, tegra30_pll_ops, 0, NULL, pll_ref)
 
 DEFINE_PLL (pll_x, PLL_HAS_CPCON|PLL_ALT_MISC_REG|PLLX, 0xe0, 1700000000, 2000000, 31000000, 1000000, 6000000, 20000000, 1700000000, tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref)
 
 DEFINE_PLL_OUT (pll_x_out0, DIV_2|PLLX, 0, 0, 850000000, tegra30_pll_div_ops, pll_x, CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED)
 
 DEFINE_PLL (pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000, 12000000, 12000000, 1200000000, 2400000000U, tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL, pll_ref)
 
 DEFINE_CLK_TEGRA (cml0, 0,&tegra_cml_clk_ops, 0, mux_plle, mux_plle_p,&tegra_pll_e)
 
 DEFINE_CLK_TEGRA (cml1, 0,&tegra_cml_clk_ops, 0, mux_plle, mux_plle_p,&tegra_pll_e)
 
 DEFINE_CLK_TEGRA (pciex, 0,&tegra_pciex_clk_ops, 0, mux_plle, mux_plle_p,&tegra_pll_e)
 
 SYNC_SOURCE (spdif_in)
 
 SYNC_SOURCE (i2s0)
 
 SYNC_SOURCE (i2s1)
 
 SYNC_SOURCE (i2s2)
 
 SYNC_SOURCE (i2s3)
 
 SYNC_SOURCE (i2s4)
 
 SYNC_SOURCE (vimclk)
 
 AUDIO_SYNC_CLK (audio0, 0)
 
 AUDIO_SYNC_CLK (audio1, 1)
 
 AUDIO_SYNC_CLK (audio2, 2)
 
 AUDIO_SYNC_CLK (audio3, 3)
 
 AUDIO_SYNC_CLK (audio4, 4)
 
 AUDIO_SYNC_CLK (audio5, 5)
 
 AUDIO_SYNC_2X_CLK (audio0, 0)
 
 AUDIO_SYNC_2X_CLK (audio1, 1)
 
 AUDIO_SYNC_2X_CLK (audio2, 2)
 
 AUDIO_SYNC_2X_CLK (audio3, 3)
 
 AUDIO_SYNC_2X_CLK (audio4, 4)
 
 AUDIO_SYNC_2X_CLK (audio5, 5)
 
 MUX_I2S_SPDIF (audio0)
 
 MUX_I2S_SPDIF (audio1)
 
 MUX_I2S_SPDIF (audio2)
 
 MUX_I2S_SPDIF (audio3)
 
 MUX_I2S_SPDIF (audio4)
 
 MUX_I2S_SPDIF (audio5)
 
 MUX_EXTERN_OUT (1)
 
 MUX_EXTERN_OUT (2)
 
 MUX_EXTERN_OUT (3)
 
 CLK_OUT_CLK (clk_out_1, 1)
 
 CLK_OUT_CLK (clk_out_2, 2)
 
 CLK_OUT_CLK (clk_out_3, 3)
 
 PERIPH_CLK (apbdma,"tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0)
 
 PERIPH_CLK (rtc,"rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET|PERIPH_ON_APB)
 
 PERIPH_CLK (kbc,"tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET|PERIPH_ON_APB)
 
 PERIPH_CLK (timer,"timer", NULL, 5, 0, 26000000, mux_clk_m, 0)
 
 PERIPH_CLK (kfuse,"kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0)
 
 PERIPH_CLK (fuse,"fuse-tegra","fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB)
 
 PERIPH_CLK (fuse_burn,"fuse-tegra","fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB)
 
 PERIPH_CLK (apbif,"tegra30-ahub","apbif", 107, 0, 26000000, mux_clk_m, 0)
 
 PERIPH_CLK (i2s0,"tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (i2s1,"tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (i2s2,"tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (i2s3,"tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (i2s4,"tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (spdif_out,"tegra30-spdif","spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio5_2x_pllp_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (spdif_in,"tegra30-spdif","spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (pwm,"tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX|MUX_PWM|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (d_audio,"tegra30-ahub","d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (dam0,"tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (dam1,"tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (dam2,"tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (hda,"tegra30-hda","hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (hda2codec_2x,"tegra30-hda","hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (hda2hdmi,"tegra30-hda","hda2hdmi", 128, 0, 48000000, mux_clk_m, 0)
 
 PERIPH_CLK (sbc1,"spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (sbc2,"spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (sbc3,"spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (sbc4,"spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (sbc5,"spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (sbc6,"spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (sata_oob,"tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (sata,"tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (sata_cold,"tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0)
 
 PERIPH_CLK (ndflash,"tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (ndspeed,"tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (vfir,"vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (sdmmc1,"sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (sdmmc2,"sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (sdmmc3,"sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (sdmmc4,"sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (vcp,"tegra-avp","vcp", 29, 0, 250000000, mux_clk_m, 0)
 
 PERIPH_CLK (bsea,"tegra-avp","bsea", 62, 0, 250000000, mux_clk_m, 0)
 
 PERIPH_CLK (bsev,"tegra-aes","bsev", 63, 0, 250000000, mux_clk_m, 0)
 
 PERIPH_CLK (vde,"vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|DIV_U71_INT)
 
 PERIPH_CLK (csite,"csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (la,"la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (owr,"tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (nor,"nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (mipi,"mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (i2c1,"tegra-i2c.0","div-clk", 12, 0x124, 26000000, mux_pllp_clkm, MUX|DIV_U16|PERIPH_ON_APB)
 
 PERIPH_CLK (i2c2,"tegra-i2c.1","div-clk", 54, 0x198, 26000000, mux_pllp_clkm, MUX|DIV_U16|PERIPH_ON_APB)
 
 PERIPH_CLK (i2c3,"tegra-i2c.2","div-clk", 67, 0x1b8, 26000000, mux_pllp_clkm, MUX|DIV_U16|PERIPH_ON_APB)
 
 PERIPH_CLK (i2c4,"tegra-i2c.3","div-clk", 103, 0x3c4, 26000000, mux_pllp_clkm, MUX|DIV_U16|PERIPH_ON_APB)
 
 PERIPH_CLK (i2c5,"tegra-i2c.4","div-clk", 47, 0x128, 26000000, mux_pllp_clkm, MUX|DIV_U16|PERIPH_ON_APB)
 
 PERIPH_CLK (uarta,"tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|DIV_U71_UART|PERIPH_ON_APB)
 
 PERIPH_CLK (uartb,"tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|DIV_U71_UART|PERIPH_ON_APB)
 
 PERIPH_CLK (uartc,"tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|DIV_U71_UART|PERIPH_ON_APB)
 
 PERIPH_CLK (uartd,"tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|DIV_U71_UART|PERIPH_ON_APB)
 
 PERIPH_CLK (uarte,"tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|DIV_U71_UART|PERIPH_ON_APB)
 
 PERIPH_CLK (vi,"tegra_camera","vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71|DIV_U71_INT)
 
 PERIPH_CLK (3d,"3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71|DIV_U71_INT|DIV_U71_IDLE|PERIPH_MANUAL_RESET)
 
 PERIPH_CLK (3d2,"3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71|DIV_U71_INT|DIV_U71_IDLE|PERIPH_MANUAL_RESET)
 
 PERIPH_CLK (2d,"2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71|DIV_U71_INT|DIV_U71_IDLE)
 
 PERIPH_CLK (vi_sensor,"tegra_camera","vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71|PERIPH_NO_RESET)
 
 PERIPH_CLK (epp,"epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71|DIV_U71_INT)
 
 PERIPH_CLK (mpe,"mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71|DIV_U71_INT)
 
 PERIPH_CLK (host1x,"host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX|DIV_U71|DIV_U71_INT)
 
 PERIPH_CLK (cve,"cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (tvo,"tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (dtv,"dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0)
 
 PERIPH_CLK (hdmi,"hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX|MUX8|DIV_U71)
 
 PERIPH_CLK (tvdac,"tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (disp1,"tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX|MUX8)
 
 PERIPH_CLK (disp2,"tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX|MUX8)
 
 PERIPH_CLK (usbd,"fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0)
 
 PERIPH_CLK (usb2,"tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0)
 
 PERIPH_CLK (usb3,"tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0)
 
 PERIPH_CLK (dsia,"tegradc.0","dsia", 48, 0, 500000000, mux_plld_out0, 0)
 
 PERIPH_CLK (csi,"tegra_camera","csi", 52, 0, 102000000, mux_pllp_out3, 0)
 
 PERIPH_CLK (isp,"tegra_camera","isp", 23, 0, 150000000, mux_clk_m, 0)
 
 PERIPH_CLK (csus,"tegra_camera","csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET)
 
 PERIPH_CLK (tsensor,"tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX|DIV_U71)
 
 PERIPH_CLK (actmon,"actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX|DIV_U71)
 
 PERIPH_CLK (extern1,"extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX|MUX8|DIV_U71)
 
 PERIPH_CLK (extern2,"extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX|MUX8|DIV_U71)
 
 PERIPH_CLK (extern3,"extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX|MUX8|DIV_U71)
 
 PERIPH_CLK (i2cslow,"i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX|DIV_U71|PERIPH_ON_APB)
 
 PERIPH_CLK (pcie,"tegra-pcie","pcie", 70, 0, 250000000, mux_clk_m, 0)
 
 PERIPH_CLK (afi,"tegra-pcie","afi", 72, 0, 250000000, mux_clk_m, 0)
 
 PERIPH_CLK (se,"se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX|DIV_U71|DIV_U71_INT)
 
void __init tegra30_init_clocks (void)
 

Variables

struct clk * tegra_list_clks []
 
struct clk_duplicate tegra_clk_duplicates []
 
struct clk * tegra_ptr_clks []
 

Macro Definition Documentation

#define AUDIO_SYNC_2X_CLK (   _name,
  _index 
)
Value:
static const char *_name##_parent_names[] = { \
"tegra_" #_name, \
}; \
static struct clk *_name##_parents[] = { \
&tegra_##_name, \
}; \
static struct clk tegra_##_name##_2x; \
static struct clk_tegra tegra_##_name##_2x_hw = { \
.hw = { \
.clk = &tegra_##_name##_2x, \
}, \
.flags = PERIPH_NO_RESET, \
.max_rate = 48000000, \
.reg = 0x49C, \
.reg_shift = 24 + (_index), \
.u.periph = { \
.clk_num = 113 + (_index), \
}, \
}; \
static struct clk tegra_##_name##_2x = { \
.name = #_name "_2x", \
.ops = &tegra30_clk_double_ops, \
.hw = &tegra_##_name##_2x_hw.hw, \
.parent_names = _name##_parent_names, \
.parents = _name##_parents, \
.parent = &tegra_##_name, \
.num_parents = 1, \
};

Definition at line 547 of file tegra30_clocks_data.c.

#define AUDIO_SYNC_CLK (   _name,
  _index 
)
Value:
static struct clk tegra_##_name; \
static struct clk_tegra tegra_##_name##_hw = { \
.hw = { \
.clk = &tegra_##_name, \
}, \
.max_rate = 24000000, \
.reg = 0x4A0 + (_index) * 4, \
}; \
static struct clk tegra_##_name = { \
.name = #_name, \
.ops = &tegra30_audio_sync_clk_ops, \
.hw = &tegra_##_name##_hw.hw, \
.parent_names = mux_audio_sync_clk, \
.parents = tegra_sync_source_list, \
.num_parents = ARRAY_SIZE(mux_audio_sync_clk), \
};

Definition at line 513 of file tegra30_clocks_data.c.

#define CLK_DUPLICATE (   _name,
  _dev,
  _con 
)
Value:
{ \
.name = _name, \
.lookup = { \
.dev_id = _dev, \
.con_id = _con, \
}, \
}

Definition at line 1235 of file tegra30_clocks_data.c.

#define CLK_OUT_CLK (   _name,
  _index 
)
Value:
static struct clk tegra_##_name; \
static struct clk_tegra tegra_##_name##_hw = { \
.hw = { \
.clk = &tegra_##_name, \
}, \
.lookup = { \
.dev_id = #_name, \
.con_id = "extern" #_index, \
}, \
.flags = MUX_CLK_OUT, \
.fixed_rate = 216000000, \
.reg = 0x1a8, \
.u.periph = { \
.clk_num = (_index - 1) * 8 + 2, \
}, \
}; \
static struct clk tegra_##_name = { \
.name = #_name, \
.ops = &tegra_clk_out_ops, \
.hw = &tegra_##_name##_hw.hw, \
.parent_names = mux_clkm_clkm2_clkm4_extern##_index, \
.parents = mux_clkm_clkm2_clkm4_extern##_index##_p, \
.num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
};

Definition at line 637 of file tegra30_clocks_data.c.

#define DEFINE_CLK_TEGRA (   _name,
  _rate,
  _ops,
  _flags,
  _parent_names,
  _parents,
  _parent 
)
Value:
static struct clk tegra_##_name = { \
.hw = &tegra_##_name##_hw.hw, \
.name = #_name, \
.rate = _rate, \
.ops = _ops, \
.flags = _flags, \
.parent_names = _parent_names, \
.parents = _parents, \
.num_parents = ARRAY_SIZE(_parent_names), \
.parent = _parent, \
};

Definition at line 37 of file tegra30_clocks_data.c.

#define DEFINE_PLL (   _name,
  _flags,
  _reg,
  _max_rate,
  _input_min,
  _input_max,
  _cf_min,
  _cf_max,
  _vco_min,
  _vco_max,
  _freq_table,
  _lock_delay,
  _ops,
  _fixed_rate,
  _clk_cfg_ex,
  _parent 
)
Value:
static struct clk tegra_##_name; \
static const char *_name##_parent_names[] = { \
#_parent, \
}; \
static struct clk *_name##_parents[] = { \
&tegra_##_parent, \
}; \
static struct clk_tegra tegra_##_name##_hw = { \
.hw = { \
.clk = &tegra_##_name, \
}, \
.flags = _flags, \
.reg = _reg, \
.max_rate = _max_rate, \
.u.pll = { \
.input_min = _input_min, \
.input_max = _input_max, \
.cf_min = _cf_min, \
.cf_max = _cf_max, \
.vco_min = _vco_min, \
.vco_max = _vco_max, \
.freq_table = _freq_table, \
.lock_delay = _lock_delay, \
.fixed_rate = _fixed_rate, \
}, \
.clk_cfg_ex = _clk_cfg_ex, \
}; \
DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED, \
_name##_parent_names, _name##_parents, \
&tegra_##_parent);

Definition at line 125 of file tegra30_clocks_data.c.

#define DEFINE_PLL_OUT (   _name,
  _flags,
  _reg,
  _reg_shift,
  _max_rate,
  _ops,
  _parent,
  _clk_flags 
)
Value:
static const char *_name##_parent_names[] = { \
#_parent, \
}; \
static struct clk *_name##_parents[] = { \
&tegra_##_parent, \
}; \
static struct clk tegra_##_name; \
static struct clk_tegra tegra_##_name##_hw = { \
.hw = { \
.clk = &tegra_##_name, \
}, \
.flags = _flags, \
.reg = _reg, \
.max_rate = _max_rate, \
.reg_shift = _reg_shift, \
}; \
DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops, \
_clk_flags, _name##_parent_names, \
_name##_parents, &tegra_##_parent);

Definition at line 160 of file tegra30_clocks_data.c.

#define MUX_EXTERN_OUT (   _id)
Value:
static const char *mux_clkm_clkm2_clkm4_extern##_id[] = { \
"clk_m", \
"clk_m_div2", \
"clk_m_div4", \
"extern" #_id, \
}; \
static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = { \
&tegra_clk_m, \
&tegra_clk_m_div2, \
&tegra_clk_m_div4, \
&tegra_extern##_id, \
};

Definition at line 619 of file tegra30_clocks_data.c.

#define MUX_I2S_SPDIF (   _id)
Value:
static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
"pll_a_out0", \
#_id "_2x", \
"pll_p", \
"clk_m", \
}; \
static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = { \
&tegra_pll_a_out0, \
&tegra_##_id##_2x, \
&tegra_pll_p, \
&tegra_clk_m, \
};

Definition at line 593 of file tegra30_clocks_data.c.

#define PERIPH_CLK (   _name,
  _dev,
  _con,
  _clk_num,
  _reg,
  _max,
  _inputs,
  _flags 
)
Value:
static struct clk tegra_##_name; \
static struct clk_tegra tegra_##_name##_hw = { \
.hw = { \
.clk = &tegra_##_name, \
}, \
.lookup = { \
.dev_id = _dev, \
.con_id = _con, \
}, \
.reg = _reg, \
.flags = _flags, \
.max_rate = _max, \
.u.periph = { \
.clk_num = _clk_num, \
}, \
.reset = &tegra30_periph_clk_reset, \
}; \
static struct clk tegra_##_name = { \
.name = #_name, \
.ops = &tegra30_periph_clk_ops, \
.hw = &tegra_##_name##_hw.hw, \
.parent_names = _inputs, \
.parents = _inputs##_p, \
.num_parents = ARRAY_SIZE(_inputs), \
};

Definition at line 998 of file tegra30_clocks_data.c.

#define SYNC_SOURCE (   _name)
Value:
static struct clk tegra_##_name##_sync; \
static struct clk_tegra tegra_##_name##_sync_hw = { \
.hw = { \
.clk = &tegra_##_name##_sync, \
}, \
.max_rate = 24000000, \
.fixed_rate = 24000000, \
}; \
static struct clk tegra_##_name##_sync = { \
.name = #_name "_sync", \
.hw = &tegra_##_name##_sync_hw.hw, \
.ops = &tegra_sync_source_ops, \
.flags = CLK_IS_ROOT, \
};

Definition at line 469 of file tegra30_clocks_data.c.

Function Documentation

AUDIO_SYNC_2X_CLK ( audio0  ,
0   
)
AUDIO_SYNC_2X_CLK ( audio1  ,
1   
)
AUDIO_SYNC_2X_CLK ( audio2  ,
2   
)
AUDIO_SYNC_2X_CLK ( audio3  ,
3   
)
AUDIO_SYNC_2X_CLK ( audio4  ,
4   
)
AUDIO_SYNC_2X_CLK ( audio5  ,
5   
)
AUDIO_SYNC_CLK ( audio0  ,
0   
)
AUDIO_SYNC_CLK ( audio1  ,
1   
)
AUDIO_SYNC_CLK ( audio2  ,
2   
)
AUDIO_SYNC_CLK ( audio3  ,
3   
)
AUDIO_SYNC_CLK ( audio4  ,
4   
)
AUDIO_SYNC_CLK ( audio5  ,
5   
)
CLK_OUT_CLK ( clk_out_1  ,
1   
)
CLK_OUT_CLK ( clk_out_2  ,
2   
)
CLK_OUT_CLK ( clk_out_3  ,
3   
)
DEFINE_CLK_TEGRA ( clk_m_div2  ,
0  ,
&  tegra_clk_m_div_ops,
0  ,
clk_m_div_parent_names  ,
clk_m_div_parents  ,
&  tegra_clk_m 
)
DEFINE_CLK_TEGRA ( clk_m_div4  ,
0  ,
&  tegra_clk_m_div_ops,
0  ,
clk_m_div_parent_names  ,
clk_m_div_parents  ,
&  tegra_clk_m 
)
DEFINE_CLK_TEGRA ( pll_ref  ,
0  ,
&  tegra_pll_ref_ops,
0  ,
clk_m_div_parent_names  ,
clk_m_div_parents  ,
&  tegra_clk_m 
)
DEFINE_CLK_TEGRA ( cml0  ,
0  ,
&  tegra_cml_clk_ops,
0  ,
mux_plle  ,
mux_plle_p  ,
&  tegra_pll_e 
)
DEFINE_CLK_TEGRA ( cml1  ,
0  ,
&  tegra_cml_clk_ops,
0  ,
mux_plle  ,
mux_plle_p  ,
&  tegra_pll_e 
)
DEFINE_CLK_TEGRA ( pciex  ,
0  ,
&  tegra_pciex_clk_ops,
0  ,
mux_plle  ,
mux_plle_p  ,
&  tegra_pll_e 
)
DEFINE_PLL ( pll_c  ,
PLL_HAS_CPCON  ,
0x80  ,
1400000000  ,
2000000  ,
31000000  ,
1000000  ,
6000000  ,
20000000  ,
1400000000  ,
tegra_pll_c_freq_table  ,
300  ,
tegra30_pll_ops  ,
0  ,
NULL  ,
pll_ref   
)
DEFINE_PLL ( pll_m  ,
PLL_HAS_CPCON|  PLLM,
0x90  ,
800000000  ,
2000000  ,
31000000  ,
1000000  ,
6000000  ,
20000000  ,
1200000000  ,
tegra_pll_m_freq_table  ,
300  ,
tegra30_pll_ops  ,
0  ,
NULL  ,
pll_ref   
)
DEFINE_PLL ( pll_p  ,
ENABLE_ON_INIT|PLL_FIXED|  PLL_HAS_CPCON,
0xa0  ,
432000000  ,
2000000  ,
31000000  ,
1000000  ,
6000000  ,
20000000  ,
1400000000  ,
tegra_pll_p_freq_table  ,
300  ,
tegra30_pll_ops  ,
408000000  ,
NULL  ,
pll_ref   
)
DEFINE_PLL ( pll_a  ,
PLL_HAS_CPCON  ,
0xb0  ,
700000000  ,
2000000  ,
31000000  ,
1000000  ,
6000000  ,
20000000  ,
1400000000  ,
tegra_pll_a_freq_table  ,
300  ,
tegra30_pll_ops  ,
0  ,
NULL  ,
pll_p_out1   
)
DEFINE_PLL ( pll_d  ,
PLL_HAS_CPCON|  PLLD,
0xd0  ,
1000000000  ,
2000000  ,
40000000  ,
1000000  ,
6000000  ,
40000000  ,
1000000000  ,
tegra_pll_d_freq_table  ,
1000  ,
tegra30_pll_ops  ,
0  ,
tegra30_plld_clk_cfg_ex  ,
pll_ref   
)
DEFINE_PLL ( pll_d2  ,
PLL_HAS_CPCON|PLL_ALT_MISC_REG|  PLLD,
0x4b8  ,
1000000000  ,
2000000  ,
40000000  ,
1000000  ,
6000000  ,
40000000  ,
1000000000  ,
tegra_pll_d_freq_table  ,
1000  ,
tegra30_pll_ops  ,
0  ,
NULL  ,
pll_ref   
)
DEFINE_PLL ( pll_u  ,
PLL_HAS_CPCON|  PLLU,
0xc0  ,
480000000  ,
2000000  ,
40000000  ,
1000000  ,
6000000  ,
48000000  ,
960000000  ,
tegra_pll_u_freq_table  ,
1000  ,
tegra30_pll_ops  ,
0  ,
NULL  ,
pll_ref   
)
DEFINE_PLL ( pll_x  ,
PLL_HAS_CPCON|PLL_ALT_MISC_REG|  PLLX,
0xe0  ,
1700000000  ,
2000000  ,
31000000  ,
1000000  ,
6000000  ,
20000000  ,
1700000000  ,
tegra_pll_x_freq_table  ,
300  ,
tegra30_pll_ops  ,
0  ,
NULL  ,
pll_ref   
)
DEFINE_PLL ( pll_e  ,
PLL_ALT_MISC_REG  ,
0xe8  ,
100000000  ,
2000000  ,
216000000  ,
12000000  ,
12000000  ,
1200000000  ,
2400000000U  ,
tegra_pll_e_freq_table  ,
300  ,
tegra30_plle_ops  ,
100000000  ,
NULL  ,
pll_ref   
)
DEFINE_PLL_OUT ( pll_c_out1  ,
DIV_U71  ,
0x84  ,
0  ,
700000000  ,
tegra30_pll_div_ops  ,
pll_c  ,
CLK_IGNORE_UNUSED   
)
DEFINE_PLL_OUT ( pll_m_out1  ,
DIV_U71  ,
0x94  ,
0  ,
600000000  ,
tegra30_pll_div_ops  ,
pll_m  ,
CLK_IGNORE_UNUSED   
)
DEFINE_PLL_OUT ( pll_p_out1  ,
ENABLE_ON_INIT|DIV_U71|  DIV_U71_FIXED,
0xa4  ,
0  ,
432000000  ,
tegra30_pll_div_ops  ,
pll_p  ,
CLK_IGNORE_UNUSED   
)
DEFINE_PLL_OUT ( pll_p_out2  ,
ENABLE_ON_INIT|DIV_U71|  DIV_U71_FIXED,
0xa4  ,
16  ,
432000000  ,
tegra30_pll_div_ops  ,
pll_p  ,
CLK_IGNORE_UNUSED   
)
DEFINE_PLL_OUT ( pll_p_out3  ,
ENABLE_ON_INIT|DIV_U71|  DIV_U71_FIXED,
0xa8  ,
0  ,
432000000  ,
tegra30_pll_div_ops  ,
pll_p  ,
CLK_IGNORE_UNUSED   
)
DEFINE_PLL_OUT ( pll_p_out4  ,
ENABLE_ON_INIT|DIV_U71|  DIV_U71_FIXED,
0xa8  ,
16  ,
432000000  ,
tegra30_pll_div_ops  ,
pll_p  ,
CLK_IGNORE_UNUSED   
)
DEFINE_PLL_OUT ( pll_a_out0  ,
DIV_U71  ,
0xb4  ,
0  ,
100000000  ,
tegra30_pll_div_ops  ,
pll_a  ,
CLK_IGNORE_UNUSED   
)
DEFINE_PLL_OUT ( pll_d_out0  ,
DIV_2|  PLLD,
0  ,
0  ,
500000000  ,
tegra30_pll_div_ops  ,
pll_d  ,
CLK_SET_RATE_PARENT|  CLK_IGNORE_UNUSED 
)
DEFINE_PLL_OUT ( pll_d2_out0  ,
DIV_2|  PLLD,
0  ,
0  ,
500000000  ,
tegra30_pll_div_ops  ,
pll_d2  ,
CLK_SET_RATE_PARENT|  CLK_IGNORE_UNUSED 
)
DEFINE_PLL_OUT ( pll_x_out0  ,
DIV_2|  PLLX,
0  ,
0  ,
850000000  ,
tegra30_pll_div_ops  ,
pll_x  ,
CLK_SET_RATE_PARENT|  CLK_IGNORE_UNUSED 
)
MUX_EXTERN_OUT ( 1  )
MUX_EXTERN_OUT ( 2  )
MUX_EXTERN_OUT ( 3  )
MUX_I2S_SPDIF ( audio0  )
MUX_I2S_SPDIF ( audio1  )
MUX_I2S_SPDIF ( audio2  )
MUX_I2S_SPDIF ( audio3  )
MUX_I2S_SPDIF ( audio4  )
MUX_I2S_SPDIF ( audio5  )
PERIPH_CLK ( apbdma  ,
"tegra-apbdma"  ,
NULL  ,
34  ,
0  ,
26000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( rtc  ,
"rtc-tegra"  ,
NULL  ,
4  ,
0  ,
32768  ,
mux_clk_32k  ,
PERIPH_NO_RESET|  PERIPH_ON_APB 
)
PERIPH_CLK ( kbc  ,
"tegra-kbc"  ,
NULL  ,
36  ,
0  ,
32768  ,
mux_clk_32k  ,
PERIPH_NO_RESET|  PERIPH_ON_APB 
)
PERIPH_CLK ( timer  ,
"timer"  ,
NULL  ,
5  ,
0  ,
26000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( kfuse  ,
"kfuse-tegra"  ,
NULL  ,
40  ,
0  ,
26000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( fuse  ,
"fuse-tegra"  ,
"fuse"  ,
39  ,
0  ,
26000000  ,
mux_clk_m  ,
PERIPH_ON_APB   
)
PERIPH_CLK ( fuse_burn  ,
"fuse-tegra"  ,
"fuse_burn"  ,
39  ,
0  ,
26000000  ,
mux_clk_m  ,
PERIPH_ON_APB   
)
PERIPH_CLK ( apbif  ,
"tegra30-ahub"  ,
"apbif"  ,
107  ,
0  ,
26000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( i2s0  ,
"tegra30-i2s.0"  ,
NULL  ,
30  ,
0x1d8  ,
26000000  ,
mux_pllaout0_audio0_2x_pllp_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( i2s1  ,
"tegra30-i2s.1"  ,
NULL  ,
11  ,
0x100  ,
26000000  ,
mux_pllaout0_audio1_2x_pllp_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( i2s2  ,
"tegra30-i2s.2"  ,
NULL  ,
18  ,
0x104  ,
26000000  ,
mux_pllaout0_audio2_2x_pllp_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( i2s3  ,
"tegra30-i2s.3"  ,
NULL  ,
101  ,
0x3bc  ,
26000000  ,
mux_pllaout0_audio3_2x_pllp_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( i2s4  ,
"tegra30-i2s.4"  ,
NULL  ,
102  ,
0x3c0  ,
26000000  ,
mux_pllaout0_audio4_2x_pllp_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( spdif_out  ,
"tegra30-spdif"  ,
"spdif_out"  ,
10  ,
0x108  ,
100000000  ,
mux_pllaout0_audio5_2x_pllp_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( spdif_in  ,
"tegra30-spdif"  ,
"spdif_in"  ,
10  ,
0x10c  ,
100000000  ,
mux_pllp_pllc_pllm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( pwm  ,
"tegra-pwm"  ,
NULL  ,
17  ,
0x110  ,
432000000  ,
mux_pllp_pllc_clk32_clkm  ,
MUX|MUX_PWM|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( d_audio  ,
"tegra30-ahub"  ,
"d_audio"  ,
106  ,
0x3d0  ,
48000000  ,
mux_plla_pllc_pllp_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( dam0  ,
"tegra30-dam.0"  ,
NULL  ,
108  ,
0x3d8  ,
48000000  ,
mux_plla_pllc_pllp_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( dam1  ,
"tegra30-dam.1"  ,
NULL  ,
109  ,
0x3dc  ,
48000000  ,
mux_plla_pllc_pllp_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( dam2  ,
"tegra30-dam.2"  ,
NULL  ,
110  ,
0x3e0  ,
48000000  ,
mux_plla_pllc_pllp_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( hda  ,
"tegra30-hda"  ,
"hda"  ,
125  ,
0x428  ,
108000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( hda2codec_2x  ,
"tegra30-hda"  ,
"hda2codec"  ,
111  ,
0x3e4  ,
48000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( hda2hdmi  ,
"tegra30-hda"  ,
"hda2hdmi"  ,
128  ,
0  ,
48000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( sbc1  ,
"spi_tegra.0"  ,
NULL  ,
41  ,
0x134  ,
160000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( sbc2  ,
"spi_tegra.1"  ,
NULL  ,
44  ,
0x118  ,
160000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( sbc3  ,
"spi_tegra.2"  ,
NULL  ,
46  ,
0x11c  ,
160000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( sbc4  ,
"spi_tegra.3"  ,
NULL  ,
68  ,
0x1b4  ,
160000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( sbc5  ,
"spi_tegra.4"  ,
NULL  ,
104  ,
0x3c8  ,
160000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( sbc6  ,
"spi_tegra.5"  ,
NULL  ,
105  ,
0x3cc  ,
160000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( sata_oob  ,
"tegra_sata_oob"  ,
NULL  ,
123  ,
0x420  ,
216000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( sata  ,
"tegra_sata"  ,
NULL  ,
124  ,
0x424  ,
216000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( sata_cold  ,
"tegra_sata_cold"  ,
NULL  ,
129  ,
0  ,
48000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( ndflash  ,
"tegra_nand"  ,
NULL  ,
13  ,
0x160  ,
240000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( ndspeed  ,
"tegra_nand_speed"  ,
NULL  ,
80  ,
0x3f8  ,
240000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( vfir  ,
"vfir"  ,
NULL  ,
7  ,
0x168  ,
72000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( sdmmc1  ,
"sdhci-tegra.0"  ,
NULL  ,
14  ,
0x150  ,
208000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( sdmmc2  ,
"sdhci-tegra.1"  ,
NULL  ,
9  ,
0x154  ,
104000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( sdmmc3  ,
"sdhci-tegra.2"  ,
NULL  ,
69  ,
0x1bc  ,
208000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( sdmmc4  ,
"sdhci-tegra.3"  ,
NULL  ,
15  ,
0x164  ,
104000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( vcp  ,
"tegra-avp"  ,
"vcp"  ,
29  ,
0  ,
250000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( bsea  ,
"tegra-avp"  ,
"bsea"  ,
62  ,
0  ,
250000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( bsev  ,
"tegra-aes"  ,
"bsev"  ,
63  ,
0  ,
250000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( vde  ,
"vde"  ,
NULL  ,
61  ,
0x1c8  ,
520000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|  DIV_U71_INT 
)
PERIPH_CLK ( csite  ,
"csite"  ,
NULL  ,
73  ,
0x1d4  ,
144000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( la  ,
"la"  ,
NULL  ,
76  ,
0x1f8  ,
26000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( owr  ,
"tegra_w1"  ,
NULL  ,
71  ,
0x1cc  ,
26000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( nor  ,
"nor"  ,
NULL  ,
42  ,
0x1d0  ,
127000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( mipi  ,
"mipi"  ,
NULL  ,
50  ,
0x174  ,
60000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( i2c1  ,
"tegra-i2c.0"  ,
"div-clk"  ,
12  ,
0x124  ,
26000000  ,
mux_pllp_clkm  ,
MUX|DIV_U16|  PERIPH_ON_APB 
)
PERIPH_CLK ( i2c2  ,
"tegra-i2c.1"  ,
"div-clk"  ,
54  ,
0x198  ,
26000000  ,
mux_pllp_clkm  ,
MUX|DIV_U16|  PERIPH_ON_APB 
)
PERIPH_CLK ( i2c3  ,
"tegra-i2c.2"  ,
"div-clk"  ,
67  ,
0x1b8  ,
26000000  ,
mux_pllp_clkm  ,
MUX|DIV_U16|  PERIPH_ON_APB 
)
PERIPH_CLK ( i2c4  ,
"tegra-i2c.3"  ,
"div-clk"  ,
103  ,
0x3c4  ,
26000000  ,
mux_pllp_clkm  ,
MUX|DIV_U16|  PERIPH_ON_APB 
)
PERIPH_CLK ( i2c5  ,
"tegra-i2c.4"  ,
"div-clk"  ,
47  ,
0x128  ,
26000000  ,
mux_pllp_clkm  ,
MUX|DIV_U16|  PERIPH_ON_APB 
)
PERIPH_CLK ( uarta  ,
"tegra-uart.0"  ,
NULL  ,
6  ,
0x178  ,
800000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|DIV_U71_UART|  PERIPH_ON_APB 
)
PERIPH_CLK ( uartb  ,
"tegra-uart.1"  ,
NULL  ,
7  ,
0x17c  ,
800000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|DIV_U71_UART|  PERIPH_ON_APB 
)
PERIPH_CLK ( uartc  ,
"tegra-uart.2"  ,
NULL  ,
55  ,
0x1a0  ,
800000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|DIV_U71_UART|  PERIPH_ON_APB 
)
PERIPH_CLK ( uartd  ,
"tegra-uart.3"  ,
NULL  ,
65  ,
0x1c0  ,
800000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|DIV_U71_UART|  PERIPH_ON_APB 
)
PERIPH_CLK ( uarte  ,
"tegra-uart.4"  ,
NULL  ,
66  ,
0x1c4  ,
800000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|DIV_U71_UART|  PERIPH_ON_APB 
)
PERIPH_CLK ( vi  ,
"tegra_camera"  ,
"vi"  ,
20  ,
0x148  ,
425000000  ,
mux_pllm_pllc_pllp_plla  ,
MUX|DIV_U71|  DIV_U71_INT 
)
PERIPH_CLK ( 3d  ,
"3d"  ,
NULL  ,
24  ,
0x158  ,
520000000  ,
mux_pllm_pllc_pllp_plla  ,
MUX|DIV_U71|DIV_U71_INT|DIV_U71_IDLE|  PERIPH_MANUAL_RESET 
)
PERIPH_CLK ( 3d2  ,
"3d2"  ,
NULL  ,
98  ,
0x3b0  ,
520000000  ,
mux_pllm_pllc_pllp_plla  ,
MUX|DIV_U71|DIV_U71_INT|DIV_U71_IDLE|  PERIPH_MANUAL_RESET 
)
PERIPH_CLK ( 2d  ,
"2d"  ,
NULL  ,
21  ,
0x15c  ,
520000000  ,
mux_pllm_pllc_pllp_plla  ,
MUX|DIV_U71|DIV_U71_INT|  DIV_U71_IDLE 
)
PERIPH_CLK ( vi_sensor  ,
"tegra_camera"  ,
"vi_sensor"  ,
20  ,
0x1a8  ,
150000000  ,
mux_pllm_pllc_pllp_plla  ,
MUX|DIV_U71|  PERIPH_NO_RESET 
)
PERIPH_CLK ( epp  ,
"epp"  ,
NULL  ,
19  ,
0x16c  ,
520000000  ,
mux_pllm_pllc_pllp_plla  ,
MUX|DIV_U71|  DIV_U71_INT 
)
PERIPH_CLK ( mpe  ,
"mpe"  ,
NULL  ,
60  ,
0x170  ,
520000000  ,
mux_pllm_pllc_pllp_plla  ,
MUX|DIV_U71|  DIV_U71_INT 
)
PERIPH_CLK ( host1x  ,
"host1x"  ,
NULL  ,
28  ,
0x180  ,
260000000  ,
mux_pllm_pllc_pllp_plla  ,
MUX|DIV_U71|  DIV_U71_INT 
)
PERIPH_CLK ( cve  ,
"cve"  ,
NULL  ,
49  ,
0x140  ,
250000000  ,
mux_pllp_plld_pllc_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( tvo  ,
"tvo"  ,
NULL  ,
49  ,
0x188  ,
250000000  ,
mux_pllp_plld_pllc_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( dtv  ,
"dtv"  ,
NULL  ,
79  ,
0x1dc  ,
250000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( hdmi  ,
"hdmi"  ,
NULL  ,
51  ,
0x18c  ,
148500000  ,
mux_pllp_pllm_plld_plla_pllc_plld2_clkm  ,
MUX|MUX8|  DIV_U71 
)
PERIPH_CLK ( tvdac  ,
"tvdac"  ,
NULL  ,
53  ,
0x194  ,
220000000  ,
mux_pllp_plld_pllc_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( disp1  ,
"tegradc.0"  ,
NULL  ,
27  ,
0x138  ,
600000000  ,
mux_pllp_pllm_plld_plla_pllc_plld2_clkm  ,
MUX|  MUX8 
)
PERIPH_CLK ( disp2  ,
"tegradc.1"  ,
NULL  ,
26  ,
0x13c  ,
600000000  ,
mux_pllp_pllm_plld_plla_pllc_plld2_clkm  ,
MUX|  MUX8 
)
PERIPH_CLK ( usbd  ,
"fsl-tegra-udc"  ,
NULL  ,
22  ,
0  ,
480000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( usb2  ,
"tegra-ehci.1"  ,
NULL  ,
58  ,
0  ,
480000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( usb3  ,
"tegra-ehci.2"  ,
NULL  ,
59  ,
0  ,
480000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( dsia  ,
"tegradc.0"  ,
"dsia"  ,
48  ,
0  ,
500000000  ,
mux_plld_out0  ,
0   
)
PERIPH_CLK ( csi  ,
"tegra_camera"  ,
"csi"  ,
52  ,
0  ,
102000000  ,
mux_pllp_out3  ,
0   
)
PERIPH_CLK ( isp  ,
"tegra_camera"  ,
"isp"  ,
23  ,
0  ,
150000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( csus  ,
"tegra_camera"  ,
"csus"  ,
92  ,
0  ,
150000000  ,
mux_clk_m  ,
PERIPH_NO_RESET   
)
PERIPH_CLK ( tsensor  ,
"tegra-tsensor"  ,
NULL  ,
100  ,
0x3b8  ,
216000000  ,
mux_pllp_pllc_clkm_clk32  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( actmon  ,
"actmon"  ,
NULL  ,
119  ,
0x3e8  ,
216000000  ,
mux_pllp_pllc_clk32_clkm  ,
MUX|  DIV_U71 
)
PERIPH_CLK ( extern1  ,
"extern1"  ,
NULL  ,
120  ,
0x3ec  ,
216000000  ,
mux_plla_clk32_pllp_clkm_plle  ,
MUX|MUX8|  DIV_U71 
)
PERIPH_CLK ( extern2  ,
"extern2"  ,
NULL  ,
121  ,
0x3f0  ,
216000000  ,
mux_plla_clk32_pllp_clkm_plle  ,
MUX|MUX8|  DIV_U71 
)
PERIPH_CLK ( extern3  ,
"extern3"  ,
NULL  ,
122  ,
0x3f4  ,
216000000  ,
mux_plla_clk32_pllp_clkm_plle  ,
MUX|MUX8|  DIV_U71 
)
PERIPH_CLK ( i2cslow  ,
"i2cslow"  ,
NULL  ,
81  ,
0x3fc  ,
26000000  ,
mux_pllp_pllc_clk32_clkm  ,
MUX|DIV_U71|  PERIPH_ON_APB 
)
PERIPH_CLK ( pcie  ,
"tegra-pcie"  ,
"pcie"  ,
70  ,
0  ,
250000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( afi  ,
"tegra-pcie"  ,
"afi"  ,
72  ,
0  ,
250000000  ,
mux_clk_m  ,
0   
)
PERIPH_CLK ( se  ,
"se"  ,
NULL  ,
127  ,
0x42c  ,
520000000  ,
mux_pllp_pllc_pllm_clkm  ,
MUX|DIV_U71|  DIV_U71_INT 
)
SYNC_SOURCE ( spdif_in  )
SYNC_SOURCE ( i2s0  )
SYNC_SOURCE ( i2s1  )
SYNC_SOURCE ( i2s2  )
SYNC_SOURCE ( i2s3  )
SYNC_SOURCE ( i2s4  )
SYNC_SOURCE ( vimclk  )
void __init tegra30_init_clocks ( void  )

Definition at line 1344 of file tegra30_clocks_data.c.

Variable Documentation

struct clk_duplicate tegra_clk_duplicates[]

Definition at line 1248 of file tegra30_clocks_data.c.

struct clk* tegra_list_clks[]

Definition at line 1142 of file tegra30_clocks_data.c.

struct clk* tegra_ptr_clks[]

Definition at line 1298 of file tegra30_clocks_data.c.

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