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radeon_pm.c
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1 /*
2  * drivers/video/aty/radeon_pm.c
3  *
4  * Copyright 2003,2004 Ben. Herrenschmidt <[email protected]>
5  * Copyright 2004 Paul Mackerras <[email protected]>
6  *
7  * This is the power management code for ATI radeon chipsets. It contains
8  * some dynamic clock PM enable/disable code similar to what X.org does,
9  * some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs,
10  * and the necessary bits to re-initialize from scratch a few chips found
11  * on PowerMacs as well. The later could be extended to more platforms
12  * provided the memory controller configuration code be made more generic,
13  * and you can get the proper mode register commands for your RAMs.
14  * Those things may be found in the BIOS image...
15  */
16 
17 #include "radeonfb.h"
18 
19 #include <linux/console.h>
20 #include <linux/agp_backend.h>
21 
22 #ifdef CONFIG_PPC_PMAC
23 #include <asm/machdep.h>
24 #include <asm/prom.h>
25 #include <asm/pmac_feature.h>
26 #endif
27 
28 #include "ati_ids.h"
29 
30 /*
31  * Workarounds for bugs in PC laptops:
32  * - enable D2 sleep in some IBM Thinkpads
33  * - special case for Samsung P35
34  *
35  * Whitelist by subsystem vendor/device because
36  * its the subsystem vendor's fault!
37  */
38 
39 #if defined(CONFIG_PM) && defined(CONFIG_X86)
40 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo);
41 
42 struct radeon_device_id {
43  const char *ident; /* (arbitrary) Name */
44  const unsigned short subsystem_vendor; /* Subsystem Vendor ID */
45  const unsigned short subsystem_device; /* Subsystem Device ID */
46  const enum radeon_pm_mode pm_mode_modifier; /* modify pm_mode */
47  const reinit_function_ptr new_reinit_func; /* changed reinit_func */
48 };
49 
50 #define BUGFIX(model, sv, sd, pm, fn) { \
51  .ident = model, \
52  .subsystem_vendor = sv, \
53  .subsystem_device = sd, \
54  .pm_mode_modifier = pm, \
55  .new_reinit_func = fn \
56 }
57 
58 static struct radeon_device_id radeon_workaround_list[] = {
59  BUGFIX("IBM Thinkpad R32",
60  PCI_VENDOR_ID_IBM, 0x1905,
61  radeon_pm_d2, NULL),
62  BUGFIX("IBM Thinkpad R40",
63  PCI_VENDOR_ID_IBM, 0x0526,
64  radeon_pm_d2, NULL),
65  BUGFIX("IBM Thinkpad R40",
66  PCI_VENDOR_ID_IBM, 0x0527,
67  radeon_pm_d2, NULL),
68  BUGFIX("IBM Thinkpad R50/R51/T40/T41",
69  PCI_VENDOR_ID_IBM, 0x0531,
70  radeon_pm_d2, NULL),
71  BUGFIX("IBM Thinkpad R51/T40/T41/T42",
72  PCI_VENDOR_ID_IBM, 0x0530,
73  radeon_pm_d2, NULL),
74  BUGFIX("IBM Thinkpad T30",
75  PCI_VENDOR_ID_IBM, 0x0517,
76  radeon_pm_d2, NULL),
77  BUGFIX("IBM Thinkpad T40p",
78  PCI_VENDOR_ID_IBM, 0x054d,
79  radeon_pm_d2, NULL),
80  BUGFIX("IBM Thinkpad T42",
81  PCI_VENDOR_ID_IBM, 0x0550,
82  radeon_pm_d2, NULL),
83  BUGFIX("IBM Thinkpad X31/X32",
84  PCI_VENDOR_ID_IBM, 0x052f,
85  radeon_pm_d2, NULL),
86  BUGFIX("Samsung P35",
87  PCI_VENDOR_ID_SAMSUNG, 0xc00c,
88  radeon_pm_off, radeon_reinitialize_M10),
89  BUGFIX("Acer Aspire 2010",
90  PCI_VENDOR_ID_AI, 0x0061,
91  radeon_pm_off, radeon_reinitialize_M10),
92  BUGFIX("Acer Travelmate 290D/292LMi",
93  PCI_VENDOR_ID_AI, 0x005a,
94  radeon_pm_off, radeon_reinitialize_M10),
95  { .ident = NULL }
96 };
97 
98 static int radeon_apply_workarounds(struct radeonfb_info *rinfo)
99 {
100  struct radeon_device_id *id;
101 
102  for (id = radeon_workaround_list; id->ident != NULL; id++ )
103  if ((id->subsystem_vendor == rinfo->pdev->subsystem_vendor ) &&
104  (id->subsystem_device == rinfo->pdev->subsystem_device )) {
105 
106  /* we found a device that requires workaround */
107  printk(KERN_DEBUG "radeonfb: %s detected"
108  ", enabling workaround\n", id->ident);
109 
110  rinfo->pm_mode |= id->pm_mode_modifier;
111 
112  if (id->new_reinit_func != NULL)
113  rinfo->reinit_func = id->new_reinit_func;
114 
115  return 1;
116  }
117  return 0; /* not found */
118 }
119 
120 #else /* defined(CONFIG_PM) && defined(CONFIG_X86) */
121 static inline int radeon_apply_workarounds(struct radeonfb_info *rinfo)
122 {
123  return 0;
124 }
125 #endif /* defined(CONFIG_PM) && defined(CONFIG_X86) */
126 
127 
128 
129 static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
130 {
131  u32 tmp;
132 
133  /* RV100 */
134  if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) {
135  if (rinfo->has_CRTC2) {
136  tmp = INPLL(pllSCLK_CNTL);
137  tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK;
138  tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK;
139  OUTPLL(pllSCLK_CNTL, tmp);
140  }
141  tmp = INPLL(pllMCLK_CNTL);
142  tmp |= (MCLK_CNTL__FORCE_MCLKA |
143  MCLK_CNTL__FORCE_MCLKB |
144  MCLK_CNTL__FORCE_YCLKA |
145  MCLK_CNTL__FORCE_YCLKB |
146  MCLK_CNTL__FORCE_AIC |
147  MCLK_CNTL__FORCE_MC);
148  OUTPLL(pllMCLK_CNTL, tmp);
149  return;
150  }
151  /* R100 */
152  if (!rinfo->has_CRTC2) {
153  tmp = INPLL(pllSCLK_CNTL);
154  tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_HDP |
155  SCLK_CNTL__FORCE_DISP1 | SCLK_CNTL__FORCE_TOP |
156  SCLK_CNTL__FORCE_E2 | SCLK_CNTL__FORCE_SE |
157  SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_VIP |
158  SCLK_CNTL__FORCE_RE | SCLK_CNTL__FORCE_PB |
159  SCLK_CNTL__FORCE_TAM | SCLK_CNTL__FORCE_TDM |
160  SCLK_CNTL__FORCE_RB);
161  OUTPLL(pllSCLK_CNTL, tmp);
162  return;
163  }
164  /* RV350 (M10/M11) */
165  if (rinfo->family == CHIP_FAMILY_RV350) {
166  /* for RV350/M10/M11, no delays are required. */
167  tmp = INPLL(pllSCLK_CNTL2);
168  tmp |= (SCLK_CNTL2__R300_FORCE_TCL |
169  SCLK_CNTL2__R300_FORCE_GA |
170  SCLK_CNTL2__R300_FORCE_CBA);
171  OUTPLL(pllSCLK_CNTL2, tmp);
172 
173  tmp = INPLL(pllSCLK_CNTL);
174  tmp |= (SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP |
175  SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
176  SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 |
177  SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
178  SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR |
179  SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
180  SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
181  SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
182  OUTPLL(pllSCLK_CNTL, tmp);
183 
184  tmp = INPLL(pllSCLK_MORE_CNTL);
185  tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS | SCLK_MORE_CNTL__FORCE_MC_GUI |
186  SCLK_MORE_CNTL__FORCE_MC_HOST);
187  OUTPLL(pllSCLK_MORE_CNTL, tmp);
188 
189  tmp = INPLL(pllMCLK_CNTL);
190  tmp |= (MCLK_CNTL__FORCE_MCLKA |
191  MCLK_CNTL__FORCE_MCLKB |
192  MCLK_CNTL__FORCE_YCLKA |
193  MCLK_CNTL__FORCE_YCLKB |
194  MCLK_CNTL__FORCE_MC);
195  OUTPLL(pllMCLK_CNTL, tmp);
196 
197  tmp = INPLL(pllVCLK_ECP_CNTL);
198  tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
199  VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb |
200  VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
201  OUTPLL(pllVCLK_ECP_CNTL, tmp);
202 
203  tmp = INPLL(pllPIXCLKS_CNTL);
204  tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
205  PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb |
206  PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
207  PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb |
208  PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb |
209  PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
210  PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb |
211  PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb |
212  PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb |
213  PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb |
214  PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb |
215  PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
216  PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
217  OUTPLL(pllPIXCLKS_CNTL, tmp);
218 
219  return;
220  }
221 
222  /* Default */
223 
224  /* Force Core Clocks */
225  tmp = INPLL(pllSCLK_CNTL);
226  tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2);
227 
228  /* XFree doesn't do that case, but we had this code from Apple and it
229  * seem necessary for proper suspend/resume operations
230  */
231  if (rinfo->is_mobility) {
232  tmp |= SCLK_CNTL__FORCE_HDP|
233  SCLK_CNTL__FORCE_DISP1|
234  SCLK_CNTL__FORCE_DISP2|
235  SCLK_CNTL__FORCE_TOP|
236  SCLK_CNTL__FORCE_SE|
237  SCLK_CNTL__FORCE_IDCT|
238  SCLK_CNTL__FORCE_VIP|
239  SCLK_CNTL__FORCE_PB|
240  SCLK_CNTL__FORCE_RE|
241  SCLK_CNTL__FORCE_TAM|
242  SCLK_CNTL__FORCE_TDM|
243  SCLK_CNTL__FORCE_RB|
244  SCLK_CNTL__FORCE_TV_SCLK|
245  SCLK_CNTL__FORCE_SUBPIC|
246  SCLK_CNTL__FORCE_OV0;
247  }
248  else if (rinfo->family == CHIP_FAMILY_R300 ||
249  rinfo->family == CHIP_FAMILY_R350) {
250  tmp |= SCLK_CNTL__FORCE_HDP |
251  SCLK_CNTL__FORCE_DISP1 |
252  SCLK_CNTL__FORCE_DISP2 |
253  SCLK_CNTL__FORCE_TOP |
254  SCLK_CNTL__FORCE_IDCT |
255  SCLK_CNTL__FORCE_VIP;
256  }
257  OUTPLL(pllSCLK_CNTL, tmp);
258  radeon_msleep(16);
259 
260  if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
261  tmp = INPLL(pllSCLK_CNTL2);
262  tmp |= SCLK_CNTL2__R300_FORCE_TCL |
263  SCLK_CNTL2__R300_FORCE_GA |
264  SCLK_CNTL2__R300_FORCE_CBA;
265  OUTPLL(pllSCLK_CNTL2, tmp);
266  radeon_msleep(16);
267  }
268 
269  tmp = INPLL(pllCLK_PIN_CNTL);
270  tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
271  OUTPLL(pllCLK_PIN_CNTL, tmp);
272  radeon_msleep(15);
273 
274  if (rinfo->is_IGP) {
275  /* Weird ... X is _un_ forcing clocks here, I think it's
276  * doing backward. Imitate it for now...
277  */
278  tmp = INPLL(pllMCLK_CNTL);
279  tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
280  MCLK_CNTL__FORCE_YCLKA);
281  OUTPLL(pllMCLK_CNTL, tmp);
282  radeon_msleep(16);
283  }
284  /* Hrm... same shit, X doesn't do that but I have to */
285  else if (rinfo->is_mobility) {
286  tmp = INPLL(pllMCLK_CNTL);
287  tmp |= (MCLK_CNTL__FORCE_MCLKA |
288  MCLK_CNTL__FORCE_MCLKB |
289  MCLK_CNTL__FORCE_YCLKA |
290  MCLK_CNTL__FORCE_YCLKB);
291  OUTPLL(pllMCLK_CNTL, tmp);
292  radeon_msleep(16);
293 
294  tmp = INPLL(pllMCLK_MISC);
295  tmp &= ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
296  MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
297  MCLK_MISC__MC_MCLK_DYN_ENABLE|
298  MCLK_MISC__IO_MCLK_DYN_ENABLE);
299  OUTPLL(pllMCLK_MISC, tmp);
300  radeon_msleep(15);
301  }
302 
303  if (rinfo->is_mobility) {
304  tmp = INPLL(pllSCLK_MORE_CNTL);
305  tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS|
306  SCLK_MORE_CNTL__FORCE_MC_GUI|
307  SCLK_MORE_CNTL__FORCE_MC_HOST;
308  OUTPLL(pllSCLK_MORE_CNTL, tmp);
309  radeon_msleep(16);
310  }
311 
312  tmp = INPLL(pllPIXCLKS_CNTL);
313  tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
314  PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
315  PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
316  PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
317  PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
318  PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
319  PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
320  OUTPLL(pllPIXCLKS_CNTL, tmp);
321  radeon_msleep(16);
322 
323  tmp = INPLL( pllVCLK_ECP_CNTL);
324  tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
325  VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
326  OUTPLL( pllVCLK_ECP_CNTL, tmp);
327  radeon_msleep(16);
328 }
329 
330 static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
331 {
332  u32 tmp;
333 
334  /* R100 */
335  if (!rinfo->has_CRTC2) {
336  tmp = INPLL(pllSCLK_CNTL);
337 
338  if ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13)
339  tmp &= ~(SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_RB);
340  tmp &= ~(SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
341  SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_SE |
342  SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_RE |
343  SCLK_CNTL__FORCE_PB | SCLK_CNTL__FORCE_TAM |
344  SCLK_CNTL__FORCE_TDM);
345  OUTPLL(pllSCLK_CNTL, tmp);
346  return;
347  }
348 
349  /* M10/M11 */
350  if (rinfo->family == CHIP_FAMILY_RV350) {
351  tmp = INPLL(pllSCLK_CNTL2);
352  tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
353  SCLK_CNTL2__R300_FORCE_GA |
354  SCLK_CNTL2__R300_FORCE_CBA);
355  tmp |= (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT |
356  SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT |
357  SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT);
358  OUTPLL(pllSCLK_CNTL2, tmp);
359 
360  tmp = INPLL(pllSCLK_CNTL);
361  tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP |
362  SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
363  SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 |
364  SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
365  SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR |
366  SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
367  SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
368  SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
369  tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK;
370  OUTPLL(pllSCLK_CNTL, tmp);
371 
372  tmp = INPLL(pllSCLK_MORE_CNTL);
373  tmp &= ~SCLK_MORE_CNTL__FORCEON;
374  tmp |= SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT |
375  SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT |
376  SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT;
377  OUTPLL(pllSCLK_MORE_CNTL, tmp);
378 
379  tmp = INPLL(pllVCLK_ECP_CNTL);
380  tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
381  VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
382  OUTPLL(pllVCLK_ECP_CNTL, tmp);
383 
384  tmp = INPLL(pllPIXCLKS_CNTL);
385  tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
386  PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb |
387  PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
388  PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb |
389  PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb |
390  PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
391  PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb |
392  PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb |
393  PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb |
394  PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb |
395  PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb |
396  PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
397  PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb);
398  OUTPLL(pllPIXCLKS_CNTL, tmp);
399 
400  tmp = INPLL(pllMCLK_MISC);
401  tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE |
402  MCLK_MISC__IO_MCLK_DYN_ENABLE);
403  OUTPLL(pllMCLK_MISC, tmp);
404 
405  tmp = INPLL(pllMCLK_CNTL);
406  tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB);
407  tmp &= ~(MCLK_CNTL__FORCE_YCLKA |
408  MCLK_CNTL__FORCE_YCLKB |
409  MCLK_CNTL__FORCE_MC);
410 
411  /* Some releases of vbios have set DISABLE_MC_MCLKA
412  * and DISABLE_MC_MCLKB bits in the vbios table. Setting these
413  * bits will cause H/W hang when reading video memory with dynamic
414  * clocking enabled.
415  */
416  if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) &&
417  (tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) {
418  /* If both bits are set, then check the active channels */
419  tmp = INPLL(pllMCLK_CNTL);
420  if (rinfo->vram_width == 64) {
421  if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
422  tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB;
423  else
424  tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA;
425  } else {
426  tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA |
427  MCLK_CNTL__R300_DISABLE_MC_MCLKB);
428  }
429  }
430  OUTPLL(pllMCLK_CNTL, tmp);
431  return;
432  }
433 
434  /* R300 */
435  if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
436  tmp = INPLL(pllSCLK_CNTL);
437  tmp &= ~(SCLK_CNTL__R300_FORCE_VAP);
438  tmp |= SCLK_CNTL__FORCE_CP;
439  OUTPLL(pllSCLK_CNTL, tmp);
440  radeon_msleep(15);
441 
442  tmp = INPLL(pllSCLK_CNTL2);
443  tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
444  SCLK_CNTL2__R300_FORCE_GA |
445  SCLK_CNTL2__R300_FORCE_CBA);
446  OUTPLL(pllSCLK_CNTL2, tmp);
447  }
448 
449  /* Others */
450 
451  tmp = INPLL( pllCLK_PWRMGT_CNTL);
452  tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
453  CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK|
454  CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK);
455  tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK |
456  (0x01 << CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT);
457  OUTPLL( pllCLK_PWRMGT_CNTL, tmp);
458  radeon_msleep(15);
459 
460  tmp = INPLL(pllCLK_PIN_CNTL);
461  tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
462  OUTPLL(pllCLK_PIN_CNTL, tmp);
463  radeon_msleep(15);
464 
465  /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
466  * to lockup randomly, leave them as set by BIOS.
467  */
468  tmp = INPLL(pllSCLK_CNTL);
469  tmp &= ~SCLK_CNTL__FORCEON_MASK;
470 
471  /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
472  if ((rinfo->family == CHIP_FAMILY_RV250 &&
473  ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) ||
474  ((rinfo->family == CHIP_FAMILY_RV100) &&
475  ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) {
476  tmp |= SCLK_CNTL__FORCE_CP;
477  tmp |= SCLK_CNTL__FORCE_VIP;
478  }
479  OUTPLL(pllSCLK_CNTL, tmp);
480  radeon_msleep(15);
481 
482  if ((rinfo->family == CHIP_FAMILY_RV200) ||
483  (rinfo->family == CHIP_FAMILY_RV250) ||
484  (rinfo->family == CHIP_FAMILY_RV280)) {
485  tmp = INPLL(pllSCLK_MORE_CNTL);
486  tmp &= ~SCLK_MORE_CNTL__FORCEON;
487 
488  /* RV200::A11 A12 RV250::A11 A12 */
489  if (((rinfo->family == CHIP_FAMILY_RV200) ||
490  (rinfo->family == CHIP_FAMILY_RV250)) &&
491  ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13))
492  tmp |= SCLK_MORE_CNTL__FORCEON;
493 
494  OUTPLL(pllSCLK_MORE_CNTL, tmp);
495  radeon_msleep(15);
496  }
497 
498 
499  /* RV200::A11 A12, RV250::A11 A12 */
500  if (((rinfo->family == CHIP_FAMILY_RV200) ||
501  (rinfo->family == CHIP_FAMILY_RV250)) &&
502  ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) {
503  tmp = INPLL(pllPLL_PWRMGT_CNTL);
504  tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE;
505  OUTPLL(pllPLL_PWRMGT_CNTL, tmp);
506  radeon_msleep(15);
507  }
508 
509  tmp = INPLL(pllPIXCLKS_CNTL);
510  tmp |= PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
511  PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb|
512  PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
513  PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb|
514  PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb|
515  PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
516  PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb;
517  OUTPLL(pllPIXCLKS_CNTL, tmp);
518  radeon_msleep(15);
519 
520  tmp = INPLL(pllVCLK_ECP_CNTL);
521  tmp |= VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
522  VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb;
523  OUTPLL(pllVCLK_ECP_CNTL, tmp);
524 
525  /* X doesn't do that ... hrm, we do on mobility && Macs */
526 #ifdef CONFIG_PPC_OF
527  if (rinfo->is_mobility) {
528  tmp = INPLL(pllMCLK_CNTL);
529  tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
530  MCLK_CNTL__FORCE_MCLKB |
531  MCLK_CNTL__FORCE_YCLKA |
532  MCLK_CNTL__FORCE_YCLKB);
533  OUTPLL(pllMCLK_CNTL, tmp);
534  radeon_msleep(15);
535 
536  tmp = INPLL(pllMCLK_MISC);
537  tmp |= MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
538  MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
539  MCLK_MISC__MC_MCLK_DYN_ENABLE|
540  MCLK_MISC__IO_MCLK_DYN_ENABLE;
541  OUTPLL(pllMCLK_MISC, tmp);
542  radeon_msleep(15);
543  }
544 #endif /* CONFIG_PPC_OF */
545 }
546 
547 #ifdef CONFIG_PM
548 
549 static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value)
550 {
551  OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN);
552  OUTREG( MC_IND_DATA, value);
553 }
554 
555 static u32 INMC(struct radeonfb_info *rinfo, u8 indx)
556 {
557  OUTREG( MC_IND_INDEX, indx);
558  return INREG( MC_IND_DATA);
559 }
560 
561 static void radeon_pm_save_regs(struct radeonfb_info *rinfo, int saving_for_d3)
562 {
563  rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
564  rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
565  rinfo->save_regs[2] = INPLL(MCLK_CNTL);
566  rinfo->save_regs[3] = INPLL(SCLK_CNTL);
567  rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
568  rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
569  rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
570  rinfo->save_regs[7] = INPLL(MCLK_MISC);
571  rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
572 
573  rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
574  rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
575  rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
576  rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
577  rinfo->save_regs[14] = INREG(BUS_CNTL1);
578  rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
579  rinfo->save_regs[16] = INREG(AGP_CNTL);
580  rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
581  rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
582  rinfo->save_regs[19] = INREG(GPIOPAD_A);
583  rinfo->save_regs[20] = INREG(GPIOPAD_EN);
584  rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
585  rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
586  rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
587  rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
588  rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
589  rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
590  rinfo->save_regs[27] = INREG(GPIO_MONID);
591  rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
592 
593  rinfo->save_regs[29] = INREG(SURFACE_CNTL);
594  rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
595  rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
596  rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
597  rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
598 
599  rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL);
600  rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG);
601  rinfo->save_regs[36] = INREG(BUS_CNTL);
602  rinfo->save_regs[39] = INREG(RBBM_CNTL);
603  rinfo->save_regs[40] = INREG(DAC_CNTL);
604  rinfo->save_regs[41] = INREG(HOST_PATH_CNTL);
605  rinfo->save_regs[37] = INREG(MPP_TB_CONFIG);
606  rinfo->save_regs[38] = INREG(FCP_CNTL);
607 
608  if (rinfo->is_mobility) {
609  rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
610  rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL);
611  rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV);
612  rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0);
613  rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL);
614  rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL);
615  rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL);
616  }
617 
618  if (rinfo->family >= CHIP_FAMILY_RV200) {
619  rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL);
620  rinfo->save_regs[46] = INREG(MC_CNTL);
621  rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER);
622  rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER);
623  rinfo->save_regs[49] = INREG(MC_TIMING_CNTL);
624  rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB);
625  rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL);
626  rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB);
627  rinfo->save_regs[53] = INREG(MC_DEBUG);
628  }
629  rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL);
630  rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL);
631  rinfo->save_regs[56] = INREG(PAD_CTLR_MISC);
632  rinfo->save_regs[57] = INREG(FW_CNTL);
633 
634  if (rinfo->family >= CHIP_FAMILY_R300) {
635  rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER);
636  rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL);
637  rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0);
638  rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1);
639  rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0);
640  rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1);
641  rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3);
642  rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0);
643  rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1);
644  rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0);
645  rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1);
646  rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL);
647  rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL);
648  rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0);
649  rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL);
650  rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD);
651  } else {
652  rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL);
653  rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0);
654  rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1);
655  rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0);
656  rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1);
657  rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0);
658  }
659 
660  rinfo->save_regs[73] = INPLL(pllMPLL_CNTL);
661  rinfo->save_regs[74] = INPLL(pllSPLL_CNTL);
662  rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL);
663  rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL);
664  rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV);
665  rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL);
666  rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL);
667 
668  rinfo->save_regs[80] = INREG(OV0_BASE_ADDR);
669  rinfo->save_regs[82] = INREG(FP_GEN_CNTL);
670  rinfo->save_regs[83] = INREG(FP2_GEN_CNTL);
671  rinfo->save_regs[84] = INREG(TMDS_CNTL);
672  rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL);
673  rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL);
674  rinfo->save_regs[87] = INREG(DISP_HW_DEBUG);
675  rinfo->save_regs[88] = INREG(TV_MASTER_CNTL);
676  rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV);
677  rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0);
678  rinfo->save_regs[93] = INPLL(pllPPLL_CNTL);
679  rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL);
680  rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL);
681  rinfo->save_regs[96] = INREG(HDP_DEBUG);
682  rinfo->save_regs[97] = INPLL(pllMDLL_CKO);
683  rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA);
684  rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB);
685 }
686 
687 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
688 {
689  OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
690 
691  OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
692  OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
693  OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
694  OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
695  OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
696  OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
697  OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
698  OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
699  if (rinfo->family == CHIP_FAMILY_RV350)
700  OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]);
701 
702  OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
703  OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
704  OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
705  OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
706  OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
707  OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
708 
709  OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
710  OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
711  OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
712  OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
713  OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
714  OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
715  OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
716  OUTREG(AGP_CNTL, rinfo->save_regs[16]);
717  OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
718  OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
719  OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
720 
721  OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
722  OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
723  OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
724  OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
725  OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
726  OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
727  OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
728  OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
729  OUTREG(GPIO_MONID, rinfo->save_regs[27]);
730  OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
731 }
732 
733 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
734 {
735  OUTREG(GPIOPAD_MASK, 0x0001ffff);
736  OUTREG(GPIOPAD_EN, 0x00000400);
737  OUTREG(GPIOPAD_A, 0x00000000);
738  OUTREG(ZV_LCDPAD_MASK, 0x00000000);
739  OUTREG(ZV_LCDPAD_EN, 0x00000000);
740  OUTREG(ZV_LCDPAD_A, 0x00000000);
741  OUTREG(GPIO_VGA_DDC, 0x00030000);
742  OUTREG(GPIO_DVI_DDC, 0x00000000);
743  OUTREG(GPIO_MONID, 0x00030000);
744  OUTREG(GPIO_CRT2_DDC, 0x00000000);
745 }
746 
747 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
748 {
749  /* Set v2clk to 65MHz */
750  if (rinfo->family <= CHIP_FAMILY_RV280) {
751  OUTPLL(pllPIXCLKS_CNTL,
752  __INPLL(rinfo, pllPIXCLKS_CNTL)
753  & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK);
754 
755  OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
756  OUTPLL(pllP2PLL_CNTL, 0x0000bf00);
757  } else {
758  OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
759  INPLL(pllP2PLL_REF_DIV);
760  OUTPLL(pllP2PLL_CNTL, 0x0000a700);
761  }
762 
763  OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W);
764 
765  OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);
766  mdelay(1);
767 
768  OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);
769  mdelay( 1);
770 
771  OUTPLL(pllPIXCLKS_CNTL,
772  (INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK)
773  | (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT));
774  mdelay( 1);
775 }
776 
777 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
778 {
779  u32 reg;
780 
781  reg = INREG(BUS_CNTL1);
782  if (rinfo->family <= CHIP_FAMILY_RV280) {
783  reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
784  reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
785  } else {
786  reg |= 0x4080;
787  }
788  OUTREG(BUS_CNTL1, reg);
789 
790  reg = INPLL(PLL_PWRMGT_CNTL);
791  reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
792  PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
793  reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
794  reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
795  OUTPLL(PLL_PWRMGT_CNTL, reg);
796 
797  reg = INREG(TV_DAC_CNTL);
798  reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
799  reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
800  TV_DAC_CNTL_BDACPD |
801  (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
802  OUTREG(TV_DAC_CNTL, reg);
803 
804  reg = INREG(TMDS_TRANSMITTER_CNTL);
805  reg &= ~(TMDS_PLL_EN | TMDS_PLLRST);
806  OUTREG(TMDS_TRANSMITTER_CNTL, reg);
807 
808  reg = INREG(DAC_CNTL);
809  reg &= ~DAC_CMP_EN;
810  OUTREG(DAC_CNTL, reg);
811 
812  reg = INREG(DAC_CNTL2);
813  reg &= ~DAC2_CMP_EN;
814  OUTREG(DAC_CNTL2, reg);
815 
816  reg = INREG(TV_DAC_CNTL);
817  reg &= ~TV_DAC_CNTL_DETECT;
818  OUTREG(TV_DAC_CNTL, reg);
819 }
820 
821 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
822 {
823 
824  u32 sclk_cntl, mclk_cntl, sclk_more_cntl;
825 
826  u32 pll_pwrmgt_cntl;
827  u32 clk_pwrmgt_cntl;
828  u32 clk_pin_cntl;
829  u32 vclk_ecp_cntl;
830  u32 pixclks_cntl;
831  u32 disp_mis_cntl;
832  u32 disp_pwr_man;
833  u32 tmp;
834 
835  /* Force Core Clocks */
836  sclk_cntl = INPLL( pllSCLK_CNTL);
837  sclk_cntl |= SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
838  SCLK_CNTL__VIP_MAX_DYN_STOP_LAT|
839  SCLK_CNTL__RE_MAX_DYN_STOP_LAT|
840  SCLK_CNTL__PB_MAX_DYN_STOP_LAT|
841  SCLK_CNTL__TAM_MAX_DYN_STOP_LAT|
842  SCLK_CNTL__TDM_MAX_DYN_STOP_LAT|
843  SCLK_CNTL__RB_MAX_DYN_STOP_LAT|
844 
845  SCLK_CNTL__FORCE_DISP2|
846  SCLK_CNTL__FORCE_CP|
847  SCLK_CNTL__FORCE_HDP|
848  SCLK_CNTL__FORCE_DISP1|
849  SCLK_CNTL__FORCE_TOP|
850  SCLK_CNTL__FORCE_E2|
851  SCLK_CNTL__FORCE_SE|
852  SCLK_CNTL__FORCE_IDCT|
853  SCLK_CNTL__FORCE_VIP|
854 
855  SCLK_CNTL__FORCE_PB|
856  SCLK_CNTL__FORCE_TAM|
857  SCLK_CNTL__FORCE_TDM|
858  SCLK_CNTL__FORCE_RB|
859  SCLK_CNTL__FORCE_TV_SCLK|
860  SCLK_CNTL__FORCE_SUBPIC|
861  SCLK_CNTL__FORCE_OV0;
862  if (rinfo->family <= CHIP_FAMILY_RV280)
863  sclk_cntl |= SCLK_CNTL__FORCE_RE;
864  else
865  sclk_cntl |= SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
866  SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
867  SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
868  SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
869  SCLK_CNTL__CP_MAX_DYN_STOP_LAT;
870 
871  OUTPLL( pllSCLK_CNTL, sclk_cntl);
872 
873  sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL);
874  sclk_more_cntl |= SCLK_MORE_CNTL__FORCE_DISPREGS |
875  SCLK_MORE_CNTL__FORCE_MC_GUI |
876  SCLK_MORE_CNTL__FORCE_MC_HOST;
877 
878  OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);
879 
880 
881  mclk_cntl = INPLL( pllMCLK_CNTL);
882  mclk_cntl &= ~( MCLK_CNTL__FORCE_MCLKA |
883  MCLK_CNTL__FORCE_MCLKB |
884  MCLK_CNTL__FORCE_YCLKA |
885  MCLK_CNTL__FORCE_YCLKB |
886  MCLK_CNTL__FORCE_MC
887  );
888  OUTPLL( pllMCLK_CNTL, mclk_cntl);
889 
890  /* Force Display clocks */
891  vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);
892  vclk_ecp_cntl &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
893  | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
894  vclk_ecp_cntl |= VCLK_ECP_CNTL__ECP_FORCE_ON;
895  OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);
896 
897 
898  pixclks_cntl = INPLL( pllPIXCLKS_CNTL);
899  pixclks_cntl &= ~( PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
900  PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
901  PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
902  PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
903  PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
904  PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
905  PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
906 
907  OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);
908 
909  /* Switch off LVDS interface */
910  OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) &
911  ~(LVDS_BLON | LVDS_EN | LVDS_ON | LVDS_DIGON));
912 
913  /* Enable System power management */
914  pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL);
915 
916  pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__SPLL_TURNOFF |
917  PLL_PWRMGT_CNTL__MPLL_TURNOFF|
918  PLL_PWRMGT_CNTL__PPLL_TURNOFF|
919  PLL_PWRMGT_CNTL__P2PLL_TURNOFF|
920  PLL_PWRMGT_CNTL__TVPLL_TURNOFF;
921 
922  OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
923 
924  clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
925 
926  clk_pwrmgt_cntl &= ~( CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF|
927  CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF|
928  CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF|
929  CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF|
930  CLK_PWRMGT_CNTL__MCLK_TURNOFF|
931  CLK_PWRMGT_CNTL__SCLK_TURNOFF|
932  CLK_PWRMGT_CNTL__PCLK_TURNOFF|
933  CLK_PWRMGT_CNTL__P2CLK_TURNOFF|
934  CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF|
935  CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN|
936  CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE|
937  CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
938  CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK
939  );
940 
941  clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN
942  | CLK_PWRMGT_CNTL__DISP_PM;
943 
944  OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
945 
946  clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
947 
948  clk_pin_cntl &= ~CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND;
949 
950  /* because both INPLL and OUTPLL take the same lock, that's why. */
951  tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND;
952  OUTPLL( pllMCLK_MISC, tmp);
953 
954  /* BUS_CNTL1__MOBILE_PLATORM_SEL setting is northbridge chipset
955  * and radeon chip dependent. Thus we only enable it on Mac for
956  * now (until we get more info on how to compute the correct
957  * value for various X86 bridges).
958  */
959 #ifdef CONFIG_PPC_PMAC
960  if (machine_is(powermac)) {
961  /* AGP PLL control */
962  if (rinfo->family <= CHIP_FAMILY_RV280) {
963  OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID);
964  OUTREG(BUS_CNTL1,
965  (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK)
966  | (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT)); // 440BX
967  } else {
968  OUTREG(BUS_CNTL1, INREG(BUS_CNTL1));
969  OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000);
970  }
971  }
972 #endif
973 
974  OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL)
975  & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN));
976 
977  clk_pin_cntl &= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN;
978  clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
979  OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
980 
981  /* Solano2M */
982  OUTREG(AGP_CNTL,
983  (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK))
984  | (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT));
985 
986  /* ACPI mode */
987  /* because both INPLL and OUTPLL take the same lock, that's why. */
988  tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL;
989  OUTPLL( pllPLL_PWRMGT_CNTL, tmp);
990 
991 
992  disp_mis_cntl = INREG(DISP_MISC_CNTL);
993 
994  disp_mis_cntl &= ~( DISP_MISC_CNTL__SOFT_RESET_GRPH_PP |
995  DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP |
996  DISP_MISC_CNTL__SOFT_RESET_OV0_PP |
997  DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK|
998  DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK|
999  DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK|
1000  DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP|
1001  DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK|
1002  DISP_MISC_CNTL__SOFT_RESET_LVDS|
1003  DISP_MISC_CNTL__SOFT_RESET_TMDS|
1004  DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS|
1005  DISP_MISC_CNTL__SOFT_RESET_TV);
1006 
1007  OUTREG(DISP_MISC_CNTL, disp_mis_cntl);
1008 
1009  disp_pwr_man = INREG(DISP_PWR_MAN);
1010 
1011  disp_pwr_man &= ~( DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN |
1012  DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN |
1013  DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK|
1014  DISP_PWR_MAN__DISP_D3_RST|
1015  DISP_PWR_MAN__DISP_D3_REG_RST
1016  );
1017 
1018  disp_pwr_man |= DISP_PWR_MAN__DISP_D3_GRPH_RST|
1019  DISP_PWR_MAN__DISP_D3_SUBPIC_RST|
1020  DISP_PWR_MAN__DISP_D3_OV0_RST|
1021  DISP_PWR_MAN__DISP_D1D2_GRPH_RST|
1022  DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST|
1023  DISP_PWR_MAN__DISP_D1D2_OV0_RST|
1024  DISP_PWR_MAN__DIG_TMDS_ENABLE_RST|
1025  DISP_PWR_MAN__TV_ENABLE_RST|
1026 // DISP_PWR_MAN__AUTO_PWRUP_EN|
1027  0;
1028 
1029  OUTREG(DISP_PWR_MAN, disp_pwr_man);
1030 
1031  clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
1032  pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ;
1033  clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
1034  disp_pwr_man = INREG(DISP_PWR_MAN);
1035 
1036 
1037  /* D2 */
1038  clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__DISP_PM;
1039  pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__MOBILE_SU | PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK;
1040  clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
1041  disp_pwr_man &= ~(DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK
1042  | DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK);
1043 
1044  OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
1045  OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
1046  OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
1047  OUTREG(DISP_PWR_MAN, disp_pwr_man);
1048 
1049  /* disable display request & disable display */
1050  OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN)
1051  | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1052  OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN)
1053  | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1054 
1055  mdelay(17);
1056 
1057 }
1058 
1059 static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo)
1060 {
1061  u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
1062 
1063  mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1)
1064  & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
1065  mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1)
1066  & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
1067 
1068  OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1
1069  | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
1070  OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1
1071  | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
1072 
1073  OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1074  OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1075 
1076  mdelay( 1);
1077 }
1078 
1079 static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info *rinfo)
1080 {
1081  u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
1082 
1083  mc_chp_io_cntl_a1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1)
1084  & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
1085  mc_chp_io_cntl_b1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1)
1086  & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
1087 
1088  OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1,
1089  mc_chp_io_cntl_a1 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
1090  OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1,
1091  mc_chp_io_cntl_b1 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
1092 
1093  OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1094  OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1095 
1096  mdelay( 1);
1097 }
1098 
1099 static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value,
1100  u8 delay_required)
1101 {
1102  u32 mem_sdram_mode;
1103 
1104  mem_sdram_mode = INREG( MEM_SDRAM_MODE_REG);
1105 
1106  mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK;
1107  mem_sdram_mode |= (value<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT)
1108  | MEM_SDRAM_MODE_REG__MEM_CFG_TYPE;
1109  OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1110  if (delay_required >= 2)
1111  mdelay(1);
1112 
1113  mem_sdram_mode |= MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1114  OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1115  if (delay_required >= 2)
1116  mdelay(1);
1117 
1118  mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1119  OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1120  if (delay_required >= 2)
1121  mdelay(1);
1122 
1123  if (delay_required) {
1124  do {
1125  if (delay_required >= 2)
1126  mdelay(1);
1127  } while ((INREG(MC_STATUS)
1128  & (MC_STATUS__MEM_PWRUP_COMPL_A |
1129  MC_STATUS__MEM_PWRUP_COMPL_B)) == 0);
1130  }
1131 }
1132 
1133 static void radeon_pm_m10_program_mode_wait(struct radeonfb_info *rinfo)
1134 {
1135  int cnt;
1136 
1137  for (cnt = 0; cnt < 100; ++cnt) {
1138  mdelay(1);
1139  if (INREG(MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A
1140  | MC_STATUS__MEM_PWRUP_COMPL_B))
1141  break;
1142  }
1143 }
1144 
1145 
1146 static void radeon_pm_enable_dll(struct radeonfb_info *rinfo)
1147 {
1148 #define DLL_RESET_DELAY 5
1149 #define DLL_SLEEP_DELAY 1
1150 
1151  u32 cko = INPLL(pllMDLL_CKO) | MDLL_CKO__MCKOA_SLEEP
1152  | MDLL_CKO__MCKOA_RESET;
1153  u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP
1154  | MDLL_RDCKA__MRDCKA1_SLEEP | MDLL_RDCKA__MRDCKA0_RESET
1155  | MDLL_RDCKA__MRDCKA1_RESET;
1156  u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP
1157  | MDLL_RDCKB__MRDCKB1_SLEEP | MDLL_RDCKB__MRDCKB0_RESET
1158  | MDLL_RDCKB__MRDCKB1_RESET;
1159 
1160  /* Setting up the DLL range for write */
1161  OUTPLL(pllMDLL_CKO, cko);
1162  OUTPLL(pllMDLL_RDCKA, cka);
1163  OUTPLL(pllMDLL_RDCKB, ckb);
1164 
1165  mdelay(DLL_RESET_DELAY*2);
1166 
1167  cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
1168  OUTPLL(pllMDLL_CKO, cko);
1169  mdelay(DLL_SLEEP_DELAY);
1170  cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
1171  OUTPLL(pllMDLL_CKO, cko);
1172  mdelay(DLL_RESET_DELAY);
1173 
1174  cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
1175  OUTPLL(pllMDLL_RDCKA, cka);
1176  mdelay(DLL_SLEEP_DELAY);
1177  cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
1178  OUTPLL(pllMDLL_RDCKA, cka);
1179  mdelay(DLL_RESET_DELAY);
1180 
1181  ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
1182  OUTPLL(pllMDLL_RDCKB, ckb);
1183  mdelay(DLL_SLEEP_DELAY);
1184  ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
1185  OUTPLL(pllMDLL_RDCKB, ckb);
1186  mdelay(DLL_RESET_DELAY);
1187 
1188 
1189 #undef DLL_RESET_DELAY
1190 #undef DLL_SLEEP_DELAY
1191 }
1192 
1193 static void radeon_pm_enable_dll_m10(struct radeonfb_info *rinfo)
1194 {
1195  u32 dll_value;
1196  u32 dll_sleep_mask = 0;
1197  u32 dll_reset_mask = 0;
1198  u32 mc;
1199 
1200 #define DLL_RESET_DELAY 5
1201 #define DLL_SLEEP_DELAY 1
1202 
1203  OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1204  mc = INREG(MC_CNTL);
1205  /* Check which channels are enabled */
1206  switch (mc & 0x3) {
1207  case 1:
1208  if (mc & 0x4)
1209  break;
1210  case 2:
1211  dll_sleep_mask |= MDLL_R300_RDCK__MRDCKB_SLEEP;
1212  dll_reset_mask |= MDLL_R300_RDCK__MRDCKB_RESET;
1213  case 0:
1214  dll_sleep_mask |= MDLL_R300_RDCK__MRDCKA_SLEEP;
1215  dll_reset_mask |= MDLL_R300_RDCK__MRDCKA_RESET;
1216  }
1217  switch (mc & 0x3) {
1218  case 1:
1219  if (!(mc & 0x4))
1220  break;
1221  case 2:
1222  dll_sleep_mask |= MDLL_R300_RDCK__MRDCKD_SLEEP;
1223  dll_reset_mask |= MDLL_R300_RDCK__MRDCKD_RESET;
1224  dll_sleep_mask |= MDLL_R300_RDCK__MRDCKC_SLEEP;
1225  dll_reset_mask |= MDLL_R300_RDCK__MRDCKC_RESET;
1226  }
1227 
1228  dll_value = INPLL(pllMDLL_RDCKA);
1229 
1230  /* Power Up */
1231  dll_value &= ~(dll_sleep_mask);
1232  OUTPLL(pllMDLL_RDCKA, dll_value);
1233  mdelay( DLL_SLEEP_DELAY);
1234 
1235  dll_value &= ~(dll_reset_mask);
1236  OUTPLL(pllMDLL_RDCKA, dll_value);
1237  mdelay( DLL_RESET_DELAY);
1238 
1239 #undef DLL_RESET_DELAY
1240 #undef DLL_SLEEP_DELAY
1241 }
1242 
1243 
1244 static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo)
1245 {
1246  u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl,
1247  fp_gen_cntl, fp2_gen_cntl;
1248 
1249  crtcGenCntl = INREG( CRTC_GEN_CNTL);
1250  crtcGenCntl2 = INREG( CRTC2_GEN_CNTL);
1251 
1252  crtc_more_cntl = INREG( CRTC_MORE_CNTL);
1253  fp_gen_cntl = INREG( FP_GEN_CNTL);
1254  fp2_gen_cntl = INREG( FP2_GEN_CNTL);
1255 
1256 
1257  OUTREG( CRTC_MORE_CNTL, 0);
1258  OUTREG( FP_GEN_CNTL, 0);
1259  OUTREG( FP2_GEN_CNTL,0);
1260 
1261  OUTREG( CRTC_GEN_CNTL, (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) );
1262  OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) );
1263 
1264  /* This is the code for the Aluminium PowerBooks M10 / iBooks M11 */
1265  if (rinfo->family == CHIP_FAMILY_RV350) {
1266  u32 sdram_mode_reg = rinfo->save_regs[35];
1267  static const u32 default_mrtable[] =
1268  { 0x21320032,
1269  0x21321000, 0xa1321000, 0x21321000, 0xffffffff,
1270  0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1271  0x21321002, 0xa1321002, 0x21321002, 0xffffffff,
1272  0x21320132, 0xa1320132, 0x21320132, 0xffffffff,
1273  0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1274  0x31320032 };
1275 
1276  const u32 *mrtable = default_mrtable;
1277  int i, mrtable_size = ARRAY_SIZE(default_mrtable);
1278 
1279  mdelay(30);
1280 
1281  /* Disable refresh */
1282  memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1283  & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1284  OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1285  | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1286 
1287  /* Configure and enable M & SPLLs */
1288  radeon_pm_enable_dll_m10(rinfo);
1289  radeon_pm_yclk_mclk_sync_m10(rinfo);
1290 
1291 #ifdef CONFIG_PPC_OF
1292  if (rinfo->of_node != NULL) {
1293  int size;
1294 
1295  mrtable = of_get_property(rinfo->of_node, "ATY,MRT", &size);
1296  if (mrtable)
1297  mrtable_size = size >> 2;
1298  else
1299  mrtable = default_mrtable;
1300  }
1301 #endif /* CONFIG_PPC_OF */
1302 
1303  /* Program the SDRAM */
1304  sdram_mode_reg = mrtable[0];
1305  OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1306  for (i = 0; i < mrtable_size; i++) {
1307  if (mrtable[i] == 0xffffffffu)
1308  radeon_pm_m10_program_mode_wait(rinfo);
1309  else {
1310  sdram_mode_reg &= ~(MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK
1311  | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
1312  | MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET);
1313  sdram_mode_reg |= mrtable[i];
1314 
1315  OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1316  mdelay(1);
1317  }
1318  }
1319 
1320  /* Restore memory refresh */
1321  OUTREG(MEM_REFRESH_CNTL, memRefreshCntl);
1322  mdelay(30);
1323 
1324  }
1325  /* Here come the desktop RV200 "QW" card */
1326  else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) {
1327  /* Disable refresh */
1328  memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1329  & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1330  OUTREG(MEM_REFRESH_CNTL, memRefreshCntl
1331  | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1332  mdelay(30);
1333 
1334  /* Reset memory */
1335  OUTREG(MEM_SDRAM_MODE_REG,
1336  INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1337 
1338  radeon_pm_program_mode_reg(rinfo, 0x2002, 2);
1339  radeon_pm_program_mode_reg(rinfo, 0x0132, 2);
1340  radeon_pm_program_mode_reg(rinfo, 0x0032, 2);
1341 
1342  OUTREG(MEM_SDRAM_MODE_REG,
1343  INREG(MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1344 
1345  OUTREG( MEM_REFRESH_CNTL, memRefreshCntl);
1346 
1347  }
1348  /* The M6 */
1349  else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) {
1350  /* Disable refresh */
1351  memRefreshCntl = INREG(EXT_MEM_CNTL) & ~(1 << 20);
1352  OUTREG( EXT_MEM_CNTL, memRefreshCntl | (1 << 20));
1353 
1354  /* Reset memory */
1355  OUTREG( MEM_SDRAM_MODE_REG,
1356  INREG( MEM_SDRAM_MODE_REG)
1357  & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1358 
1359  /* DLL */
1360  radeon_pm_enable_dll(rinfo);
1361 
1362  /* MLCK / YCLK sync */
1363  radeon_pm_yclk_mclk_sync(rinfo);
1364 
1365  /* Program Mode Register */
1366  radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1367  radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1368  radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1369  radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1370  radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1371 
1372  /* Complete & re-enable refresh */
1373  OUTREG( MEM_SDRAM_MODE_REG,
1374  INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1375 
1376  OUTREG(EXT_MEM_CNTL, memRefreshCntl);
1377  }
1378  /* And finally, the M7..M9 models, including M9+ (RV280) */
1379  else if (rinfo->is_mobility) {
1380 
1381  /* Disable refresh */
1382  memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1383  & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1384  OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1385  | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1386 
1387  /* Reset memory */
1388  OUTREG( MEM_SDRAM_MODE_REG,
1389  INREG( MEM_SDRAM_MODE_REG)
1390  & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1391 
1392  /* DLL */
1393  radeon_pm_enable_dll(rinfo);
1394 
1395  /* MLCK / YCLK sync */
1396  radeon_pm_yclk_mclk_sync(rinfo);
1397 
1398  /* M6, M7 and M9 so far ... */
1399  if (rinfo->family <= CHIP_FAMILY_RV250) {
1400  radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1401  radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1402  radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1403  radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1404  radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1405  }
1406  /* M9+ (iBook G4) */
1407  else if (rinfo->family == CHIP_FAMILY_RV280) {
1408  radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1409  radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1410  radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1411  }
1412 
1413  /* Complete & re-enable refresh */
1414  OUTREG( MEM_SDRAM_MODE_REG,
1415  INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1416 
1417  OUTREG( MEM_REFRESH_CNTL, memRefreshCntl);
1418  }
1419 
1420  OUTREG( CRTC_GEN_CNTL, crtcGenCntl);
1421  OUTREG( CRTC2_GEN_CNTL, crtcGenCntl2);
1422  OUTREG( FP_GEN_CNTL, fp_gen_cntl);
1423  OUTREG( FP2_GEN_CNTL, fp2_gen_cntl);
1424 
1425  OUTREG( CRTC_MORE_CNTL, crtc_more_cntl);
1426 
1427  mdelay( 15);
1428 }
1429 
1430 static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo)
1431 {
1432  u32 tmp, tmp2;
1433  int i,j;
1434 
1435  /* Reset the PAD_CTLR_STRENGTH & wait for it to be stable */
1436  INREG(PAD_CTLR_STRENGTH);
1437  OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE);
1438  tmp = INREG(PAD_CTLR_STRENGTH);
1439  for (i = j = 0; i < 65; ++i) {
1440  mdelay(1);
1441  tmp2 = INREG(PAD_CTLR_STRENGTH);
1442  if (tmp != tmp2) {
1443  tmp = tmp2;
1444  i = 0;
1445  j++;
1446  if (j > 10) {
1447  printk(KERN_WARNING "radeon: PAD_CTLR_STRENGTH doesn't "
1448  "stabilize !\n");
1449  break;
1450  }
1451  }
1452  }
1453 }
1454 
1455 static void radeon_pm_all_ppls_off(struct radeonfb_info *rinfo)
1456 {
1457  u32 tmp;
1458 
1459  tmp = INPLL(pllPPLL_CNTL);
1460  OUTPLL(pllPPLL_CNTL, tmp | 0x3);
1461  tmp = INPLL(pllP2PLL_CNTL);
1462  OUTPLL(pllP2PLL_CNTL, tmp | 0x3);
1463  tmp = INPLL(pllSPLL_CNTL);
1464  OUTPLL(pllSPLL_CNTL, tmp | 0x3);
1465  tmp = INPLL(pllMPLL_CNTL);
1466  OUTPLL(pllMPLL_CNTL, tmp | 0x3);
1467 }
1468 
1469 static void radeon_pm_start_mclk_sclk(struct radeonfb_info *rinfo)
1470 {
1471  u32 tmp;
1472 
1473  /* Switch SPLL to PCI source */
1474  tmp = INPLL(pllSCLK_CNTL);
1475  OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK);
1476 
1477  /* Reconfigure SPLL charge pump, VCO gain, duty cycle */
1478  tmp = INPLL(pllSPLL_CNTL);
1479  OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1480  radeon_pll_errata_after_index(rinfo);
1481  OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1482  radeon_pll_errata_after_data(rinfo);
1483 
1484  /* Set SPLL feedback divider */
1485  tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1486  tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul);
1487  OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1488 
1489  /* Power up SPLL */
1490  tmp = INPLL(pllSPLL_CNTL);
1491  OUTPLL(pllSPLL_CNTL, tmp & ~1);
1492  (void)INPLL(pllSPLL_CNTL);
1493 
1494  mdelay(10);
1495 
1496  /* Release SPLL reset */
1497  tmp = INPLL(pllSPLL_CNTL);
1498  OUTPLL(pllSPLL_CNTL, tmp & ~0x2);
1499  (void)INPLL(pllSPLL_CNTL);
1500 
1501  mdelay(10);
1502 
1503  /* Select SCLK source */
1504  tmp = INPLL(pllSCLK_CNTL);
1505  tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK;
1506  tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK;
1507  OUTPLL(pllSCLK_CNTL, tmp);
1508  (void)INPLL(pllSCLK_CNTL);
1509 
1510  mdelay(10);
1511 
1512  /* Reconfigure MPLL charge pump, VCO gain, duty cycle */
1513  tmp = INPLL(pllMPLL_CNTL);
1514  OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN);
1515  radeon_pll_errata_after_index(rinfo);
1516  OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1517  radeon_pll_errata_after_data(rinfo);
1518 
1519  /* Set MPLL feedback divider */
1520  tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1521  tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul);
1522 
1523  OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1524  /* Power up MPLL */
1525  tmp = INPLL(pllMPLL_CNTL);
1526  OUTPLL(pllMPLL_CNTL, tmp & ~0x2);
1527  (void)INPLL(pllMPLL_CNTL);
1528 
1529  mdelay(10);
1530 
1531  /* Un-reset MPLL */
1532  tmp = INPLL(pllMPLL_CNTL);
1533  OUTPLL(pllMPLL_CNTL, tmp & ~0x1);
1534  (void)INPLL(pllMPLL_CNTL);
1535 
1536  mdelay(10);
1537 
1538  /* Select source for MCLK */
1539  tmp = INPLL(pllMCLK_CNTL);
1540  tmp |= rinfo->save_regs[2] & 0xffff;
1541  OUTPLL(pllMCLK_CNTL, tmp);
1542  (void)INPLL(pllMCLK_CNTL);
1543 
1544  mdelay(10);
1545 }
1546 
1547 static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info *rinfo)
1548 {
1549  u32 r2ec;
1550 
1551  /* GACK ! I though we didn't have a DDA on Radeon's anymore
1552  * here we rewrite with the same value, ... I suppose we clear
1553  * some bits that are already clear ? Or maybe this 0x2ec
1554  * register is something new ?
1555  */
1556  mdelay(20);
1557  r2ec = INREG(VGA_DDA_ON_OFF);
1558  OUTREG(VGA_DDA_ON_OFF, r2ec);
1559  mdelay(1);
1560 
1561  /* Spread spectrum PLLL off */
1562  OUTPLL(pllSSPLL_CNTL, 0xbf03);
1563 
1564  /* Spread spectrum disabled */
1565  OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);
1566 
1567  /* The trace shows read & rewrite of LVDS_PLL_CNTL here with same
1568  * value, not sure what for...
1569  */
1570 
1571  r2ec |= 0x3f0;
1572  OUTREG(VGA_DDA_ON_OFF, r2ec);
1573  mdelay(1);
1574 }
1575 
1576 static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo)
1577 {
1578  u32 r2ec, tmp;
1579 
1580  /* GACK (bis) ! I though we didn't have a DDA on Radeon's anymore
1581  * here we rewrite with the same value, ... I suppose we clear/set
1582  * some bits that are already clear/set ?
1583  */
1584  r2ec = INREG(VGA_DDA_ON_OFF);
1585  OUTREG(VGA_DDA_ON_OFF, r2ec);
1586  mdelay(1);
1587 
1588  /* Enable spread spectrum */
1589  OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3);
1590  mdelay(3);
1591 
1592  OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]);
1593  OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]);
1594  tmp = INPLL(pllSSPLL_CNTL);
1595  OUTPLL(pllSSPLL_CNTL, tmp & ~0x2);
1596  mdelay(6);
1597  tmp = INPLL(pllSSPLL_CNTL);
1598  OUTPLL(pllSSPLL_CNTL, tmp & ~0x1);
1599  mdelay(5);
1600 
1601  OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]);
1602 
1603  r2ec |= 8;
1604  OUTREG(VGA_DDA_ON_OFF, r2ec);
1605  mdelay(20);
1606 
1607  /* Enable LVDS interface */
1608  tmp = INREG(LVDS_GEN_CNTL);
1609  OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN);
1610 
1611  /* Enable LVDS_PLL */
1612  tmp = INREG(LVDS_PLL_CNTL);
1613  tmp &= ~0x30000;
1614  tmp |= 0x10000;
1615  OUTREG(LVDS_PLL_CNTL, tmp);
1616 
1617  OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]);
1618  OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]);
1619 
1620  /* The trace reads that one here, waiting for something to settle down ? */
1621  INREG(RBBM_STATUS);
1622 
1623  /* Ugh ? SS_TST_DEC is supposed to be a read register in the
1624  * R300 register spec at least...
1625  */
1626  tmp = INPLL(pllSS_TST_CNTL);
1627  tmp |= 0x00400000;
1628  OUTPLL(pllSS_TST_CNTL, tmp);
1629 }
1630 
1631 static void radeon_pm_restore_pixel_pll(struct radeonfb_info *rinfo)
1632 {
1633  u32 tmp;
1634 
1635  OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN);
1636  radeon_pll_errata_after_index(rinfo);
1637  OUTREG8(CLOCK_CNTL_DATA, 0);
1638  radeon_pll_errata_after_data(rinfo);
1639 
1640  tmp = INPLL(pllVCLK_ECP_CNTL);
1641  OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80);
1642  mdelay(5);
1643 
1644  tmp = INPLL(pllPPLL_REF_DIV);
1645  tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
1646  OUTPLL(pllPPLL_REF_DIV, tmp);
1647  INPLL(pllPPLL_REF_DIV);
1648 
1649  /* Reconfigure SPLL charge pump, VCO gain, duty cycle,
1650  * probably useless since we already did it ...
1651  */
1652  tmp = INPLL(pllPPLL_CNTL);
1653  OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1654  radeon_pll_errata_after_index(rinfo);
1655  OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1656  radeon_pll_errata_after_data(rinfo);
1657 
1658  /* Restore our "reference" PPLL divider set by firmware
1659  * according to proper spread spectrum calculations
1660  */
1661  OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
1662 
1663  tmp = INPLL(pllPPLL_CNTL);
1664  OUTPLL(pllPPLL_CNTL, tmp & ~0x2);
1665  mdelay(5);
1666 
1667  tmp = INPLL(pllPPLL_CNTL);
1668  OUTPLL(pllPPLL_CNTL, tmp & ~0x1);
1669  mdelay(5);
1670 
1671  tmp = INPLL(pllVCLK_ECP_CNTL);
1672  OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1673  mdelay(5);
1674 
1675  tmp = INPLL(pllVCLK_ECP_CNTL);
1676  OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1677  mdelay(5);
1678 
1679  /* Switch pixel clock to firmware default div 0 */
1680  OUTREG8(CLOCK_CNTL_INDEX+1, 0);
1681  radeon_pll_errata_after_index(rinfo);
1682  radeon_pll_errata_after_data(rinfo);
1683 }
1684 
1685 static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info *rinfo)
1686 {
1687  OUTREG(MC_CNTL, rinfo->save_regs[46]);
1688  OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1689  OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1690  OUTREG(MEM_SDRAM_MODE_REG,
1691  rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1692  OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1693  OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1694  OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1695  OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1696  OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1697  OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1698 
1699  OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]);
1700  OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]);
1701  OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]);
1702  OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]);
1703  OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]);
1704  OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]);
1705  OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]);
1706  OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]);
1707  OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]);
1708  OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]);
1709  OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]);
1710  OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]);
1711  OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1712  OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]);
1713  OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]);
1714  OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]);
1715  OUTREG(MC_IND_INDEX, 0);
1716 }
1717 
1718 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo)
1719 {
1720  u32 tmp, i;
1721 
1722  /* Restore a bunch of registers first */
1723  OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1724  OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1725  OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1726  OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1727  OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1728  OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
1729  OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1730  OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1731  OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1732  OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1733  OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1734  OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1735  OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1736  OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1737 
1738  /* Hrm... */
1739  OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1740 
1741  /* Reset the PAD CTLR */
1742  radeon_pm_reset_pad_ctlr_strength(rinfo);
1743 
1744  /* Some PLLs are Read & written identically in the trace here...
1745  * I suppose it's actually to switch them all off & reset,
1746  * let's assume off is what we want. I'm just doing that for all major PLLs now.
1747  */
1748  radeon_pm_all_ppls_off(rinfo);
1749 
1750  /* Clear tiling, reset swappers */
1751  INREG(SURFACE_CNTL);
1752  OUTREG(SURFACE_CNTL, 0);
1753 
1754  /* Some black magic with TV_DAC_CNTL, we should restore those from backups
1755  * rather than hard coding...
1756  */
1757  tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
1758  tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT;
1759  OUTREG(TV_DAC_CNTL, tmp);
1760 
1761  tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
1762  tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT;
1763  OUTREG(TV_DAC_CNTL, tmp);
1764 
1765  /* More registers restored */
1766  OUTREG(AGP_CNTL, rinfo->save_regs[16]);
1767  OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
1768  OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
1769 
1770  /* Hrmmm ... What is that ? */
1771  tmp = rinfo->save_regs[1]
1772  & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
1773  CLK_PWRMGT_CNTL__MC_BUSY);
1774  OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
1775 
1776  OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]);
1777  OUTREG(FW_CNTL, rinfo->save_regs[57]);
1778  OUTREG(HDP_DEBUG, rinfo->save_regs[96]);
1779  OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
1780  OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
1781  OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
1782 
1783  /* Restore Memory Controller configuration */
1784  radeon_pm_m10_reconfigure_mc(rinfo);
1785 
1786  /* Make sure CRTC's dont touch memory */
1787  OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL)
1788  | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1789  OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL)
1790  | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1791  mdelay(30);
1792 
1793  /* Disable SDRAM refresh */
1794  OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
1795  | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1796 
1797  /* Restore XTALIN routing (CLK_PIN_CNTL) */
1798  OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
1799 
1800  /* Switch MCLK, YCLK and SCLK PLLs to PCI source & force them ON */
1801  tmp = rinfo->save_regs[2] & 0xff000000;
1802  tmp |= MCLK_CNTL__FORCE_MCLKA |
1803  MCLK_CNTL__FORCE_MCLKB |
1804  MCLK_CNTL__FORCE_YCLKA |
1805  MCLK_CNTL__FORCE_YCLKB |
1806  MCLK_CNTL__FORCE_MC;
1807  OUTPLL(pllMCLK_CNTL, tmp);
1808 
1809  /* Force all clocks on in SCLK */
1810  tmp = INPLL(pllSCLK_CNTL);
1811  tmp |= SCLK_CNTL__FORCE_DISP2|
1812  SCLK_CNTL__FORCE_CP|
1813  SCLK_CNTL__FORCE_HDP|
1814  SCLK_CNTL__FORCE_DISP1|
1815  SCLK_CNTL__FORCE_TOP|
1816  SCLK_CNTL__FORCE_E2|
1817  SCLK_CNTL__FORCE_SE|
1818  SCLK_CNTL__FORCE_IDCT|
1819  SCLK_CNTL__FORCE_VIP|
1820  SCLK_CNTL__FORCE_PB|
1821  SCLK_CNTL__FORCE_TAM|
1822  SCLK_CNTL__FORCE_TDM|
1823  SCLK_CNTL__FORCE_RB|
1824  SCLK_CNTL__FORCE_TV_SCLK|
1825  SCLK_CNTL__FORCE_SUBPIC|
1826  SCLK_CNTL__FORCE_OV0;
1827  tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT |
1828  SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
1829  SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
1830  SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
1831  SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
1832  SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
1833  SCLK_CNTL__VIP_MAX_DYN_STOP_LAT |
1834  SCLK_CNTL__RE_MAX_DYN_STOP_LAT |
1835  SCLK_CNTL__PB_MAX_DYN_STOP_LAT |
1836  SCLK_CNTL__TAM_MAX_DYN_STOP_LAT |
1837  SCLK_CNTL__TDM_MAX_DYN_STOP_LAT |
1838  SCLK_CNTL__RB_MAX_DYN_STOP_LAT;
1839  OUTPLL(pllSCLK_CNTL, tmp);
1840 
1841  OUTPLL(pllVCLK_ECP_CNTL, 0);
1842  OUTPLL(pllPIXCLKS_CNTL, 0);
1843  OUTPLL(pllMCLK_MISC,
1844  MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
1845  MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
1846 
1847  mdelay(5);
1848 
1849  /* Restore the M_SPLL_REF_FB_DIV, MPLL_AUX_CNTL and SPLL_AUX_CNTL values */
1850  OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
1851  OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
1852  OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
1853 
1854  /* Now restore the major PLLs settings, keeping them off & reset though */
1855  OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
1856  OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
1857  OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
1858  OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
1859 
1860  /* Restore MC DLL state and switch it off/reset too */
1861  OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1862 
1863  /* Switch MDLL off & reset */
1864  OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff);
1865  mdelay(5);
1866 
1867  /* Setup some black magic bits in PLL_PWRMGT_CNTL. Hrm... we saved
1868  * 0xa1100007... and MacOS writes 0xa1000007 ..
1869  */
1870  OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]);
1871 
1872  /* Restore more stuffs */
1873  OUTPLL(pllHTOTAL_CNTL, 0);
1874  OUTPLL(pllHTOTAL2_CNTL, 0);
1875 
1876  /* More PLL initial configuration */
1877  tmp = INPLL(pllSCLK_CNTL2); /* What for ? */
1878  OUTPLL(pllSCLK_CNTL2, tmp);
1879 
1880  tmp = INPLL(pllSCLK_MORE_CNTL);
1881  tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS | /* a guess */
1882  SCLK_MORE_CNTL__FORCE_MC_GUI |
1883  SCLK_MORE_CNTL__FORCE_MC_HOST;
1884  OUTPLL(pllSCLK_MORE_CNTL, tmp);
1885 
1886  /* Now we actually start MCLK and SCLK */
1887  radeon_pm_start_mclk_sclk(rinfo);
1888 
1889  /* Full reset sdrams, this also re-inits the MDLL */
1890  radeon_pm_full_reset_sdram(rinfo);
1891 
1892  /* Fill palettes */
1893  OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
1894  for (i=0; i<256; i++)
1895  OUTREG(PALETTE_30_DATA, 0x15555555);
1896  OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
1897  udelay(20);
1898  for (i=0; i<256; i++)
1899  OUTREG(PALETTE_30_DATA, 0x15555555);
1900 
1901  OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
1902  mdelay(3);
1903 
1904  /* Restore TMDS */
1905  OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]);
1906  OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]);
1907 
1908  /* Set LVDS registers but keep interface & pll down */
1909  OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
1910  ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
1911  OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
1912 
1913  OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]);
1914 
1915  /* Restore GPIOPAD state */
1916  OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
1917  OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
1918  OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
1919 
1920  /* write some stuff to the framebuffer... */
1921  for (i = 0; i < 0x8000; ++i)
1922  writeb(0, rinfo->fb_base + i);
1923 
1924  mdelay(40);
1925  OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
1926  mdelay(40);
1927 
1928  /* Restore a few more things */
1929  OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
1930  OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
1931 
1932  /* Take care of spread spectrum & PPLLs now */
1933  radeon_pm_m10_disable_spread_spectrum(rinfo);
1934  radeon_pm_restore_pixel_pll(rinfo);
1935 
1936  /* GRRRR... I can't figure out the proper LVDS power sequence, and the
1937  * code I have for blank/unblank doesn't quite work on some laptop models
1938  * it seems ... Hrm. What I have here works most of the time ...
1939  */
1940  radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
1941 }
1942 
1943 #ifdef CONFIG_PPC_OF
1944 
1945 static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo)
1946 {
1947  OUTREG(MC_CNTL, rinfo->save_regs[46]);
1948  OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1949  OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1950  OUTREG(MEM_SDRAM_MODE_REG,
1951  rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1952  OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1953  OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1954  OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1955  OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1956  OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1957  OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1958 
1959  OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/);
1960  OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/);
1961  OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/);
1962  OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/);
1963  OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/);
1964  OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/);
1965  OUTREG(MC_IND_INDEX, 0);
1966  OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
1967 
1968  mdelay(20);
1969 }
1970 
1971 static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo)
1972 {
1973  u32 tmp, i;
1974 
1975  /* Restore a bunch of registers first */
1976  OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
1977  OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1978  OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1979  OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1980  OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1981  OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1982  OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1983  OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1984  OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1985  OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1986  OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1987 
1988  OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1989  OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1990 
1991  /* Reset the PAD CTLR */
1992  radeon_pm_reset_pad_ctlr_strength(rinfo);
1993 
1994  /* Some PLLs are Read & written identically in the trace here...
1995  * I suppose it's actually to switch them all off & reset,
1996  * let's assume off is what we want. I'm just doing that for all major PLLs now.
1997  */
1998  radeon_pm_all_ppls_off(rinfo);
1999 
2000  /* Clear tiling, reset swappers */
2001  INREG(SURFACE_CNTL);
2002  OUTREG(SURFACE_CNTL, 0);
2003 
2004  /* Some black magic with TV_DAC_CNTL, we should restore those from backups
2005  * rather than hard coding...
2006  */
2007  tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
2008  tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT;
2009  OUTREG(TV_DAC_CNTL, tmp);
2010 
2011  tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
2012  tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT;
2013  OUTREG(TV_DAC_CNTL, tmp);
2014 
2015  OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]);
2016 
2017  OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
2018  OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
2019  OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
2020 
2021  OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2022  OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */
2023  OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2024 
2025  tmp = rinfo->save_regs[1]
2026  & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
2027  CLK_PWRMGT_CNTL__MC_BUSY);
2028  OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
2029 
2030  OUTREG(FW_CNTL, rinfo->save_regs[57]);
2031 
2032  /* Disable SDRAM refresh */
2033  OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
2034  | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
2035 
2036  /* Restore XTALIN routing (CLK_PIN_CNTL) */
2037  OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
2038 
2039  /* Force MCLK to be PCI sourced and forced ON */
2040  tmp = rinfo->save_regs[2] & 0xff000000;
2041  tmp |= MCLK_CNTL__FORCE_MCLKA |
2042  MCLK_CNTL__FORCE_MCLKB |
2043  MCLK_CNTL__FORCE_YCLKA |
2044  MCLK_CNTL__FORCE_YCLKB |
2045  MCLK_CNTL__FORCE_MC |
2046  MCLK_CNTL__FORCE_AIC;
2047  OUTPLL(pllMCLK_CNTL, tmp);
2048 
2049  /* Force SCLK to be PCI sourced with a bunch forced */
2050  tmp = 0 |
2051  SCLK_CNTL__FORCE_DISP2|
2052  SCLK_CNTL__FORCE_CP|
2053  SCLK_CNTL__FORCE_HDP|
2054  SCLK_CNTL__FORCE_DISP1|
2055  SCLK_CNTL__FORCE_TOP|
2056  SCLK_CNTL__FORCE_E2|
2057  SCLK_CNTL__FORCE_SE|
2058  SCLK_CNTL__FORCE_IDCT|
2059  SCLK_CNTL__FORCE_VIP|
2060  SCLK_CNTL__FORCE_RE|
2061  SCLK_CNTL__FORCE_PB|
2062  SCLK_CNTL__FORCE_TAM|
2063  SCLK_CNTL__FORCE_TDM|
2064  SCLK_CNTL__FORCE_RB;
2065  OUTPLL(pllSCLK_CNTL, tmp);
2066 
2067  /* Clear VCLK_ECP_CNTL & PIXCLKS_CNTL */
2068  OUTPLL(pllVCLK_ECP_CNTL, 0);
2069  OUTPLL(pllPIXCLKS_CNTL, 0);
2070 
2071  /* Setup MCLK_MISC, non dynamic mode */
2072  OUTPLL(pllMCLK_MISC,
2073  MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
2074  MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
2075 
2076  mdelay(5);
2077 
2078  /* Set back the default clock dividers */
2079  OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
2080  OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
2081  OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
2082 
2083  /* PPLL and P2PLL default values & off */
2084  OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
2085  OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
2086 
2087  /* S and M PLLs are reset & off, configure them */
2088  OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
2089  OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
2090 
2091  /* Default values for MDLL ... fixme */
2092  OUTPLL(pllMDLL_CKO, 0x9c009c);
2093  OUTPLL(pllMDLL_RDCKA, 0x08830883);
2094  OUTPLL(pllMDLL_RDCKB, 0x08830883);
2095  mdelay(5);
2096 
2097  /* Restore PLL_PWRMGT_CNTL */ // XXXX
2098  tmp = rinfo->save_regs[0];
2099  tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK;
2100  tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
2101  OUTPLL(PLL_PWRMGT_CNTL, tmp);
2102 
2103  /* Clear HTOTAL_CNTL & HTOTAL2_CNTL */
2104  OUTPLL(pllHTOTAL_CNTL, 0);
2105  OUTPLL(pllHTOTAL2_CNTL, 0);
2106 
2107  /* All outputs off */
2108  OUTREG(CRTC_GEN_CNTL, 0x04000000);
2109  OUTREG(CRTC2_GEN_CNTL, 0x04000000);
2110  OUTREG(FP_GEN_CNTL, 0x00004008);
2111  OUTREG(FP2_GEN_CNTL, 0x00000008);
2112  OUTREG(LVDS_GEN_CNTL, 0x08000008);
2113 
2114  /* Restore Memory Controller configuration */
2115  radeon_pm_m9p_reconfigure_mc(rinfo);
2116 
2117  /* Now we actually start MCLK and SCLK */
2118  radeon_pm_start_mclk_sclk(rinfo);
2119 
2120  /* Full reset sdrams, this also re-inits the MDLL */
2121  radeon_pm_full_reset_sdram(rinfo);
2122 
2123  /* Fill palettes */
2124  OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
2125  for (i=0; i<256; i++)
2126  OUTREG(PALETTE_30_DATA, 0x15555555);
2127  OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
2128  udelay(20);
2129  for (i=0; i<256; i++)
2130  OUTREG(PALETTE_30_DATA, 0x15555555);
2131 
2132  OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
2133  mdelay(3);
2134 
2135  /* Restore TV stuff, make sure TV DAC is down */
2136  OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]);
2137  OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000);
2138 
2139  /* Restore GPIOS. MacOS does some magic here with one of the GPIO bits,
2140  * possibly related to the weird PLL related workarounds and to the
2141  * fact that CLK_PIN_CNTL is tweaked in ways I don't fully understand,
2142  * but we keep things the simple way here
2143  */
2144  OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2145  OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2146  OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2147 
2148  /* Now do things with SCLK_MORE_CNTL. Force bits are already set, copy
2149  * high bits from backup
2150  */
2151  tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2152  tmp |= rinfo->save_regs[34] & 0xffff0000;
2153  tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2154  OUTPLL(pllSCLK_MORE_CNTL, tmp);
2155 
2156  tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2157  tmp |= rinfo->save_regs[34] & 0xffff0000;
2158  tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2159  OUTPLL(pllSCLK_MORE_CNTL, tmp);
2160 
2161  OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
2162  ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
2163  OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON);
2164  OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
2165  mdelay(20);
2166 
2167  /* write some stuff to the framebuffer... */
2168  for (i = 0; i < 0x8000; ++i)
2169  writeb(0, rinfo->fb_base + i);
2170 
2171  OUTREG(0x2ec, 0x6332a020);
2172  OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */);
2173  OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */);
2174  tmp = INPLL(pllSSPLL_CNTL);
2175  tmp &= ~2;
2176  OUTPLL(pllSSPLL_CNTL, tmp);
2177  mdelay(6);
2178  tmp &= ~1;
2179  OUTPLL(pllSSPLL_CNTL, tmp);
2180  mdelay(5);
2181  tmp |= 3;
2182  OUTPLL(pllSSPLL_CNTL, tmp);
2183  mdelay(5);
2184 
2185  OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/
2186  OUTREG(0x2ec, 0x6332a3f0);
2187  mdelay(17);
2188 
2189  OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);
2190  OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
2191 
2192  mdelay(40);
2193  OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
2194  mdelay(40);
2195 
2196  /* Restore a few more things */
2197  OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
2198  OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
2199 
2200  /* Restore PPLL, spread spectrum & LVDS */
2201  radeon_pm_m10_disable_spread_spectrum(rinfo);
2202  radeon_pm_restore_pixel_pll(rinfo);
2203  radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
2204 }
2205 
2206 #if 0 /* Not ready yet */
2207 static void radeon_reinitialize_QW(struct radeonfb_info *rinfo)
2208 {
2209  int i;
2210  u32 tmp, tmp2;
2211  u32 cko, cka, ckb;
2212  u32 cgc, cec, c2gc;
2213 
2214  OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2215  OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2216  OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2217  OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2218  OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2219  OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2220 
2221  INREG(PAD_CTLR_STRENGTH);
2222  OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000);
2223  for (i = 0; i < 65; ++i) {
2224  mdelay(1);
2225  INREG(PAD_CTLR_STRENGTH);
2226  }
2227 
2228  OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000);
2229  OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100);
2230  OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL));
2231  OUTREG(DAC_CNTL, 0xff00410a);
2232  OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL));
2233  OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000);
2234 
2235  OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2236  OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2237  OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2238  OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2239 
2240  OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, 0xf7bb4433);
2241  OUTREG(MC_IND_INDEX, 0);
2242  OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, 0xf7bb4433);
2243  OUTREG(MC_IND_INDEX, 0);
2244 
2245  OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL));
2246 
2247  tmp = INPLL(pllVCLK_ECP_CNTL);
2248  OUTPLL(pllVCLK_ECP_CNTL, tmp);
2249  tmp = INPLL(pllPIXCLKS_CNTL);
2250  OUTPLL(pllPIXCLKS_CNTL, tmp);
2251 
2252  OUTPLL(MCLK_CNTL, 0xaa3f0000);
2253  OUTPLL(SCLK_CNTL, 0xffff0000);
2254  OUTPLL(pllMPLL_AUX_CNTL, 6);
2255  OUTPLL(pllSPLL_AUX_CNTL, 1);
2256  OUTPLL(MDLL_CKO, 0x9f009f);
2257  OUTPLL(MDLL_RDCKA, 0x830083);
2258  OUTPLL(pllMDLL_RDCKB, 0x830083);
2259  OUTPLL(PPLL_CNTL, 0xa433);
2260  OUTPLL(P2PLL_CNTL, 0xa433);
2261  OUTPLL(MPLL_CNTL, 0x0400a403);
2262  OUTPLL(SPLL_CNTL, 0x0400a433);
2263 
2264  tmp = INPLL(M_SPLL_REF_FB_DIV);
2265  OUTPLL(M_SPLL_REF_FB_DIV, tmp);
2266  tmp = INPLL(M_SPLL_REF_FB_DIV);
2267  OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
2268  INPLL(M_SPLL_REF_FB_DIV);
2269 
2270  tmp = INPLL(MPLL_CNTL);
2271  OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN);
2272  radeon_pll_errata_after_index(rinfo);
2273  OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2274  radeon_pll_errata_after_data(rinfo);
2275 
2276  tmp = INPLL(M_SPLL_REF_FB_DIV);
2277  OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
2278 
2279  tmp = INPLL(MPLL_CNTL);
2280  OUTPLL(MPLL_CNTL, tmp & ~0x2);
2281  mdelay(1);
2282  tmp = INPLL(MPLL_CNTL);
2283  OUTPLL(MPLL_CNTL, tmp & ~0x1);
2284  mdelay(10);
2285 
2286  OUTPLL(MCLK_CNTL, 0xaa3f1212);
2287  mdelay(1);
2288 
2289  INPLL(M_SPLL_REF_FB_DIV);
2290  INPLL(MCLK_CNTL);
2291  INPLL(M_SPLL_REF_FB_DIV);
2292 
2293  tmp = INPLL(SPLL_CNTL);
2294  OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN);
2295  radeon_pll_errata_after_index(rinfo);
2296  OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2297  radeon_pll_errata_after_data(rinfo);
2298 
2299  tmp = INPLL(M_SPLL_REF_FB_DIV);
2300  OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
2301 
2302  tmp = INPLL(SPLL_CNTL);
2303  OUTPLL(SPLL_CNTL, tmp & ~0x1);
2304  mdelay(1);
2305  tmp = INPLL(SPLL_CNTL);
2306  OUTPLL(SPLL_CNTL, tmp & ~0x2);
2307  mdelay(10);
2308 
2309  tmp = INPLL(SCLK_CNTL);
2310  OUTPLL(SCLK_CNTL, tmp | 2);
2311  mdelay(1);
2312 
2313  cko = INPLL(pllMDLL_CKO);
2314  cka = INPLL(pllMDLL_RDCKA);
2315  ckb = INPLL(pllMDLL_RDCKB);
2316 
2317  cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
2318  OUTPLL(pllMDLL_CKO, cko);
2319  mdelay(1);
2320  cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
2321  OUTPLL(pllMDLL_CKO, cko);
2322  mdelay(5);
2323 
2324  cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
2325  OUTPLL(pllMDLL_RDCKA, cka);
2326  mdelay(1);
2327  cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
2328  OUTPLL(pllMDLL_RDCKA, cka);
2329  mdelay(5);
2330 
2331  ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
2332  OUTPLL(pllMDLL_RDCKB, ckb);
2333  mdelay(1);
2334  ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
2335  OUTPLL(pllMDLL_RDCKB, ckb);
2336  mdelay(5);
2337 
2338  OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x151550ff);
2339  OUTREG(MC_IND_INDEX, 0);
2340  OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x151550ff);
2341  OUTREG(MC_IND_INDEX, 0);
2342  mdelay(1);
2343  OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x141550ff);
2344  OUTREG(MC_IND_INDEX, 0);
2345  OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x141550ff);
2346  OUTREG(MC_IND_INDEX, 0);
2347  mdelay(1);
2348 
2349  OUTPLL(pllHTOTAL_CNTL, 0);
2350  OUTPLL(pllHTOTAL2_CNTL, 0);
2351 
2352  OUTREG(MEM_CNTL, 0x29002901);
2353  OUTREG(MEM_SDRAM_MODE_REG, 0x45320032); /* XXX use save_regs[35]? */
2354  OUTREG(EXT_MEM_CNTL, 0x1a394333);
2355  OUTREG(MEM_IO_CNTL_A1, 0x0aac0aac);
2356  OUTREG(MEM_INIT_LATENCY_TIMER, 0x34444444);
2357  OUTREG(MEM_REFRESH_CNTL, 0x1f1f7218); /* XXX or save_regs[42]? */
2358  OUTREG(MC_DEBUG, 0);
2359  OUTREG(MEM_IO_OE_CNTL, 0x04300430);
2360 
2361  OUTMC(rinfo, ixMC_IMP_CNTL, 0x00f460d6);
2362  OUTREG(MC_IND_INDEX, 0);
2363  OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249);
2364  OUTREG(MC_IND_INDEX, 0);
2365 
2366  OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
2367 
2368  radeon_pm_full_reset_sdram(rinfo);
2369 
2370  INREG(FP_GEN_CNTL);
2371  OUTREG(TMDS_CNTL, 0x01000000); /* XXX ? */
2372  tmp = INREG(FP_GEN_CNTL);
2373  tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200;
2374  OUTREG(FP_GEN_CNTL, tmp);
2375 
2376  tmp = INREG(DISP_OUTPUT_CNTL);
2377  tmp &= ~0x400;
2378  OUTREG(DISP_OUTPUT_CNTL, tmp);
2379 
2380  OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2381  OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2382  OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2383 
2384  tmp = INPLL(MCLK_MISC);
2385  tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE;
2386  OUTPLL(MCLK_MISC, tmp);
2387 
2388  tmp = INPLL(SCLK_CNTL);
2389  OUTPLL(SCLK_CNTL, tmp);
2390 
2391  OUTREG(CRTC_MORE_CNTL, 0);
2392  OUTREG8(CRTC_GEN_CNTL+1, 6);
2393  OUTREG8(CRTC_GEN_CNTL+3, 1);
2394  OUTREG(CRTC_PITCH, 32);
2395 
2396  tmp = INPLL(VCLK_ECP_CNTL);
2397  OUTPLL(VCLK_ECP_CNTL, tmp);
2398 
2399  tmp = INPLL(PPLL_CNTL);
2400  OUTPLL(PPLL_CNTL, tmp);
2401 
2402  /* palette stuff and BIOS_1_SCRATCH... */
2403 
2404  tmp = INREG(FP_GEN_CNTL);
2405  tmp2 = INREG(TMDS_TRANSMITTER_CNTL);
2406  tmp |= 2;
2407  OUTREG(FP_GEN_CNTL, tmp);
2408  mdelay(5);
2409  OUTREG(FP_GEN_CNTL, tmp);
2410  mdelay(5);
2411  OUTREG(TMDS_TRANSMITTER_CNTL, tmp2);
2412  OUTREG(CRTC_MORE_CNTL, 0);
2413  mdelay(20);
2414 
2415  tmp = INREG(CRTC_MORE_CNTL);
2416  OUTREG(CRTC_MORE_CNTL, tmp);
2417 
2418  cgc = INREG(CRTC_GEN_CNTL);
2419  cec = INREG(CRTC_EXT_CNTL);
2420  c2gc = INREG(CRTC2_GEN_CNTL);
2421 
2422  OUTREG(CRTC_H_SYNC_STRT_WID, 0x008e0580);
2423  OUTREG(CRTC_H_TOTAL_DISP, 0x009f00d2);
2424  OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN);
2425  radeon_pll_errata_after_index(rinfo);
2426  OUTREG8(CLOCK_CNTL_DATA, 0);
2427  radeon_pll_errata_after_data(rinfo);
2428  OUTREG(CRTC_V_SYNC_STRT_WID, 0x00830403);
2429  OUTREG(CRTC_V_TOTAL_DISP, 0x03ff0429);
2430  OUTREG(FP_CRTC_H_TOTAL_DISP, 0x009f0033);
2431  OUTREG(FP_H_SYNC_STRT_WID, 0x008e0080);
2432  OUTREG(CRT_CRTC_H_SYNC_STRT_WID, 0x008e0080);
2433  OUTREG(FP_CRTC_V_TOTAL_DISP, 0x03ff002a);
2434  OUTREG(FP_V_SYNC_STRT_WID, 0x00830004);
2435  OUTREG(CRT_CRTC_V_SYNC_STRT_WID, 0x00830004);
2436  OUTREG(FP_HORZ_VERT_ACTIVE, 0x009f03ff);
2437  OUTREG(FP_HORZ_STRETCH, 0);
2438  OUTREG(FP_VERT_STRETCH, 0);
2439  OUTREG(OVR_CLR, 0);
2440  OUTREG(OVR_WID_LEFT_RIGHT, 0);
2441  OUTREG(OVR_WID_TOP_BOTTOM, 0);
2442 
2443  tmp = INPLL(PPLL_REF_DIV);
2444  tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
2445  OUTPLL(PPLL_REF_DIV, tmp);
2446  INPLL(PPLL_REF_DIV);
2447 
2448  OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
2449  radeon_pll_errata_after_index(rinfo);
2450  OUTREG8(CLOCK_CNTL_DATA + 1, 0xbc);
2451  radeon_pll_errata_after_data(rinfo);
2452 
2453  tmp = INREG(CLOCK_CNTL_INDEX);
2454  radeon_pll_errata_after_index(rinfo);
2455  OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff);
2456  radeon_pll_errata_after_index(rinfo);
2457  radeon_pll_errata_after_data(rinfo);
2458 
2459  OUTPLL(PPLL_DIV_0, 0x48090);
2460 
2461  tmp = INPLL(PPLL_CNTL);
2462  OUTPLL(PPLL_CNTL, tmp & ~0x2);
2463  mdelay(1);
2464  tmp = INPLL(PPLL_CNTL);
2465  OUTPLL(PPLL_CNTL, tmp & ~0x1);
2466  mdelay(10);
2467 
2468  tmp = INPLL(VCLK_ECP_CNTL);
2469  OUTPLL(VCLK_ECP_CNTL, tmp | 3);
2470  mdelay(1);
2471 
2472  tmp = INPLL(VCLK_ECP_CNTL);
2473  OUTPLL(VCLK_ECP_CNTL, tmp);
2474 
2475  c2gc |= CRTC2_DISP_REQ_EN_B;
2476  OUTREG(CRTC2_GEN_CNTL, c2gc);
2477  cgc |= CRTC_EN;
2478  OUTREG(CRTC_GEN_CNTL, cgc);
2479  OUTREG(CRTC_EXT_CNTL, cec);
2480  OUTREG(CRTC_PITCH, 0xa0);
2481  OUTREG(CRTC_OFFSET, 0);
2482  OUTREG(CRTC_OFFSET_CNTL, 0);
2483 
2484  OUTREG(GRPH_BUFFER_CNTL, 0x20117c7c);
2485  OUTREG(GRPH2_BUFFER_CNTL, 0x00205c5c);
2486 
2487  tmp2 = INREG(FP_GEN_CNTL);
2488  tmp = INREG(TMDS_TRANSMITTER_CNTL);
2489  OUTREG(0x2a8, 0x0000061b);
2490  tmp |= TMDS_PLL_EN;
2491  OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2492  mdelay(1);
2493  tmp &= ~TMDS_PLLRST;
2494  OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2495  tmp2 &= ~2;
2496  tmp2 |= FP_TMDS_EN;
2497  OUTREG(FP_GEN_CNTL, tmp2);
2498  mdelay(5);
2499  tmp2 |= FP_FPON;
2500  OUTREG(FP_GEN_CNTL, tmp2);
2501 
2502  OUTREG(CUR_HORZ_VERT_OFF, CUR_LOCK | 1);
2503  cgc = INREG(CRTC_GEN_CNTL);
2504  OUTREG(CUR_HORZ_VERT_POSN, 0xbfff0fff);
2505  cgc |= 0x10000;
2506  OUTREG(CUR_OFFSET, 0);
2507 }
2508 #endif /* 0 */
2509 
2510 #endif /* CONFIG_PPC_OF */
2511 
2512 static void radeonfb_whack_power_state(struct radeonfb_info *rinfo, pci_power_t state)
2513 {
2514  u16 pwr_cmd;
2515 
2516  for (;;) {
2517  pci_read_config_word(rinfo->pdev,
2518  rinfo->pm_reg+PCI_PM_CTRL,
2519  &pwr_cmd);
2520  if (pwr_cmd & 2)
2521  break;
2522  pwr_cmd = (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2;
2523  pci_write_config_word(rinfo->pdev,
2524  rinfo->pm_reg+PCI_PM_CTRL,
2525  pwr_cmd);
2526  msleep(500);
2527  }
2528  rinfo->pdev->current_state = state;
2529 }
2530 
2531 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2532 {
2533  u32 tmp;
2534 
2535  if (!rinfo->pm_reg)
2536  return;
2537 
2538  /* Set the chip into appropriate suspend mode (we use D2,
2539  * D3 would require a compete re-initialization of the chip,
2540  * including PCI config registers, clocks, AGP conf, ...)
2541  */
2542  if (suspend) {
2543  printk(KERN_DEBUG "radeonfb (%s): switching to D2 state...\n",
2544  pci_name(rinfo->pdev));
2545 
2546  /* Disable dynamic power management of clocks for the
2547  * duration of the suspend/resume process
2548  */
2549  radeon_pm_disable_dynamic_mode(rinfo);
2550 
2551  /* Save some registers */
2552  radeon_pm_save_regs(rinfo, 0);
2553 
2554  /* Prepare mobility chips for suspend.
2555  */
2556  if (rinfo->is_mobility) {
2557  /* Program V2CLK */
2558  radeon_pm_program_v2clk(rinfo);
2559 
2560  /* Disable IO PADs */
2561  radeon_pm_disable_iopad(rinfo);
2562 
2563  /* Set low current */
2564  radeon_pm_low_current(rinfo);
2565 
2566  /* Prepare chip for power management */
2567  radeon_pm_setup_for_suspend(rinfo);
2568 
2569  if (rinfo->family <= CHIP_FAMILY_RV280) {
2570  /* Reset the MDLL */
2571  /* because both INPLL and OUTPLL take the same
2572  * lock, that's why. */
2573  tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET
2574  | MDLL_CKO__MCKOB_RESET;
2575  OUTPLL( pllMDLL_CKO, tmp );
2576  }
2577  }
2578 
2579  /* Switch PCI power management to D2. */
2580  pci_disable_device(rinfo->pdev);
2581  pci_save_state(rinfo->pdev);
2582  /* The chip seems to need us to whack the PM register
2583  * repeatedly until it sticks. We do that -prior- to
2584  * calling pci_set_power_state()
2585  */
2586  radeonfb_whack_power_state(rinfo, PCI_D2);
2587  __pci_complete_power_transition(rinfo->pdev, PCI_D2);
2588  } else {
2589  printk(KERN_DEBUG "radeonfb (%s): switching to D0 state...\n",
2590  pci_name(rinfo->pdev));
2591 
2592  if (rinfo->family <= CHIP_FAMILY_RV250) {
2593  /* Reset the SDRAM controller */
2594  radeon_pm_full_reset_sdram(rinfo);
2595 
2596  /* Restore some registers */
2597  radeon_pm_restore_regs(rinfo);
2598  } else {
2599  /* Restore registers first */
2600  radeon_pm_restore_regs(rinfo);
2601  /* init sdram controller */
2602  radeon_pm_full_reset_sdram(rinfo);
2603  }
2604  }
2605 }
2606 
2607 int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
2608 {
2609  struct fb_info *info = pci_get_drvdata(pdev);
2610  struct radeonfb_info *rinfo = info->par;
2611 
2612  if (mesg.event == pdev->dev.power.power_state.event)
2613  return 0;
2614 
2615  printk(KERN_DEBUG "radeonfb (%s): suspending for event: %d...\n",
2616  pci_name(pdev), mesg.event);
2617 
2618  /* For suspend-to-disk, we cheat here. We don't suspend anything and
2619  * let fbcon continue drawing until we are all set. That shouldn't
2620  * really cause any problem at this point, provided that the wakeup
2621  * code knows that any state in memory may not match the HW
2622  */
2623  switch (mesg.event) {
2624  case PM_EVENT_FREEZE: /* about to take snapshot */
2625  case PM_EVENT_PRETHAW: /* before restoring snapshot */
2626  goto done;
2627  }
2628 
2629  console_lock();
2630 
2631  fb_set_suspend(info, 1);
2632 
2633  if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
2634  /* Make sure engine is reset */
2635  radeon_engine_idle();
2636  radeonfb_engine_reset(rinfo);
2637  radeon_engine_idle();
2638  }
2639 
2640  /* Blank display and LCD */
2641  radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1);
2642 
2643  /* Sleep */
2644  rinfo->asleep = 1;
2645  rinfo->lock_blank = 1;
2646  del_timer_sync(&rinfo->lvds_timer);
2647 
2648 #ifdef CONFIG_PPC_PMAC
2649  /* On powermac, we have hooks to properly suspend/resume AGP now,
2650  * use them here. We'll ultimately need some generic support here,
2651  * but the generic code isn't quite ready for that yet
2652  */
2653  pmac_suspend_agp_for_card(pdev);
2654 #endif /* CONFIG_PPC_PMAC */
2655 
2656  /* It's unclear whether or when the generic code will do that, so let's
2657  * do it ourselves. We save state before we do any power management
2658  */
2659  pci_save_state(pdev);
2660 
2661  /* If we support wakeup from poweroff, we save all regs we can including cfg
2662  * space
2663  */
2664  if (rinfo->pm_mode & radeon_pm_off) {
2665  /* Always disable dynamic clocks or weird things are happening when
2666  * the chip goes off (basically the panel doesn't shut down properly
2667  * and we crash on wakeup),
2668  * also, we want the saved regs context to have no dynamic clocks in
2669  * it, we'll restore the dynamic clocks state on wakeup
2670  */
2671  radeon_pm_disable_dynamic_mode(rinfo);
2672  mdelay(50);
2673  radeon_pm_save_regs(rinfo, 1);
2674 
2675  if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) {
2676  /* Switch off LVDS interface */
2677  mdelay(1);
2678  OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN));
2679  mdelay(1);
2680  OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON));
2681  OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000);
2682  mdelay(20);
2683  OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON));
2684  }
2685  pci_disable_device(pdev);
2686  }
2687  /* If we support D2, we go to it (should be fixed later with a flag forcing
2688  * D3 only for some laptops)
2689  */
2690  if (rinfo->pm_mode & radeon_pm_d2)
2691  radeon_set_suspend(rinfo, 1);
2692 
2693  console_unlock();
2694 
2695  done:
2696  pdev->dev.power.power_state = mesg;
2697 
2698  return 0;
2699 }
2700 
2701 static int radeon_check_power_loss(struct radeonfb_info *rinfo)
2702 {
2703  return rinfo->save_regs[4] != INPLL(CLK_PIN_CNTL) ||
2704  rinfo->save_regs[2] != INPLL(MCLK_CNTL) ||
2705  rinfo->save_regs[3] != INPLL(SCLK_CNTL);
2706 }
2707 
2708 int radeonfb_pci_resume(struct pci_dev *pdev)
2709 {
2710  struct fb_info *info = pci_get_drvdata(pdev);
2711  struct radeonfb_info *rinfo = info->par;
2712  int rc = 0;
2713 
2714  if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2715  return 0;
2716 
2717  if (rinfo->no_schedule) {
2718  if (!console_trylock())
2719  return 0;
2720  } else
2721  console_lock();
2722 
2723  printk(KERN_DEBUG "radeonfb (%s): resuming from state: %d...\n",
2724  pci_name(pdev), pdev->dev.power.power_state.event);
2725 
2726  /* PCI state will have been restored by the core, so
2727  * we should be in D0 now with our config space fully
2728  * restored
2729  */
2730  if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2731  /* Wakeup chip */
2732  if ((rinfo->pm_mode & radeon_pm_off) && radeon_check_power_loss(rinfo)) {
2733  if (rinfo->reinit_func != NULL)
2734  rinfo->reinit_func(rinfo);
2735  else {
2736  printk(KERN_ERR "radeonfb (%s): can't resume radeon from"
2737  " D3 cold, need softboot !", pci_name(pdev));
2738  rc = -EIO;
2739  goto bail;
2740  }
2741  }
2742  /* If we support D2, try to resume... we should check what was our
2743  * state though... (were we really in D2 state ?). Right now, this code
2744  * is only enable on Macs so it's fine.
2745  */
2746  else if (rinfo->pm_mode & radeon_pm_d2)
2747  radeon_set_suspend(rinfo, 0);
2748 
2749  rinfo->asleep = 0;
2750  } else
2751  radeon_engine_idle();
2752 
2753  /* Restore display & engine */
2754  radeon_write_mode (rinfo, &rinfo->state, 1);
2755  if (!(info->flags & FBINFO_HWACCEL_DISABLED))
2756  radeonfb_engine_init (rinfo);
2757 
2758  fb_pan_display(info, &info->var);
2759  fb_set_cmap(&info->cmap, info);
2760 
2761  /* Refresh */
2762  fb_set_suspend(info, 0);
2763 
2764  /* Unblank */
2765  rinfo->lock_blank = 0;
2766  radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 1);
2767 
2768 #ifdef CONFIG_PPC_PMAC
2769  /* On powermac, we have hooks to properly suspend/resume AGP now,
2770  * use them here. We'll ultimately need some generic support here,
2771  * but the generic code isn't quite ready for that yet
2772  */
2773  pmac_resume_agp_for_card(pdev);
2774 #endif /* CONFIG_PPC_PMAC */
2775 
2776 
2777  /* Check status of dynclk */
2778  if (rinfo->dynclk == 1)
2779  radeon_pm_enable_dynamic_mode(rinfo);
2780  else if (rinfo->dynclk == 0)
2781  radeon_pm_disable_dynamic_mode(rinfo);
2782 
2783  pdev->dev.power.power_state = PMSG_ON;
2784 
2785  bail:
2786  console_unlock();
2787 
2788  return rc;
2789 }
2790 
2791 #ifdef CONFIG_PPC_OF__disabled
2792 static void radeonfb_early_resume(void *data)
2793 {
2794  struct radeonfb_info *rinfo = data;
2795 
2796  rinfo->no_schedule = 1;
2797  pci_restore_state(rinfo->pdev);
2798  radeonfb_pci_resume(rinfo->pdev);
2799  rinfo->no_schedule = 0;
2800 }
2801 #endif /* CONFIG_PPC_OF */
2802 
2803 #endif /* CONFIG_PM */
2804 
2805 void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep)
2806 {
2807  /* Find PM registers in config space if any*/
2808  rinfo->pm_reg = pci_find_capability(rinfo->pdev, PCI_CAP_ID_PM);
2809 
2810  /* Enable/Disable dynamic clocks: TODO add sysfs access */
2811  if (rinfo->family == CHIP_FAMILY_RS480)
2812  rinfo->dynclk = -1;
2813  else
2814  rinfo->dynclk = dynclk;
2815 
2816  if (rinfo->dynclk == 1) {
2817  radeon_pm_enable_dynamic_mode(rinfo);
2818  printk("radeonfb: Dynamic Clock Power Management enabled\n");
2819  } else if (rinfo->dynclk == 0) {
2820  radeon_pm_disable_dynamic_mode(rinfo);
2821  printk("radeonfb: Dynamic Clock Power Management disabled\n");
2822  }
2823 
2824 #if defined(CONFIG_PM)
2825 #if defined(CONFIG_PPC_PMAC)
2826  /* Check if we can power manage on suspend/resume. We can do
2827  * D2 on M6, M7 and M9, and we can resume from D3 cold a few other
2828  * "Mac" cards, but that's all. We need more infos about what the
2829  * BIOS does tho. Right now, all this PM stuff is pmac-only for that
2830  * reason. --BenH
2831  */
2832  if (machine_is(powermac) && rinfo->of_node) {
2833  if (rinfo->is_mobility && rinfo->pm_reg &&
2834  rinfo->family <= CHIP_FAMILY_RV250)
2835  rinfo->pm_mode |= radeon_pm_d2;
2836 
2837  /* We can restart Jasper (M10 chip in albooks), BlueStone (7500 chip
2838  * in some desktop G4s), Via (M9+ chip on iBook G4) and
2839  * Snowy (M11 chip on iBook G4 manufactured after July 2005)
2840  */
2841  if (!strcmp(rinfo->of_node->name, "ATY,JasperParent") ||
2842  !strcmp(rinfo->of_node->name, "ATY,SnowyParent")) {
2843  rinfo->reinit_func = radeon_reinitialize_M10;
2844  rinfo->pm_mode |= radeon_pm_off;
2845  }
2846 #if 0 /* Not ready yet */
2847  if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) {
2848  rinfo->reinit_func = radeon_reinitialize_QW;
2849  rinfo->pm_mode |= radeon_pm_off;
2850  }
2851 #endif
2852  if (!strcmp(rinfo->of_node->name, "ATY,ViaParent")) {
2853  rinfo->reinit_func = radeon_reinitialize_M9P;
2854  rinfo->pm_mode |= radeon_pm_off;
2855  }
2856 
2857  /* If any of the above is set, we assume the machine can sleep/resume.
2858  * It's a bit of a "shortcut" but will work fine. Ideally, we need infos
2859  * from the platform about what happens to the chip...
2860  * Now we tell the platform about our capability
2861  */
2862  if (rinfo->pm_mode != radeon_pm_none) {
2863  pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1);
2864 #if 0 /* Disable the early video resume hack for now as it's causing problems, among
2865  * others we now rely on the PCI core restoring the config space for us, which
2866  * isn't the case with that hack, and that code path causes various things to
2867  * be called with interrupts off while they shouldn't. I'm leaving the code in
2868  * as it can be useful for debugging purposes
2869  */
2870  pmac_set_early_video_resume(radeonfb_early_resume, rinfo);
2871 #endif
2872  }
2873 
2874 #if 0
2875  /* Power down TV DAC, that saves a significant amount of power,
2876  * we'll have something better once we actually have some TVOut
2877  * support
2878  */
2879  OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000);
2880 #endif
2881  }
2882 #endif /* defined(CONFIG_PPC_PMAC) */
2883 #endif /* defined(CONFIG_PM) */
2884 
2885  if (ignore_devlist)
2886  printk(KERN_DEBUG
2887  "radeonfb: skipping test for device workarounds\n");
2888  else
2889  radeon_apply_workarounds(rinfo);
2890 
2891  if (force_sleep) {
2892  printk(KERN_DEBUG
2893  "radeonfb: forcefully enabling D2 sleep mode\n");
2894  rinfo->pm_mode |= radeon_pm_d2;
2895  }
2896 }
2897 
2898 void radeonfb_pm_exit(struct radeonfb_info *rinfo)
2899 {
2900 #if defined(CONFIG_PM) && defined(CONFIG_PPC_PMAC)
2901  if (rinfo->pm_mode != radeon_pm_none)
2902  pmac_set_early_video_resume(NULL, NULL);
2903 #endif
2904 }
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