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Macros | Functions
atl1c_hw.h File Reference
#include <linux/types.h>
#include <linux/mii.h>

Go to the source code of this file.

Macros

#define FIELD_GETX(_x, _name)   ((_x) >> (_name##_SHIFT) & (_name##_MASK))
 
#define FIELD_SETX(_x, _name, _v)
 
#define FIELDX(_name, _v)   (((_v) & (_name##_MASK)) << (_name##_SHIFT))
 
#define PCI_DEVICE_ID_ATTANSIC_L2C   0x1062
 
#define PCI_DEVICE_ID_ATTANSIC_L1C   0x1063
 
#define PCI_DEVICE_ID_ATHEROS_L2C_B   0x2060 /* AR8152 v1.1 Fast 10/100 */
 
#define PCI_DEVICE_ID_ATHEROS_L2C_B2   0x2062 /* AR8152 v2.0 Fast 10/100 */
 
#define PCI_DEVICE_ID_ATHEROS_L1D   0x1073 /* AR8151 v1.0 Gigabit 1000 */
 
#define PCI_DEVICE_ID_ATHEROS_L1D_2_0   0x1083 /* AR8151 v2.0 Gigabit 1000 */
 
#define L2CB_V10   0xc0
 
#define L2CB_V11   0xc1
 
#define L2CB_V20   0xc0
 
#define L2CB_V21   0xc1
 
#define REG_DEVICE_CAP   0x5C
 
#define DEVICE_CAP_MAX_PAYLOAD_MASK   0x7
 
#define DEVICE_CAP_MAX_PAYLOAD_SHIFT   0
 
#define DEVICE_CTRL_MAXRRS_MIN   2
 
#define REG_LINK_CTRL   0x68
 
#define LINK_CTRL_L0S_EN   0x01
 
#define LINK_CTRL_L1_EN   0x02
 
#define LINK_CTRL_EXT_SYNC   0x80
 
#define REG_PCIE_IND_ACC_ADDR   0x80
 
#define REG_PCIE_IND_ACC_DATA   0x84
 
#define REG_DEV_SERIALNUM_CTRL   0x200
 
#define REG_DEV_MAC_SEL_MASK   0x0 /* 0:EUI; 1:MAC */
 
#define REG_DEV_MAC_SEL_SHIFT   0
 
#define REG_DEV_SERIAL_NUM_EN_MASK   0x1
 
#define REG_DEV_SERIAL_NUM_EN_SHIFT   1
 
#define REG_TWSI_CTRL   0x218
 
#define TWSI_CTLR_FREQ_MASK   0x3UL
 
#define TWSI_CTRL_FREQ_SHIFT   24
 
#define TWSI_CTRL_FREQ_100K   0
 
#define TWSI_CTRL_FREQ_200K   1
 
#define TWSI_CTRL_FREQ_300K   2
 
#define TWSI_CTRL_FREQ_400K   3
 
#define TWSI_CTRL_LD_EXIST   BIT(23)
 
#define TWSI_CTRL_HW_LDSTAT   BIT(12) /* 0:finish,1:in progress */
 
#define TWSI_CTRL_SW_LDSTART   BIT(11)
 
#define TWSI_CTRL_LD_OFFSET_MASK   0xFF
 
#define TWSI_CTRL_LD_OFFSET_SHIFT   0
 
#define REG_PCIE_DEV_MISC_CTRL   0x21C
 
#define PCIE_DEV_MISC_EXT_PIPE   0x2
 
#define PCIE_DEV_MISC_RETRY_BUFDIS   0x1
 
#define PCIE_DEV_MISC_SPIROM_EXIST   0x4
 
#define PCIE_DEV_MISC_SERDES_ENDIAN   0x8
 
#define PCIE_DEV_MISC_SERDES_SEL_DIN   0x10
 
#define REG_PCIE_PHYMISC   0x1000
 
#define PCIE_PHYMISC_FORCE_RCV_DET   BIT(2)
 
#define PCIE_PHYMISC_NFTS_MASK   0xFFUL
 
#define PCIE_PHYMISC_NFTS_SHIFT   16
 
#define REG_PCIE_PHYMISC2   0x1004
 
#define PCIE_PHYMISC2_L0S_TH_MASK   0x3UL
 
#define PCIE_PHYMISC2_L0S_TH_SHIFT   18
 
#define L2CB1_PCIE_PHYMISC2_L0S_TH   3
 
#define PCIE_PHYMISC2_CDR_BW_MASK   0x3UL
 
#define PCIE_PHYMISC2_CDR_BW_SHIFT   16
 
#define L2CB1_PCIE_PHYMISC2_CDR_BW   3
 
#define REG_TWSI_DEBUG   0x1108
 
#define TWSI_DEBUG_DEV_EXIST   BIT(29)
 
#define REG_DMA_DBG   0x1114
 
#define DMA_DBG_VENDOR_MSG   BIT(0)
 
#define REG_EEPROM_CTRL   0x12C0
 
#define EEPROM_CTRL_DATA_HI_MASK   0xFFFF
 
#define EEPROM_CTRL_DATA_HI_SHIFT   0
 
#define EEPROM_CTRL_ADDR_MASK   0x3FF
 
#define EEPROM_CTRL_ADDR_SHIFT   16
 
#define EEPROM_CTRL_ACK   0x40000000
 
#define EEPROM_CTRL_RW   0x80000000
 
#define REG_EEPROM_DATA_LO   0x12C4
 
#define REG_OTP_CTRL   0x12F0
 
#define OTP_CTRL_CLK_EN   BIT(1)
 
#define REG_PM_CTRL   0x12F8
 
#define PM_CTRL_HOTRST   BIT(31)
 
#define PM_CTRL_MAC_ASPM_CHK
 
#define PM_CTRL_SA_DLY_EN   BIT(29)
 
#define PM_CTRL_L0S_BUFSRX_EN   BIT(28)
 
#define PM_CTRL_LCKDET_TIMER_MASK   0xFUL
 
#define PM_CTRL_LCKDET_TIMER_SHIFT   24
 
#define PM_CTRL_LCKDET_TIMER_DEF   0xC
 
#define PM_CTRL_PM_REQ_TIMER_MASK   0xFUL
 
#define PM_CTRL_PM_REQ_TIMER_SHIFT
 
#define PM_CTRL_PM_REQ_TO_DEF   0xF
 
#define PMCTRL_TXL1_AFTER_L0S   BIT(19) /* l1dv2.0+ */
 
#define L1D_PMCTRL_L1_ENTRY_TM_MASK   7UL /* l1dv2.0+, 3bits */
 
#define L1D_PMCTRL_L1_ENTRY_TM_SHIFT   16
 
#define L1D_PMCTRL_L1_ENTRY_TM_DIS   0
 
#define L1D_PMCTRL_L1_ENTRY_TM_2US   1
 
#define L1D_PMCTRL_L1_ENTRY_TM_4US   2
 
#define L1D_PMCTRL_L1_ENTRY_TM_8US   3
 
#define L1D_PMCTRL_L1_ENTRY_TM_16US   4
 
#define L1D_PMCTRL_L1_ENTRY_TM_24US   5
 
#define L1D_PMCTRL_L1_ENTRY_TM_32US   6
 
#define L1D_PMCTRL_L1_ENTRY_TM_63US   7
 
#define PM_CTRL_L1_ENTRY_TIMER_MASK   0xFUL /* l1C 4bits */
 
#define PM_CTRL_L1_ENTRY_TIMER_SHIFT   16
 
#define L2CB1_PM_CTRL_L1_ENTRY_TM   7
 
#define L1C_PM_CTRL_L1_ENTRY_TM   0xF
 
#define PM_CTRL_RCVR_WT_TIMER   BIT(15) /* 1:1us, 0:2ms */
 
#define PM_CTRL_CLK_PWM_VER1_1   BIT(14) /* 0:1.0a,1:1.1 */
 
#define PM_CTRL_CLK_SWH_L1   BIT(13) /* en pcie clk sw in L1 */
 
#define PM_CTRL_ASPM_L0S_EN   BIT(12)
 
#define PM_CTRL_RXL1_AFTER_L0S   BIT(11) /* l1dv2.0+ */
 
#define L1D_PMCTRL_L0S_TIMER_MASK   7UL /* l1d2.0+, 3bits*/
 
#define L1D_PMCTRL_L0S_TIMER_SHIFT   8
 
#define PM_CTRL_L0S_ENTRY_TIMER_MASK   0xFUL /* l1c, 4bits */
 
#define PM_CTRL_L0S_ENTRY_TIMER_SHIFT   8
 
#define PM_CTRL_SERDES_BUFS_RX_L1_EN   BIT(7)
 
#define PM_CTRL_SERDES_PD_EX_L1   BIT(6) /* power down serdes rx */
 
#define PM_CTRL_SERDES_PLL_L1_EN   BIT(5)
 
#define PM_CTRL_SERDES_L1_EN   BIT(4)
 
#define PM_CTRL_ASPM_L1_EN   BIT(3)
 
#define PM_CTRL_CLK_REQ_EN   BIT(2)
 
#define PM_CTRL_RBER_EN   BIT(1)
 
#define PM_CTRL_SPRSDWER_EN   BIT(0)
 
#define REG_LTSSM_ID_CTRL   0x12FC
 
#define LTSSM_ID_EN_WRO   0x1000
 
#define REG_MASTER_CTRL   0x1400
 
#define MASTER_CTRL_OTP_SEL   BIT(31)
 
#define MASTER_DEV_NUM_MASK   0x7FUL
 
#define MASTER_DEV_NUM_SHIFT   24
 
#define MASTER_REV_NUM_MASK   0xFFUL
 
#define MASTER_REV_NUM_SHIFT   16
 
#define MASTER_CTRL_INT_RDCLR   BIT(14)
 
#define MASTER_CTRL_CLK_SEL_DIS
 
#define MASTER_CTRL_RX_ITIMER_EN   BIT(11) /* IRQ MODURATION FOR RX */
 
#define MASTER_CTRL_TX_ITIMER_EN   BIT(10) /* MODURATION FOR TX/RX */
 
#define MASTER_CTRL_MANU_INT   BIT(9) /* SOFT MANUAL INT */
 
#define MASTER_CTRL_MANUTIMER_EN   BIT(8)
 
#define MASTER_CTRL_SA_TIMER_EN   BIT(7) /* SYS ALIVE TIMER EN */
 
#define MASTER_CTRL_OOB_DIS   BIT(6) /* OUT OF BOX DIS */
 
#define MASTER_CTRL_WAKEN_25M   BIT(5) /* WAKE WO. PCIE CLK */
 
#define MASTER_CTRL_BERT_START   BIT(4)
 
#define MASTER_PCIE_TSTMOD_MASK   3UL
 
#define MASTER_PCIE_TSTMOD_SHIFT   2
 
#define MASTER_PCIE_RST   BIT(1)
 
#define MASTER_CTRL_SOFT_RST   BIT(0) /* RST MAC & DMA */
 
#define DMA_MAC_RST_TO   50
 
#define REG_MANUAL_TIMER_INIT   0x1404
 
#define REG_IRQ_MODRT_TIMER_INIT   0x1408
 
#define IRQ_MODRT_TIMER_MASK   0xffff
 
#define IRQ_MODRT_TX_TIMER_SHIFT   0
 
#define IRQ_MODRT_RX_TIMER_SHIFT   16
 
#define REG_GPHY_CTRL   0x140C
 
#define GPHY_CTRL_ADDR_MASK   0x1FUL
 
#define GPHY_CTRL_ADDR_SHIFT   19
 
#define GPHY_CTRL_BP_VLTGSW   BIT(18)
 
#define GPHY_CTRL_100AB_EN   BIT(17)
 
#define GPHY_CTRL_10AB_EN   BIT(16)
 
#define GPHY_CTRL_PHY_PLL_BYPASS   BIT(15)
 
#define GPHY_CTRL_PWDOWN_HW   BIT(14) /* affect MAC&PHY, to low pw */
 
#define GPHY_CTRL_PHY_PLL_ON   BIT(13) /* 1:pll always on, 0:can sw */
 
#define GPHY_CTRL_SEL_ANA_RST   BIT(12)
 
#define GPHY_CTRL_HIB_PULSE   BIT(11)
 
#define GPHY_CTRL_HIB_EN   BIT(10)
 
#define GPHY_CTRL_GIGA_DIS   BIT(9)
 
#define GPHY_CTRL_PHY_IDDQ_DIS   BIT(8) /* pw on RST */
 
#define GPHY_CTRL_PHY_IDDQ   BIT(7) /* bit8 affect bit7 while rb */
 
#define GPHY_CTRL_LPW_EXIT   BIT(6)
 
#define GPHY_CTRL_GATE_25M_EN   BIT(5)
 
#define GPHY_CTRL_REV_ANEG   BIT(4)
 
#define GPHY_CTRL_ANEG_NOW   BIT(3)
 
#define GPHY_CTRL_LED_MODE   BIT(2)
 
#define GPHY_CTRL_RTL_MODE   BIT(1)
 
#define GPHY_CTRL_EXT_RESET   BIT(0) /* 1:out of DSP RST status */
 
#define GPHY_CTRL_EXT_RST_TO   80 /* 800us atmost */
 
#define GPHY_CTRL_CLS
 
#define REG_IDLE_STATUS   0x1410
 
#define IDLE_STATUS_SFORCE_MASK   0xFUL
 
#define IDLE_STATUS_SFORCE_SHIFT   14
 
#define IDLE_STATUS_CALIB_DONE   BIT(13)
 
#define IDLE_STATUS_CALIB_RES_MASK   0x1FUL
 
#define IDLE_STATUS_CALIB_RES_SHIFT   8
 
#define IDLE_STATUS_CALIBERR_MASK   0xFUL
 
#define IDLE_STATUS_CALIBERR_SHIFT   4
 
#define IDLE_STATUS_TXQ_BUSY   BIT(3)
 
#define IDLE_STATUS_RXQ_BUSY   BIT(2)
 
#define IDLE_STATUS_TXMAC_BUSY   BIT(1)
 
#define IDLE_STATUS_RXMAC_BUSY   BIT(0)
 
#define IDLE_STATUS_MASK
 
#define REG_MDIO_CTRL   0x1414
 
#define MDIO_CTRL_MODE_EXT   BIT(30)
 
#define MDIO_CTRL_POST_READ   BIT(29)
 
#define MDIO_CTRL_AP_EN   BIT(28)
 
#define MDIO_CTRL_BUSY   BIT(27)
 
#define MDIO_CTRL_CLK_SEL_MASK   0x7UL
 
#define MDIO_CTRL_CLK_SEL_SHIFT   24
 
#define MDIO_CTRL_CLK_25_4   0 /* 25MHz divide 4 */
 
#define MDIO_CTRL_CLK_25_6   2
 
#define MDIO_CTRL_CLK_25_8   3
 
#define MDIO_CTRL_CLK_25_10   4
 
#define MDIO_CTRL_CLK_25_32   5
 
#define MDIO_CTRL_CLK_25_64   6
 
#define MDIO_CTRL_CLK_25_128   7
 
#define MDIO_CTRL_START   BIT(23)
 
#define MDIO_CTRL_SPRES_PRMBL   BIT(22)
 
#define MDIO_CTRL_OP_READ   BIT(21) /* 1:read, 0:write */
 
#define MDIO_CTRL_REG_MASK   0x1FUL
 
#define MDIO_CTRL_REG_SHIFT   16
 
#define MDIO_CTRL_DATA_MASK   0xFFFFUL
 
#define MDIO_CTRL_DATA_SHIFT   0
 
#define MDIO_MAX_AC_TO   120 /* 1.2ms timeout for slow clk */
 
#define REG_MDIO_EXTN   0x1448
 
#define MDIO_EXTN_PORTAD_MASK   0x1FUL
 
#define MDIO_EXTN_PORTAD_SHIFT   21
 
#define MDIO_EXTN_DEVAD_MASK   0x1FUL
 
#define MDIO_EXTN_DEVAD_SHIFT   16
 
#define MDIO_EXTN_REG_MASK   0xFFFFUL
 
#define MDIO_EXTN_REG_SHIFT   0
 
#define REG_BIST0_CTRL   0x141c
 
#define BIST0_NOW   0x1
 
#define BIST0_SRAM_FAIL
 
#define BIST0_FUSE_FLAG   0x4
 
#define REG_BIST1_CTRL   0x1420
 
#define BIST1_NOW   0x1
 
#define BIST1_SRAM_FAIL   0x2
 
#define BIST1_FUSE_FLAG   0x4
 
#define REG_SERDES   0x1424
 
#define SERDES_PHY_CLK_SLOWDOWN   BIT(18)
 
#define SERDES_MAC_CLK_SLOWDOWN   BIT(17)
 
#define SERDES_SELFB_PLL_MASK   0x3UL
 
#define SERDES_SELFB_PLL_SHIFT   14
 
#define SERDES_PHYCLK_SEL_GTX   BIT(13) /* 1:gtx_clk, 0:25M */
 
#define SERDES_PCIECLK_SEL_SRDS   BIT(12) /* 1:serdes,0:25M */
 
#define SERDES_BUFS_RX_EN   BIT(11)
 
#define SERDES_PD_RX   BIT(10)
 
#define SERDES_PLL_EN   BIT(9)
 
#define SERDES_EN   BIT(8)
 
#define SERDES_SELFB_PLL_SEL_CSR   BIT(6) /* 0:state-machine,1:csr */
 
#define SERDES_SELFB_PLL_CSR_MASK   0x3UL
 
#define SERDES_SELFB_PLL_CSR_SHIFT   4
 
#define SERDES_SELFB_PLL_CSR_4   3 /* 4-12% OV-CLK */
 
#define SERDES_SELFB_PLL_CSR_0   2 /* 0-4% OV-CLK */
 
#define SERDES_SELFB_PLL_CSR_12   1 /* 12-18% OV-CLK */
 
#define SERDES_SELFB_PLL_CSR_18   0 /* 18-25% OV-CLK */
 
#define SERDES_VCO_SLOW   BIT(3)
 
#define SERDES_VCO_FAST   BIT(2)
 
#define SERDES_LOCK_DETECT_EN   BIT(1)
 
#define SERDES_LOCK_DETECT   BIT(0)
 
#define REG_LPI_DECISN_TIMER   0x143C
 
#define L2CB_LPI_DESISN_TIMER   0x7D00
 
#define REG_LPI_CTRL   0x1440
 
#define LPI_CTRL_CHK_DA   BIT(31)
 
#define LPI_CTRL_ENH_TO_MASK   0x1FFFUL
 
#define LPI_CTRL_ENH_TO_SHIFT   12
 
#define LPI_CTRL_ENH_TH_MASK   0x1FUL
 
#define LPI_CTRL_ENH_TH_SHIFT   6
 
#define LPI_CTRL_ENH_EN   BIT(5)
 
#define LPI_CTRL_CHK_RX   BIT(4)
 
#define LPI_CTRL_CHK_STATE   BIT(3)
 
#define LPI_CTRL_GMII   BIT(2)
 
#define LPI_CTRL_TO_PHY   BIT(1)
 
#define LPI_CTRL_EN   BIT(0)
 
#define REG_LPI_WAIT   0x1444
 
#define LPI_WAIT_TIMER_MASK   0xFFFFUL
 
#define LPI_WAIT_TIMER_SHIFT   0
 
#define REG_MAC_CTRL   0x1480
 
#define MAC_CTRL_SPEED_MODE_SW   BIT(30) /* 0:phy,1:sw */
 
#define MAC_CTRL_HASH_ALG_CRC32   BIT(29) /* 1:legacy,0:lw_5b */
 
#define MAC_CTRL_SINGLE_PAUSE_EN   BIT(28)
 
#define MAC_CTRL_DBG   BIT(27)
 
#define MAC_CTRL_BC_EN   BIT(26)
 
#define MAC_CTRL_MC_ALL_EN   BIT(25)
 
#define MAC_CTRL_RX_CHKSUM_EN   BIT(24)
 
#define MAC_CTRL_TX_HUGE   BIT(23)
 
#define MAC_CTRL_DBG_TX_BKPRESURE   BIT(22)
 
#define MAC_CTRL_SPEED_MASK   3UL
 
#define MAC_CTRL_SPEED_SHIFT   20
 
#define MAC_CTRL_SPEED_10_100   1
 
#define MAC_CTRL_SPEED_1000   2
 
#define MAC_CTRL_TX_SIMURST   BIT(19)
 
#define MAC_CTRL_SCNT   BIT(17)
 
#define MAC_CTRL_TX_PAUSE   BIT(16)
 
#define MAC_CTRL_PROMIS_EN   BIT(15)
 
#define MAC_CTRL_RMV_VLAN   BIT(14)
 
#define MAC_CTRL_PRMLEN_MASK   0xFUL
 
#define MAC_CTRL_PRMLEN_SHIFT   10
 
#define MAC_CTRL_HUGE_EN   BIT(9)
 
#define MAC_CTRL_LENCHK   BIT(8)
 
#define MAC_CTRL_PAD   BIT(7)
 
#define MAC_CTRL_ADD_CRC   BIT(6)
 
#define MAC_CTRL_DUPLX   BIT(5)
 
#define MAC_CTRL_LOOPBACK   BIT(4)
 
#define MAC_CTRL_RX_FLOW   BIT(3)
 
#define MAC_CTRL_TX_FLOW   BIT(2)
 
#define MAC_CTRL_RX_EN   BIT(1)
 
#define MAC_CTRL_TX_EN   BIT(0)
 
#define REG_MAC_IPG_IFG   0x1484
 
#define MAC_IPG_IFG_IPGT_SHIFT
 
#define MAC_IPG_IFG_IPGT_MASK   0x7f
 
#define MAC_IPG_IFG_MIFG_SHIFT
 
#define MAC_IPG_IFG_MIFG_MASK   0xff /* Frame gap below such IFP is dropped */
 
#define MAC_IPG_IFG_IPGR1_SHIFT   16 /* 64bit Carrier-Sense window */
 
#define MAC_IPG_IFG_IPGR1_MASK   0x7f
 
#define MAC_IPG_IFG_IPGR2_SHIFT   24 /* 96-bit IPG window */
 
#define MAC_IPG_IFG_IPGR2_MASK   0x7f
 
#define REG_MAC_STA_ADDR   0x1488
 
#define REG_RX_HASH_TABLE   0x1490
 
#define REG_MAC_HALF_DUPLX_CTRL   0x1498
 
#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT   0 /* Collision Window */
 
#define MAC_HALF_DUPLX_CTRL_LCOL_MASK   0x3ff
 
#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT   12
 
#define MAC_HALF_DUPLX_CTRL_RETRY_MASK   0xf
 
#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN   0x10000
 
#define MAC_HALF_DUPLX_CTRL_NO_BACK_C   0x20000
 
#define MAC_HALF_DUPLX_CTRL_NO_BACK_P
 
#define MAC_HALF_DUPLX_CTRL_ABEBE   0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
 
#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT   20 /* Maximum binary exponential number */
 
#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK   0xf
 
#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT   24 /* IPG to start JAM for collision based flow control in half-duplex */
 
#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK   0xf /* mode. In unit of 8-bit time */
 
#define REG_MTU   0x149c
 
#define REG_WOL_CTRL   0x14a0
 
#define WOL_PT7_MATCH   BIT(31)
 
#define WOL_PT6_MATCH   BIT(30)
 
#define WOL_PT5_MATCH   BIT(29)
 
#define WOL_PT4_MATCH   BIT(28)
 
#define WOL_PT3_MATCH   BIT(27)
 
#define WOL_PT2_MATCH   BIT(26)
 
#define WOL_PT1_MATCH   BIT(25)
 
#define WOL_PT0_MATCH   BIT(24)
 
#define WOL_PT7_EN   BIT(23)
 
#define WOL_PT6_EN   BIT(22)
 
#define WOL_PT5_EN   BIT(21)
 
#define WOL_PT4_EN   BIT(20)
 
#define WOL_PT3_EN   BIT(19)
 
#define WOL_PT2_EN   BIT(18)
 
#define WOL_PT1_EN   BIT(17)
 
#define WOL_PT0_EN   BIT(16)
 
#define WOL_LNKCHG_ST   BIT(10)
 
#define WOL_MAGIC_ST   BIT(9)
 
#define WOL_PATTERN_ST   BIT(8)
 
#define WOL_OOB_EN   BIT(6)
 
#define WOL_LINK_CHG_PME_EN   BIT(5)
 
#define WOL_LINK_CHG_EN   BIT(4)
 
#define WOL_MAGIC_PME_EN   BIT(3)
 
#define WOL_MAGIC_EN   BIT(2)
 
#define WOL_PATTERN_PME_EN   BIT(1)
 
#define WOL_PATTERN_EN   BIT(0)
 
#define REG_WOL_PTLEN1   0x14A4
 
#define WOL_PTLEN1_3_MASK   0xFFUL
 
#define WOL_PTLEN1_3_SHIFT   24
 
#define WOL_PTLEN1_2_MASK   0xFFUL
 
#define WOL_PTLEN1_2_SHIFT   16
 
#define WOL_PTLEN1_1_MASK   0xFFUL
 
#define WOL_PTLEN1_1_SHIFT   8
 
#define WOL_PTLEN1_0_MASK   0xFFUL
 
#define WOL_PTLEN1_0_SHIFT   0
 
#define REG_WOL_PTLEN2   0x14A8
 
#define WOL_PTLEN2_7_MASK   0xFFUL
 
#define WOL_PTLEN2_7_SHIFT   24
 
#define WOL_PTLEN2_6_MASK   0xFFUL
 
#define WOL_PTLEN2_6_SHIFT   16
 
#define WOL_PTLEN2_5_MASK   0xFFUL
 
#define WOL_PTLEN2_5_SHIFT   8
 
#define WOL_PTLEN2_4_MASK   0xFFUL
 
#define WOL_PTLEN2_4_SHIFT   0
 
#define RFDX_HEAD_ADDR_MASK   0x03FF
 
#define RFDX_HARD_ADDR_SHIFT   0
 
#define RFDX_TAIL_ADDR_MASK   0x03FF
 
#define RFDX_TAIL_ADDR_SHIFT   16
 
#define REG_SRAM_RFD0_INFO   0x1500
 
#define REG_SRAM_RFD1_INFO   0x1504
 
#define REG_SRAM_RFD2_INFO   0x1508
 
#define REG_SRAM_RFD3_INFO   0x150C
 
#define REG_RFD_NIC_LEN   0x1510 /* In 8-bytes */
 
#define RFD_NIC_LEN_MASK   0x03FF
 
#define REG_SRAM_TRD_ADDR   0x1518
 
#define TPD_HEAD_ADDR_MASK   0x03FF
 
#define TPD_HEAD_ADDR_SHIFT   0
 
#define TPD_TAIL_ADDR_MASK   0x03FF
 
#define TPD_TAIL_ADDR_SHIFT   16
 
#define REG_SRAM_TRD_LEN   0x151C /* In 8-bytes */
 
#define TPD_NIC_LEN_MASK   0x03FF
 
#define REG_SRAM_RXF_ADDR   0x1520
 
#define REG_SRAM_RXF_LEN   0x1524
 
#define REG_SRAM_TXF_ADDR   0x1528
 
#define REG_SRAM_TXF_LEN   0x152C
 
#define REG_SRAM_TCPH_ADDR   0x1530
 
#define REG_SRAM_PKTH_ADDR   0x1532
 
#define REG_LOAD_PTR   0x1534
 
#define REG_RX_BASE_ADDR_HI   0x1540
 
#define REG_TX_BASE_ADDR_HI   0x1544
 
#define REG_RFD0_HEAD_ADDR_LO   0x1550
 
#define REG_RFD_RING_SIZE   0x1560
 
#define RFD_RING_SIZE_MASK   0x0FFF
 
#define REG_RX_BUF_SIZE   0x1564
 
#define RX_BUF_SIZE_MASK   0xFFFF
 
#define REG_RRD0_HEAD_ADDR_LO   0x1568
 
#define REG_RRD_RING_SIZE   0x1578
 
#define RRD_RING_SIZE_MASK   0x0FFF
 
#define REG_TPD_PRI1_ADDR_LO   0x157C
 
#define REG_TPD_PRI0_ADDR_LO   0x1580
 
#define REG_TPD_RING_SIZE   0x1584
 
#define TPD_RING_SIZE_MASK   0xFFFF
 
#define REG_TXQ_CTRL   0x1590
 
#define TXQ_TXF_BURST_NUM_MASK   0xFFFFUL
 
#define TXQ_TXF_BURST_NUM_SHIFT   16
 
#define L1C_TXQ_TXF_BURST_PREF   0x200
 
#define L2CB_TXQ_TXF_BURST_PREF   0x40
 
#define TXQ_CTRL_PEDING_CLR   BIT(8)
 
#define TXQ_CTRL_LS_8023_EN   BIT(7)
 
#define TXQ_CTRL_ENH_MODE   BIT(6)
 
#define TXQ_CTRL_EN   BIT(5)
 
#define TXQ_CTRL_IP_OPTION_EN   BIT(4)
 
#define TXQ_NUM_TPD_BURST_MASK   0xFUL
 
#define TXQ_NUM_TPD_BURST_SHIFT   0
 
#define TXQ_NUM_TPD_BURST_DEF   5
 
#define TXQ_CFGV
 
#define L1C_TXQ_CFGV
 
#define L2CB_TXQ_CFGV
 
#define REG_TX_TSO_OFFLOAD_THRESH   0x1594 /* In 8-bytes */
 
#define TX_TSO_OFFLOAD_THRESH_MASK   0x07FF
 
#define MAX_TSO_FRAME_SIZE   (7*1024)
 
#define REG_TXF_WATER_MARK   0x1598 /* In 8-bytes */
 
#define TXF_WATER_MARK_MASK   0x0FFF
 
#define TXF_LOW_WATER_MARK_SHIFT   0
 
#define TXF_HIGH_WATER_MARK_SHIFT   16
 
#define TXQ_CTRL_BURST_MODE_EN   0x80000000
 
#define REG_THRUPUT_MON_CTRL   0x159C
 
#define THRUPUT_MON_RATE_MASK   0x3
 
#define THRUPUT_MON_RATE_SHIFT   0
 
#define THRUPUT_MON_EN   0x80
 
#define REG_RXQ_CTRL   0x15A0
 
#define ASPM_THRUPUT_LIMIT_MASK   0x3
 
#define ASPM_THRUPUT_LIMIT_SHIFT   0
 
#define ASPM_THRUPUT_LIMIT_NO   0x00
 
#define ASPM_THRUPUT_LIMIT_1M   0x01
 
#define ASPM_THRUPUT_LIMIT_10M   0x02
 
#define ASPM_THRUPUT_LIMIT_100M   0x03
 
#define IPV6_CHKSUM_CTRL_EN   BIT(7)
 
#define RXQ_RFD_BURST_NUM_MASK   0x003F
 
#define RXQ_RFD_BURST_NUM_SHIFT   20
 
#define RXQ_NUM_RFD_PREF_DEF   8
 
#define RSS_MODE_MASK   3UL
 
#define RSS_MODE_SHIFT   26
 
#define RSS_MODE_DIS   0
 
#define RSS_MODE_SQSI   1
 
#define RSS_MODE_MQSI   2
 
#define RSS_MODE_MQMI   3
 
#define RSS_NIP_QUEUE_SEL   BIT(28) /* 0:q0, 1:table */
 
#define RRS_HASH_CTRL_EN   BIT(29)
 
#define RX_CUT_THRU_EN   BIT(30)
 
#define RXQ_CTRL_EN   BIT(31)
 
#define REG_RFD_FREE_THRESH   0x15A4
 
#define RFD_FREE_THRESH_MASK   0x003F
 
#define RFD_FREE_HI_THRESH_SHIFT   0
 
#define RFD_FREE_LO_THRESH_SHIFT   6
 
#define REG_RXQ_RXF_PAUSE_THRESH   0x15A8
 
#define RXQ_RXF_PAUSE_TH_HI_SHIFT   0
 
#define RXQ_RXF_PAUSE_TH_HI_MASK   0x0FFF
 
#define RXQ_RXF_PAUSE_TH_LO_SHIFT   16
 
#define RXQ_RXF_PAUSE_TH_LO_MASK   0x0FFF
 
#define REG_RXD_DMA_CTRL   0x15AC
 
#define RXD_DMA_THRESH_MASK   0x0FFF /* In 8-bytes */
 
#define RXD_DMA_THRESH_SHIFT   0
 
#define RXD_DMA_DOWN_TIMER_MASK   0xFFFF
 
#define RXD_DMA_DOWN_TIMER_SHIFT   16
 
#define REG_DMA_CTRL   0x15C0
 
#define DMA_CTRL_SMB_NOW   BIT(31)
 
#define DMA_CTRL_WPEND_CLR   BIT(30)
 
#define DMA_CTRL_RPEND_CLR   BIT(29)
 
#define DMA_CTRL_WDLY_CNT_MASK   0xFUL
 
#define DMA_CTRL_WDLY_CNT_SHIFT   16
 
#define DMA_CTRL_WDLY_CNT_DEF   4
 
#define DMA_CTRL_RDLY_CNT_MASK   0x1FUL
 
#define DMA_CTRL_RDLY_CNT_SHIFT   11
 
#define DMA_CTRL_RDLY_CNT_DEF   15
 
#define DMA_CTRL_RREQ_PRI_DATA   BIT(10) /* 0:tpd, 1:data */
 
#define DMA_CTRL_WREQ_BLEN_MASK   7UL
 
#define DMA_CTRL_WREQ_BLEN_SHIFT   7
 
#define DMA_CTRL_RREQ_BLEN_MASK   7UL
 
#define DMA_CTRL_RREQ_BLEN_SHIFT   4
 
#define L1C_CTRL_DMA_RCB_LEN128   BIT(3) /* 0:64bytes,1:128bytes */
 
#define DMA_CTRL_RORDER_MODE_MASK   7UL
 
#define DMA_CTRL_RORDER_MODE_SHIFT   0
 
#define DMA_CTRL_RORDER_MODE_OUT   4
 
#define DMA_CTRL_RORDER_MODE_ENHANCE   2
 
#define DMA_CTRL_RORDER_MODE_IN   1
 
#define REG_SMB_STAT_TIMER   0x15C4 /* 2us resolution */
 
#define SMB_STAT_TIMER_MASK   0xFFFFFF
 
#define REG_TINT_TPD_THRESH   0x15C8 /* tpd th to trig intrrupt */
 
#define MB_RFDX_PROD_IDX_MASK   0xFFFF
 
#define REG_MB_RFD0_PROD_IDX   0x15E0
 
#define REG_TPD_PRI1_PIDX   0x15F0 /* 16bit,hi-tpd producer idx */
 
#define REG_TPD_PRI0_PIDX   0x15F2 /* 16bit,lo-tpd producer idx */
 
#define REG_TPD_PRI1_CIDX   0x15F4 /* 16bit,hi-tpd consumer idx */
 
#define REG_TPD_PRI0_CIDX   0x15F6 /* 16bit,lo-tpd consumer idx */
 
#define REG_MB_RFD01_CONS_IDX   0x15F8
 
#define MB_RFD0_CONS_IDX_MASK   0x0000FFFF
 
#define MB_RFD1_CONS_IDX_MASK   0xFFFF0000
 
#define REG_ISR   0x1600
 
#define ISR_SMB   0x00000001
 
#define ISR_TIMER   0x00000002
 
#define ISR_MANUAL   0x00000004
 
#define ISR_HW_RXF_OV   0x00000008 /* RXF overflow interrupt */
 
#define ISR_RFD0_UR   0x00000010 /* RFD0 under run */
 
#define ISR_RFD1_UR   0x00000020
 
#define ISR_RFD2_UR   0x00000040
 
#define ISR_RFD3_UR   0x00000080
 
#define ISR_TXF_UR   0x00000100
 
#define ISR_DMAR_TO_RST   0x00000200
 
#define ISR_DMAW_TO_RST   0x00000400
 
#define ISR_TX_CREDIT   0x00000800
 
#define ISR_GPHY   0x00001000
 
#define ISR_GPHY_LPW   0x00002000
 
#define ISR_TXQ_TO_RST   0x00004000
 
#define ISR_TX_PKT   0x00008000
 
#define ISR_RX_PKT_0   0x00010000
 
#define ISR_RX_PKT_1   0x00020000
 
#define ISR_RX_PKT_2   0x00040000
 
#define ISR_RX_PKT_3   0x00080000
 
#define ISR_MAC_RX   0x00100000
 
#define ISR_MAC_TX   0x00200000
 
#define ISR_UR_DETECTED   0x00400000
 
#define ISR_FERR_DETECTED   0x00800000
 
#define ISR_NFERR_DETECTED   0x01000000
 
#define ISR_CERR_DETECTED   0x02000000
 
#define ISR_PHY_LINKDOWN   0x04000000
 
#define ISR_DIS_INT   0x80000000
 
#define REG_IMR   0x1604
 
#define IMR_NORMAL_MASK
 
#define ISR_RX_PKT
 
#define ISR_OVER
 
#define ISR_ERROR
 
#define REG_INT_RETRIG_TIMER   0x1608
 
#define INT_RETRIG_TIMER_MASK   0xFFFF
 
#define REG_MAC_RX_STATUS_BIN   0x1700
 
#define REG_MAC_RX_STATUS_END   0x175c
 
#define REG_MAC_TX_STATUS_BIN   0x1760
 
#define REG_MAC_TX_STATUS_END   0x17c0
 
#define REG_CLK_GATING_CTRL   0x1814
 
#define CLK_GATING_DMAW_EN   0x0001
 
#define CLK_GATING_DMAR_EN   0x0002
 
#define CLK_GATING_TXQ_EN   0x0004
 
#define CLK_GATING_RXQ_EN   0x0008
 
#define CLK_GATING_TXMAC_EN   0x0010
 
#define CLK_GATING_RXMAC_EN   0x0020
 
#define CLK_GATING_EN_ALL
 
#define REG_DEBUG_DATA0   0x1900
 
#define REG_DEBUG_DATA1   0x1904
 
#define L1D_MPW_PHYID1   0xD01C /* V7 */
 
#define L1D_MPW_PHYID2   0xD01D /* V1-V6 */
 
#define L1D_MPW_PHYID3   0xD01E /* V8 */
 
#define ADVERTISE_DEFAULT_CAP   (ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)
 
#define GIGA_CR_1000T_REPEATER_DTE   0x0400 /* 1=Repeater/switch device port 0=DTE device */
 
#define GIGA_CR_1000T_MS_VALUE   0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
 
#define GIGA_CR_1000T_MS_ENABLE   0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
 
#define GIGA_CR_1000T_TEST_MODE_NORMAL   0x0000 /* Normal Operation */
 
#define GIGA_CR_1000T_TEST_MODE_1   0x2000 /* Transmit Waveform test */
 
#define GIGA_CR_1000T_TEST_MODE_2   0x4000 /* Master Transmit Jitter test */
 
#define GIGA_CR_1000T_TEST_MODE_3   0x6000 /* Slave Transmit Jitter test */
 
#define GIGA_CR_1000T_TEST_MODE_4   0x8000 /* Transmitter Distortion test */
 
#define GIGA_CR_1000T_SPEED_MASK   0x0300
 
#define GIGA_CR_1000T_DEFAULT_CAP   0x0300
 
#define MII_GIGA_PSSR   0x11
 
#define GIGA_PSSR_SPD_DPLX_RESOLVED   0x0800 /* 1=Speed & Duplex resolved */
 
#define GIGA_PSSR_DPLX   0x2000 /* 1=Duplex 0=Half Duplex */
 
#define GIGA_PSSR_SPEED   0xC000 /* Speed, bits 14:15 */
 
#define GIGA_PSSR_10MBS   0x0000 /* 00=10Mbs */
 
#define GIGA_PSSR_100MBS   0x4000 /* 01=100Mbs */
 
#define GIGA_PSSR_1000MBS   0x8000 /* 10=1000Mbs */
 
#define MII_IER   0x12
 
#define IER_LINK_UP   0x0400
 
#define IER_LINK_DOWN   0x0800
 
#define MII_ISR   0x13
 
#define ISR_LINK_UP   0x0400
 
#define ISR_LINK_DOWN   0x0800
 
#define MII_CDTC   0x16
 
#define CDTC_EN_OFF   0 /* sc */
 
#define CDTC_EN_BITS   1
 
#define CDTC_PAIR_OFF   8
 
#define CDTC_PAIR_BIT   2
 
#define MII_CDTS   0x1C
 
#define CDTS_STATUS_OFF   8
 
#define CDTS_STATUS_BITS   2
 
#define CDTS_STATUS_NORMAL   0
 
#define CDTS_STATUS_SHORT   1
 
#define CDTS_STATUS_OPEN   2
 
#define CDTS_STATUS_INVALID   3
 
#define MII_DBG_ADDR   0x1D
 
#define MII_DBG_DATA   0x1E
 
#define MIIDBG_ANACTRL   0x00
 
#define ANACTRL_CLK125M_DELAY_EN   0x8000
 
#define ANACTRL_VCO_FAST   0x4000
 
#define ANACTRL_VCO_SLOW   0x2000
 
#define ANACTRL_AFE_MODE_EN   0x1000
 
#define ANACTRL_LCKDET_PHY   0x800
 
#define ANACTRL_LCKDET_EN   0x400
 
#define ANACTRL_OEN_125M   0x200
 
#define ANACTRL_HBIAS_EN   0x100
 
#define ANACTRL_HB_EN   0x80
 
#define ANACTRL_SEL_HSP   0x40
 
#define ANACTRL_CLASSA_EN   0x20
 
#define ANACTRL_MANUSWON_SWR_MASK   3U
 
#define ANACTRL_MANUSWON_SWR_SHIFT   2
 
#define ANACTRL_MANUSWON_SWR_2V   0
 
#define ANACTRL_MANUSWON_SWR_1P9V   1
 
#define ANACTRL_MANUSWON_SWR_1P8V   2
 
#define ANACTRL_MANUSWON_SWR_1P7V   3
 
#define ANACTRL_MANUSWON_BW3_4M   0x2
 
#define ANACTRL_RESTART_CAL   0x1
 
#define ANACTRL_DEF   0x02EF
 
#define MIIDBG_SYSMODCTRL   0x04
 
#define SYSMODCTRL_IECHOADJ_PFMH_PHY   0x8000
 
#define SYSMODCTRL_IECHOADJ_BIASGEN   0x4000
 
#define SYSMODCTRL_IECHOADJ_PFML_PHY   0x2000
 
#define SYSMODCTRL_IECHOADJ_PS_MASK   3U
 
#define SYSMODCTRL_IECHOADJ_PS_SHIFT   10
 
#define SYSMODCTRL_IECHOADJ_PS_40   3
 
#define SYSMODCTRL_IECHOADJ_PS_20   2
 
#define SYSMODCTRL_IECHOADJ_PS_0   1
 
#define SYSMODCTRL_IECHOADJ_10BT_100MV   0x40 /* 1:100mv, 0:200mv */
 
#define SYSMODCTRL_IECHOADJ_HLFAP_MASK   3U
 
#define SYSMODCTRL_IECHOADJ_HLFAP_SHIFT   4
 
#define SYSMODCTRL_IECHOADJ_VDFULBW   0x8
 
#define SYSMODCTRL_IECHOADJ_VDBIASHLF   0x4
 
#define SYSMODCTRL_IECHOADJ_VDAMPHLF   0x2
 
#define SYSMODCTRL_IECHOADJ_VDLANSW   0x1
 
#define SYSMODCTRL_IECHOADJ_DEF   0x88BB /* ???? */
 
#define SYSMODCTRL_IECHOADJ_CUR_ADD   0x8000
 
#define SYSMODCTRL_IECHOADJ_CUR_MASK   7U
 
#define SYSMODCTRL_IECHOADJ_CUR_SHIFT   12
 
#define SYSMODCTRL_IECHOADJ_VOL_MASK   0xFU
 
#define SYSMODCTRL_IECHOADJ_VOL_SHIFT   8
 
#define SYSMODCTRL_IECHOADJ_VOL_17ALL   3
 
#define SYSMODCTRL_IECHOADJ_VOL_100M15   1
 
#define SYSMODCTRL_IECHOADJ_VOL_10M17   0
 
#define SYSMODCTRL_IECHOADJ_BIAS1_MASK   0xFU
 
#define SYSMODCTRL_IECHOADJ_BIAS1_SHIFT   4
 
#define SYSMODCTRL_IECHOADJ_BIAS2_MASK   0xFU
 
#define SYSMODCTRL_IECHOADJ_BIAS2_SHIFT   0
 
#define L1D_SYSMODCTRL_IECHOADJ_DEF   0x4FBB
 
#define MIIDBG_SRDSYSMOD   0x05
 
#define SRDSYSMOD_LCKDET_EN   0x2000
 
#define SRDSYSMOD_PLL_EN   0x800
 
#define SRDSYSMOD_SEL_HSP   0x400
 
#define SRDSYSMOD_HLFTXDR   0x200
 
#define SRDSYSMOD_TXCLK_DELAY_EN   0x100
 
#define SRDSYSMOD_TXELECIDLE   0x80
 
#define SRDSYSMOD_DEEMP_EN   0x40
 
#define SRDSYSMOD_MS_PAD   0x4
 
#define SRDSYSMOD_CDR_ADC_VLTG   0x2
 
#define SRDSYSMOD_CDR_DAC_1MA   0x1
 
#define SRDSYSMOD_DEF   0x2C46
 
#define MIIDBG_CFGLPSPD   0x0A
 
#define CFGLPSPD_RSTCNT_MASK   3U
 
#define CFGLPSPD_RSTCNT_SHIFT   14
 
#define CFGLPSPD_RSTCNT_CLK125SW   0x2000
 
#define MIIDBG_HIBNEG   0x0B
 
#define HIBNEG_PSHIB_EN   0x8000
 
#define HIBNEG_WAKE_BOTH   0x4000
 
#define HIBNEG_ONOFF_ANACHG_SUDEN   0x2000
 
#define HIBNEG_HIB_PULSE   0x1000
 
#define HIBNEG_GATE_25M_EN   0x800
 
#define HIBNEG_RST_80U   0x400
 
#define HIBNEG_RST_TIMER_MASK   3U
 
#define HIBNEG_RST_TIMER_SHIFT   8
 
#define HIBNEG_GTX_CLK_DELAY_MASK   3U
 
#define HIBNEG_GTX_CLK_DELAY_SHIFT   5
 
#define HIBNEG_BYPSS_BRKTIMER   0x10
 
#define HIBNEG_DEF   0xBC40
 
#define MIIDBG_TST10BTCFG   0x12
 
#define TST10BTCFG_INTV_TIMER_MASK   3U
 
#define TST10BTCFG_INTV_TIMER_SHIFT   14
 
#define TST10BTCFG_TRIGER_TIMER_MASK   3U
 
#define TST10BTCFG_TRIGER_TIMER_SHIFT   12
 
#define TST10BTCFG_DIV_MAN_MLT3_EN   0x800
 
#define TST10BTCFG_OFF_DAC_IDLE   0x400
 
#define TST10BTCFG_LPBK_DEEP   0x4 /* 1:deep,0:shallow */
 
#define TST10BTCFG_DEF   0x4C04
 
#define MIIDBG_AZ_ANADECT   0x15
 
#define AZ_ANADECT_10BTRX_TH   0x8000
 
#define AZ_ANADECT_BOTH_01CHNL   0x4000
 
#define AZ_ANADECT_INTV_MASK   0x3FU
 
#define AZ_ANADECT_INTV_SHIFT   8
 
#define AZ_ANADECT_THRESH_MASK   0xFU
 
#define AZ_ANADECT_THRESH_SHIFT   4
 
#define AZ_ANADECT_CHNL_MASK   0xFU
 
#define AZ_ANADECT_CHNL_SHIFT   0
 
#define AZ_ANADECT_DEF   0x3220
 
#define AZ_ANADECT_LONG   0xb210
 
#define MIIDBG_MSE16DB   0x18 /* l1d */
 
#define L1D_MSE16DB_UP   0x05EA
 
#define L1D_MSE16DB_DOWN   0x02EA
 
#define MIIDBG_LEGCYPS   0x29
 
#define LEGCYPS_EN   0x8000
 
#define LEGCYPS_DAC_AMP1000_MASK   7U
 
#define LEGCYPS_DAC_AMP1000_SHIFT   12
 
#define LEGCYPS_DAC_AMP100_MASK   7U
 
#define LEGCYPS_DAC_AMP100_SHIFT   9
 
#define LEGCYPS_DAC_AMP10_MASK   7U
 
#define LEGCYPS_DAC_AMP10_SHIFT   6
 
#define LEGCYPS_UNPLUG_TIMER_MASK   7U
 
#define LEGCYPS_UNPLUG_TIMER_SHIFT   3
 
#define LEGCYPS_UNPLUG_DECT_EN   0x4
 
#define LEGCYPS_ECNC_PS_EN   0x1
 
#define L1D_LEGCYPS_DEF   0x129D
 
#define L1C_LEGCYPS_DEF   0x36DD
 
#define MIIDBG_TST100BTCFG   0x36
 
#define TST100BTCFG_NORMAL_BW_EN   0x8000
 
#define TST100BTCFG_BADLNK_BYPASS   0x4000
 
#define TST100BTCFG_SHORTCABL_TH_MASK   0x3FU
 
#define TST100BTCFG_SHORTCABL_TH_SHIFT   8
 
#define TST100BTCFG_LITCH_EN   0x80
 
#define TST100BTCFG_VLT_SW   0x40
 
#define TST100BTCFG_LONGCABL_TH_MASK   0x3FU
 
#define TST100BTCFG_LONGCABL_TH_SHIFT   0
 
#define TST100BTCFG_DEF   0xE12C
 
#define MIIDBG_VOLT_CTRL   0x3B /* only for l2cb 1 & 2 */
 
#define VOLT_CTRL_CABLE1TH_MASK   0x1FFU
 
#define VOLT_CTRL_CABLE1TH_SHIFT   7
 
#define VOLT_CTRL_AMPCTRL_MASK   3U
 
#define VOLT_CTRL_AMPCTRL_SHIFT   5
 
#define VOLT_CTRL_SW_BYPASS   0x10
 
#define VOLT_CTRL_SWLOWEST   0x8
 
#define VOLT_CTRL_DACAMP10_MASK   7U
 
#define VOLT_CTRL_DACAMP10_SHIFT   0
 
#define MIIDBG_CABLE1TH_DET   0x3E
 
#define CABLE1TH_DET_EN   0x8000
 
#define MIIEXT_PCS   3
 
#define MIIEXT_CLDCTRL3   0x8003
 
#define CLDCTRL3_BP_CABLE1TH_DET_GT   0x8000
 
#define CLDCTRL3_AZ_DISAMP   0x1000
 
#define L2CB_CLDCTRL3   0x4D19
 
#define L1D_CLDCTRL3   0xDD19
 
#define MIIEXT_CLDCTRL6   0x8006
 
#define CLDCTRL6_CAB_LEN_MASK   0x1FFU
 
#define CLDCTRL6_CAB_LEN_SHIFT   0
 
#define CLDCTRL6_CAB_LEN_SHORT   0x50
 
#define MIIEXT_ANEG   7
 
#define MIIEXT_LOCAL_EEEADV   0x3C
 
#define LOCAL_EEEADV_1000BT   0x4
 
#define LOCAL_EEEADV_100BT   0x2
 
#define MIIEXT_REMOTE_EEEADV   0x3D
 
#define REMOTE_EEEADV_1000BT   0x4
 
#define REMOTE_EEEADV_100BT   0x2
 
#define MIIEXT_EEE_ANEG   0x8000
 
#define EEE_ANEG_1000M   0x4
 
#define EEE_ANEG_100M   0x2
 

Functions

void atl1c_phy_disable (struct atl1c_hw *hw)
 
void atl1c_hw_set_mac_addr (struct atl1c_hw *hw, u8 *mac_addr)
 
int atl1c_phy_reset (struct atl1c_hw *hw)
 
int atl1c_read_mac_addr (struct atl1c_hw *hw)
 
int atl1c_get_speed_and_duplex (struct atl1c_hw *hw, u16 *speed, u16 *duplex)
 
u32 atl1c_hash_mc_addr (struct atl1c_hw *hw, u8 *mc_addr)
 
void atl1c_hash_set (struct atl1c_hw *hw, u32 hash_value)
 
int atl1c_read_phy_reg (struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
 
int atl1c_write_phy_reg (struct atl1c_hw *hw, u32 reg_addr, u16 phy_data)
 
bool atl1c_read_eeprom (struct atl1c_hw *hw, u32 offset, u32 *p_value)
 
int atl1c_phy_init (struct atl1c_hw *hw)
 
int atl1c_check_eeprom_exist (struct atl1c_hw *hw)
 
int atl1c_restart_autoneg (struct atl1c_hw *hw)
 
int atl1c_phy_to_ps_link (struct atl1c_hw *hw)
 
int atl1c_power_saving (struct atl1c_hw *hw, u32 wufc)
 
bool atl1c_wait_mdio_idle (struct atl1c_hw *hw)
 
void atl1c_stop_phy_polling (struct atl1c_hw *hw)
 
void atl1c_start_phy_polling (struct atl1c_hw *hw, u16 clk_sel)
 
int atl1c_read_phy_core (struct atl1c_hw *hw, bool ext, u8 dev, u16 reg, u16 *phy_data)
 
int atl1c_write_phy_core (struct atl1c_hw *hw, bool ext, u8 dev, u16 reg, u16 phy_data)
 
int atl1c_read_phy_ext (struct atl1c_hw *hw, u8 dev_addr, u16 reg_addr, u16 *phy_data)
 
int atl1c_write_phy_ext (struct atl1c_hw *hw, u8 dev_addr, u16 reg_addr, u16 phy_data)
 
int atl1c_read_phy_dbg (struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
 
int atl1c_write_phy_dbg (struct atl1c_hw *hw, u16 reg_addr, u16 phy_data)
 
void atl1c_post_phy_linkchg (struct atl1c_hw *hw, u16 link_speed)
 

Macro Definition Documentation

#define ADVERTISE_DEFAULT_CAP   (ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)

Definition at line 774 of file atl1c_hw.h.

#define ANACTRL_AFE_MODE_EN   0x1000

Definition at line 834 of file atl1c_hw.h.

#define ANACTRL_CLASSA_EN   0x20

Definition at line 841 of file atl1c_hw.h.

#define ANACTRL_CLK125M_DELAY_EN   0x8000

Definition at line 831 of file atl1c_hw.h.

#define ANACTRL_DEF   0x02EF

Definition at line 850 of file atl1c_hw.h.

#define ANACTRL_HB_EN   0x80

Definition at line 839 of file atl1c_hw.h.

#define ANACTRL_HBIAS_EN   0x100

Definition at line 838 of file atl1c_hw.h.

#define ANACTRL_LCKDET_EN   0x400

Definition at line 836 of file atl1c_hw.h.

#define ANACTRL_LCKDET_PHY   0x800

Definition at line 835 of file atl1c_hw.h.

#define ANACTRL_MANUSWON_BW3_4M   0x2

Definition at line 848 of file atl1c_hw.h.

#define ANACTRL_MANUSWON_SWR_1P7V   3

Definition at line 847 of file atl1c_hw.h.

#define ANACTRL_MANUSWON_SWR_1P8V   2

Definition at line 846 of file atl1c_hw.h.

#define ANACTRL_MANUSWON_SWR_1P9V   1

Definition at line 845 of file atl1c_hw.h.

#define ANACTRL_MANUSWON_SWR_2V   0

Definition at line 844 of file atl1c_hw.h.

#define ANACTRL_MANUSWON_SWR_MASK   3U

Definition at line 842 of file atl1c_hw.h.

#define ANACTRL_MANUSWON_SWR_SHIFT   2

Definition at line 843 of file atl1c_hw.h.

#define ANACTRL_OEN_125M   0x200

Definition at line 837 of file atl1c_hw.h.

#define ANACTRL_RESTART_CAL   0x1

Definition at line 849 of file atl1c_hw.h.

#define ANACTRL_SEL_HSP   0x40

Definition at line 840 of file atl1c_hw.h.

#define ANACTRL_VCO_FAST   0x4000

Definition at line 832 of file atl1c_hw.h.

#define ANACTRL_VCO_SLOW   0x2000

Definition at line 833 of file atl1c_hw.h.

#define ASPM_THRUPUT_LIMIT_100M   0x03

Definition at line 593 of file atl1c_hw.h.

#define ASPM_THRUPUT_LIMIT_10M   0x02

Definition at line 592 of file atl1c_hw.h.

#define ASPM_THRUPUT_LIMIT_1M   0x01

Definition at line 591 of file atl1c_hw.h.

#define ASPM_THRUPUT_LIMIT_MASK   0x3

Definition at line 588 of file atl1c_hw.h.

#define ASPM_THRUPUT_LIMIT_NO   0x00

Definition at line 590 of file atl1c_hw.h.

#define ASPM_THRUPUT_LIMIT_SHIFT   0

Definition at line 589 of file atl1c_hw.h.

#define AZ_ANADECT_10BTRX_TH   0x8000

Definition at line 928 of file atl1c_hw.h.

#define AZ_ANADECT_BOTH_01CHNL   0x4000

Definition at line 929 of file atl1c_hw.h.

#define AZ_ANADECT_CHNL_MASK   0xFU

Definition at line 934 of file atl1c_hw.h.

#define AZ_ANADECT_CHNL_SHIFT   0

Definition at line 935 of file atl1c_hw.h.

#define AZ_ANADECT_DEF   0x3220

Definition at line 936 of file atl1c_hw.h.

#define AZ_ANADECT_INTV_MASK   0x3FU

Definition at line 930 of file atl1c_hw.h.

#define AZ_ANADECT_INTV_SHIFT   8

Definition at line 931 of file atl1c_hw.h.

#define AZ_ANADECT_LONG   0xb210

Definition at line 937 of file atl1c_hw.h.

#define AZ_ANADECT_THRESH_MASK   0xFU

Definition at line 932 of file atl1c_hw.h.

#define AZ_ANADECT_THRESH_SHIFT   4

Definition at line 933 of file atl1c_hw.h.

#define BIST0_FUSE_FLAG   0x4

Definition at line 317 of file atl1c_hw.h.

#define BIST0_NOW   0x1

Definition at line 315 of file atl1c_hw.h.

#define BIST0_SRAM_FAIL
Value:
0x2 /* 1: The SRAM failure is
* un-repairable because
* it has address decoder
* failure or more than 1 cell
* stuck-to-x failure */

Definition at line 316 of file atl1c_hw.h.

#define BIST1_FUSE_FLAG   0x4

Definition at line 323 of file atl1c_hw.h.

#define BIST1_NOW   0x1

Definition at line 321 of file atl1c_hw.h.

#define BIST1_SRAM_FAIL   0x2

Definition at line 322 of file atl1c_hw.h.

#define CABLE1TH_DET_EN   0x8000

Definition at line 980 of file atl1c_hw.h.

#define CDTC_EN_BITS   1

Definition at line 812 of file atl1c_hw.h.

#define CDTC_EN_OFF   0 /* sc */

Definition at line 811 of file atl1c_hw.h.

#define CDTC_PAIR_BIT   2

Definition at line 814 of file atl1c_hw.h.

#define CDTC_PAIR_OFF   8

Definition at line 813 of file atl1c_hw.h.

#define CDTS_STATUS_BITS   2

Definition at line 819 of file atl1c_hw.h.

#define CDTS_STATUS_INVALID   3

Definition at line 823 of file atl1c_hw.h.

#define CDTS_STATUS_NORMAL   0

Definition at line 820 of file atl1c_hw.h.

#define CDTS_STATUS_OFF   8

Definition at line 818 of file atl1c_hw.h.

#define CDTS_STATUS_OPEN   2

Definition at line 822 of file atl1c_hw.h.

#define CDTS_STATUS_SHORT   1

Definition at line 821 of file atl1c_hw.h.

#define CFGLPSPD_RSTCNT_CLK125SW   0x2000

Definition at line 901 of file atl1c_hw.h.

#define CFGLPSPD_RSTCNT_MASK   3U

Definition at line 899 of file atl1c_hw.h.

#define CFGLPSPD_RSTCNT_SHIFT   14

Definition at line 900 of file atl1c_hw.h.

#define CLDCTRL3_AZ_DISAMP   0x1000

Definition at line 988 of file atl1c_hw.h.

#define CLDCTRL3_BP_CABLE1TH_DET_GT   0x8000

Definition at line 987 of file atl1c_hw.h.

#define CLDCTRL6_CAB_LEN_MASK   0x1FFU

Definition at line 993 of file atl1c_hw.h.

#define CLDCTRL6_CAB_LEN_SHIFT   0

Definition at line 994 of file atl1c_hw.h.

#define CLDCTRL6_CAB_LEN_SHORT   0x50

Definition at line 995 of file atl1c_hw.h.

#define CLK_GATING_DMAR_EN   0x0002

Definition at line 751 of file atl1c_hw.h.

#define CLK_GATING_DMAW_EN   0x0001

Definition at line 750 of file atl1c_hw.h.

#define CLK_GATING_EN_ALL
Value:
(CLK_GATING_DMAW_EN |\
CLK_GATING_DMAR_EN |\
CLK_GATING_TXQ_EN |\
CLK_GATING_RXQ_EN |\
CLK_GATING_TXMAC_EN|\
CLK_GATING_RXMAC_EN)

Definition at line 757 of file atl1c_hw.h.

#define CLK_GATING_RXMAC_EN   0x0020

Definition at line 755 of file atl1c_hw.h.

#define CLK_GATING_RXQ_EN   0x0008

Definition at line 753 of file atl1c_hw.h.

#define CLK_GATING_TXMAC_EN   0x0010

Definition at line 754 of file atl1c_hw.h.

#define CLK_GATING_TXQ_EN   0x0004

Definition at line 752 of file atl1c_hw.h.

#define DEVICE_CAP_MAX_PAYLOAD_MASK   0x7

Definition at line 82 of file atl1c_hw.h.

#define DEVICE_CAP_MAX_PAYLOAD_SHIFT   0

Definition at line 83 of file atl1c_hw.h.

#define DEVICE_CTRL_MAXRRS_MIN   2

Definition at line 85 of file atl1c_hw.h.

#define DMA_CTRL_RDLY_CNT_DEF   15

Definition at line 637 of file atl1c_hw.h.

#define DMA_CTRL_RDLY_CNT_MASK   0x1FUL

Definition at line 635 of file atl1c_hw.h.

#define DMA_CTRL_RDLY_CNT_SHIFT   11

Definition at line 636 of file atl1c_hw.h.

#define DMA_CTRL_RORDER_MODE_ENHANCE   2

Definition at line 647 of file atl1c_hw.h.

#define DMA_CTRL_RORDER_MODE_IN   1

Definition at line 648 of file atl1c_hw.h.

#define DMA_CTRL_RORDER_MODE_MASK   7UL

Definition at line 644 of file atl1c_hw.h.

#define DMA_CTRL_RORDER_MODE_OUT   4

Definition at line 646 of file atl1c_hw.h.

#define DMA_CTRL_RORDER_MODE_SHIFT   0

Definition at line 645 of file atl1c_hw.h.

#define DMA_CTRL_RPEND_CLR   BIT(29)

Definition at line 631 of file atl1c_hw.h.

#define DMA_CTRL_RREQ_BLEN_MASK   7UL

Definition at line 641 of file atl1c_hw.h.

#define DMA_CTRL_RREQ_BLEN_SHIFT   4

Definition at line 642 of file atl1c_hw.h.

#define DMA_CTRL_RREQ_PRI_DATA   BIT(10) /* 0:tpd, 1:data */

Definition at line 638 of file atl1c_hw.h.

#define DMA_CTRL_SMB_NOW   BIT(31)

Definition at line 629 of file atl1c_hw.h.

#define DMA_CTRL_WDLY_CNT_DEF   4

Definition at line 634 of file atl1c_hw.h.

#define DMA_CTRL_WDLY_CNT_MASK   0xFUL

Definition at line 632 of file atl1c_hw.h.

#define DMA_CTRL_WDLY_CNT_SHIFT   16

Definition at line 633 of file atl1c_hw.h.

#define DMA_CTRL_WPEND_CLR   BIT(30)

Definition at line 630 of file atl1c_hw.h.

#define DMA_CTRL_WREQ_BLEN_MASK   7UL

Definition at line 639 of file atl1c_hw.h.

#define DMA_CTRL_WREQ_BLEN_SHIFT   7

Definition at line 640 of file atl1c_hw.h.

#define DMA_DBG_VENDOR_MSG   BIT(0)

Definition at line 138 of file atl1c_hw.h.

#define DMA_MAC_RST_TO   50

Definition at line 222 of file atl1c_hw.h.

#define EEE_ANEG_1000M   0x4

Definition at line 1009 of file atl1c_hw.h.

#define EEE_ANEG_100M   0x2

Definition at line 1010 of file atl1c_hw.h.

#define EEPROM_CTRL_ACK   0x40000000

Definition at line 145 of file atl1c_hw.h.

#define EEPROM_CTRL_ADDR_MASK   0x3FF

Definition at line 143 of file atl1c_hw.h.

#define EEPROM_CTRL_ADDR_SHIFT   16

Definition at line 144 of file atl1c_hw.h.

#define EEPROM_CTRL_DATA_HI_MASK   0xFFFF

Definition at line 141 of file atl1c_hw.h.

#define EEPROM_CTRL_DATA_HI_SHIFT   0

Definition at line 142 of file atl1c_hw.h.

#define EEPROM_CTRL_RW   0x80000000

Definition at line 146 of file atl1c_hw.h.

#define FIELD_GETX (   _x,
  _name 
)    ((_x) >> (_name##_SHIFT) & (_name##_MASK))

Definition at line 28 of file atl1c_hw.h.

#define FIELD_SETX (   _x,
  _name,
  _v 
)
Value:
(((_x) & ~((_name##_MASK) << (_name##_SHIFT))) |\
(((_v) & (_name##_MASK)) << (_name##_SHIFT)))

Definition at line 29 of file atl1c_hw.h.

#define FIELDX (   _name,
  _v 
)    (((_v) & (_name##_MASK)) << (_name##_SHIFT))

Definition at line 32 of file atl1c_hw.h.

#define GIGA_CR_1000T_DEFAULT_CAP   0x0300

Definition at line 788 of file atl1c_hw.h.

#define GIGA_CR_1000T_MS_ENABLE   0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */

Definition at line 781 of file atl1c_hw.h.

#define GIGA_CR_1000T_MS_VALUE   0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */

Definition at line 780 of file atl1c_hw.h.

#define GIGA_CR_1000T_REPEATER_DTE   0x0400 /* 1=Repeater/switch device port 0=DTE device */

Definition at line 778 of file atl1c_hw.h.

#define GIGA_CR_1000T_SPEED_MASK   0x0300

Definition at line 787 of file atl1c_hw.h.

#define GIGA_CR_1000T_TEST_MODE_1   0x2000 /* Transmit Waveform test */

Definition at line 783 of file atl1c_hw.h.

#define GIGA_CR_1000T_TEST_MODE_2   0x4000 /* Master Transmit Jitter test */

Definition at line 784 of file atl1c_hw.h.

#define GIGA_CR_1000T_TEST_MODE_3   0x6000 /* Slave Transmit Jitter test */

Definition at line 785 of file atl1c_hw.h.

#define GIGA_CR_1000T_TEST_MODE_4   0x8000 /* Transmitter Distortion test */

Definition at line 786 of file atl1c_hw.h.

#define GIGA_CR_1000T_TEST_MODE_NORMAL   0x0000 /* Normal Operation */

Definition at line 782 of file atl1c_hw.h.

#define GIGA_PSSR_1000MBS   0x8000 /* 10=1000Mbs */

Definition at line 797 of file atl1c_hw.h.

#define GIGA_PSSR_100MBS   0x4000 /* 01=100Mbs */

Definition at line 796 of file atl1c_hw.h.

#define GIGA_PSSR_10MBS   0x0000 /* 00=10Mbs */

Definition at line 795 of file atl1c_hw.h.

#define GIGA_PSSR_DPLX   0x2000 /* 1=Duplex 0=Half Duplex */

Definition at line 793 of file atl1c_hw.h.

#define GIGA_PSSR_SPD_DPLX_RESOLVED   0x0800 /* 1=Speed & Duplex resolved */

Definition at line 792 of file atl1c_hw.h.

#define GIGA_PSSR_SPEED   0xC000 /* Speed, bits 14:15 */

Definition at line 794 of file atl1c_hw.h.

#define GPHY_CTRL_100AB_EN   BIT(17)

Definition at line 237 of file atl1c_hw.h.

#define GPHY_CTRL_10AB_EN   BIT(16)

Definition at line 238 of file atl1c_hw.h.

#define GPHY_CTRL_ADDR_MASK   0x1FUL

Definition at line 234 of file atl1c_hw.h.

#define GPHY_CTRL_ADDR_SHIFT   19

Definition at line 235 of file atl1c_hw.h.

#define GPHY_CTRL_ANEG_NOW   BIT(3)

Definition at line 251 of file atl1c_hw.h.

#define GPHY_CTRL_BP_VLTGSW   BIT(18)

Definition at line 236 of file atl1c_hw.h.

#define GPHY_CTRL_CLS
Value:
(\
GPHY_CTRL_LED_MODE |\
GPHY_CTRL_100AB_EN |\
GPHY_CTRL_PHY_PLL_ON)

Definition at line 256 of file atl1c_hw.h.

#define GPHY_CTRL_EXT_RESET   BIT(0) /* 1:out of DSP RST status */

Definition at line 254 of file atl1c_hw.h.

#define GPHY_CTRL_EXT_RST_TO   80 /* 800us atmost */

Definition at line 255 of file atl1c_hw.h.

#define GPHY_CTRL_GATE_25M_EN   BIT(5)

Definition at line 249 of file atl1c_hw.h.

#define GPHY_CTRL_GIGA_DIS   BIT(9)

Definition at line 245 of file atl1c_hw.h.

#define GPHY_CTRL_HIB_EN   BIT(10)

Definition at line 244 of file atl1c_hw.h.

#define GPHY_CTRL_HIB_PULSE   BIT(11)

Definition at line 243 of file atl1c_hw.h.

#define GPHY_CTRL_LED_MODE   BIT(2)

Definition at line 252 of file atl1c_hw.h.

#define GPHY_CTRL_LPW_EXIT   BIT(6)

Definition at line 248 of file atl1c_hw.h.

#define GPHY_CTRL_PHY_IDDQ   BIT(7) /* bit8 affect bit7 while rb */

Definition at line 247 of file atl1c_hw.h.

#define GPHY_CTRL_PHY_IDDQ_DIS   BIT(8) /* pw on RST */

Definition at line 246 of file atl1c_hw.h.

#define GPHY_CTRL_PHY_PLL_BYPASS   BIT(15)

Definition at line 239 of file atl1c_hw.h.

#define GPHY_CTRL_PHY_PLL_ON   BIT(13) /* 1:pll always on, 0:can sw */

Definition at line 241 of file atl1c_hw.h.

#define GPHY_CTRL_PWDOWN_HW   BIT(14) /* affect MAC&PHY, to low pw */

Definition at line 240 of file atl1c_hw.h.

#define GPHY_CTRL_REV_ANEG   BIT(4)

Definition at line 250 of file atl1c_hw.h.

#define GPHY_CTRL_RTL_MODE   BIT(1)

Definition at line 253 of file atl1c_hw.h.

#define GPHY_CTRL_SEL_ANA_RST   BIT(12)

Definition at line 242 of file atl1c_hw.h.

#define HIBNEG_BYPSS_BRKTIMER   0x10

Definition at line 914 of file atl1c_hw.h.

#define HIBNEG_DEF   0xBC40

Definition at line 915 of file atl1c_hw.h.

#define HIBNEG_GATE_25M_EN   0x800

Definition at line 908 of file atl1c_hw.h.

#define HIBNEG_GTX_CLK_DELAY_MASK   3U

Definition at line 912 of file atl1c_hw.h.

#define HIBNEG_GTX_CLK_DELAY_SHIFT   5

Definition at line 913 of file atl1c_hw.h.

#define HIBNEG_HIB_PULSE   0x1000

Definition at line 907 of file atl1c_hw.h.

#define HIBNEG_ONOFF_ANACHG_SUDEN   0x2000

Definition at line 906 of file atl1c_hw.h.

#define HIBNEG_PSHIB_EN   0x8000

Definition at line 904 of file atl1c_hw.h.

#define HIBNEG_RST_80U   0x400

Definition at line 909 of file atl1c_hw.h.

#define HIBNEG_RST_TIMER_MASK   3U

Definition at line 910 of file atl1c_hw.h.

#define HIBNEG_RST_TIMER_SHIFT   8

Definition at line 911 of file atl1c_hw.h.

#define HIBNEG_WAKE_BOTH   0x4000

Definition at line 905 of file atl1c_hw.h.

#define IDLE_STATUS_CALIB_DONE   BIT(13)

Definition at line 265 of file atl1c_hw.h.

#define IDLE_STATUS_CALIB_RES_MASK   0x1FUL

Definition at line 266 of file atl1c_hw.h.

#define IDLE_STATUS_CALIB_RES_SHIFT   8

Definition at line 267 of file atl1c_hw.h.

#define IDLE_STATUS_CALIBERR_MASK   0xFUL

Definition at line 268 of file atl1c_hw.h.

#define IDLE_STATUS_CALIBERR_SHIFT   4

Definition at line 269 of file atl1c_hw.h.

#define IDLE_STATUS_MASK
Value:
(\
IDLE_STATUS_TXQ_BUSY |\
IDLE_STATUS_RXQ_BUSY |\
IDLE_STATUS_TXMAC_BUSY |\
IDLE_STATUS_RXMAC_BUSY)

Definition at line 274 of file atl1c_hw.h.

#define IDLE_STATUS_RXMAC_BUSY   BIT(0)

Definition at line 273 of file atl1c_hw.h.

#define IDLE_STATUS_RXQ_BUSY   BIT(2)

Definition at line 271 of file atl1c_hw.h.

#define IDLE_STATUS_SFORCE_MASK   0xFUL

Definition at line 263 of file atl1c_hw.h.

#define IDLE_STATUS_SFORCE_SHIFT   14

Definition at line 264 of file atl1c_hw.h.

#define IDLE_STATUS_TXMAC_BUSY   BIT(1)

Definition at line 272 of file atl1c_hw.h.

#define IDLE_STATUS_TXQ_BUSY   BIT(3)

Definition at line 270 of file atl1c_hw.h.

#define IER_LINK_DOWN   0x0800

Definition at line 802 of file atl1c_hw.h.

#define IER_LINK_UP   0x0400

Definition at line 801 of file atl1c_hw.h.

#define IMR_NORMAL_MASK
Value:
(\
ISR_MANUAL |\
ISR_HW_RXF_OV |\
ISR_RFD0_UR |\
ISR_TXF_UR |\
ISR_DMAR_TO_RST |\
ISR_TXQ_TO_RST |\
ISR_DMAW_TO_RST |\
ISR_GPHY |\
ISR_TX_PKT |\
ISR_RX_PKT_0 |\
ISR_GPHY_LPW |\
ISR_PHY_LINKDOWN)

Definition at line 707 of file atl1c_hw.h.

#define INT_RETRIG_TIMER_MASK   0xFFFF

Definition at line 742 of file atl1c_hw.h.

#define IPV6_CHKSUM_CTRL_EN   BIT(7)

Definition at line 594 of file atl1c_hw.h.

#define IRQ_MODRT_RX_TIMER_SHIFT   16

Definition at line 231 of file atl1c_hw.h.

#define IRQ_MODRT_TIMER_MASK   0xffff

Definition at line 229 of file atl1c_hw.h.

#define IRQ_MODRT_TX_TIMER_SHIFT   0

Definition at line 230 of file atl1c_hw.h.

#define ISR_CERR_DETECTED   0x02000000

Definition at line 700 of file atl1c_hw.h.

#define ISR_DIS_INT   0x80000000

Definition at line 702 of file atl1c_hw.h.

#define ISR_DMAR_TO_RST   0x00000200

Definition at line 683 of file atl1c_hw.h.

#define ISR_DMAW_TO_RST   0x00000400

Definition at line 684 of file atl1c_hw.h.

#define ISR_ERROR
Value:
(\
ISR_DMAR_TO_RST |\
ISR_TXQ_TO_RST |\
ISR_DMAW_TO_RST |\
ISR_PHY_LINKDOWN)

Definition at line 735 of file atl1c_hw.h.

#define ISR_FERR_DETECTED   0x00800000

Definition at line 698 of file atl1c_hw.h.

#define ISR_GPHY   0x00001000

Definition at line 686 of file atl1c_hw.h.

#define ISR_GPHY_LPW   0x00002000

Definition at line 688 of file atl1c_hw.h.

#define ISR_HW_RXF_OV   0x00000008 /* RXF overflow interrupt */

Definition at line 677 of file atl1c_hw.h.

#define ISR_LINK_DOWN   0x0800

Definition at line 807 of file atl1c_hw.h.

#define ISR_LINK_UP   0x0400

Definition at line 806 of file atl1c_hw.h.

#define ISR_MAC_RX   0x00100000

Definition at line 695 of file atl1c_hw.h.

#define ISR_MAC_TX   0x00200000

Definition at line 696 of file atl1c_hw.h.

#define ISR_MANUAL   0x00000004

Definition at line 676 of file atl1c_hw.h.

#define ISR_NFERR_DETECTED   0x01000000

Definition at line 699 of file atl1c_hw.h.

#define ISR_OVER
Value:
(\
ISR_RFD0_UR |\
ISR_RFD1_UR |\
ISR_RFD2_UR |\
ISR_RFD3_UR |\
ISR_HW_RXF_OV |\
ISR_TXF_UR)

Definition at line 727 of file atl1c_hw.h.

#define ISR_PHY_LINKDOWN   0x04000000

Definition at line 701 of file atl1c_hw.h.

#define ISR_RFD0_UR   0x00000010 /* RFD0 under run */

Definition at line 678 of file atl1c_hw.h.

#define ISR_RFD1_UR   0x00000020

Definition at line 679 of file atl1c_hw.h.

#define ISR_RFD2_UR   0x00000040

Definition at line 680 of file atl1c_hw.h.

#define ISR_RFD3_UR   0x00000080

Definition at line 681 of file atl1c_hw.h.

#define ISR_RX_PKT
Value:
(\
ISR_RX_PKT_0 |\
ISR_RX_PKT_1 |\
ISR_RX_PKT_2 |\
ISR_RX_PKT_3)

Definition at line 721 of file atl1c_hw.h.

#define ISR_RX_PKT_0   0x00010000

Definition at line 691 of file atl1c_hw.h.

#define ISR_RX_PKT_1   0x00020000

Definition at line 692 of file atl1c_hw.h.

#define ISR_RX_PKT_2   0x00040000

Definition at line 693 of file atl1c_hw.h.

#define ISR_RX_PKT_3   0x00080000

Definition at line 694 of file atl1c_hw.h.

#define ISR_SMB   0x00000001

Definition at line 670 of file atl1c_hw.h.

#define ISR_TIMER   0x00000002

Definition at line 671 of file atl1c_hw.h.

#define ISR_TX_CREDIT   0x00000800

Definition at line 685 of file atl1c_hw.h.

#define ISR_TX_PKT   0x00008000

Definition at line 690 of file atl1c_hw.h.

#define ISR_TXF_UR   0x00000100

Definition at line 682 of file atl1c_hw.h.

#define ISR_TXQ_TO_RST   0x00004000

Definition at line 689 of file atl1c_hw.h.

#define ISR_UR_DETECTED   0x00400000

Definition at line 697 of file atl1c_hw.h.

#define L1C_CTRL_DMA_RCB_LEN128   BIT(3) /* 0:64bytes,1:128bytes */

Definition at line 643 of file atl1c_hw.h.

#define L1C_LEGCYPS_DEF   0x36DD

Definition at line 956 of file atl1c_hw.h.

#define L1C_PM_CTRL_L1_ENTRY_TM   0xF

Definition at line 178 of file atl1c_hw.h.

#define L1C_TXQ_CFGV
Value:
(\
TXQ_CFGV |\
FIELDX(TXQ_TXF_BURST_NUM, L1C_TXQ_TXF_BURST_PREF))

Definition at line 562 of file atl1c_hw.h.

#define L1C_TXQ_TXF_BURST_PREF   0x200

Definition at line 547 of file atl1c_hw.h.

#define L1D_CLDCTRL3   0xDD19

Definition at line 990 of file atl1c_hw.h.

#define L1D_LEGCYPS_DEF   0x129D

Definition at line 955 of file atl1c_hw.h.

#define L1D_MPW_PHYID1   0xD01C /* V7 */

Definition at line 768 of file atl1c_hw.h.

#define L1D_MPW_PHYID2   0xD01D /* V1-V6 */

Definition at line 769 of file atl1c_hw.h.

#define L1D_MPW_PHYID3   0xD01E /* V8 */

Definition at line 770 of file atl1c_hw.h.

#define L1D_MSE16DB_DOWN   0x02EA

Definition at line 941 of file atl1c_hw.h.

#define L1D_MSE16DB_UP   0x05EA

Definition at line 940 of file atl1c_hw.h.

#define L1D_PMCTRL_L0S_TIMER_MASK   7UL /* l1d2.0+, 3bits*/

Definition at line 184 of file atl1c_hw.h.

#define L1D_PMCTRL_L0S_TIMER_SHIFT   8

Definition at line 185 of file atl1c_hw.h.

#define L1D_PMCTRL_L1_ENTRY_TM_16US   4

Definition at line 171 of file atl1c_hw.h.

#define L1D_PMCTRL_L1_ENTRY_TM_24US   5

Definition at line 172 of file atl1c_hw.h.

#define L1D_PMCTRL_L1_ENTRY_TM_2US   1

Definition at line 168 of file atl1c_hw.h.

#define L1D_PMCTRL_L1_ENTRY_TM_32US   6

Definition at line 173 of file atl1c_hw.h.

#define L1D_PMCTRL_L1_ENTRY_TM_4US   2

Definition at line 169 of file atl1c_hw.h.

#define L1D_PMCTRL_L1_ENTRY_TM_63US   7

Definition at line 174 of file atl1c_hw.h.

#define L1D_PMCTRL_L1_ENTRY_TM_8US   3

Definition at line 170 of file atl1c_hw.h.

#define L1D_PMCTRL_L1_ENTRY_TM_DIS   0

Definition at line 167 of file atl1c_hw.h.

#define L1D_PMCTRL_L1_ENTRY_TM_MASK   7UL /* l1dv2.0+, 3bits */

Definition at line 165 of file atl1c_hw.h.

#define L1D_PMCTRL_L1_ENTRY_TM_SHIFT   16

Definition at line 166 of file atl1c_hw.h.

#define L1D_SYSMODCTRL_IECHOADJ_DEF   0x4FBB

Definition at line 883 of file atl1c_hw.h.

#define L2CB1_PCIE_PHYMISC2_CDR_BW   3

Definition at line 132 of file atl1c_hw.h.

#define L2CB1_PCIE_PHYMISC2_L0S_TH   3

Definition at line 129 of file atl1c_hw.h.

#define L2CB1_PM_CTRL_L1_ENTRY_TM   7

Definition at line 177 of file atl1c_hw.h.

#define L2CB_CLDCTRL3   0x4D19

Definition at line 989 of file atl1c_hw.h.

#define L2CB_LPI_DESISN_TIMER   0x7D00

Definition at line 350 of file atl1c_hw.h.

#define L2CB_TXQ_CFGV
Value:
(\
TXQ_CFGV |\
FIELDX(TXQ_TXF_BURST_NUM, L2CB_TXQ_TXF_BURST_PREF))

Definition at line 565 of file atl1c_hw.h.

#define L2CB_TXQ_TXF_BURST_PREF   0x40

Definition at line 548 of file atl1c_hw.h.

#define L2CB_V10   0xc0

Definition at line 75 of file atl1c_hw.h.

#define L2CB_V11   0xc1

Definition at line 76 of file atl1c_hw.h.

#define L2CB_V20   0xc0

Definition at line 77 of file atl1c_hw.h.

#define L2CB_V21   0xc1

Definition at line 78 of file atl1c_hw.h.

#define LEGCYPS_DAC_AMP1000_MASK   7U

Definition at line 945 of file atl1c_hw.h.

#define LEGCYPS_DAC_AMP1000_SHIFT   12

Definition at line 946 of file atl1c_hw.h.

#define LEGCYPS_DAC_AMP100_MASK   7U

Definition at line 947 of file atl1c_hw.h.

#define LEGCYPS_DAC_AMP100_SHIFT   9

Definition at line 948 of file atl1c_hw.h.

#define LEGCYPS_DAC_AMP10_MASK   7U

Definition at line 949 of file atl1c_hw.h.

#define LEGCYPS_DAC_AMP10_SHIFT   6

Definition at line 950 of file atl1c_hw.h.

#define LEGCYPS_ECNC_PS_EN   0x1

Definition at line 954 of file atl1c_hw.h.

#define LEGCYPS_EN   0x8000

Definition at line 944 of file atl1c_hw.h.

#define LEGCYPS_UNPLUG_DECT_EN   0x4

Definition at line 953 of file atl1c_hw.h.

#define LEGCYPS_UNPLUG_TIMER_MASK   7U

Definition at line 951 of file atl1c_hw.h.

#define LEGCYPS_UNPLUG_TIMER_SHIFT   3

Definition at line 952 of file atl1c_hw.h.

#define LINK_CTRL_EXT_SYNC   0x80

Definition at line 90 of file atl1c_hw.h.

#define LINK_CTRL_L0S_EN   0x01

Definition at line 88 of file atl1c_hw.h.

#define LINK_CTRL_L1_EN   0x02

Definition at line 89 of file atl1c_hw.h.

#define LOCAL_EEEADV_1000BT   0x4

Definition at line 1001 of file atl1c_hw.h.

#define LOCAL_EEEADV_100BT   0x2

Definition at line 1002 of file atl1c_hw.h.

#define LPI_CTRL_CHK_DA   BIT(31)

Definition at line 353 of file atl1c_hw.h.

#define LPI_CTRL_CHK_RX   BIT(4)

Definition at line 359 of file atl1c_hw.h.

#define LPI_CTRL_CHK_STATE   BIT(3)

Definition at line 360 of file atl1c_hw.h.

#define LPI_CTRL_EN   BIT(0)

Definition at line 363 of file atl1c_hw.h.

#define LPI_CTRL_ENH_EN   BIT(5)

Definition at line 358 of file atl1c_hw.h.

#define LPI_CTRL_ENH_TH_MASK   0x1FUL

Definition at line 356 of file atl1c_hw.h.

#define LPI_CTRL_ENH_TH_SHIFT   6

Definition at line 357 of file atl1c_hw.h.

#define LPI_CTRL_ENH_TO_MASK   0x1FFFUL

Definition at line 354 of file atl1c_hw.h.

#define LPI_CTRL_ENH_TO_SHIFT   12

Definition at line 355 of file atl1c_hw.h.

#define LPI_CTRL_GMII   BIT(2)

Definition at line 361 of file atl1c_hw.h.

#define LPI_CTRL_TO_PHY   BIT(1)

Definition at line 362 of file atl1c_hw.h.

#define LPI_WAIT_TIMER_MASK   0xFFFFUL

Definition at line 366 of file atl1c_hw.h.

#define LPI_WAIT_TIMER_SHIFT   0

Definition at line 367 of file atl1c_hw.h.

#define LTSSM_ID_EN_WRO   0x1000

Definition at line 198 of file atl1c_hw.h.

#define MAC_CTRL_ADD_CRC   BIT(6)

Definition at line 394 of file atl1c_hw.h.

#define MAC_CTRL_BC_EN   BIT(26)

Definition at line 375 of file atl1c_hw.h.

#define MAC_CTRL_DBG   BIT(27)

Definition at line 374 of file atl1c_hw.h.

#define MAC_CTRL_DBG_TX_BKPRESURE   BIT(22)

Definition at line 379 of file atl1c_hw.h.

#define MAC_CTRL_DUPLX   BIT(5)

Definition at line 395 of file atl1c_hw.h.

#define MAC_CTRL_HASH_ALG_CRC32   BIT(29) /* 1:legacy,0:lw_5b */

Definition at line 372 of file atl1c_hw.h.

#define MAC_CTRL_HUGE_EN   BIT(9)

Definition at line 391 of file atl1c_hw.h.

#define MAC_CTRL_LENCHK   BIT(8)

Definition at line 392 of file atl1c_hw.h.

#define MAC_CTRL_LOOPBACK   BIT(4)

Definition at line 396 of file atl1c_hw.h.

#define MAC_CTRL_MC_ALL_EN   BIT(25)

Definition at line 376 of file atl1c_hw.h.

#define MAC_CTRL_PAD   BIT(7)

Definition at line 393 of file atl1c_hw.h.

#define MAC_CTRL_PRMLEN_MASK   0xFUL

Definition at line 389 of file atl1c_hw.h.

#define MAC_CTRL_PRMLEN_SHIFT   10

Definition at line 390 of file atl1c_hw.h.

#define MAC_CTRL_PROMIS_EN   BIT(15)

Definition at line 387 of file atl1c_hw.h.

#define MAC_CTRL_RMV_VLAN   BIT(14)

Definition at line 388 of file atl1c_hw.h.

#define MAC_CTRL_RX_CHKSUM_EN   BIT(24)

Definition at line 377 of file atl1c_hw.h.

#define MAC_CTRL_RX_EN   BIT(1)

Definition at line 399 of file atl1c_hw.h.

#define MAC_CTRL_RX_FLOW   BIT(3)

Definition at line 397 of file atl1c_hw.h.

#define MAC_CTRL_SCNT   BIT(17)

Definition at line 385 of file atl1c_hw.h.

#define MAC_CTRL_SINGLE_PAUSE_EN   BIT(28)

Definition at line 373 of file atl1c_hw.h.

#define MAC_CTRL_SPEED_1000   2

Definition at line 383 of file atl1c_hw.h.

#define MAC_CTRL_SPEED_10_100   1

Definition at line 382 of file atl1c_hw.h.

#define MAC_CTRL_SPEED_MASK   3UL

Definition at line 380 of file atl1c_hw.h.

#define MAC_CTRL_SPEED_MODE_SW   BIT(30) /* 0:phy,1:sw */

Definition at line 371 of file atl1c_hw.h.

#define MAC_CTRL_SPEED_SHIFT   20

Definition at line 381 of file atl1c_hw.h.

#define MAC_CTRL_TX_EN   BIT(0)

Definition at line 400 of file atl1c_hw.h.

#define MAC_CTRL_TX_FLOW   BIT(2)

Definition at line 398 of file atl1c_hw.h.

#define MAC_CTRL_TX_HUGE   BIT(23)

Definition at line 378 of file atl1c_hw.h.

#define MAC_CTRL_TX_PAUSE   BIT(16)

Definition at line 386 of file atl1c_hw.h.

#define MAC_CTRL_TX_SIMURST   BIT(19)

Definition at line 384 of file atl1c_hw.h.

#define MAC_HALF_DUPLX_CTRL_ABEBE   0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */

Definition at line 428 of file atl1c_hw.h.

#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK   0xf

Definition at line 430 of file atl1c_hw.h.

#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT   20 /* Maximum binary exponential number */

Definition at line 429 of file atl1c_hw.h.

#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN   0x10000

Definition at line 425 of file atl1c_hw.h.

#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK   0xf /* mode. In unit of 8-bit time */

Definition at line 432 of file atl1c_hw.h.

#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT   24 /* IPG to start JAM for collision based flow control in half-duplex */

Definition at line 431 of file atl1c_hw.h.

#define MAC_HALF_DUPLX_CTRL_LCOL_MASK   0x3ff

Definition at line 422 of file atl1c_hw.h.

#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT   0 /* Collision Window */

Definition at line 421 of file atl1c_hw.h.

#define MAC_HALF_DUPLX_CTRL_NO_BACK_C   0x20000

Definition at line 426 of file atl1c_hw.h.

#define MAC_HALF_DUPLX_CTRL_NO_BACK_P
Value:
0x40000 /* No back-off on backpressure,
* immediately start the
* transmission after back pressure */

Definition at line 427 of file atl1c_hw.h.

#define MAC_HALF_DUPLX_CTRL_RETRY_MASK   0xf

Definition at line 424 of file atl1c_hw.h.

#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT   12

Definition at line 423 of file atl1c_hw.h.

#define MAC_IPG_IFG_IPGR1_MASK   0x7f

Definition at line 409 of file atl1c_hw.h.

#define MAC_IPG_IFG_IPGR1_SHIFT   16 /* 64bit Carrier-Sense window */

Definition at line 408 of file atl1c_hw.h.

#define MAC_IPG_IFG_IPGR2_MASK   0x7f

Definition at line 411 of file atl1c_hw.h.

#define MAC_IPG_IFG_IPGR2_SHIFT   24 /* 96-bit IPG window */

Definition at line 410 of file atl1c_hw.h.

#define MAC_IPG_IFG_IPGT_MASK   0x7f

Definition at line 405 of file atl1c_hw.h.

#define MAC_IPG_IFG_IPGT_SHIFT
Value:
0 /* Desired back to back
* inter-packet gap. The
* default is 96-bit time */

Definition at line 404 of file atl1c_hw.h.

#define MAC_IPG_IFG_MIFG_MASK   0xff /* Frame gap below such IFP is dropped */

Definition at line 407 of file atl1c_hw.h.

#define MAC_IPG_IFG_MIFG_SHIFT
Value:
8 /* Minimum number of IFG to
* enforce in between RX frames */

Definition at line 406 of file atl1c_hw.h.

#define MASTER_CTRL_BERT_START   BIT(4)

Definition at line 217 of file atl1c_hw.h.

#define MASTER_CTRL_CLK_SEL_DIS
Value:
BIT(12) /* 1:alwys sel pclk from
* serdes, not sw to 25M */

Definition at line 209 of file atl1c_hw.h.

#define MASTER_CTRL_INT_RDCLR   BIT(14)

Definition at line 208 of file atl1c_hw.h.

#define MASTER_CTRL_MANU_INT   BIT(9) /* SOFT MANUAL INT */

Definition at line 212 of file atl1c_hw.h.

#define MASTER_CTRL_MANUTIMER_EN   BIT(8)

Definition at line 213 of file atl1c_hw.h.

#define MASTER_CTRL_OOB_DIS   BIT(6) /* OUT OF BOX DIS */

Definition at line 215 of file atl1c_hw.h.

#define MASTER_CTRL_OTP_SEL   BIT(31)

Definition at line 203 of file atl1c_hw.h.

#define MASTER_CTRL_RX_ITIMER_EN   BIT(11) /* IRQ MODURATION FOR RX */

Definition at line 210 of file atl1c_hw.h.

#define MASTER_CTRL_SA_TIMER_EN   BIT(7) /* SYS ALIVE TIMER EN */

Definition at line 214 of file atl1c_hw.h.

#define MASTER_CTRL_SOFT_RST   BIT(0) /* RST MAC & DMA */

Definition at line 221 of file atl1c_hw.h.

#define MASTER_CTRL_TX_ITIMER_EN   BIT(10) /* MODURATION FOR TX/RX */

Definition at line 211 of file atl1c_hw.h.

#define MASTER_CTRL_WAKEN_25M   BIT(5) /* WAKE WO. PCIE CLK */

Definition at line 216 of file atl1c_hw.h.

#define MASTER_DEV_NUM_MASK   0x7FUL

Definition at line 204 of file atl1c_hw.h.

#define MASTER_DEV_NUM_SHIFT   24

Definition at line 205 of file atl1c_hw.h.

#define MASTER_PCIE_RST   BIT(1)

Definition at line 220 of file atl1c_hw.h.

#define MASTER_PCIE_TSTMOD_MASK   3UL

Definition at line 218 of file atl1c_hw.h.

#define MASTER_PCIE_TSTMOD_SHIFT   2

Definition at line 219 of file atl1c_hw.h.

#define MASTER_REV_NUM_MASK   0xFFUL

Definition at line 206 of file atl1c_hw.h.

#define MASTER_REV_NUM_SHIFT   16

Definition at line 207 of file atl1c_hw.h.

#define MAX_TSO_FRAME_SIZE   (7*1024)

Definition at line 573 of file atl1c_hw.h.

#define MB_RFD0_CONS_IDX_MASK   0x0000FFFF

Definition at line 665 of file atl1c_hw.h.

#define MB_RFD1_CONS_IDX_MASK   0xFFFF0000

Definition at line 666 of file atl1c_hw.h.

#define MB_RFDX_PROD_IDX_MASK   0xFFFF

Definition at line 656 of file atl1c_hw.h.

#define MDIO_CTRL_AP_EN   BIT(28)

Definition at line 284 of file atl1c_hw.h.

#define MDIO_CTRL_BUSY   BIT(27)

Definition at line 285 of file atl1c_hw.h.

#define MDIO_CTRL_CLK_25_10   4

Definition at line 291 of file atl1c_hw.h.

#define MDIO_CTRL_CLK_25_128   7

Definition at line 294 of file atl1c_hw.h.

#define MDIO_CTRL_CLK_25_32   5

Definition at line 292 of file atl1c_hw.h.

#define MDIO_CTRL_CLK_25_4   0 /* 25MHz divide 4 */

Definition at line 288 of file atl1c_hw.h.

#define MDIO_CTRL_CLK_25_6   2

Definition at line 289 of file atl1c_hw.h.

#define MDIO_CTRL_CLK_25_64   6

Definition at line 293 of file atl1c_hw.h.

#define MDIO_CTRL_CLK_25_8   3

Definition at line 290 of file atl1c_hw.h.

#define MDIO_CTRL_CLK_SEL_MASK   0x7UL

Definition at line 286 of file atl1c_hw.h.

#define MDIO_CTRL_CLK_SEL_SHIFT   24

Definition at line 287 of file atl1c_hw.h.

#define MDIO_CTRL_DATA_MASK   0xFFFFUL

Definition at line 300 of file atl1c_hw.h.

#define MDIO_CTRL_DATA_SHIFT   0

Definition at line 301 of file atl1c_hw.h.

#define MDIO_CTRL_MODE_EXT   BIT(30)

Definition at line 282 of file atl1c_hw.h.

#define MDIO_CTRL_OP_READ   BIT(21) /* 1:read, 0:write */

Definition at line 297 of file atl1c_hw.h.

#define MDIO_CTRL_POST_READ   BIT(29)

Definition at line 283 of file atl1c_hw.h.

#define MDIO_CTRL_REG_MASK   0x1FUL

Definition at line 298 of file atl1c_hw.h.

#define MDIO_CTRL_REG_SHIFT   16

Definition at line 299 of file atl1c_hw.h.

#define MDIO_CTRL_SPRES_PRMBL   BIT(22)

Definition at line 296 of file atl1c_hw.h.

#define MDIO_CTRL_START   BIT(23)

Definition at line 295 of file atl1c_hw.h.

#define MDIO_EXTN_DEVAD_MASK   0x1FUL

Definition at line 308 of file atl1c_hw.h.

#define MDIO_EXTN_DEVAD_SHIFT   16

Definition at line 309 of file atl1c_hw.h.

#define MDIO_EXTN_PORTAD_MASK   0x1FUL

Definition at line 306 of file atl1c_hw.h.

#define MDIO_EXTN_PORTAD_SHIFT   21

Definition at line 307 of file atl1c_hw.h.

#define MDIO_EXTN_REG_MASK   0xFFFFUL

Definition at line 310 of file atl1c_hw.h.

#define MDIO_EXTN_REG_SHIFT   0

Definition at line 311 of file atl1c_hw.h.

#define MDIO_MAX_AC_TO   120 /* 1.2ms timeout for slow clk */

Definition at line 302 of file atl1c_hw.h.

#define MII_CDTC   0x16

Definition at line 810 of file atl1c_hw.h.

#define MII_CDTS   0x1C

Definition at line 817 of file atl1c_hw.h.

#define MII_DBG_ADDR   0x1D

Definition at line 825 of file atl1c_hw.h.

#define MII_DBG_DATA   0x1E

Definition at line 826 of file atl1c_hw.h.

#define MII_GIGA_PSSR   0x11

Definition at line 791 of file atl1c_hw.h.

#define MII_IER   0x12

Definition at line 800 of file atl1c_hw.h.

#define MII_ISR   0x13

Definition at line 805 of file atl1c_hw.h.

#define MIIDBG_ANACTRL   0x00

Definition at line 830 of file atl1c_hw.h.

#define MIIDBG_AZ_ANADECT   0x15

Definition at line 927 of file atl1c_hw.h.

#define MIIDBG_CABLE1TH_DET   0x3E

Definition at line 979 of file atl1c_hw.h.

#define MIIDBG_CFGLPSPD   0x0A

Definition at line 898 of file atl1c_hw.h.

#define MIIDBG_HIBNEG   0x0B

Definition at line 903 of file atl1c_hw.h.

#define MIIDBG_LEGCYPS   0x29

Definition at line 943 of file atl1c_hw.h.

#define MIIDBG_MSE16DB   0x18 /* l1d */

Definition at line 939 of file atl1c_hw.h.

#define MIIDBG_SRDSYSMOD   0x05

Definition at line 885 of file atl1c_hw.h.

#define MIIDBG_SYSMODCTRL   0x04

Definition at line 852 of file atl1c_hw.h.

#define MIIDBG_TST100BTCFG   0x36

Definition at line 958 of file atl1c_hw.h.

#define MIIDBG_TST10BTCFG   0x12

Definition at line 917 of file atl1c_hw.h.

#define MIIDBG_VOLT_CTRL   0x3B /* only for l2cb 1 & 2 */

Definition at line 969 of file atl1c_hw.h.

#define MIIEXT_ANEG   7

Definition at line 998 of file atl1c_hw.h.

#define MIIEXT_CLDCTRL3   0x8003

Definition at line 986 of file atl1c_hw.h.

#define MIIEXT_CLDCTRL6   0x8006

Definition at line 992 of file atl1c_hw.h.

#define MIIEXT_EEE_ANEG   0x8000

Definition at line 1008 of file atl1c_hw.h.

#define MIIEXT_LOCAL_EEEADV   0x3C

Definition at line 1000 of file atl1c_hw.h.

#define MIIEXT_PCS   3

Definition at line 984 of file atl1c_hw.h.

#define MIIEXT_REMOTE_EEEADV   0x3D

Definition at line 1004 of file atl1c_hw.h.

#define OTP_CTRL_CLK_EN   BIT(1)

Definition at line 151 of file atl1c_hw.h.

#define PCI_DEVICE_ID_ATHEROS_L1D   0x1073 /* AR8151 v1.0 Gigabit 1000 */

Definition at line 73 of file atl1c_hw.h.

#define PCI_DEVICE_ID_ATHEROS_L1D_2_0   0x1083 /* AR8151 v2.0 Gigabit 1000 */

Definition at line 74 of file atl1c_hw.h.

#define PCI_DEVICE_ID_ATHEROS_L2C_B   0x2060 /* AR8152 v1.1 Fast 10/100 */

Definition at line 71 of file atl1c_hw.h.

#define PCI_DEVICE_ID_ATHEROS_L2C_B2   0x2062 /* AR8152 v2.0 Fast 10/100 */

Definition at line 72 of file atl1c_hw.h.

#define PCI_DEVICE_ID_ATTANSIC_L1C   0x1063

Definition at line 70 of file atl1c_hw.h.

#define PCI_DEVICE_ID_ATTANSIC_L2C   0x1062

Definition at line 69 of file atl1c_hw.h.

#define PCIE_DEV_MISC_EXT_PIPE   0x2

Definition at line 115 of file atl1c_hw.h.

#define PCIE_DEV_MISC_RETRY_BUFDIS   0x1

Definition at line 116 of file atl1c_hw.h.

#define PCIE_DEV_MISC_SERDES_ENDIAN   0x8

Definition at line 118 of file atl1c_hw.h.

#define PCIE_DEV_MISC_SERDES_SEL_DIN   0x10

Definition at line 119 of file atl1c_hw.h.

#define PCIE_DEV_MISC_SPIROM_EXIST   0x4

Definition at line 117 of file atl1c_hw.h.

#define PCIE_PHYMISC2_CDR_BW_MASK   0x3UL

Definition at line 130 of file atl1c_hw.h.

#define PCIE_PHYMISC2_CDR_BW_SHIFT   16

Definition at line 131 of file atl1c_hw.h.

#define PCIE_PHYMISC2_L0S_TH_MASK   0x3UL

Definition at line 127 of file atl1c_hw.h.

#define PCIE_PHYMISC2_L0S_TH_SHIFT   18

Definition at line 128 of file atl1c_hw.h.

#define PCIE_PHYMISC_FORCE_RCV_DET   BIT(2)

Definition at line 122 of file atl1c_hw.h.

#define PCIE_PHYMISC_NFTS_MASK   0xFFUL

Definition at line 123 of file atl1c_hw.h.

#define PCIE_PHYMISC_NFTS_SHIFT   16

Definition at line 124 of file atl1c_hw.h.

#define PM_CTRL_ASPM_L0S_EN   BIT(12)

Definition at line 182 of file atl1c_hw.h.

#define PM_CTRL_ASPM_L1_EN   BIT(3)

Definition at line 192 of file atl1c_hw.h.

#define PM_CTRL_CLK_PWM_VER1_1   BIT(14) /* 0:1.0a,1:1.1 */

Definition at line 180 of file atl1c_hw.h.

#define PM_CTRL_CLK_REQ_EN   BIT(2)

Definition at line 193 of file atl1c_hw.h.

#define PM_CTRL_CLK_SWH_L1   BIT(13) /* en pcie clk sw in L1 */

Definition at line 181 of file atl1c_hw.h.

#define PM_CTRL_HOTRST   BIT(31)

Definition at line 154 of file atl1c_hw.h.

#define PM_CTRL_L0S_BUFSRX_EN   BIT(28)

Definition at line 157 of file atl1c_hw.h.

#define PM_CTRL_L0S_ENTRY_TIMER_MASK   0xFUL /* l1c, 4bits */

Definition at line 186 of file atl1c_hw.h.

#define PM_CTRL_L0S_ENTRY_TIMER_SHIFT   8

Definition at line 187 of file atl1c_hw.h.

#define PM_CTRL_L1_ENTRY_TIMER_MASK   0xFUL /* l1C 4bits */

Definition at line 175 of file atl1c_hw.h.

#define PM_CTRL_L1_ENTRY_TIMER_SHIFT   16

Definition at line 176 of file atl1c_hw.h.

#define PM_CTRL_LCKDET_TIMER_DEF   0xC

Definition at line 160 of file atl1c_hw.h.

#define PM_CTRL_LCKDET_TIMER_MASK   0xFUL

Definition at line 158 of file atl1c_hw.h.

#define PM_CTRL_LCKDET_TIMER_SHIFT   24

Definition at line 159 of file atl1c_hw.h.

#define PM_CTRL_MAC_ASPM_CHK
Value:
BIT(30) /* L0s/L1 dis by MAC based on
* thrghput(setting in 15A0) */

Definition at line 155 of file atl1c_hw.h.

#define PM_CTRL_PM_REQ_TIMER_MASK   0xFUL

Definition at line 161 of file atl1c_hw.h.

#define PM_CTRL_PM_REQ_TIMER_SHIFT
Value:
20 /* pm_request_l1 time > @
* ->L0s not L1 */

Definition at line 162 of file atl1c_hw.h.

#define PM_CTRL_PM_REQ_TO_DEF   0xF

Definition at line 163 of file atl1c_hw.h.

#define PM_CTRL_RBER_EN   BIT(1)

Definition at line 194 of file atl1c_hw.h.

#define PM_CTRL_RCVR_WT_TIMER   BIT(15) /* 1:1us, 0:2ms */

Definition at line 179 of file atl1c_hw.h.

#define PM_CTRL_RXL1_AFTER_L0S   BIT(11) /* l1dv2.0+ */

Definition at line 183 of file atl1c_hw.h.

#define PM_CTRL_SA_DLY_EN   BIT(29)

Definition at line 156 of file atl1c_hw.h.

#define PM_CTRL_SERDES_BUFS_RX_L1_EN   BIT(7)

Definition at line 188 of file atl1c_hw.h.

#define PM_CTRL_SERDES_L1_EN   BIT(4)

Definition at line 191 of file atl1c_hw.h.

#define PM_CTRL_SERDES_PD_EX_L1   BIT(6) /* power down serdes rx */

Definition at line 189 of file atl1c_hw.h.

#define PM_CTRL_SERDES_PLL_L1_EN   BIT(5)

Definition at line 190 of file atl1c_hw.h.

#define PM_CTRL_SPRSDWER_EN   BIT(0)

Definition at line 195 of file atl1c_hw.h.

#define PMCTRL_TXL1_AFTER_L0S   BIT(19) /* l1dv2.0+ */

Definition at line 164 of file atl1c_hw.h.

#define REG_BIST0_CTRL   0x141c

Definition at line 314 of file atl1c_hw.h.

#define REG_BIST1_CTRL   0x1420

Definition at line 320 of file atl1c_hw.h.

#define REG_CLK_GATING_CTRL   0x1814

Definition at line 749 of file atl1c_hw.h.

#define REG_DEBUG_DATA0   0x1900

Definition at line 765 of file atl1c_hw.h.

#define REG_DEBUG_DATA1   0x1904

Definition at line 766 of file atl1c_hw.h.

#define REG_DEV_MAC_SEL_MASK   0x0 /* 0:EUI; 1:MAC */

Definition at line 96 of file atl1c_hw.h.

#define REG_DEV_MAC_SEL_SHIFT   0

Definition at line 97 of file atl1c_hw.h.

#define REG_DEV_SERIAL_NUM_EN_MASK   0x1

Definition at line 98 of file atl1c_hw.h.

#define REG_DEV_SERIAL_NUM_EN_SHIFT   1

Definition at line 99 of file atl1c_hw.h.

#define REG_DEV_SERIALNUM_CTRL   0x200

Definition at line 95 of file atl1c_hw.h.

#define REG_DEVICE_CAP   0x5C

Definition at line 81 of file atl1c_hw.h.

#define REG_DMA_CTRL   0x15C0

Definition at line 628 of file atl1c_hw.h.

#define REG_DMA_DBG   0x1114

Definition at line 137 of file atl1c_hw.h.

#define REG_EEPROM_CTRL   0x12C0

Definition at line 140 of file atl1c_hw.h.

#define REG_EEPROM_DATA_LO   0x12C4

Definition at line 148 of file atl1c_hw.h.

#define REG_GPHY_CTRL   0x140C

Definition at line 233 of file atl1c_hw.h.

#define REG_IDLE_STATUS   0x1410

Definition at line 262 of file atl1c_hw.h.

#define REG_IMR   0x1604

Definition at line 705 of file atl1c_hw.h.

#define REG_INT_RETRIG_TIMER   0x1608

Definition at line 741 of file atl1c_hw.h.

#define REG_IRQ_MODRT_TIMER_INIT   0x1408

Definition at line 228 of file atl1c_hw.h.

#define REG_ISR   0x1600

Definition at line 669 of file atl1c_hw.h.

#define REG_LINK_CTRL   0x68

Definition at line 87 of file atl1c_hw.h.

#define REG_LOAD_PTR   0x1534

Definition at line 520 of file atl1c_hw.h.

#define REG_LPI_CTRL   0x1440

Definition at line 352 of file atl1c_hw.h.

#define REG_LPI_DECISN_TIMER   0x143C

Definition at line 349 of file atl1c_hw.h.

#define REG_LPI_WAIT   0x1444

Definition at line 365 of file atl1c_hw.h.

#define REG_LTSSM_ID_CTRL   0x12FC

Definition at line 197 of file atl1c_hw.h.

#define REG_MAC_CTRL   0x1480

Definition at line 370 of file atl1c_hw.h.

#define REG_MAC_HALF_DUPLX_CTRL   0x1498

Definition at line 420 of file atl1c_hw.h.

#define REG_MAC_IPG_IFG   0x1484

Definition at line 403 of file atl1c_hw.h.

#define REG_MAC_RX_STATUS_BIN   0x1700

Definition at line 744 of file atl1c_hw.h.

#define REG_MAC_RX_STATUS_END   0x175c

Definition at line 745 of file atl1c_hw.h.

#define REG_MAC_STA_ADDR   0x1488

Definition at line 414 of file atl1c_hw.h.

#define REG_MAC_TX_STATUS_BIN   0x1760

Definition at line 746 of file atl1c_hw.h.

#define REG_MAC_TX_STATUS_END   0x17c0

Definition at line 747 of file atl1c_hw.h.

#define REG_MANUAL_TIMER_INIT   0x1404

Definition at line 225 of file atl1c_hw.h.

#define REG_MASTER_CTRL   0x1400

Definition at line 202 of file atl1c_hw.h.

#define REG_MB_RFD01_CONS_IDX   0x15F8

Definition at line 664 of file atl1c_hw.h.

#define REG_MB_RFD0_PROD_IDX   0x15E0

Definition at line 657 of file atl1c_hw.h.

#define REG_MDIO_CTRL   0x1414

Definition at line 281 of file atl1c_hw.h.

#define REG_MDIO_EXTN   0x1448

Definition at line 305 of file atl1c_hw.h.

#define REG_MTU   0x149c

Definition at line 435 of file atl1c_hw.h.

#define REG_OTP_CTRL   0x12F0

Definition at line 150 of file atl1c_hw.h.

#define REG_PCIE_DEV_MISC_CTRL   0x21C

Definition at line 114 of file atl1c_hw.h.

#define REG_PCIE_IND_ACC_ADDR   0x80

Definition at line 92 of file atl1c_hw.h.

#define REG_PCIE_IND_ACC_DATA   0x84

Definition at line 93 of file atl1c_hw.h.

#define REG_PCIE_PHYMISC   0x1000

Definition at line 121 of file atl1c_hw.h.

#define REG_PCIE_PHYMISC2   0x1004

Definition at line 126 of file atl1c_hw.h.

#define REG_PM_CTRL   0x12F8

Definition at line 153 of file atl1c_hw.h.

#define REG_RFD0_HEAD_ADDR_LO   0x1550

Definition at line 530 of file atl1c_hw.h.

#define REG_RFD_FREE_THRESH   0x15A4

Definition at line 609 of file atl1c_hw.h.

#define REG_RFD_NIC_LEN   0x1510 /* In 8-bytes */

Definition at line 498 of file atl1c_hw.h.

#define REG_RFD_RING_SIZE   0x1560

Definition at line 531 of file atl1c_hw.h.

#define REG_RRD0_HEAD_ADDR_LO   0x1568

Definition at line 535 of file atl1c_hw.h.

#define REG_RRD_RING_SIZE   0x1578

Definition at line 536 of file atl1c_hw.h.

#define REG_RX_BASE_ADDR_HI   0x1540

Definition at line 528 of file atl1c_hw.h.

#define REG_RX_BUF_SIZE   0x1564

Definition at line 533 of file atl1c_hw.h.

#define REG_RX_HASH_TABLE   0x1490

Definition at line 417 of file atl1c_hw.h.

#define REG_RXD_DMA_CTRL   0x15AC

Definition at line 621 of file atl1c_hw.h.

#define REG_RXQ_CTRL   0x15A0

Definition at line 587 of file atl1c_hw.h.

#define REG_RXQ_RXF_PAUSE_THRESH   0x15A8

Definition at line 615 of file atl1c_hw.h.

#define REG_SERDES   0x1424

Definition at line 326 of file atl1c_hw.h.

#define REG_SMB_STAT_TIMER   0x15C4 /* 2us resolution */

Definition at line 651 of file atl1c_hw.h.

#define REG_SRAM_PKTH_ADDR   0x1532

Definition at line 515 of file atl1c_hw.h.

#define REG_SRAM_RFD0_INFO   0x1500

Definition at line 493 of file atl1c_hw.h.

#define REG_SRAM_RFD1_INFO   0x1504

Definition at line 494 of file atl1c_hw.h.

#define REG_SRAM_RFD2_INFO   0x1508

Definition at line 495 of file atl1c_hw.h.

#define REG_SRAM_RFD3_INFO   0x150C

Definition at line 496 of file atl1c_hw.h.

#define REG_SRAM_RXF_ADDR   0x1520

Definition at line 510 of file atl1c_hw.h.

#define REG_SRAM_RXF_LEN   0x1524

Definition at line 511 of file atl1c_hw.h.

#define REG_SRAM_TCPH_ADDR   0x1530

Definition at line 514 of file atl1c_hw.h.

#define REG_SRAM_TRD_ADDR   0x1518

Definition at line 501 of file atl1c_hw.h.

#define REG_SRAM_TRD_LEN   0x151C /* In 8-bytes */

Definition at line 507 of file atl1c_hw.h.

#define REG_SRAM_TXF_ADDR   0x1528

Definition at line 512 of file atl1c_hw.h.

#define REG_SRAM_TXF_LEN   0x152C

Definition at line 513 of file atl1c_hw.h.

#define REG_THRUPUT_MON_CTRL   0x159C

Definition at line 581 of file atl1c_hw.h.

#define REG_TINT_TPD_THRESH   0x15C8 /* tpd th to trig intrrupt */

Definition at line 653 of file atl1c_hw.h.

#define REG_TPD_PRI0_ADDR_LO   0x1580

Definition at line 539 of file atl1c_hw.h.

#define REG_TPD_PRI0_CIDX   0x15F6 /* 16bit,lo-tpd consumer idx */

Definition at line 662 of file atl1c_hw.h.

#define REG_TPD_PRI0_PIDX   0x15F2 /* 16bit,lo-tpd producer idx */

Definition at line 660 of file atl1c_hw.h.

#define REG_TPD_PRI1_ADDR_LO   0x157C

Definition at line 538 of file atl1c_hw.h.

#define REG_TPD_PRI1_CIDX   0x15F4 /* 16bit,hi-tpd consumer idx */

Definition at line 661 of file atl1c_hw.h.

#define REG_TPD_PRI1_PIDX   0x15F0 /* 16bit,hi-tpd producer idx */

Definition at line 659 of file atl1c_hw.h.

#define REG_TPD_RING_SIZE   0x1584

Definition at line 540 of file atl1c_hw.h.

#define REG_TWSI_CTRL   0x218

Definition at line 101 of file atl1c_hw.h.

#define REG_TWSI_DEBUG   0x1108

Definition at line 134 of file atl1c_hw.h.

#define REG_TX_BASE_ADDR_HI   0x1544

Definition at line 529 of file atl1c_hw.h.

#define REG_TX_TSO_OFFLOAD_THRESH   0x1594 /* In 8-bytes */

Definition at line 571 of file atl1c_hw.h.

#define REG_TXF_WATER_MARK   0x1598 /* In 8-bytes */

Definition at line 575 of file atl1c_hw.h.

#define REG_TXQ_CTRL   0x1590

Definition at line 544 of file atl1c_hw.h.

#define REG_WOL_CTRL   0x14a0

Definition at line 438 of file atl1c_hw.h.

#define REG_WOL_PTLEN1   0x14A4

Definition at line 467 of file atl1c_hw.h.

#define REG_WOL_PTLEN2   0x14A8

Definition at line 477 of file atl1c_hw.h.

#define REMOTE_EEEADV_1000BT   0x4

Definition at line 1005 of file atl1c_hw.h.

#define REMOTE_EEEADV_100BT   0x2

Definition at line 1006 of file atl1c_hw.h.

#define RFD_FREE_HI_THRESH_SHIFT   0

Definition at line 611 of file atl1c_hw.h.

#define RFD_FREE_LO_THRESH_SHIFT   6

Definition at line 612 of file atl1c_hw.h.

#define RFD_FREE_THRESH_MASK   0x003F

Definition at line 610 of file atl1c_hw.h.

#define RFD_NIC_LEN_MASK   0x03FF

Definition at line 499 of file atl1c_hw.h.

#define RFD_RING_SIZE_MASK   0x0FFF

Definition at line 532 of file atl1c_hw.h.

#define RFDX_HARD_ADDR_SHIFT   0

Definition at line 489 of file atl1c_hw.h.

#define RFDX_HEAD_ADDR_MASK   0x03FF

Definition at line 488 of file atl1c_hw.h.

#define RFDX_TAIL_ADDR_MASK   0x03FF

Definition at line 490 of file atl1c_hw.h.

#define RFDX_TAIL_ADDR_SHIFT   16

Definition at line 491 of file atl1c_hw.h.

#define RRD_RING_SIZE_MASK   0x0FFF

Definition at line 537 of file atl1c_hw.h.

#define RRS_HASH_CTRL_EN   BIT(29)

Definition at line 605 of file atl1c_hw.h.

#define RSS_MODE_DIS   0

Definition at line 600 of file atl1c_hw.h.

#define RSS_MODE_MASK   3UL

Definition at line 598 of file atl1c_hw.h.

#define RSS_MODE_MQMI   3

Definition at line 603 of file atl1c_hw.h.

#define RSS_MODE_MQSI   2

Definition at line 602 of file atl1c_hw.h.

#define RSS_MODE_SHIFT   26

Definition at line 599 of file atl1c_hw.h.

#define RSS_MODE_SQSI   1

Definition at line 601 of file atl1c_hw.h.

#define RSS_NIP_QUEUE_SEL   BIT(28) /* 0:q0, 1:table */

Definition at line 604 of file atl1c_hw.h.

#define RX_BUF_SIZE_MASK   0xFFFF

Definition at line 534 of file atl1c_hw.h.

#define RX_CUT_THRU_EN   BIT(30)

Definition at line 606 of file atl1c_hw.h.

#define RXD_DMA_DOWN_TIMER_MASK   0xFFFF

Definition at line 624 of file atl1c_hw.h.

#define RXD_DMA_DOWN_TIMER_SHIFT   16

Definition at line 625 of file atl1c_hw.h.

#define RXD_DMA_THRESH_MASK   0x0FFF /* In 8-bytes */

Definition at line 622 of file atl1c_hw.h.

#define RXD_DMA_THRESH_SHIFT   0

Definition at line 623 of file atl1c_hw.h.

#define RXQ_CTRL_EN   BIT(31)

Definition at line 607 of file atl1c_hw.h.

#define RXQ_NUM_RFD_PREF_DEF   8

Definition at line 597 of file atl1c_hw.h.

#define RXQ_RFD_BURST_NUM_MASK   0x003F

Definition at line 595 of file atl1c_hw.h.

#define RXQ_RFD_BURST_NUM_SHIFT   20

Definition at line 596 of file atl1c_hw.h.

#define RXQ_RXF_PAUSE_TH_HI_MASK   0x0FFF

Definition at line 617 of file atl1c_hw.h.

#define RXQ_RXF_PAUSE_TH_HI_SHIFT   0

Definition at line 616 of file atl1c_hw.h.

#define RXQ_RXF_PAUSE_TH_LO_MASK   0x0FFF

Definition at line 619 of file atl1c_hw.h.

#define RXQ_RXF_PAUSE_TH_LO_SHIFT   16

Definition at line 618 of file atl1c_hw.h.

#define SERDES_BUFS_RX_EN   BIT(11)

Definition at line 333 of file atl1c_hw.h.

#define SERDES_EN   BIT(8)

Definition at line 336 of file atl1c_hw.h.

#define SERDES_LOCK_DETECT   BIT(0)

Definition at line 347 of file atl1c_hw.h.

#define SERDES_LOCK_DETECT_EN   BIT(1)

Definition at line 346 of file atl1c_hw.h.

#define SERDES_MAC_CLK_SLOWDOWN   BIT(17)

Definition at line 328 of file atl1c_hw.h.

#define SERDES_PCIECLK_SEL_SRDS   BIT(12) /* 1:serdes,0:25M */

Definition at line 332 of file atl1c_hw.h.

#define SERDES_PD_RX   BIT(10)

Definition at line 334 of file atl1c_hw.h.

#define SERDES_PHY_CLK_SLOWDOWN   BIT(18)

Definition at line 327 of file atl1c_hw.h.

#define SERDES_PHYCLK_SEL_GTX   BIT(13) /* 1:gtx_clk, 0:25M */

Definition at line 331 of file atl1c_hw.h.

#define SERDES_PLL_EN   BIT(9)

Definition at line 335 of file atl1c_hw.h.

#define SERDES_SELFB_PLL_CSR_0   2 /* 0-4% OV-CLK */

Definition at line 341 of file atl1c_hw.h.

#define SERDES_SELFB_PLL_CSR_12   1 /* 12-18% OV-CLK */

Definition at line 342 of file atl1c_hw.h.

#define SERDES_SELFB_PLL_CSR_18   0 /* 18-25% OV-CLK */

Definition at line 343 of file atl1c_hw.h.

#define SERDES_SELFB_PLL_CSR_4   3 /* 4-12% OV-CLK */

Definition at line 340 of file atl1c_hw.h.

#define SERDES_SELFB_PLL_CSR_MASK   0x3UL

Definition at line 338 of file atl1c_hw.h.

#define SERDES_SELFB_PLL_CSR_SHIFT   4

Definition at line 339 of file atl1c_hw.h.

#define SERDES_SELFB_PLL_MASK   0x3UL

Definition at line 329 of file atl1c_hw.h.

#define SERDES_SELFB_PLL_SEL_CSR   BIT(6) /* 0:state-machine,1:csr */

Definition at line 337 of file atl1c_hw.h.

#define SERDES_SELFB_PLL_SHIFT   14

Definition at line 330 of file atl1c_hw.h.

#define SERDES_VCO_FAST   BIT(2)

Definition at line 345 of file atl1c_hw.h.

#define SERDES_VCO_SLOW   BIT(3)

Definition at line 344 of file atl1c_hw.h.

#define SMB_STAT_TIMER_MASK   0xFFFFFF

Definition at line 652 of file atl1c_hw.h.

#define SRDSYSMOD_CDR_ADC_VLTG   0x2

Definition at line 894 of file atl1c_hw.h.

#define SRDSYSMOD_CDR_DAC_1MA   0x1

Definition at line 895 of file atl1c_hw.h.

#define SRDSYSMOD_DEEMP_EN   0x40

Definition at line 892 of file atl1c_hw.h.

#define SRDSYSMOD_DEF   0x2C46

Definition at line 896 of file atl1c_hw.h.

#define SRDSYSMOD_HLFTXDR   0x200

Definition at line 889 of file atl1c_hw.h.

#define SRDSYSMOD_LCKDET_EN   0x2000

Definition at line 886 of file atl1c_hw.h.

#define SRDSYSMOD_MS_PAD   0x4

Definition at line 893 of file atl1c_hw.h.

#define SRDSYSMOD_PLL_EN   0x800

Definition at line 887 of file atl1c_hw.h.

#define SRDSYSMOD_SEL_HSP   0x400

Definition at line 888 of file atl1c_hw.h.

#define SRDSYSMOD_TXCLK_DELAY_EN   0x100

Definition at line 890 of file atl1c_hw.h.

#define SRDSYSMOD_TXELECIDLE   0x80

Definition at line 891 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_10BT_100MV   0x40 /* 1:100mv, 0:200mv */

Definition at line 861 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_BIAS1_MASK   0xFU

Definition at line 879 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_BIAS1_SHIFT   4

Definition at line 880 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_BIAS2_MASK   0xFU

Definition at line 881 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_BIAS2_SHIFT   0

Definition at line 882 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_BIASGEN   0x4000

Definition at line 854 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_CUR_ADD   0x8000

Definition at line 871 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_CUR_MASK   7U

Definition at line 872 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_CUR_SHIFT   12

Definition at line 873 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_DEF   0x88BB /* ???? */

Definition at line 868 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_HLFAP_MASK   3U

Definition at line 862 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_HLFAP_SHIFT   4

Definition at line 863 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_PFMH_PHY   0x8000

Definition at line 853 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_PFML_PHY   0x2000

Definition at line 855 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_PS_0   1

Definition at line 860 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_PS_20   2

Definition at line 859 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_PS_40   3

Definition at line 858 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_PS_MASK   3U

Definition at line 856 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_PS_SHIFT   10

Definition at line 857 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_VDAMPHLF   0x2

Definition at line 866 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_VDBIASHLF   0x4

Definition at line 865 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_VDFULBW   0x8

Definition at line 864 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_VDLANSW   0x1

Definition at line 867 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_VOL_100M15   1

Definition at line 877 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_VOL_10M17   0

Definition at line 878 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_VOL_17ALL   3

Definition at line 876 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_VOL_MASK   0xFU

Definition at line 874 of file atl1c_hw.h.

#define SYSMODCTRL_IECHOADJ_VOL_SHIFT   8

Definition at line 875 of file atl1c_hw.h.

#define THRUPUT_MON_EN   0x80

Definition at line 584 of file atl1c_hw.h.

#define THRUPUT_MON_RATE_MASK   0x3

Definition at line 582 of file atl1c_hw.h.

#define THRUPUT_MON_RATE_SHIFT   0

Definition at line 583 of file atl1c_hw.h.

#define TPD_HEAD_ADDR_MASK   0x03FF

Definition at line 502 of file atl1c_hw.h.

#define TPD_HEAD_ADDR_SHIFT   0

Definition at line 503 of file atl1c_hw.h.

#define TPD_NIC_LEN_MASK   0x03FF

Definition at line 508 of file atl1c_hw.h.

#define TPD_RING_SIZE_MASK   0xFFFF

Definition at line 541 of file atl1c_hw.h.

#define TPD_TAIL_ADDR_MASK   0x03FF

Definition at line 504 of file atl1c_hw.h.

#define TPD_TAIL_ADDR_SHIFT   16

Definition at line 505 of file atl1c_hw.h.

#define TST100BTCFG_BADLNK_BYPASS   0x4000

Definition at line 960 of file atl1c_hw.h.

#define TST100BTCFG_DEF   0xE12C

Definition at line 967 of file atl1c_hw.h.

#define TST100BTCFG_LITCH_EN   0x80

Definition at line 963 of file atl1c_hw.h.

#define TST100BTCFG_LONGCABL_TH_MASK   0x3FU

Definition at line 965 of file atl1c_hw.h.

#define TST100BTCFG_LONGCABL_TH_SHIFT   0

Definition at line 966 of file atl1c_hw.h.

#define TST100BTCFG_NORMAL_BW_EN   0x8000

Definition at line 959 of file atl1c_hw.h.

#define TST100BTCFG_SHORTCABL_TH_MASK   0x3FU

Definition at line 961 of file atl1c_hw.h.

#define TST100BTCFG_SHORTCABL_TH_SHIFT   8

Definition at line 962 of file atl1c_hw.h.

#define TST100BTCFG_VLT_SW   0x40

Definition at line 964 of file atl1c_hw.h.

#define TST10BTCFG_DEF   0x4C04

Definition at line 925 of file atl1c_hw.h.

#define TST10BTCFG_DIV_MAN_MLT3_EN   0x800

Definition at line 922 of file atl1c_hw.h.

#define TST10BTCFG_INTV_TIMER_MASK   3U

Definition at line 918 of file atl1c_hw.h.

#define TST10BTCFG_INTV_TIMER_SHIFT   14

Definition at line 919 of file atl1c_hw.h.

#define TST10BTCFG_LPBK_DEEP   0x4 /* 1:deep,0:shallow */

Definition at line 924 of file atl1c_hw.h.

#define TST10BTCFG_OFF_DAC_IDLE   0x400

Definition at line 923 of file atl1c_hw.h.

#define TST10BTCFG_TRIGER_TIMER_MASK   3U

Definition at line 920 of file atl1c_hw.h.

#define TST10BTCFG_TRIGER_TIMER_SHIFT   12

Definition at line 921 of file atl1c_hw.h.

#define TWSI_CTLR_FREQ_MASK   0x3UL

Definition at line 102 of file atl1c_hw.h.

#define TWSI_CTRL_FREQ_100K   0

Definition at line 104 of file atl1c_hw.h.

#define TWSI_CTRL_FREQ_200K   1

Definition at line 105 of file atl1c_hw.h.

#define TWSI_CTRL_FREQ_300K   2

Definition at line 106 of file atl1c_hw.h.

#define TWSI_CTRL_FREQ_400K   3

Definition at line 107 of file atl1c_hw.h.

#define TWSI_CTRL_FREQ_SHIFT   24

Definition at line 103 of file atl1c_hw.h.

#define TWSI_CTRL_HW_LDSTAT   BIT(12) /* 0:finish,1:in progress */

Definition at line 109 of file atl1c_hw.h.

#define TWSI_CTRL_LD_EXIST   BIT(23)

Definition at line 108 of file atl1c_hw.h.

#define TWSI_CTRL_LD_OFFSET_MASK   0xFF

Definition at line 111 of file atl1c_hw.h.

#define TWSI_CTRL_LD_OFFSET_SHIFT   0

Definition at line 112 of file atl1c_hw.h.

#define TWSI_CTRL_SW_LDSTART   BIT(11)

Definition at line 110 of file atl1c_hw.h.

#define TWSI_DEBUG_DEV_EXIST   BIT(29)

Definition at line 135 of file atl1c_hw.h.

#define TX_TSO_OFFLOAD_THRESH_MASK   0x07FF

Definition at line 572 of file atl1c_hw.h.

#define TXF_HIGH_WATER_MARK_SHIFT   16

Definition at line 578 of file atl1c_hw.h.

#define TXF_LOW_WATER_MARK_SHIFT   0

Definition at line 577 of file atl1c_hw.h.

#define TXF_WATER_MARK_MASK   0x0FFF

Definition at line 576 of file atl1c_hw.h.

#define TXQ_CFGV
Value:
(\
FIELDX(TXQ_NUM_TPD_BURST, TXQ_NUM_TPD_BURST_DEF) |\
TXQ_CTRL_ENH_MODE |\
TXQ_CTRL_LS_8023_EN |\
TXQ_CTRL_IP_OPTION_EN)

Definition at line 557 of file atl1c_hw.h.

#define TXQ_CTRL_BURST_MODE_EN   0x80000000

Definition at line 579 of file atl1c_hw.h.

#define TXQ_CTRL_EN   BIT(5)

Definition at line 552 of file atl1c_hw.h.

#define TXQ_CTRL_ENH_MODE   BIT(6)

Definition at line 551 of file atl1c_hw.h.

#define TXQ_CTRL_IP_OPTION_EN   BIT(4)

Definition at line 553 of file atl1c_hw.h.

#define TXQ_CTRL_LS_8023_EN   BIT(7)

Definition at line 550 of file atl1c_hw.h.

#define TXQ_CTRL_PEDING_CLR   BIT(8)

Definition at line 549 of file atl1c_hw.h.

#define TXQ_NUM_TPD_BURST_DEF   5

Definition at line 556 of file atl1c_hw.h.

#define TXQ_NUM_TPD_BURST_MASK   0xFUL

Definition at line 554 of file atl1c_hw.h.

#define TXQ_NUM_TPD_BURST_SHIFT   0

Definition at line 555 of file atl1c_hw.h.

#define TXQ_TXF_BURST_NUM_MASK   0xFFFFUL

Definition at line 545 of file atl1c_hw.h.

#define TXQ_TXF_BURST_NUM_SHIFT   16

Definition at line 546 of file atl1c_hw.h.

#define VOLT_CTRL_AMPCTRL_MASK   3U

Definition at line 972 of file atl1c_hw.h.

#define VOLT_CTRL_AMPCTRL_SHIFT   5

Definition at line 973 of file atl1c_hw.h.

#define VOLT_CTRL_CABLE1TH_MASK   0x1FFU

Definition at line 970 of file atl1c_hw.h.

#define VOLT_CTRL_CABLE1TH_SHIFT   7

Definition at line 971 of file atl1c_hw.h.

#define VOLT_CTRL_DACAMP10_MASK   7U

Definition at line 976 of file atl1c_hw.h.

#define VOLT_CTRL_DACAMP10_SHIFT   0

Definition at line 977 of file atl1c_hw.h.

#define VOLT_CTRL_SW_BYPASS   0x10

Definition at line 974 of file atl1c_hw.h.

#define VOLT_CTRL_SWLOWEST   0x8

Definition at line 975 of file atl1c_hw.h.

#define WOL_LINK_CHG_EN   BIT(4)

Definition at line 460 of file atl1c_hw.h.

#define WOL_LINK_CHG_PME_EN   BIT(5)

Definition at line 459 of file atl1c_hw.h.

#define WOL_LNKCHG_ST   BIT(10)

Definition at line 455 of file atl1c_hw.h.

#define WOL_MAGIC_EN   BIT(2)

Definition at line 462 of file atl1c_hw.h.

#define WOL_MAGIC_PME_EN   BIT(3)

Definition at line 461 of file atl1c_hw.h.

#define WOL_MAGIC_ST   BIT(9)

Definition at line 456 of file atl1c_hw.h.

#define WOL_OOB_EN   BIT(6)

Definition at line 458 of file atl1c_hw.h.

#define WOL_PATTERN_EN   BIT(0)

Definition at line 464 of file atl1c_hw.h.

#define WOL_PATTERN_PME_EN   BIT(1)

Definition at line 463 of file atl1c_hw.h.

#define WOL_PATTERN_ST   BIT(8)

Definition at line 457 of file atl1c_hw.h.

#define WOL_PT0_EN   BIT(16)

Definition at line 454 of file atl1c_hw.h.

#define WOL_PT0_MATCH   BIT(24)

Definition at line 446 of file atl1c_hw.h.

#define WOL_PT1_EN   BIT(17)

Definition at line 453 of file atl1c_hw.h.

#define WOL_PT1_MATCH   BIT(25)

Definition at line 445 of file atl1c_hw.h.

#define WOL_PT2_EN   BIT(18)

Definition at line 452 of file atl1c_hw.h.

#define WOL_PT2_MATCH   BIT(26)

Definition at line 444 of file atl1c_hw.h.

#define WOL_PT3_EN   BIT(19)

Definition at line 451 of file atl1c_hw.h.

#define WOL_PT3_MATCH   BIT(27)

Definition at line 443 of file atl1c_hw.h.

#define WOL_PT4_EN   BIT(20)

Definition at line 450 of file atl1c_hw.h.

#define WOL_PT4_MATCH   BIT(28)

Definition at line 442 of file atl1c_hw.h.

#define WOL_PT5_EN   BIT(21)

Definition at line 449 of file atl1c_hw.h.

#define WOL_PT5_MATCH   BIT(29)

Definition at line 441 of file atl1c_hw.h.

#define WOL_PT6_EN   BIT(22)

Definition at line 448 of file atl1c_hw.h.

#define WOL_PT6_MATCH   BIT(30)

Definition at line 440 of file atl1c_hw.h.

#define WOL_PT7_EN   BIT(23)

Definition at line 447 of file atl1c_hw.h.

#define WOL_PT7_MATCH   BIT(31)

Definition at line 439 of file atl1c_hw.h.

#define WOL_PTLEN1_0_MASK   0xFFUL

Definition at line 474 of file atl1c_hw.h.

#define WOL_PTLEN1_0_SHIFT   0

Definition at line 475 of file atl1c_hw.h.

#define WOL_PTLEN1_1_MASK   0xFFUL

Definition at line 472 of file atl1c_hw.h.

#define WOL_PTLEN1_1_SHIFT   8

Definition at line 473 of file atl1c_hw.h.

#define WOL_PTLEN1_2_MASK   0xFFUL

Definition at line 470 of file atl1c_hw.h.

#define WOL_PTLEN1_2_SHIFT   16

Definition at line 471 of file atl1c_hw.h.

#define WOL_PTLEN1_3_MASK   0xFFUL

Definition at line 468 of file atl1c_hw.h.

#define WOL_PTLEN1_3_SHIFT   24

Definition at line 469 of file atl1c_hw.h.

#define WOL_PTLEN2_4_MASK   0xFFUL

Definition at line 484 of file atl1c_hw.h.

#define WOL_PTLEN2_4_SHIFT   0

Definition at line 485 of file atl1c_hw.h.

#define WOL_PTLEN2_5_MASK   0xFFUL

Definition at line 482 of file atl1c_hw.h.

#define WOL_PTLEN2_5_SHIFT   8

Definition at line 483 of file atl1c_hw.h.

#define WOL_PTLEN2_6_MASK   0xFFUL

Definition at line 480 of file atl1c_hw.h.

#define WOL_PTLEN2_6_SHIFT   16

Definition at line 481 of file atl1c_hw.h.

#define WOL_PTLEN2_7_MASK   0xFFUL

Definition at line 478 of file atl1c_hw.h.

#define WOL_PTLEN2_7_SHIFT   24

Definition at line 479 of file atl1c_hw.h.

Function Documentation

int atl1c_check_eeprom_exist ( struct atl1c_hw *  hw)

Definition at line 32 of file atl1c_hw.c.

int atl1c_get_speed_and_duplex ( struct atl1c_hw *  hw,
u16 *  speed,
u16 *  duplex 
)

Definition at line 660 of file atl1c_hw.c.

u32 atl1c_hash_mc_addr ( struct atl1c_hw *  hw,
u8 *  mc_addr 
)

Definition at line 216 of file atl1c_hw.c.

void atl1c_hash_set ( struct atl1c_hw *  hw,
u32  hash_value 
)

Definition at line 234 of file atl1c_hw.c.

void atl1c_hw_set_mac_addr ( struct atl1c_hw *  hw,
u8 *  mac_addr 
)

Definition at line 46 of file atl1c_hw.c.

void atl1c_phy_disable ( struct atl1c_hw *  hw)

Definition at line 504 of file atl1c_hw.c.

int atl1c_phy_init ( struct atl1c_hw *  hw)

Definition at line 603 of file atl1c_hw.c.

int atl1c_phy_reset ( struct atl1c_hw *  hw)

Definition at line 510 of file atl1c_hw.c.

int atl1c_phy_to_ps_link ( struct atl1c_hw *  hw)

Definition at line 697 of file atl1c_hw.c.

void atl1c_post_phy_linkchg ( struct atl1c_hw *  hw,
u16  link_speed 
)

Definition at line 832 of file atl1c_hw.c.

int atl1c_power_saving ( struct atl1c_hw *  hw,
u32  wufc 
)

Definition at line 769 of file atl1c_hw.c.

bool atl1c_read_eeprom ( struct atl1c_hw *  hw,
u32  offset,
u32 *  p_value 
)

Definition at line 153 of file atl1c_hw.c.

int atl1c_read_mac_addr ( struct atl1c_hw *  hw)

Definition at line 196 of file atl1c_hw.c.

int atl1c_read_phy_core ( struct atl1c_hw *  hw,
bool  ext,
u8  dev,
u16  reg,
u16 *  phy_data 
)

Definition at line 315 of file atl1c_hw.c.

int atl1c_read_phy_dbg ( struct atl1c_hw *  hw,
u16  reg_addr,
u16 *  phy_data 
)

Definition at line 438 of file atl1c_hw.c.

int atl1c_read_phy_ext ( struct atl1c_hw *  hw,
u8  dev_addr,
u16  reg_addr,
u16 *  phy_data 
)

Definition at line 425 of file atl1c_hw.c.

int atl1c_read_phy_reg ( struct atl1c_hw *  hw,
u16  reg_addr,
u16 *  phy_data 
)

Definition at line 408 of file atl1c_hw.c.

int atl1c_restart_autoneg ( struct atl1c_hw *  hw)

Definition at line 756 of file atl1c_hw.c.

void atl1c_start_phy_polling ( struct atl1c_hw *  hw,
u16  clk_sel 
)

Definition at line 287 of file atl1c_hw.c.

void atl1c_stop_phy_polling ( struct atl1c_hw *  hw)

Definition at line 278 of file atl1c_hw.c.

bool atl1c_wait_mdio_idle ( struct atl1c_hw *  hw)

Definition at line 263 of file atl1c_hw.c.

int atl1c_write_phy_core ( struct atl1c_hw *  hw,
bool  ext,
u8  dev,
u16  reg,
u16  phy_data 
)

Definition at line 364 of file atl1c_hw.c.

int atl1c_write_phy_dbg ( struct atl1c_hw *  hw,
u16  reg_addr,
u16  phy_data 
)

Definition at line 451 of file atl1c_hw.c.

int atl1c_write_phy_ext ( struct atl1c_hw *  hw,
u8  dev_addr,
u16  reg_addr,
u16  phy_data 
)

Definition at line 432 of file atl1c_hw.c.

int atl1c_write_phy_reg ( struct atl1c_hw *  hw,
u32  reg_addr,
u16  phy_data 
)

Definition at line 419 of file atl1c_hw.c.

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