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ixp4xx_eth.c
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1 /*
2  * Intel IXP4xx Ethernet driver for Linux
3  *
4  * Copyright (C) 2007 Krzysztof Halasa <[email protected]>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of version 2 of the GNU General Public License
8  * as published by the Free Software Foundation.
9  *
10  * Ethernet port config (0x00 is not present on IXP42X):
11  *
12  * logical port 0x00 0x10 0x20
13  * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
14  * physical PortId 2 0 1
15  * TX queue 23 24 25
16  * RX-free queue 26 27 28
17  * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
18  *
19  *
20  * Queue entries:
21  * bits 0 -> 1 - NPE ID (RX and TX-done)
22  * bits 0 -> 2 - priority (TX, per 802.1D)
23  * bits 3 -> 4 - port ID (user-set?)
24  * bits 5 -> 31 - physical descriptor address
25  */
26 
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/dmapool.h>
30 #include <linux/etherdevice.h>
31 #include <linux/io.h>
32 #include <linux/kernel.h>
33 #include <linux/net_tstamp.h>
34 #include <linux/phy.h>
35 #include <linux/platform_device.h>
36 #include <linux/ptp_classify.h>
37 #include <linux/slab.h>
38 #include <linux/module.h>
39 #include <mach/ixp46x_ts.h>
40 #include <mach/npe.h>
41 #include <mach/qmgr.h>
42 
43 #define DEBUG_DESC 0
44 #define DEBUG_RX 0
45 #define DEBUG_TX 0
46 #define DEBUG_PKT_BYTES 0
47 #define DEBUG_MDIO 0
48 #define DEBUG_CLOSE 0
49 
50 #define DRV_NAME "ixp4xx_eth"
51 
52 #define MAX_NPES 3
53 
54 #define RX_DESCS 64 /* also length of all RX queues */
55 #define TX_DESCS 16 /* also length of all TX queues */
56 #define TXDONE_QUEUE_LEN 64 /* dwords */
57 
58 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
59 #define REGS_SIZE 0x1000
60 #define MAX_MRU 1536 /* 0x600 */
61 #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
62 
63 #define NAPI_WEIGHT 16
64 #define MDIO_INTERVAL (3 * HZ)
65 #define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
66 #define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
67 
68 #define NPE_ID(port_id) ((port_id) >> 4)
69 #define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
70 #define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
71 #define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
72 #define TXDONE_QUEUE 31
73 
74 #define PTP_SLAVE_MODE 1
75 #define PTP_MASTER_MODE 2
76 #define PORT2CHANNEL(p) NPE_ID(p->id)
77 
78 /* TX Control Registers */
79 #define TX_CNTRL0_TX_EN 0x01
80 #define TX_CNTRL0_HALFDUPLEX 0x02
81 #define TX_CNTRL0_RETRY 0x04
82 #define TX_CNTRL0_PAD_EN 0x08
83 #define TX_CNTRL0_APPEND_FCS 0x10
84 #define TX_CNTRL0_2DEFER 0x20
85 #define TX_CNTRL0_RMII 0x40 /* reduced MII */
86 #define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
87 
88 /* RX Control Registers */
89 #define RX_CNTRL0_RX_EN 0x01
90 #define RX_CNTRL0_PADSTRIP_EN 0x02
91 #define RX_CNTRL0_SEND_FCS 0x04
92 #define RX_CNTRL0_PAUSE_EN 0x08
93 #define RX_CNTRL0_LOOP_EN 0x10
94 #define RX_CNTRL0_ADDR_FLTR_EN 0x20
95 #define RX_CNTRL0_RX_RUNT_EN 0x40
96 #define RX_CNTRL0_BCAST_DIS 0x80
97 #define RX_CNTRL1_DEFER_EN 0x01
98 
99 /* Core Control Register */
100 #define CORE_RESET 0x01
101 #define CORE_RX_FIFO_FLUSH 0x02
102 #define CORE_TX_FIFO_FLUSH 0x04
103 #define CORE_SEND_JAM 0x08
104 #define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
105 
106 #define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
107  TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
108  TX_CNTRL0_2DEFER)
109 #define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
110 #define DEFAULT_CORE_CNTRL CORE_MDC_EN
111 
112 
113 /* NPE message codes */
114 #define NPE_GETSTATUS 0x00
115 #define NPE_EDB_SETPORTADDRESS 0x01
116 #define NPE_EDB_GETMACADDRESSDATABASE 0x02
117 #define NPE_EDB_SETMACADDRESSSDATABASE 0x03
118 #define NPE_GETSTATS 0x04
119 #define NPE_RESETSTATS 0x05
120 #define NPE_SETMAXFRAMELENGTHS 0x06
121 #define NPE_VLAN_SETRXTAGMODE 0x07
122 #define NPE_VLAN_SETDEFAULTRXVID 0x08
123 #define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
124 #define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
125 #define NPE_VLAN_SETRXQOSENTRY 0x0B
126 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
127 #define NPE_STP_SETBLOCKINGSTATE 0x0D
128 #define NPE_FW_SETFIREWALLMODE 0x0E
129 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
130 #define NPE_PC_SETAPMACTABLE 0x11
131 #define NPE_SETLOOPBACK_MODE 0x12
132 #define NPE_PC_SETBSSIDTABLE 0x13
133 #define NPE_ADDRESS_FILTER_CONFIG 0x14
134 #define NPE_APPENDFCSCONFIG 0x15
135 #define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
136 #define NPE_MAC_RECOVERY_START 0x17
137 
138 
139 #ifdef __ARMEB__
140 typedef struct sk_buff buffer_t;
141 #define free_buffer dev_kfree_skb
142 #define free_buffer_irq dev_kfree_skb_irq
143 #else
144 typedef void buffer_t;
145 #define free_buffer kfree
146 #define free_buffer_irq kfree
147 #endif
148 
149 struct eth_regs {
150  u32 tx_control[2], __res1[2]; /* 000 */
151  u32 rx_control[2], __res2[2]; /* 010 */
152  u32 random_seed, __res3[3]; /* 020 */
153  u32 partial_empty_threshold, __res4; /* 030 */
154  u32 partial_full_threshold, __res5; /* 038 */
155  u32 tx_start_bytes, __res6[3]; /* 040 */
156  u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
157  u32 tx_2part_deferral[2], __res8[2]; /* 060 */
158  u32 slot_time, __res9[3]; /* 070 */
159  u32 mdio_command[4]; /* 080 */
160  u32 mdio_status[4]; /* 090 */
161  u32 mcast_mask[6], __res10[2]; /* 0A0 */
162  u32 mcast_addr[6], __res11[2]; /* 0C0 */
163  u32 int_clock_threshold, __res12[3]; /* 0E0 */
164  u32 hw_addr[6], __res13[61]; /* 0F0 */
165  u32 core_control; /* 1FC */
166 };
167 
168 struct port {
169  struct resource *mem_res;
170  struct eth_regs __iomem *regs;
171  struct npe *npe;
172  struct net_device *netdev;
173  struct napi_struct napi;
174  struct phy_device *phydev;
175  struct eth_plat_info *plat;
176  buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
177  struct desc *desc_tab; /* coherent */
178  u32 desc_tab_phys;
179  int id; /* logical port ID */
180  int speed, duplex;
181  u8 firmware[4];
182  int hwts_tx_en;
183  int hwts_rx_en;
184 };
185 
186 /* NPE message structure */
187 struct msg {
188 #ifdef __ARMEB__
189  u8 cmd, eth_id, byte2, byte3;
190  u8 byte4, byte5, byte6, byte7;
191 #else
192  u8 byte3, byte2, eth_id, cmd;
193  u8 byte7, byte6, byte5, byte4;
194 #endif
195 };
196 
197 /* Ethernet packet descriptor */
198 struct desc {
199  u32 next; /* pointer to next buffer, unused */
200 
201 #ifdef __ARMEB__
202  u16 buf_len; /* buffer length */
203  u16 pkt_len; /* packet length */
204  u32 data; /* pointer to data buffer in RAM */
205  u8 dest_id;
206  u8 src_id;
207  u16 flags;
208  u8 qos;
209  u8 padlen;
210  u16 vlan_tci;
211 #else
212  u16 pkt_len; /* packet length */
213  u16 buf_len; /* buffer length */
214  u32 data; /* pointer to data buffer in RAM */
215  u16 flags;
216  u8 src_id;
217  u8 dest_id;
218  u16 vlan_tci;
219  u8 padlen;
220  u8 qos;
221 #endif
222 
223 #ifdef __ARMEB__
224  u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
225  u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
226  u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
227 #else
228  u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
229  u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
230  u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
231 #endif
232 };
233 
234 
235 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
236  (n) * sizeof(struct desc))
237 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
238 
239 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
240  ((n) + RX_DESCS) * sizeof(struct desc))
241 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
242 
243 #ifndef __ARMEB__
244 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
245 {
246  int i;
247  for (i = 0; i < cnt; i++)
248  dest[i] = swab32(src[i]);
249 }
250 #endif
251 
252 static spinlock_t mdio_lock;
253 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
254 static struct mii_bus *mdio_bus;
255 static int ports_open;
256 static struct port *npe_port_tab[MAX_NPES];
257 static struct dma_pool *dma_pool;
258 
259 static struct sock_filter ptp_filter[] = {
260  PTP_FILTER
261 };
262 
263 static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
264 {
265  u8 *data = skb->data;
266  unsigned int offset;
267  u16 *hi, *id;
268  u32 lo;
269 
270  if (sk_run_filter(skb, ptp_filter) != PTP_CLASS_V1_IPV4)
271  return 0;
272 
273  offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
274 
275  if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
276  return 0;
277 
278  hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
279  id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
280 
281  memcpy(&lo, &hi[1], sizeof(lo));
282 
283  return (uid_hi == ntohs(*hi) &&
284  uid_lo == ntohl(lo) &&
285  seqid == ntohs(*id));
286 }
287 
288 static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb)
289 {
290  struct skb_shared_hwtstamps *shhwtstamps;
291  struct ixp46x_ts_regs *regs;
292  u64 ns;
293  u32 ch, hi, lo, val;
294  u16 uid, seq;
295 
296  if (!port->hwts_rx_en)
297  return;
298 
299  ch = PORT2CHANNEL(port);
300 
301  regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
302 
303  val = __raw_readl(&regs->channel[ch].ch_event);
304 
305  if (!(val & RX_SNAPSHOT_LOCKED))
306  return;
307 
308  lo = __raw_readl(&regs->channel[ch].src_uuid_lo);
309  hi = __raw_readl(&regs->channel[ch].src_uuid_hi);
310 
311  uid = hi & 0xffff;
312  seq = (hi >> 16) & 0xffff;
313 
314  if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
315  goto out;
316 
317  lo = __raw_readl(&regs->channel[ch].rx_snap_lo);
318  hi = __raw_readl(&regs->channel[ch].rx_snap_hi);
319  ns = ((u64) hi) << 32;
320  ns |= lo;
321  ns <<= TICKS_NS_SHIFT;
322 
323  shhwtstamps = skb_hwtstamps(skb);
324  memset(shhwtstamps, 0, sizeof(*shhwtstamps));
325  shhwtstamps->hwtstamp = ns_to_ktime(ns);
326 out:
327  __raw_writel(RX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);
328 }
329 
330 static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb)
331 {
332  struct skb_shared_hwtstamps shhwtstamps;
333  struct ixp46x_ts_regs *regs;
334  struct skb_shared_info *shtx;
335  u64 ns;
336  u32 ch, cnt, hi, lo, val;
337 
338  shtx = skb_shinfo(skb);
339  if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en))
340  shtx->tx_flags |= SKBTX_IN_PROGRESS;
341  else
342  return;
343 
344  ch = PORT2CHANNEL(port);
345 
346  regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
347 
348  /*
349  * This really stinks, but we have to poll for the Tx time stamp.
350  * Usually, the time stamp is ready after 4 to 6 microseconds.
351  */
352  for (cnt = 0; cnt < 100; cnt++) {
353  val = __raw_readl(&regs->channel[ch].ch_event);
354  if (val & TX_SNAPSHOT_LOCKED)
355  break;
356  udelay(1);
357  }
358  if (!(val & TX_SNAPSHOT_LOCKED)) {
359  shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
360  return;
361  }
362 
363  lo = __raw_readl(&regs->channel[ch].tx_snap_lo);
364  hi = __raw_readl(&regs->channel[ch].tx_snap_hi);
365  ns = ((u64) hi) << 32;
366  ns |= lo;
367  ns <<= TICKS_NS_SHIFT;
368 
369  memset(&shhwtstamps, 0, sizeof(shhwtstamps));
370  shhwtstamps.hwtstamp = ns_to_ktime(ns);
371  skb_tstamp_tx(skb, &shhwtstamps);
372 
373  __raw_writel(TX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);
374 }
375 
376 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
377 {
378  struct hwtstamp_config cfg;
379  struct ixp46x_ts_regs *regs;
380  struct port *port = netdev_priv(netdev);
381  int ch;
382 
383  if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
384  return -EFAULT;
385 
386  if (cfg.flags) /* reserved for future extensions */
387  return -EINVAL;
388 
389  ch = PORT2CHANNEL(port);
390  regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
391 
392  switch (cfg.tx_type) {
393  case HWTSTAMP_TX_OFF:
394  port->hwts_tx_en = 0;
395  break;
396  case HWTSTAMP_TX_ON:
397  port->hwts_tx_en = 1;
398  break;
399  default:
400  return -ERANGE;
401  }
402 
403  switch (cfg.rx_filter) {
404  case HWTSTAMP_FILTER_NONE:
405  port->hwts_rx_en = 0;
406  break;
407  case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
408  port->hwts_rx_en = PTP_SLAVE_MODE;
409  __raw_writel(0, &regs->channel[ch].ch_control);
410  break;
411  case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
412  port->hwts_rx_en = PTP_MASTER_MODE;
413  __raw_writel(MASTER_MODE, &regs->channel[ch].ch_control);
414  break;
415  default:
416  return -ERANGE;
417  }
418 
419  /* Clear out any old time stamps. */
420  __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
421  &regs->channel[ch].ch_event);
422 
423  return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
424 }
425 
426 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
427  int write, u16 cmd)
428 {
429  int cycles = 0;
430 
431  if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
432  printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
433  return -1;
434  }
435 
436  if (write) {
437  __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
438  __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
439  }
440  __raw_writel(((phy_id << 5) | location) & 0xFF,
441  &mdio_regs->mdio_command[2]);
442  __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
443  &mdio_regs->mdio_command[3]);
444 
445  while ((cycles < MAX_MDIO_RETRIES) &&
446  (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
447  udelay(1);
448  cycles++;
449  }
450 
451  if (cycles == MAX_MDIO_RETRIES) {
452  printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
453  phy_id);
454  return -1;
455  }
456 
457 #if DEBUG_MDIO
458  printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
459  phy_id, write ? "write" : "read", cycles);
460 #endif
461 
462  if (write)
463  return 0;
464 
465  if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
466 #if DEBUG_MDIO
467  printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
468  phy_id);
469 #endif
470  return 0xFFFF; /* don't return error */
471  }
472 
473  return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
474  ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
475 }
476 
477 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
478 {
479  unsigned long flags;
480  int ret;
481 
482  spin_lock_irqsave(&mdio_lock, flags);
483  ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
484  spin_unlock_irqrestore(&mdio_lock, flags);
485 #if DEBUG_MDIO
486  printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
487  phy_id, location, ret);
488 #endif
489  return ret;
490 }
491 
492 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
493  u16 val)
494 {
495  unsigned long flags;
496  int ret;
497 
498  spin_lock_irqsave(&mdio_lock, flags);
499  ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
500  spin_unlock_irqrestore(&mdio_lock, flags);
501 #if DEBUG_MDIO
502  printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n",
503  bus->name, phy_id, location, val, ret);
504 #endif
505  return ret;
506 }
507 
508 static int ixp4xx_mdio_register(void)
509 {
510  int err;
511 
512  if (!(mdio_bus = mdiobus_alloc()))
513  return -ENOMEM;
514 
515  if (cpu_is_ixp43x()) {
516  /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
517  if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH))
518  return -ENODEV;
519  mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
520  } else {
521  /* All MII PHY accesses use NPE-B Ethernet registers */
522  if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
523  return -ENODEV;
524  mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
525  }
526 
527  __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
528  spin_lock_init(&mdio_lock);
529  mdio_bus->name = "IXP4xx MII Bus";
530  mdio_bus->read = &ixp4xx_mdio_read;
531  mdio_bus->write = &ixp4xx_mdio_write;
532  snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0");
533 
534  if ((err = mdiobus_register(mdio_bus)))
535  mdiobus_free(mdio_bus);
536  return err;
537 }
538 
539 static void ixp4xx_mdio_remove(void)
540 {
541  mdiobus_unregister(mdio_bus);
542  mdiobus_free(mdio_bus);
543 }
544 
545 
546 static void ixp4xx_adjust_link(struct net_device *dev)
547 {
548  struct port *port = netdev_priv(dev);
549  struct phy_device *phydev = port->phydev;
550 
551  if (!phydev->link) {
552  if (port->speed) {
553  port->speed = 0;
554  printk(KERN_INFO "%s: link down\n", dev->name);
555  }
556  return;
557  }
558 
559  if (port->speed == phydev->speed && port->duplex == phydev->duplex)
560  return;
561 
562  port->speed = phydev->speed;
563  port->duplex = phydev->duplex;
564 
565  if (port->duplex)
566  __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
567  &port->regs->tx_control[0]);
568  else
569  __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
570  &port->regs->tx_control[0]);
571 
572  printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
573  dev->name, port->speed, port->duplex ? "full" : "half");
574 }
575 
576 
577 static inline void debug_pkt(struct net_device *dev, const char *func,
578  u8 *data, int len)
579 {
580 #if DEBUG_PKT_BYTES
581  int i;
582 
583  printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
584  for (i = 0; i < len; i++) {
585  if (i >= DEBUG_PKT_BYTES)
586  break;
587  printk("%s%02X",
588  ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
589  data[i]);
590  }
591  printk("\n");
592 #endif
593 }
594 
595 
596 static inline void debug_desc(u32 phys, struct desc *desc)
597 {
598 #if DEBUG_DESC
599  printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
600  " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
601  phys, desc->next, desc->buf_len, desc->pkt_len,
602  desc->data, desc->dest_id, desc->src_id, desc->flags,
603  desc->qos, desc->padlen, desc->vlan_tci,
604  desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
605  desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
606  desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
607  desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
608 #endif
609 }
610 
611 static inline int queue_get_desc(unsigned int queue, struct port *port,
612  int is_tx)
613 {
614  u32 phys, tab_phys, n_desc;
615  struct desc *tab;
616 
617  if (!(phys = qmgr_get_entry(queue)))
618  return -1;
619 
620  phys &= ~0x1F; /* mask out non-address bits */
621  tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
622  tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
623  n_desc = (phys - tab_phys) / sizeof(struct desc);
624  BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
625  debug_desc(phys, &tab[n_desc]);
626  BUG_ON(tab[n_desc].next);
627  return n_desc;
628 }
629 
630 static inline void queue_put_desc(unsigned int queue, u32 phys,
631  struct desc *desc)
632 {
633  debug_desc(phys, desc);
634  BUG_ON(phys & 0x1F);
635  qmgr_put_entry(queue, phys);
636  /* Don't check for queue overflow here, we've allocated sufficient
637  length and queues >= 32 don't support this check anyway. */
638 }
639 
640 
641 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
642 {
643 #ifdef __ARMEB__
644  dma_unmap_single(&port->netdev->dev, desc->data,
645  desc->buf_len, DMA_TO_DEVICE);
646 #else
647  dma_unmap_single(&port->netdev->dev, desc->data & ~3,
648  ALIGN((desc->data & 3) + desc->buf_len, 4),
649  DMA_TO_DEVICE);
650 #endif
651 }
652 
653 
654 static void eth_rx_irq(void *pdev)
655 {
656  struct net_device *dev = pdev;
657  struct port *port = netdev_priv(dev);
658 
659 #if DEBUG_RX
660  printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
661 #endif
662  qmgr_disable_irq(port->plat->rxq);
663  napi_schedule(&port->napi);
664 }
665 
666 static int eth_poll(struct napi_struct *napi, int budget)
667 {
668  struct port *port = container_of(napi, struct port, napi);
669  struct net_device *dev = port->netdev;
670  unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
671  int received = 0;
672 
673 #if DEBUG_RX
674  printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
675 #endif
676 
677  while (received < budget) {
678  struct sk_buff *skb;
679  struct desc *desc;
680  int n;
681 #ifdef __ARMEB__
682  struct sk_buff *temp;
683  u32 phys;
684 #endif
685 
686  if ((n = queue_get_desc(rxq, port, 0)) < 0) {
687 #if DEBUG_RX
688  printk(KERN_DEBUG "%s: eth_poll napi_complete\n",
689  dev->name);
690 #endif
691  napi_complete(napi);
692  qmgr_enable_irq(rxq);
693  if (!qmgr_stat_below_low_watermark(rxq) &&
694  napi_reschedule(napi)) { /* not empty again */
695 #if DEBUG_RX
696  printk(KERN_DEBUG "%s: eth_poll"
697  " napi_reschedule successed\n",
698  dev->name);
699 #endif
700  qmgr_disable_irq(rxq);
701  continue;
702  }
703 #if DEBUG_RX
704  printk(KERN_DEBUG "%s: eth_poll all done\n",
705  dev->name);
706 #endif
707  return received; /* all work done */
708  }
709 
710  desc = rx_desc_ptr(port, n);
711 
712 #ifdef __ARMEB__
713  if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
714  phys = dma_map_single(&dev->dev, skb->data,
715  RX_BUFF_SIZE, DMA_FROM_DEVICE);
716  if (dma_mapping_error(&dev->dev, phys)) {
717  dev_kfree_skb(skb);
718  skb = NULL;
719  }
720  }
721 #else
722  skb = netdev_alloc_skb(dev,
723  ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
724 #endif
725 
726  if (!skb) {
727  dev->stats.rx_dropped++;
728  /* put the desc back on RX-ready queue */
729  desc->buf_len = MAX_MRU;
730  desc->pkt_len = 0;
731  queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
732  continue;
733  }
734 
735  /* process received frame */
736 #ifdef __ARMEB__
737  temp = skb;
738  skb = port->rx_buff_tab[n];
739  dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
740  RX_BUFF_SIZE, DMA_FROM_DEVICE);
741 #else
742  dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN,
743  RX_BUFF_SIZE, DMA_FROM_DEVICE);
744  memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
745  ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
746 #endif
747  skb_reserve(skb, NET_IP_ALIGN);
748  skb_put(skb, desc->pkt_len);
749 
750  debug_pkt(dev, "eth_poll", skb->data, skb->len);
751 
752  ixp_rx_timestamp(port, skb);
753  skb->protocol = eth_type_trans(skb, dev);
754  dev->stats.rx_packets++;
755  dev->stats.rx_bytes += skb->len;
756  netif_receive_skb(skb);
757 
758  /* put the new buffer on RX-free queue */
759 #ifdef __ARMEB__
760  port->rx_buff_tab[n] = temp;
761  desc->data = phys + NET_IP_ALIGN;
762 #endif
763  desc->buf_len = MAX_MRU;
764  desc->pkt_len = 0;
765  queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
766  received++;
767  }
768 
769 #if DEBUG_RX
770  printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
771 #endif
772  return received; /* not all work done */
773 }
774 
775 
776 static void eth_txdone_irq(void *unused)
777 {
778  u32 phys;
779 
780 #if DEBUG_TX
781  printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
782 #endif
783  while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {
784  u32 npe_id, n_desc;
785  struct port *port;
786  struct desc *desc;
787  int start;
788 
789  npe_id = phys & 3;
790  BUG_ON(npe_id >= MAX_NPES);
791  port = npe_port_tab[npe_id];
792  BUG_ON(!port);
793  phys &= ~0x1F; /* mask out non-address bits */
794  n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
795  BUG_ON(n_desc >= TX_DESCS);
796  desc = tx_desc_ptr(port, n_desc);
797  debug_desc(phys, desc);
798 
799  if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
800  port->netdev->stats.tx_packets++;
801  port->netdev->stats.tx_bytes += desc->pkt_len;
802 
803  dma_unmap_tx(port, desc);
804 #if DEBUG_TX
805  printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
806  port->netdev->name, port->tx_buff_tab[n_desc]);
807 #endif
808  free_buffer_irq(port->tx_buff_tab[n_desc]);
809  port->tx_buff_tab[n_desc] = NULL;
810  }
811 
812  start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
813  queue_put_desc(port->plat->txreadyq, phys, desc);
814  if (start) { /* TX-ready queue was empty */
815 #if DEBUG_TX
816  printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
817  port->netdev->name);
818 #endif
819  netif_wake_queue(port->netdev);
820  }
821  }
822 }
823 
824 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
825 {
826  struct port *port = netdev_priv(dev);
827  unsigned int txreadyq = port->plat->txreadyq;
828  int len, offset, bytes, n;
829  void *mem;
830  u32 phys;
831  struct desc *desc;
832 
833 #if DEBUG_TX
834  printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
835 #endif
836 
837  if (unlikely(skb->len > MAX_MRU)) {
838  dev_kfree_skb(skb);
839  dev->stats.tx_errors++;
840  return NETDEV_TX_OK;
841  }
842 
843  debug_pkt(dev, "eth_xmit", skb->data, skb->len);
844 
845  len = skb->len;
846 #ifdef __ARMEB__
847  offset = 0; /* no need to keep alignment */
848  bytes = len;
849  mem = skb->data;
850 #else
851  offset = (int)skb->data & 3; /* keep 32-bit alignment */
852  bytes = ALIGN(offset + len, 4);
853  if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
854  dev_kfree_skb(skb);
855  dev->stats.tx_dropped++;
856  return NETDEV_TX_OK;
857  }
858  memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
859 #endif
860 
861  phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
862  if (dma_mapping_error(&dev->dev, phys)) {
863  dev_kfree_skb(skb);
864 #ifndef __ARMEB__
865  kfree(mem);
866 #endif
867  dev->stats.tx_dropped++;
868  return NETDEV_TX_OK;
869  }
870 
871  n = queue_get_desc(txreadyq, port, 1);
872  BUG_ON(n < 0);
873  desc = tx_desc_ptr(port, n);
874 
875 #ifdef __ARMEB__
876  port->tx_buff_tab[n] = skb;
877 #else
878  port->tx_buff_tab[n] = mem;
879 #endif
880  desc->data = phys + offset;
881  desc->buf_len = desc->pkt_len = len;
882 
883  /* NPE firmware pads short frames with zeros internally */
884  wmb();
885  queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
886 
887  if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
888 #if DEBUG_TX
889  printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
890 #endif
891  netif_stop_queue(dev);
892  /* we could miss TX ready interrupt */
893  /* really empty in fact */
894  if (!qmgr_stat_below_low_watermark(txreadyq)) {
895 #if DEBUG_TX
896  printk(KERN_DEBUG "%s: eth_xmit ready again\n",
897  dev->name);
898 #endif
899  netif_wake_queue(dev);
900  }
901  }
902 
903 #if DEBUG_TX
904  printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
905 #endif
906 
907  ixp_tx_timestamp(port, skb);
908  skb_tx_timestamp(skb);
909 
910 #ifndef __ARMEB__
911  dev_kfree_skb(skb);
912 #endif
913  return NETDEV_TX_OK;
914 }
915 
916 
917 static void eth_set_mcast_list(struct net_device *dev)
918 {
919  struct port *port = netdev_priv(dev);
920  struct netdev_hw_addr *ha;
921  u8 diffs[ETH_ALEN], *addr;
922  int i;
923  static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
924 
925  if (dev->flags & IFF_ALLMULTI) {
926  for (i = 0; i < ETH_ALEN; i++) {
927  __raw_writel(allmulti[i], &port->regs->mcast_addr[i]);
928  __raw_writel(allmulti[i], &port->regs->mcast_mask[i]);
929  }
930  __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
931  &port->regs->rx_control[0]);
932  return;
933  }
934 
935  if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) {
936  __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
937  &port->regs->rx_control[0]);
938  return;
939  }
940 
941  memset(diffs, 0, ETH_ALEN);
942 
943  addr = NULL;
944  netdev_for_each_mc_addr(ha, dev) {
945  if (!addr)
946  addr = ha->addr; /* first MAC address */
947  for (i = 0; i < ETH_ALEN; i++)
948  diffs[i] |= addr[i] ^ ha->addr[i];
949  }
950 
951  for (i = 0; i < ETH_ALEN; i++) {
952  __raw_writel(addr[i], &port->regs->mcast_addr[i]);
953  __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
954  }
955 
956  __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
957  &port->regs->rx_control[0]);
958 }
959 
960 
961 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
962 {
963  struct port *port = netdev_priv(dev);
964 
965  if (!netif_running(dev))
966  return -EINVAL;
967 
968  if (cpu_is_ixp46x() && cmd == SIOCSHWTSTAMP)
969  return hwtstamp_ioctl(dev, req, cmd);
970 
971  return phy_mii_ioctl(port->phydev, req, cmd);
972 }
973 
974 /* ethtool support */
975 
976 static void ixp4xx_get_drvinfo(struct net_device *dev,
977  struct ethtool_drvinfo *info)
978 {
979  struct port *port = netdev_priv(dev);
980  strcpy(info->driver, DRV_NAME);
981  snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",
982  port->firmware[0], port->firmware[1],
983  port->firmware[2], port->firmware[3]);
984  strcpy(info->bus_info, "internal");
985 }
986 
987 static int ixp4xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
988 {
989  struct port *port = netdev_priv(dev);
990  return phy_ethtool_gset(port->phydev, cmd);
991 }
992 
993 static int ixp4xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
994 {
995  struct port *port = netdev_priv(dev);
996  return phy_ethtool_sset(port->phydev, cmd);
997 }
998 
999 static int ixp4xx_nway_reset(struct net_device *dev)
1000 {
1001  struct port *port = netdev_priv(dev);
1002  return phy_start_aneg(port->phydev);
1003 }
1004 
1005 int ixp46x_phc_index = -1;
1006 EXPORT_SYMBOL_GPL(ixp46x_phc_index);
1007 
1008 static int ixp4xx_get_ts_info(struct net_device *dev,
1009  struct ethtool_ts_info *info)
1010 {
1011  if (!cpu_is_ixp46x()) {
1012  info->so_timestamping =
1013  SOF_TIMESTAMPING_TX_SOFTWARE |
1014  SOF_TIMESTAMPING_RX_SOFTWARE |
1015  SOF_TIMESTAMPING_SOFTWARE;
1016  info->phc_index = -1;
1017  return 0;
1018  }
1019  info->so_timestamping =
1020  SOF_TIMESTAMPING_TX_HARDWARE |
1021  SOF_TIMESTAMPING_RX_HARDWARE |
1022  SOF_TIMESTAMPING_RAW_HARDWARE;
1023  info->phc_index = ixp46x_phc_index;
1024  info->tx_types =
1025  (1 << HWTSTAMP_TX_OFF) |
1026  (1 << HWTSTAMP_TX_ON);
1027  info->rx_filters =
1028  (1 << HWTSTAMP_FILTER_NONE) |
1029  (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1030  (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ);
1031  return 0;
1032 }
1033 
1034 static const struct ethtool_ops ixp4xx_ethtool_ops = {
1035  .get_drvinfo = ixp4xx_get_drvinfo,
1036  .get_settings = ixp4xx_get_settings,
1037  .set_settings = ixp4xx_set_settings,
1038  .nway_reset = ixp4xx_nway_reset,
1039  .get_link = ethtool_op_get_link,
1040  .get_ts_info = ixp4xx_get_ts_info,
1041 };
1042 
1043 
1044 static int request_queues(struct port *port)
1045 {
1046  int err;
1047 
1048  err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,
1049  "%s:RX-free", port->netdev->name);
1050  if (err)
1051  return err;
1052 
1053  err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,
1054  "%s:RX", port->netdev->name);
1055  if (err)
1056  goto rel_rxfree;
1057 
1058  err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,
1059  "%s:TX", port->netdev->name);
1060  if (err)
1061  goto rel_rx;
1062 
1063  err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
1064  "%s:TX-ready", port->netdev->name);
1065  if (err)
1066  goto rel_tx;
1067 
1068  /* TX-done queue handles skbs sent out by the NPEs */
1069  if (!ports_open) {
1070  err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
1071  "%s:TX-done", DRV_NAME);
1072  if (err)
1073  goto rel_txready;
1074  }
1075  return 0;
1076 
1077 rel_txready:
1078  qmgr_release_queue(port->plat->txreadyq);
1079 rel_tx:
1080  qmgr_release_queue(TX_QUEUE(port->id));
1081 rel_rx:
1082  qmgr_release_queue(port->plat->rxq);
1083 rel_rxfree:
1084  qmgr_release_queue(RXFREE_QUEUE(port->id));
1085  printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1086  port->netdev->name);
1087  return err;
1088 }
1089 
1090 static void release_queues(struct port *port)
1091 {
1092  qmgr_release_queue(RXFREE_QUEUE(port->id));
1093  qmgr_release_queue(port->plat->rxq);
1094  qmgr_release_queue(TX_QUEUE(port->id));
1095  qmgr_release_queue(port->plat->txreadyq);
1096 
1097  if (!ports_open)
1098  qmgr_release_queue(TXDONE_QUEUE);
1099 }
1100 
1101 static int init_queues(struct port *port)
1102 {
1103  int i;
1104 
1105  if (!ports_open) {
1106  dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
1107  POOL_ALLOC_SIZE, 32, 0);
1108  if (!dma_pool)
1109  return -ENOMEM;
1110  }
1111 
1112  if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
1113  &port->desc_tab_phys)))
1114  return -ENOMEM;
1115  memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
1116  memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
1117  memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
1118 
1119  /* Setup RX buffers */
1120  for (i = 0; i < RX_DESCS; i++) {
1121  struct desc *desc = rx_desc_ptr(port, i);
1122  buffer_t *buff; /* skb or kmalloc()ated memory */
1123  void *data;
1124 #ifdef __ARMEB__
1125  if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
1126  return -ENOMEM;
1127  data = buff->data;
1128 #else
1129  if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
1130  return -ENOMEM;
1131  data = buff;
1132 #endif
1133  desc->buf_len = MAX_MRU;
1134  desc->data = dma_map_single(&port->netdev->dev, data,
1135  RX_BUFF_SIZE, DMA_FROM_DEVICE);
1136  if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1137  free_buffer(buff);
1138  return -EIO;
1139  }
1140  desc->data += NET_IP_ALIGN;
1141  port->rx_buff_tab[i] = buff;
1142  }
1143 
1144  return 0;
1145 }
1146 
1147 static void destroy_queues(struct port *port)
1148 {
1149  int i;
1150 
1151  if (port->desc_tab) {
1152  for (i = 0; i < RX_DESCS; i++) {
1153  struct desc *desc = rx_desc_ptr(port, i);
1154  buffer_t *buff = port->rx_buff_tab[i];
1155  if (buff) {
1156  dma_unmap_single(&port->netdev->dev,
1157  desc->data - NET_IP_ALIGN,
1158  RX_BUFF_SIZE, DMA_FROM_DEVICE);
1159  free_buffer(buff);
1160  }
1161  }
1162  for (i = 0; i < TX_DESCS; i++) {
1163  struct desc *desc = tx_desc_ptr(port, i);
1164  buffer_t *buff = port->tx_buff_tab[i];
1165  if (buff) {
1166  dma_unmap_tx(port, desc);
1167  free_buffer(buff);
1168  }
1169  }
1170  dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1171  port->desc_tab = NULL;
1172  }
1173 
1174  if (!ports_open && dma_pool) {
1175  dma_pool_destroy(dma_pool);
1176  dma_pool = NULL;
1177  }
1178 }
1179 
1180 static int eth_open(struct net_device *dev)
1181 {
1182  struct port *port = netdev_priv(dev);
1183  struct npe *npe = port->npe;
1184  struct msg msg;
1185  int i, err;
1186 
1187  if (!npe_running(npe)) {
1188  err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
1189  if (err)
1190  return err;
1191 
1192  if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
1193  printk(KERN_ERR "%s: %s not responding\n", dev->name,
1194  npe_name(npe));
1195  return -EIO;
1196  }
1197  port->firmware[0] = msg.byte4;
1198  port->firmware[1] = msg.byte5;
1199  port->firmware[2] = msg.byte6;
1200  port->firmware[3] = msg.byte7;
1201  }
1202 
1203  memset(&msg, 0, sizeof(msg));
1204  msg.cmd = NPE_VLAN_SETRXQOSENTRY;
1205  msg.eth_id = port->id;
1206  msg.byte5 = port->plat->rxq | 0x80;
1207  msg.byte7 = port->plat->rxq << 4;
1208  for (i = 0; i < 8; i++) {
1209  msg.byte3 = i;
1210  if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
1211  return -EIO;
1212  }
1213 
1214  msg.cmd = NPE_EDB_SETPORTADDRESS;
1215  msg.eth_id = PHYSICAL_ID(port->id);
1216  msg.byte2 = dev->dev_addr[0];
1217  msg.byte3 = dev->dev_addr[1];
1218  msg.byte4 = dev->dev_addr[2];
1219  msg.byte5 = dev->dev_addr[3];
1220  msg.byte6 = dev->dev_addr[4];
1221  msg.byte7 = dev->dev_addr[5];
1222  if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1223  return -EIO;
1224 
1225  memset(&msg, 0, sizeof(msg));
1226  msg.cmd = NPE_FW_SETFIREWALLMODE;
1227  msg.eth_id = port->id;
1228  if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1229  return -EIO;
1230 
1231  if ((err = request_queues(port)) != 0)
1232  return err;
1233 
1234  if ((err = init_queues(port)) != 0) {
1235  destroy_queues(port);
1236  release_queues(port);
1237  return err;
1238  }
1239 
1240  port->speed = 0; /* force "link up" message */
1241  phy_start(port->phydev);
1242 
1243  for (i = 0; i < ETH_ALEN; i++)
1244  __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1245  __raw_writel(0x08, &port->regs->random_seed);
1246  __raw_writel(0x12, &port->regs->partial_empty_threshold);
1247  __raw_writel(0x30, &port->regs->partial_full_threshold);
1248  __raw_writel(0x08, &port->regs->tx_start_bytes);
1249  __raw_writel(0x15, &port->regs->tx_deferral);
1250  __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1251  __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1252  __raw_writel(0x80, &port->regs->slot_time);
1253  __raw_writel(0x01, &port->regs->int_clock_threshold);
1254 
1255  /* Populate queues with buffers, no failure after this point */
1256  for (i = 0; i < TX_DESCS; i++)
1257  queue_put_desc(port->plat->txreadyq,
1258  tx_desc_phys(port, i), tx_desc_ptr(port, i));
1259 
1260  for (i = 0; i < RX_DESCS; i++)
1261  queue_put_desc(RXFREE_QUEUE(port->id),
1262  rx_desc_phys(port, i), rx_desc_ptr(port, i));
1263 
1264  __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1265  __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1266  __raw_writel(0, &port->regs->rx_control[1]);
1267  __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1268 
1269  napi_enable(&port->napi);
1270  eth_set_mcast_list(dev);
1271  netif_start_queue(dev);
1272 
1273  qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1274  eth_rx_irq, dev);
1275  if (!ports_open) {
1276  qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1277  eth_txdone_irq, NULL);
1278  qmgr_enable_irq(TXDONE_QUEUE);
1279  }
1280  ports_open++;
1281  /* we may already have RX data, enables IRQ */
1282  napi_schedule(&port->napi);
1283  return 0;
1284 }
1285 
1286 static int eth_close(struct net_device *dev)
1287 {
1288  struct port *port = netdev_priv(dev);
1289  struct msg msg;
1290  int buffs = RX_DESCS; /* allocated RX buffers */
1291  int i;
1292 
1293  ports_open--;
1294  qmgr_disable_irq(port->plat->rxq);
1295  napi_disable(&port->napi);
1296  netif_stop_queue(dev);
1297 
1298  while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1299  buffs--;
1300 
1301  memset(&msg, 0, sizeof(msg));
1302  msg.cmd = NPE_SETLOOPBACK_MODE;
1303  msg.eth_id = port->id;
1304  msg.byte3 = 1;
1305  if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1306  printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1307 
1308  i = 0;
1309  do { /* drain RX buffers */
1310  while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1311  buffs--;
1312  if (!buffs)
1313  break;
1314  if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1315  /* we have to inject some packet */
1316  struct desc *desc;
1317  u32 phys;
1318  int n = queue_get_desc(port->plat->txreadyq, port, 1);
1319  BUG_ON(n < 0);
1320  desc = tx_desc_ptr(port, n);
1321  phys = tx_desc_phys(port, n);
1322  desc->buf_len = desc->pkt_len = 1;
1323  wmb();
1324  queue_put_desc(TX_QUEUE(port->id), phys, desc);
1325  }
1326  udelay(1);
1327  } while (++i < MAX_CLOSE_WAIT);
1328 
1329  if (buffs)
1330  printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1331  " left in NPE\n", dev->name, buffs);
1332 #if DEBUG_CLOSE
1333  if (!buffs)
1334  printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1335 #endif
1336 
1337  buffs = TX_DESCS;
1338  while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1339  buffs--; /* cancel TX */
1340 
1341  i = 0;
1342  do {
1343  while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1344  buffs--;
1345  if (!buffs)
1346  break;
1347  } while (++i < MAX_CLOSE_WAIT);
1348 
1349  if (buffs)
1350  printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1351  "left in NPE\n", dev->name, buffs);
1352 #if DEBUG_CLOSE
1353  if (!buffs)
1354  printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1355 #endif
1356 
1357  msg.byte3 = 0;
1358  if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1359  printk(KERN_CRIT "%s: unable to disable loopback\n",
1360  dev->name);
1361 
1362  phy_stop(port->phydev);
1363 
1364  if (!ports_open)
1365  qmgr_disable_irq(TXDONE_QUEUE);
1366  destroy_queues(port);
1367  release_queues(port);
1368  return 0;
1369 }
1370 
1371 static const struct net_device_ops ixp4xx_netdev_ops = {
1372  .ndo_open = eth_open,
1373  .ndo_stop = eth_close,
1374  .ndo_start_xmit = eth_xmit,
1375  .ndo_set_rx_mode = eth_set_mcast_list,
1376  .ndo_do_ioctl = eth_ioctl,
1377  .ndo_change_mtu = eth_change_mtu,
1378  .ndo_set_mac_address = eth_mac_addr,
1379  .ndo_validate_addr = eth_validate_addr,
1380 };
1381 
1382 static int __devinit eth_init_one(struct platform_device *pdev)
1383 {
1384  struct port *port;
1385  struct net_device *dev;
1386  struct eth_plat_info *plat = pdev->dev.platform_data;
1387  u32 regs_phys;
1388  char phy_id[MII_BUS_ID_SIZE + 3];
1389  int err;
1390 
1391  if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
1392  pr_err("ixp4xx_eth: bad ptp filter\n");
1393  return -EINVAL;
1394  }
1395 
1396  if (!(dev = alloc_etherdev(sizeof(struct port))))
1397  return -ENOMEM;
1398 
1399  SET_NETDEV_DEV(dev, &pdev->dev);
1400  port = netdev_priv(dev);
1401  port->netdev = dev;
1402  port->id = pdev->id;
1403 
1404  switch (port->id) {
1405  case IXP4XX_ETH_NPEA:
1406  port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1407  regs_phys = IXP4XX_EthA_BASE_PHYS;
1408  break;
1409  case IXP4XX_ETH_NPEB:
1410  port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1411  regs_phys = IXP4XX_EthB_BASE_PHYS;
1412  break;
1413  case IXP4XX_ETH_NPEC:
1414  port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1415  regs_phys = IXP4XX_EthC_BASE_PHYS;
1416  break;
1417  default:
1418  err = -ENODEV;
1419  goto err_free;
1420  }
1421 
1422  dev->netdev_ops = &ixp4xx_netdev_ops;
1423  dev->ethtool_ops = &ixp4xx_ethtool_ops;
1424  dev->tx_queue_len = 100;
1425 
1426  netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
1427 
1428  if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1429  err = -EIO;
1430  goto err_free;
1431  }
1432 
1433  port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1434  if (!port->mem_res) {
1435  err = -EBUSY;
1436  goto err_npe_rel;
1437  }
1438 
1439  port->plat = plat;
1440  npe_port_tab[NPE_ID(port->id)] = port;
1441  memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1442 
1443  platform_set_drvdata(pdev, dev);
1444 
1445  __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1446  &port->regs->core_control);
1447  udelay(50);
1448  __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1449  udelay(50);
1450 
1451  snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
1452  mdio_bus->id, plat->phy);
1453  port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, 0,
1454  PHY_INTERFACE_MODE_MII);
1455  if (IS_ERR(port->phydev)) {
1456  err = PTR_ERR(port->phydev);
1457  goto err_free_mem;
1458  }
1459 
1460  port->phydev->irq = PHY_POLL;
1461 
1462  if ((err = register_netdev(dev)))
1463  goto err_phy_dis;
1464 
1465  printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1466  npe_name(port->npe));
1467 
1468  return 0;
1469 
1470 err_phy_dis:
1471  phy_disconnect(port->phydev);
1472 err_free_mem:
1473  npe_port_tab[NPE_ID(port->id)] = NULL;
1474  platform_set_drvdata(pdev, NULL);
1475  release_resource(port->mem_res);
1476 err_npe_rel:
1477  npe_release(port->npe);
1478 err_free:
1479  free_netdev(dev);
1480  return err;
1481 }
1482 
1483 static int __devexit eth_remove_one(struct platform_device *pdev)
1484 {
1485  struct net_device *dev = platform_get_drvdata(pdev);
1486  struct port *port = netdev_priv(dev);
1487 
1488  unregister_netdev(dev);
1489  phy_disconnect(port->phydev);
1490  npe_port_tab[NPE_ID(port->id)] = NULL;
1491  platform_set_drvdata(pdev, NULL);
1492  npe_release(port->npe);
1493  release_resource(port->mem_res);
1494  free_netdev(dev);
1495  return 0;
1496 }
1497 
1498 static struct platform_driver ixp4xx_eth_driver = {
1499  .driver.name = DRV_NAME,
1500  .probe = eth_init_one,
1501  .remove = eth_remove_one,
1502 };
1503 
1504 static int __init eth_init_module(void)
1505 {
1506  int err;
1507  if ((err = ixp4xx_mdio_register()))
1508  return err;
1509  return platform_driver_register(&ixp4xx_eth_driver);
1510 }
1511 
1512 static void __exit eth_cleanup_module(void)
1513 {
1514  platform_driver_unregister(&ixp4xx_eth_driver);
1515  ixp4xx_mdio_remove();
1516 }
1517 
1518 MODULE_AUTHOR("Krzysztof Halasa");
1519 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1520 MODULE_LICENSE("GPL v2");
1521 MODULE_ALIAS("platform:ixp4xx_eth");
1522 module_init(eth_init_module);
1523 module_exit(eth_cleanup_module);
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