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ni_pcidio.c
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1 /*
2  comedi/drivers/ni_pcidio.c
3  driver for National Instruments PCI-DIO-32HS
4 
5  COMEDI - Linux Control and Measurement Device Interface
6  Copyright (C) 1999,2002 David A. Schleef <[email protected]>
7 
8  This program is free software; you can redistribute it and/or modify
9  it under the terms of the GNU General Public License as published by
10  the Free Software Foundation; either version 2 of the License, or
11  (at your option) any later version.
12 
13  This program is distributed in the hope that it will be useful,
14  but WITHOUT ANY WARRANTY; without even the implied warranty of
15  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  GNU General Public License for more details.
17 
18  You should have received a copy of the GNU General Public License
19  along with this program; if not, write to the Free Software
20  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 
22 */
23 /*
24 Driver: ni_pcidio
25 Description: National Instruments PCI-DIO32HS, PCI-6533
26 Author: ds
27 Status: works
28 Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
29  [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
30  [National Instruments] PCI-6534 (pci-6534)
31 Updated: Mon, 09 Jan 2012 14:27:23 +0000
32 
33 The DIO32HS board appears as one subdevice, with 32 channels.
34 Each channel is individually I/O configurable. The channel order
35 is 0=A0, 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only
36 supports simple digital I/O; no handshaking is supported.
37 
38 DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
39 
40 The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
41 scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
42 scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
43 trailing edge.
44 
45 This driver could be easily modified to support AT-MIO32HS and
46 AT-MIO96.
47 
48 The PCI-6534 requires a firmware upload after power-up to work, the
49 firmware data and instructions for loading it with comedi_config
50 it are contained in the
51 comedi_nonfree_firmware tarball available from http://www.comedi.org
52 */
53 
54 #define USE_DMA
55 /* #define DEBUG 1 */
56 /* #define DEBUG_FLAGS */
57 
58 #include <linux/interrupt.h>
59 #include <linux/sched.h>
60 #include <linux/firmware.h>
61 #include "../comedidev.h"
62 
63 #include "comedi_fc.h"
64 #include "mite.h"
65 
66 #undef DPRINTK
67 #ifdef DEBUG
68 #define DPRINTK(format, args...) pr_debug(format, ## args)
69 #else
70 #define DPRINTK(format, args...) do { } while (0)
71 #endif
72 
73 #define PCI_DIO_SIZE 4096
74 #define PCI_MITE_SIZE 4096
75 
76 /* defines for the PCI-DIO-32HS */
77 
78 #define Window_Address 4 /* W */
79 #define Interrupt_And_Window_Status 4 /* R */
80 #define IntStatus1 (1<<0)
81 #define IntStatus2 (1<<1)
82 #define WindowAddressStatus_mask 0x7c
83 
84 #define Master_DMA_And_Interrupt_Control 5 /* W */
85 #define InterruptLine(x) ((x)&3)
86 #define OpenInt (1<<2)
87 #define Group_Status 5 /* R */
88 #define DataLeft (1<<0)
89 #define Req (1<<2)
90 #define StopTrig (1<<3)
91 
92 #define Group_1_Flags 6 /* R */
93 #define Group_2_Flags 7 /* R */
94 #define TransferReady (1<<0)
95 #define CountExpired (1<<1)
96 #define Waited (1<<5)
97 #define PrimaryTC (1<<6)
98 #define SecondaryTC (1<<7)
99  /* #define SerialRose */
100  /* #define ReqRose */
101  /* #define Paused */
102 
103 #define Group_1_First_Clear 6 /* W */
104 #define Group_2_First_Clear 7 /* W */
105 #define ClearWaited (1<<3)
106 #define ClearPrimaryTC (1<<4)
107 #define ClearSecondaryTC (1<<5)
108 #define DMAReset (1<<6)
109 #define FIFOReset (1<<7)
110 #define ClearAll 0xf8
111 
112 #define Group_1_FIFO 8 /* W */
113 #define Group_2_FIFO 12 /* W */
114 
115 #define Transfer_Count 20
116 #define Chip_ID_D 24
117 #define Chip_ID_I 25
118 #define Chip_ID_O 26
119 #define Chip_Version 27
120 #define Port_IO(x) (28+(x))
121 #define Port_Pin_Directions(x) (32+(x))
122 #define Port_Pin_Mask(x) (36+(x))
123 #define Port_Pin_Polarities(x) (40+(x))
124 
125 #define Master_Clock_Routing 45
126 #define RTSIClocking(x) (((x)&3)<<4)
127 
128 #define Group_1_Second_Clear 46 /* W */
129 #define Group_2_Second_Clear 47 /* W */
130 #define ClearExpired (1<<0)
131 
132 #define Port_Pattern(x) (48+(x))
133 
134 #define Data_Path 64
135 #define FIFOEnableA (1<<0)
136 #define FIFOEnableB (1<<1)
137 #define FIFOEnableC (1<<2)
138 #define FIFOEnableD (1<<3)
139 #define Funneling(x) (((x)&3)<<4)
140 #define GroupDirection (1<<7)
141 
142 #define Protocol_Register_1 65
143 #define OpMode Protocol_Register_1
144 #define RunMode(x) ((x)&7)
145 #define Numbered (1<<3)
146 
147 #define Protocol_Register_2 66
148 #define ClockReg Protocol_Register_2
149 #define ClockLine(x) (((x)&3)<<5)
150 #define InvertStopTrig (1<<7)
151 #define DataLatching(x) (((x)&3)<<5)
152 
153 #define Protocol_Register_3 67
154 #define Sequence Protocol_Register_3
155 
156 #define Protocol_Register_14 68 /* 16 bit */
157 #define ClockSpeed Protocol_Register_14
158 
159 #define Protocol_Register_4 70
160 #define ReqReg Protocol_Register_4
161 #define ReqConditioning(x) (((x)&7)<<3)
162 
163 #define Protocol_Register_5 71
164 #define BlockMode Protocol_Register_5
165 
166 #define FIFO_Control 72
167 #define ReadyLevel(x) ((x)&7)
168 
169 #define Protocol_Register_6 73
170 #define LinePolarities Protocol_Register_6
171 #define InvertAck (1<<0)
172 #define InvertReq (1<<1)
173 #define InvertClock (1<<2)
174 #define InvertSerial (1<<3)
175 #define OpenAck (1<<4)
176 #define OpenClock (1<<5)
177 
178 #define Protocol_Register_7 74
179 #define AckSer Protocol_Register_7
180 #define AckLine(x) (((x)&3)<<2)
181 #define ExchangePins (1<<7)
182 
183 #define Interrupt_Control 75
184  /* bits same as flags */
185 
186 #define DMA_Line_Control_Group1 76
187 #define DMA_Line_Control_Group2 108
188 /* channel zero is none */
189 static inline unsigned primary_DMAChannel_bits(unsigned channel)
190 {
191  return channel & 0x3;
192 }
193 
194 static inline unsigned secondary_DMAChannel_bits(unsigned channel)
195 {
196  return (channel << 2) & 0xc;
197 }
198 
199 #define Transfer_Size_Control 77
200 #define TransferWidth(x) ((x)&3)
201 #define TransferLength(x) (((x)&3)<<3)
202 #define RequireRLevel (1<<5)
203 
204 #define Protocol_Register_15 79
205 #define DAQOptions Protocol_Register_15
206 #define StartSource(x) ((x)&0x3)
207 #define InvertStart (1<<2)
208 #define StopSource(x) (((x)&0x3)<<3)
209 #define ReqStart (1<<6)
210 #define PreStart (1<<7)
211 
212 #define Pattern_Detection 81
213 #define DetectionMethod (1<<0)
214 #define InvertMatch (1<<1)
215 #define IE_Pattern_Detection (1<<2)
216 
217 #define Protocol_Register_9 82
218 #define ReqDelay Protocol_Register_9
219 
220 #define Protocol_Register_10 83
221 #define ReqNotDelay Protocol_Register_10
222 
223 #define Protocol_Register_11 84
224 #define AckDelay Protocol_Register_11
225 
226 #define Protocol_Register_12 85
227 #define AckNotDelay Protocol_Register_12
228 
229 #define Protocol_Register_13 86
230 #define Data1Delay Protocol_Register_13
231 
232 #define Protocol_Register_8 88 /* 32 bit */
233 #define StartDelay Protocol_Register_8
234 
235 /* Firmware files for PCI-6524 */
236 #define FW_PCI_6534_MAIN "ni6534a.bin"
237 #define FW_PCI_6534_SCARAB_DI "niscrb01.bin"
238 #define FW_PCI_6534_SCARAB_DO "niscrb02.bin"
239 MODULE_FIRMWARE(FW_PCI_6534_MAIN);
240 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DI);
241 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DO);
242 
243 enum pci_6534_firmware_registers { /* 16 bit */
244  Firmware_Control_Register = 0x100,
245  Firmware_Status_Register = 0x104,
246  Firmware_Data_Register = 0x108,
247  Firmware_Mask_Register = 0x10c,
248  Firmware_Debug_Register = 0x110,
249 };
250 /* main fpga registers (32 bit)*/
251 enum pci_6534_fpga_registers {
252  FPGA_Control1_Register = 0x200,
253  FPGA_Control2_Register = 0x204,
254  FPGA_Irq_Mask_Register = 0x208,
255  FPGA_Status_Register = 0x20c,
256  FPGA_Signature_Register = 0x210,
257  FPGA_SCALS_Counter_Register = 0x280, /*write-clear */
258  FPGA_SCAMS_Counter_Register = 0x284, /*write-clear */
259  FPGA_SCBLS_Counter_Register = 0x288, /*write-clear */
260  FPGA_SCBMS_Counter_Register = 0x28c, /*write-clear */
261  FPGA_Temp_Control_Register = 0x2a0,
262  FPGA_DAR_Register = 0x2a8,
263  FPGA_ELC_Read_Register = 0x2b8,
264  FPGA_ELC_Write_Register = 0x2bc,
265 };
266 enum FPGA_Control_Bits {
267  FPGA_Enable_Bit = 0x8000,
268 };
269 
270 #define TIMER_BASE 50 /* nanoseconds */
271 
272 #ifdef USE_DMA
273 #define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC)
274 #else
275 #define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC)
276 #endif
277 
278 static int ni_pcidio_cancel(struct comedi_device *dev,
279  struct comedi_subdevice *s);
280 
281 struct nidio_board {
282  int dev_id;
283  const char *name;
284  unsigned int uses_firmware:1;
285 };
286 
287 static const struct nidio_board nidio_boards[] = {
288  {
289  .dev_id = 0x1150,
290  .name = "pci-dio-32hs",
291  }, {
292  .dev_id = 0x1320,
293  .name = "pxi-6533",
294  }, {
295  .dev_id = 0x12b0,
296  .name = "pci-6534",
297  .uses_firmware = 1,
298  },
299 };
300 
301 #define n_nidio_boards ARRAY_SIZE(nidio_boards)
302 #define this_board ((const struct nidio_board *)dev->board_ptr)
303 
304 struct nidio96_private {
305  struct mite_struct *mite;
306  int boardtype;
307  int dio;
308  unsigned short OpModeBits;
309  struct mite_channel *di_mite_chan;
310  struct mite_dma_descriptor_ring *di_mite_ring;
311  spinlock_t mite_channel_lock;
312 };
313 #define devpriv ((struct nidio96_private *)dev->private)
314 
315 static int ni_pcidio_cmdtest(struct comedi_device *dev,
316  struct comedi_subdevice *s,
317  struct comedi_cmd *cmd);
318 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
319 static int ni_pcidio_inttrig(struct comedi_device *dev,
320  struct comedi_subdevice *s, unsigned int trignum);
321 static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode);
322 static int setup_mite_dma(struct comedi_device *dev,
323  struct comedi_subdevice *s);
324 
325 #ifdef DEBUG_FLAGS
326 static void ni_pcidio_print_flags(unsigned int flags);
327 static void ni_pcidio_print_status(unsigned int status);
328 #else
329 #define ni_pcidio_print_flags(x)
330 #define ni_pcidio_print_status(x)
331 #endif
332 
333 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
334 {
335  unsigned long flags;
336 
337  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
338  BUG_ON(devpriv->di_mite_chan);
339  devpriv->di_mite_chan =
340  mite_request_channel_in_range(devpriv->mite,
341  devpriv->di_mite_ring, 1, 2);
342  if (devpriv->di_mite_chan == NULL) {
343  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
344  comedi_error(dev, "failed to reserve mite dma channel.");
345  return -EBUSY;
346  }
347  devpriv->di_mite_chan->dir = COMEDI_INPUT;
348  writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
349  secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
350  devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
351  mmiowb();
352  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
353  return 0;
354 }
355 
356 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
357 {
358  unsigned long flags;
359 
360  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
361  if (devpriv->di_mite_chan) {
362  mite_dma_disarm(devpriv->di_mite_chan);
363  mite_dma_reset(devpriv->di_mite_chan);
364  mite_release_channel(devpriv->di_mite_chan);
365  devpriv->di_mite_chan = NULL;
366  writeb(primary_DMAChannel_bits(0) |
367  secondary_DMAChannel_bits(0),
368  devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
369  mmiowb();
370  }
371  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
372 }
373 
374 static void ni_pcidio_event(struct comedi_device *dev,
375  struct comedi_subdevice *s)
376 {
377  if (s->
378  async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
379  COMEDI_CB_OVERFLOW)) {
380  ni_pcidio_cancel(dev, s);
381  }
382  comedi_event(dev, s);
383 }
384 
385 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
386 {
387  unsigned long irq_flags;
388  int count;
389 
390  spin_lock_irqsave(&dev->spinlock, irq_flags);
391  spin_lock(&devpriv->mite_channel_lock);
392  if (devpriv->di_mite_chan)
393  mite_sync_input_dma(devpriv->di_mite_chan, s->async);
394  spin_unlock(&devpriv->mite_channel_lock);
395  count = s->async->buf_write_count - s->async->buf_read_count;
396  spin_unlock_irqrestore(&dev->spinlock, irq_flags);
397  return count;
398 }
399 
400 static irqreturn_t nidio_interrupt(int irq, void *d)
401 {
402  struct comedi_device *dev = d;
403  struct comedi_subdevice *s = &dev->subdevices[0];
404  struct comedi_async *async = s->async;
405  struct mite_struct *mite = devpriv->mite;
406 
407  /* int i, j; */
408  long int AuxData = 0;
409  short data1 = 0;
410  short data2 = 0;
411  int flags;
412  int status;
413  int work = 0;
414  unsigned int m_status = 0;
415 
416  /* interrupcions parasites */
417  if (dev->attached == 0) {
418  /* assume it's from another card */
419  return IRQ_NONE;
420  }
421 
422  /* Lock to avoid race with comedi_poll */
423  spin_lock(&dev->spinlock);
424 
425  status = readb(devpriv->mite->daq_io_addr +
426  Interrupt_And_Window_Status);
427  flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
428 
429  DPRINTK("ni_pcidio_interrupt: status=0x%02x,flags=0x%02x\n",
430  status, flags);
431  ni_pcidio_print_flags(flags);
432  ni_pcidio_print_status(status);
433 
434  spin_lock(&devpriv->mite_channel_lock);
435  if (devpriv->di_mite_chan)
436  m_status = mite_get_status(devpriv->di_mite_chan);
437 #ifdef MITE_DEBUG
438  mite_print_chsr(m_status);
439 #endif
440 
441  /* mite_dump_regs(mite); */
442  if (m_status & CHSR_INT) {
443  if (m_status & CHSR_LINKC) {
444  writel(CHOR_CLRLC,
445  mite->mite_io_addr +
446  MITE_CHOR(devpriv->di_mite_chan->channel));
447  mite_sync_input_dma(devpriv->di_mite_chan, s->async);
448  /* XXX need to byteswap */
449  }
450  if (m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_DRDY |
451  CHSR_DRQ1 | CHSR_MRDY)) {
452  DPRINTK("unknown mite interrupt, disabling IRQ\n");
453  async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
454  disable_irq(dev->irq);
455  }
456  }
457  spin_unlock(&devpriv->mite_channel_lock);
458 
459  while (status & DataLeft) {
460  work++;
461  if (work > 20) {
462  DPRINTK("too much work in interrupt\n");
463  writeb(0x00,
464  devpriv->mite->daq_io_addr +
465  Master_DMA_And_Interrupt_Control);
466  break;
467  }
468 
469  flags &= IntEn;
470 
471  if (flags & TransferReady) {
472  /* DPRINTK("TransferReady\n"); */
473  while (flags & TransferReady) {
474  work++;
475  if (work > 100) {
476  DPRINTK("too much work in interrupt\n");
477  writeb(0x00,
478  devpriv->mite->daq_io_addr +
479  Master_DMA_And_Interrupt_Control
480  );
481  goto out;
482  }
483  AuxData =
484  readl(devpriv->mite->daq_io_addr +
485  Group_1_FIFO);
486  data1 = AuxData & 0xffff;
487  data2 = (AuxData & 0xffff0000) >> 16;
488  comedi_buf_put(async, data1);
489  comedi_buf_put(async, data2);
490  /* DPRINTK("read:%d, %d\n",data1,data2); */
491  flags = readb(devpriv->mite->daq_io_addr +
492  Group_1_Flags);
493  }
494  /* DPRINTK("buf_int_count: %d\n",
495  async->buf_int_count); */
496  /* DPRINTK("1) IntEn=%d,flags=%d,status=%d\n",
497  IntEn,flags,status); */
498  /* ni_pcidio_print_flags(flags); */
499  /* ni_pcidio_print_status(status); */
500  async->events |= COMEDI_CB_BLOCK;
501  }
502 
503  if (flags & CountExpired) {
504  DPRINTK("CountExpired\n");
505  writeb(ClearExpired,
506  devpriv->mite->daq_io_addr +
507  Group_1_Second_Clear);
508  async->events |= COMEDI_CB_EOA;
509 
510  writeb(0x00, devpriv->mite->daq_io_addr + OpMode);
511  break;
512  } else if (flags & Waited) {
513  DPRINTK("Waited\n");
514  writeb(ClearWaited,
515  devpriv->mite->daq_io_addr +
516  Group_1_First_Clear);
517  async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
518  break;
519  } else if (flags & PrimaryTC) {
520  DPRINTK("PrimaryTC\n");
521  writeb(ClearPrimaryTC,
522  devpriv->mite->daq_io_addr +
523  Group_1_First_Clear);
524  async->events |= COMEDI_CB_EOA;
525  } else if (flags & SecondaryTC) {
526  DPRINTK("SecondaryTC\n");
527  writeb(ClearSecondaryTC,
528  devpriv->mite->daq_io_addr +
529  Group_1_First_Clear);
530  async->events |= COMEDI_CB_EOA;
531  }
532 #if 0
533  else {
534  DPRINTK("ni_pcidio: unknown interrupt\n");
535  async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
536  writeb(0x00,
537  devpriv->mite->daq_io_addr +
538  Master_DMA_And_Interrupt_Control);
539  }
540 #endif
541  flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
542  status = readb(devpriv->mite->daq_io_addr +
543  Interrupt_And_Window_Status);
544  /* DPRINTK("loop end: IntEn=0x%02x,flags=0x%02x,"
545  "status=0x%02x\n", IntEn, flags, status); */
546  /* ni_pcidio_print_flags(flags); */
547  /* ni_pcidio_print_status(status); */
548  }
549 
550 out:
551  ni_pcidio_event(dev, s);
552 #if 0
553  if (!tag) {
554  writeb(0x03,
555  devpriv->mite->daq_io_addr +
556  Master_DMA_And_Interrupt_Control);
557  }
558 #endif
559 
560  spin_unlock(&dev->spinlock);
561  return IRQ_HANDLED;
562 }
563 
564 #ifdef DEBUG_FLAGS
565 static const char *bit_set_string(unsigned int bits, unsigned int bit,
566  const char *const strings[])
567 {
568  return (bits & (1U << bit)) ? strings[bit] : "";
569 }
570 
571 static const char *const flags_strings[] = {
572  " TransferReady", " CountExpired", " 2", " 3",
573  " 4", " Waited", " PrimaryTC", " SecondaryTC",
574 };
575 
576 
577 static void ni_pcidio_print_flags(unsigned int flags)
578 {
579  pr_debug("group_1_flags:%s%s%s%s%s%s%s%s\n",
580  bit_set_string(flags, 7, flags_strings),
581  bit_set_string(flags, 6, flags_strings),
582  bit_set_string(flags, 5, flags_strings),
583  bit_set_string(flags, 4, flags_strings),
584  bit_set_string(flags, 3, flags_strings),
585  bit_set_string(flags, 2, flags_strings),
586  bit_set_string(flags, 1, flags_strings),
587  bit_set_string(flags, 0, flags_strings));
588 }
589 
590 static const char *const status_strings[] = {
591  " DataLeft1", " Reserved1", " Req1", " StopTrig1",
592  " DataLeft2", " Reserved2", " Req2", " StopTrig2",
593 };
594 
595 static void ni_pcidio_print_status(unsigned int flags)
596 {
597  pr_debug("group_status:%s%s%s%s%s%s%s%s\n",
598  bit_set_string(flags, 7, status_strings),
599  bit_set_string(flags, 6, status_strings),
600  bit_set_string(flags, 5, status_strings),
601  bit_set_string(flags, 4, status_strings),
602  bit_set_string(flags, 3, status_strings),
603  bit_set_string(flags, 2, status_strings),
604  bit_set_string(flags, 1, status_strings),
605  bit_set_string(flags, 0, status_strings));
606 }
607 #endif
608 
609 #ifdef unused
610 static void debug_int(struct comedi_device *dev)
611 {
612  int a, b;
613  static int n_int;
614  struct timeval tv;
615 
616  do_gettimeofday(&tv);
617  a = readb(devpriv->mite->daq_io_addr + Group_Status);
618  b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
619 
620  if (n_int < 10) {
621  DPRINTK("status 0x%02x flags 0x%02x time %06d\n", a, b,
622  (int)tv.tv_usec);
623  }
624 
625  while (b & 1) {
626  writew(0xff, devpriv->mite->daq_io_addr + Group_1_FIFO);
627  b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
628  }
629 
630  b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
631 
632  if (n_int < 10) {
633  DPRINTK("new status 0x%02x\n", b);
634  n_int++;
635  }
636 }
637 #endif
638 
639 static int ni_pcidio_insn_config(struct comedi_device *dev,
640  struct comedi_subdevice *s,
641  struct comedi_insn *insn, unsigned int *data)
642 {
643  if (insn->n != 1)
644  return -EINVAL;
645  switch (data[0]) {
646  case INSN_CONFIG_DIO_OUTPUT:
647  s->io_bits |= 1 << CR_CHAN(insn->chanspec);
648  break;
649  case INSN_CONFIG_DIO_INPUT:
650  s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
651  break;
652  case INSN_CONFIG_DIO_QUERY:
653  data[1] =
654  (s->
655  io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
656  COMEDI_INPUT;
657  return insn->n;
658  break;
659  default:
660  return -EINVAL;
661  }
662  writel(s->io_bits, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
663 
664  return 1;
665 }
666 
667 static int ni_pcidio_insn_bits(struct comedi_device *dev,
668  struct comedi_subdevice *s,
669  struct comedi_insn *insn, unsigned int *data)
670 {
671  if (data[0]) {
672  s->state &= ~data[0];
673  s->state |= (data[0] & data[1]);
674  writel(s->state, devpriv->mite->daq_io_addr + Port_IO(0));
675  }
676  data[1] = readl(devpriv->mite->daq_io_addr + Port_IO(0));
677 
678  return insn->n;
679 }
680 
681 static int ni_pcidio_cmdtest(struct comedi_device *dev,
682  struct comedi_subdevice *s, struct comedi_cmd *cmd)
683 {
684  int err = 0;
685  int tmp;
686 
687  /* Step 1 : check if triggers are trivially valid */
688 
689  err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
690  err |= cfc_check_trigger_src(&cmd->scan_begin_src,
691  TRIG_TIMER | TRIG_EXT);
692  err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
693  err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
694  err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
695 
696  if (err)
697  return 1;
698 
699  /* Step 2a : make sure trigger sources are unique */
700 
701  err |= cfc_check_trigger_is_unique(cmd->start_src);
702  err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
703  err |= cfc_check_trigger_is_unique(cmd->stop_src);
704 
705  /* Step 2b : and mutually compatible */
706 
707  if (err)
708  return 2;
709 
710  /* step 3: make sure arguments are trivially compatible */
711 
712  if (cmd->start_arg != 0) {
713  /* same for both TRIG_INT and TRIG_NOW */
714  cmd->start_arg = 0;
715  err++;
716  }
717 #define MAX_SPEED (TIMER_BASE) /* in nanoseconds */
718 
719  if (cmd->scan_begin_src == TRIG_TIMER) {
720  if (cmd->scan_begin_arg < MAX_SPEED) {
721  cmd->scan_begin_arg = MAX_SPEED;
722  err++;
723  }
724  /* no minimum speed */
725  } else {
726  /* TRIG_EXT */
727  /* should be level/edge, hi/lo specification here */
728  if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
729  cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
730  err++;
731  }
732  }
733  if (cmd->convert_arg != 0) {
734  cmd->convert_arg = 0;
735  err++;
736  }
737 
738  if (cmd->scan_end_arg != cmd->chanlist_len) {
739  cmd->scan_end_arg = cmd->chanlist_len;
740  err++;
741  }
742  if (cmd->stop_src == TRIG_COUNT) {
743  /* no limit */
744  } else {
745  /* TRIG_NONE */
746  if (cmd->stop_arg != 0) {
747  cmd->stop_arg = 0;
748  err++;
749  }
750  }
751 
752  if (err)
753  return 3;
754 
755  /* step 4: fix up any arguments */
756 
757  if (cmd->scan_begin_src == TRIG_TIMER) {
758  tmp = cmd->scan_begin_arg;
759  ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
760  cmd->flags & TRIG_ROUND_MASK);
761  if (tmp != cmd->scan_begin_arg)
762  err++;
763  }
764 
765  if (err)
766  return 4;
767 
768  return 0;
769 }
770 
771 static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode)
772 {
773  int divider, base;
774 
775  base = TIMER_BASE;
776 
777  switch (round_mode) {
778  case TRIG_ROUND_NEAREST:
779  default:
780  divider = (*nanosec + base / 2) / base;
781  break;
782  case TRIG_ROUND_DOWN:
783  divider = (*nanosec) / base;
784  break;
785  case TRIG_ROUND_UP:
786  divider = (*nanosec + base - 1) / base;
787  break;
788  }
789 
790  *nanosec = base * divider;
791  return divider;
792 }
793 
794 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
795 {
796  struct comedi_cmd *cmd = &s->async->cmd;
797 
798  /* XXX configure ports for input */
799  writel(0x0000, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
800 
801  if (1) {
802  /* enable fifos A B C D */
803  writeb(0x0f, devpriv->mite->daq_io_addr + Data_Path);
804 
805  /* set transfer width a 32 bits */
806  writeb(TransferWidth(0) | TransferLength(0),
807  devpriv->mite->daq_io_addr + Transfer_Size_Control);
808  } else {
809  writeb(0x03, devpriv->mite->daq_io_addr + Data_Path);
810  writeb(TransferWidth(3) | TransferLength(0),
811  devpriv->mite->daq_io_addr + Transfer_Size_Control);
812  }
813 
814  /* protocol configuration */
815  if (cmd->scan_begin_src == TRIG_TIMER) {
816  /* page 4-5, "input with internal REQs" */
817  writeb(0, devpriv->mite->daq_io_addr + OpMode);
818  writeb(0x00, devpriv->mite->daq_io_addr + ClockReg);
819  writeb(1, devpriv->mite->daq_io_addr + Sequence);
820  writeb(0x04, devpriv->mite->daq_io_addr + ReqReg);
821  writeb(4, devpriv->mite->daq_io_addr + BlockMode);
822  writeb(3, devpriv->mite->daq_io_addr + LinePolarities);
823  writeb(0xc0, devpriv->mite->daq_io_addr + AckSer);
824  writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
825  TRIG_ROUND_NEAREST),
826  devpriv->mite->daq_io_addr + StartDelay);
827  writeb(1, devpriv->mite->daq_io_addr + ReqDelay);
828  writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay);
829  writeb(1, devpriv->mite->daq_io_addr + AckDelay);
830  writeb(0x0b, devpriv->mite->daq_io_addr + AckNotDelay);
831  writeb(0x01, devpriv->mite->daq_io_addr + Data1Delay);
832  /* manual, page 4-5: ClockSpeed comment is incorrectly listed
833  * on DAQOptions */
834  writew(0, devpriv->mite->daq_io_addr + ClockSpeed);
835  writeb(0, devpriv->mite->daq_io_addr + DAQOptions);
836  } else {
837  /* TRIG_EXT */
838  /* page 4-5, "input with external REQs" */
839  writeb(0, devpriv->mite->daq_io_addr + OpMode);
840  writeb(0x00, devpriv->mite->daq_io_addr + ClockReg);
841  writeb(0, devpriv->mite->daq_io_addr + Sequence);
842  writeb(0x00, devpriv->mite->daq_io_addr + ReqReg);
843  writeb(4, devpriv->mite->daq_io_addr + BlockMode);
844  if (!(cmd->scan_begin_arg & CR_INVERT)) {
845  /* Leading Edge pulse mode */
846  writeb(0, devpriv->mite->daq_io_addr + LinePolarities);
847  } else {
848  /* Trailing Edge pulse mode */
849  writeb(2, devpriv->mite->daq_io_addr + LinePolarities);
850  }
851  writeb(0x00, devpriv->mite->daq_io_addr + AckSer);
852  writel(1, devpriv->mite->daq_io_addr + StartDelay);
853  writeb(1, devpriv->mite->daq_io_addr + ReqDelay);
854  writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay);
855  writeb(1, devpriv->mite->daq_io_addr + AckDelay);
856  writeb(0x0C, devpriv->mite->daq_io_addr + AckNotDelay);
857  writeb(0x10, devpriv->mite->daq_io_addr + Data1Delay);
858  writew(0, devpriv->mite->daq_io_addr + ClockSpeed);
859  writeb(0x60, devpriv->mite->daq_io_addr + DAQOptions);
860  }
861 
862  if (cmd->stop_src == TRIG_COUNT) {
863  writel(cmd->stop_arg,
864  devpriv->mite->daq_io_addr + Transfer_Count);
865  } else {
866  /* XXX */
867  }
868 
869 #ifdef USE_DMA
870  writeb(ClearPrimaryTC | ClearSecondaryTC,
871  devpriv->mite->daq_io_addr + Group_1_First_Clear);
872 
873  {
874  int retval = setup_mite_dma(dev, s);
875  if (retval)
876  return retval;
877  }
878 #else
879  writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
880 #endif
881  writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group2);
882 
883  /* clear and enable interrupts */
884  writeb(0xff, devpriv->mite->daq_io_addr + Group_1_First_Clear);
885  /* writeb(ClearExpired,
886  devpriv->mite->daq_io_addr+Group_1_Second_Clear); */
887 
888  writeb(IntEn, devpriv->mite->daq_io_addr + Interrupt_Control);
889  writeb(0x03,
890  devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control);
891 
892  if (cmd->stop_src == TRIG_NONE) {
893  devpriv->OpModeBits = DataLatching(0) | RunMode(7);
894  } else { /* TRIG_TIMER */
895  devpriv->OpModeBits = Numbered | RunMode(7);
896  }
897  if (cmd->start_src == TRIG_NOW) {
898  /* start */
899  writeb(devpriv->OpModeBits,
900  devpriv->mite->daq_io_addr + OpMode);
901  s->async->inttrig = NULL;
902  } else {
903  /* TRIG_INT */
904  s->async->inttrig = ni_pcidio_inttrig;
905  }
906 
907  DPRINTK("ni_pcidio: command started\n");
908  return 0;
909 }
910 
911 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
912 {
913  int retval;
914  unsigned long flags;
915 
916  retval = ni_pcidio_request_di_mite_channel(dev);
917  if (retval)
918  return retval;
919 
920  /* write alloc the entire buffer */
921  comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
922 
923  spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
924  if (devpriv->di_mite_chan) {
925  mite_prep_dma(devpriv->di_mite_chan, 32, 32);
926  mite_dma_arm(devpriv->di_mite_chan);
927  } else
928  retval = -EIO;
929  spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
930 
931  return retval;
932 }
933 
934 static int ni_pcidio_inttrig(struct comedi_device *dev,
935  struct comedi_subdevice *s, unsigned int trignum)
936 {
937  if (trignum != 0)
938  return -EINVAL;
939 
940  writeb(devpriv->OpModeBits, devpriv->mite->daq_io_addr + OpMode);
941  s->async->inttrig = NULL;
942 
943  return 1;
944 }
945 
946 static int ni_pcidio_cancel(struct comedi_device *dev,
947  struct comedi_subdevice *s)
948 {
949  writeb(0x00,
950  devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control);
951  ni_pcidio_release_di_mite_channel(dev);
952 
953  return 0;
954 }
955 
956 static int ni_pcidio_change(struct comedi_device *dev,
957  struct comedi_subdevice *s, unsigned long new_size)
958 {
959  int ret;
960 
961  ret = mite_buf_change(devpriv->di_mite_ring, s->async);
962  if (ret < 0)
963  return ret;
964 
965  memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
966 
967  return 0;
968 }
969 
970 static int pci_6534_load_fpga(struct comedi_device *dev, int fpga_index,
971  const u8 *data, size_t data_len)
972 {
973  static const int timeout = 1000;
974  int i;
975  size_t j;
976 
977  writew(0x80 | fpga_index,
978  devpriv->mite->daq_io_addr + Firmware_Control_Register);
979  writew(0xc0 | fpga_index,
980  devpriv->mite->daq_io_addr + Firmware_Control_Register);
981  for (i = 0;
982  (readw(devpriv->mite->daq_io_addr +
983  Firmware_Status_Register) & 0x2) == 0 && i < timeout; ++i) {
984  udelay(1);
985  }
986  if (i == timeout) {
987  dev_warn(dev->class_dev,
988  "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
989  fpga_index);
990  return -EIO;
991  }
992  writew(0x80 | fpga_index,
993  devpriv->mite->daq_io_addr + Firmware_Control_Register);
994  for (i = 0;
995  readw(devpriv->mite->daq_io_addr + Firmware_Status_Register) !=
996  0x3 && i < timeout; ++i) {
997  udelay(1);
998  }
999  if (i == timeout) {
1000  dev_warn(dev->class_dev,
1001  "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
1002  fpga_index);
1003  return -EIO;
1004  }
1005  for (j = 0; j + 1 < data_len;) {
1006  unsigned int value = data[j++];
1007  value |= data[j++] << 8;
1008  writew(value,
1009  devpriv->mite->daq_io_addr + Firmware_Data_Register);
1010  for (i = 0;
1011  (readw(devpriv->mite->daq_io_addr +
1012  Firmware_Status_Register) & 0x2) == 0
1013  && i < timeout; ++i) {
1014  udelay(1);
1015  }
1016  if (i == timeout) {
1017  dev_warn(dev->class_dev,
1018  "ni_pcidio: failed to load word into fpga %i\n",
1019  fpga_index);
1020  return -EIO;
1021  }
1022  if (need_resched())
1023  schedule();
1024  }
1025  writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
1026  return 0;
1027 }
1028 
1029 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
1030 {
1031  return pci_6534_load_fpga(dev, fpga_index, NULL, 0);
1032 }
1033 
1034 static int pci_6534_reset_fpgas(struct comedi_device *dev)
1035 {
1036  int ret;
1037  int i;
1038  writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
1039  for (i = 0; i < 3; ++i) {
1040  ret = pci_6534_reset_fpga(dev, i);
1041  if (ret < 0)
1042  break;
1043  }
1044  writew(0x0, devpriv->mite->daq_io_addr + Firmware_Mask_Register);
1045  return ret;
1046 }
1047 
1048 static void pci_6534_init_main_fpga(struct comedi_device *dev)
1049 {
1050  writel(0, devpriv->mite->daq_io_addr + FPGA_Control1_Register);
1051  writel(0, devpriv->mite->daq_io_addr + FPGA_Control2_Register);
1052  writel(0, devpriv->mite->daq_io_addr + FPGA_SCALS_Counter_Register);
1053  writel(0, devpriv->mite->daq_io_addr + FPGA_SCAMS_Counter_Register);
1054  writel(0, devpriv->mite->daq_io_addr + FPGA_SCBLS_Counter_Register);
1055  writel(0, devpriv->mite->daq_io_addr + FPGA_SCBMS_Counter_Register);
1056 }
1057 
1058 static int pci_6534_upload_firmware(struct comedi_device *dev)
1059 {
1060  int ret;
1061  const struct firmware *fw;
1062  static const char *const fw_file[3] = {
1063  FW_PCI_6534_SCARAB_DI, /* loaded into scarab A for DI */
1064  FW_PCI_6534_SCARAB_DO, /* loaded into scarab B for DO */
1065  FW_PCI_6534_MAIN, /* loaded into main FPGA */
1066  };
1067  int n;
1068 
1069  ret = pci_6534_reset_fpgas(dev);
1070  if (ret < 0)
1071  return ret;
1072  /* load main FPGA first, then the two scarabs */
1073  for (n = 2; n >= 0; n--) {
1074  ret = request_firmware(&fw, fw_file[n],
1075  &devpriv->mite->pcidev->dev);
1076  if (ret == 0) {
1077  ret = pci_6534_load_fpga(dev, n, fw->data, fw->size);
1078  if (ret == 0 && n == 2)
1079  pci_6534_init_main_fpga(dev);
1080  release_firmware(fw);
1081  }
1082  if (ret < 0)
1083  break;
1084  }
1085  return ret;
1086 }
1087 
1088 static const struct nidio_board *
1089 nidio_find_boardinfo(struct pci_dev *pcidev)
1090 {
1091  unsigned int dev_id = pcidev->device;
1092  unsigned int n;
1093 
1094  for (n = 0; n < ARRAY_SIZE(nidio_boards); n++) {
1095  const struct nidio_board *board = &nidio_boards[n];
1096  if (board->dev_id == dev_id)
1097  return board;
1098  }
1099  return NULL;
1100 }
1101 
1102 static int __devinit nidio_attach_pci(struct comedi_device *dev,
1103  struct pci_dev *pcidev)
1104 {
1105  struct comedi_subdevice *s;
1106  int ret;
1107  unsigned int irq;
1108 
1109  ret = alloc_private(dev, sizeof(struct nidio96_private));
1110  if (ret < 0)
1111  return ret;
1112  spin_lock_init(&devpriv->mite_channel_lock);
1113 
1114  dev->board_ptr = nidio_find_boardinfo(pcidev);
1115  if (!dev->board_ptr)
1116  return -ENODEV;
1117  devpriv->mite = mite_alloc(pcidev);
1118  if (!devpriv->mite)
1119  return -ENOMEM;
1120 
1121  ret = mite_setup(devpriv->mite);
1122  if (ret < 0) {
1123  dev_warn(dev->class_dev, "error setting up mite\n");
1124  return ret;
1125  }
1126  comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev);
1127  devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
1128  if (devpriv->di_mite_ring == NULL)
1129  return -ENOMEM;
1130 
1131  dev->board_name = this_board->name;
1132  irq = mite_irq(devpriv->mite);
1133  if (this_board->uses_firmware) {
1134  ret = pci_6534_upload_firmware(dev);
1135  if (ret < 0)
1136  return ret;
1137  }
1138 
1139  ret = comedi_alloc_subdevices(dev, 1);
1140  if (ret)
1141  return ret;
1142 
1143  dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
1144  readb(devpriv->mite->daq_io_addr + Chip_Version));
1145 
1146  s = &dev->subdevices[0];
1147 
1148  dev->read_subdev = s;
1149  s->type = COMEDI_SUBD_DIO;
1150  s->subdev_flags =
1151  SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
1152  SDF_CMD_READ;
1153  s->n_chan = 32;
1154  s->range_table = &range_digital;
1155  s->maxdata = 1;
1156  s->insn_config = &ni_pcidio_insn_config;
1157  s->insn_bits = &ni_pcidio_insn_bits;
1158  s->do_cmd = &ni_pcidio_cmd;
1159  s->do_cmdtest = &ni_pcidio_cmdtest;
1160  s->cancel = &ni_pcidio_cancel;
1161  s->len_chanlist = 32; /* XXX */
1162  s->buf_change = &ni_pcidio_change;
1163  s->async_dma_dir = DMA_BIDIRECTIONAL;
1164  s->poll = &ni_pcidio_poll;
1165 
1166  writel(0, devpriv->mite->daq_io_addr + Port_IO(0));
1167  writel(0, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
1168  writel(0, devpriv->mite->daq_io_addr + Port_Pin_Mask(0));
1169 
1170  /* disable interrupts on board */
1171  writeb(0x00,
1172  devpriv->mite->daq_io_addr +
1173  Master_DMA_And_Interrupt_Control);
1174 
1175  ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
1176  "ni_pcidio", dev);
1177  if (ret < 0)
1178  dev_warn(dev->class_dev, "irq not available\n");
1179 
1180  dev->irq = irq;
1181 
1182  return 0;
1183 }
1184 
1185 static void nidio_detach(struct comedi_device *dev)
1186 {
1187  if (dev->irq)
1188  free_irq(dev->irq, dev);
1189  if (devpriv) {
1190  if (devpriv->di_mite_ring) {
1191  mite_free_ring(devpriv->di_mite_ring);
1192  devpriv->di_mite_ring = NULL;
1193  }
1194  if (devpriv->mite) {
1195  mite_unsetup(devpriv->mite);
1196  mite_free(devpriv->mite);
1197  }
1198  }
1199 }
1200 
1201 static struct comedi_driver ni_pcidio_driver = {
1202  .driver_name = "ni_pcidio",
1203  .module = THIS_MODULE,
1204  .attach_pci = nidio_attach_pci,
1205  .detach = nidio_detach,
1206 };
1207 
1208 static int __devinit ni_pcidio_pci_probe(struct pci_dev *dev,
1209  const struct pci_device_id *ent)
1210 {
1211  return comedi_pci_auto_config(dev, &ni_pcidio_driver);
1212 }
1213 
1214 static void __devexit ni_pcidio_pci_remove(struct pci_dev *dev)
1215 {
1216  comedi_pci_auto_unconfig(dev);
1217 }
1218 
1219 static DEFINE_PCI_DEVICE_TABLE(ni_pcidio_pci_table) = {
1220  { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1150) },
1221  { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1320) },
1222  { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x12b0) },
1223  { 0 }
1224 };
1225 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
1226 
1227 static struct pci_driver ni_pcidio_pci_driver = {
1228  .name = "ni_pcidio",
1229  .id_table = ni_pcidio_pci_table,
1230  .probe = ni_pcidio_pci_probe,
1231  .remove = __devexit_p(ni_pcidio_pci_remove),
1232 };
1233 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1234 
1235 MODULE_AUTHOR("Comedi http://www.comedi.org");
1236 MODULE_DESCRIPTION("Comedi low-level driver");
1237 MODULE_LICENSE("GPL");
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