|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
Go to the source code of this file.
Data Structures | |
| struct | uart_pmac_port |
Macros | |
| #define | MAX_ZS_PORTS 4 |
| #define | NUM_ZSREGS 17 |
| #define | PMACZILOG_FLAG_IS_CONS 0x00000001 |
| #define | PMACZILOG_FLAG_IS_KGDB 0x00000002 |
| #define | PMACZILOG_FLAG_MODEM_STATUS 0x00000004 |
| #define | PMACZILOG_FLAG_IS_CHANNEL_A 0x00000008 |
| #define | PMACZILOG_FLAG_REGS_HELD 0x00000010 |
| #define | PMACZILOG_FLAG_TX_STOPPED 0x00000020 |
| #define | PMACZILOG_FLAG_TX_ACTIVE 0x00000040 |
| #define | PMACZILOG_FLAG_IS_IRDA 0x00000100 |
| #define | PMACZILOG_FLAG_IS_INTMODEM 0x00000200 |
| #define | PMACZILOG_FLAG_HAS_DMA 0x00000400 |
| #define | PMACZILOG_FLAG_RSRC_REQUESTED 0x00000800 |
| #define | PMACZILOG_FLAG_IS_OPEN 0x00002000 |
| #define | PMACZILOG_FLAG_IS_EXTCLK 0x00008000 |
| #define | PMACZILOG_FLAG_BREAK 0x00010000 |
| #define | to_pmz(p) ((struct uart_pmac_port *)(p)) |
| #define | BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) |
| #define | BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) |
| #define | ZS_CLOCK 3686400 /* Z8530 RTxC input clock rate */ |
| #define | FLAG 0x7e |
| #define | R0 0 /* Register selects */ |
| #define | R1 1 |
| #define | R2 2 |
| #define | R3 3 |
| #define | R4 4 |
| #define | R5 5 |
| #define | R6 6 |
| #define | R7 7 |
| #define | R8 8 |
| #define | R9 9 |
| #define | R10 10 |
| #define | R11 11 |
| #define | R12 12 |
| #define | R13 13 |
| #define | R14 14 |
| #define | R15 15 |
| #define | R7P 16 |
| #define | NULLCODE 0 /* Null Code */ |
| #define | POINT_HIGH 0x8 /* Select upper half of registers */ |
| #define | RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ |
| #define | SEND_ABORT 0x18 /* HDLC Abort */ |
| #define | RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ |
| #define | RES_Tx_P 0x28 /* Reset TxINT Pending */ |
| #define | ERR_RES 0x30 /* Error Reset */ |
| #define | RES_H_IUS 0x38 /* Reset highest IUS */ |
| #define | RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ |
| #define | RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ |
| #define | RES_EOM_L 0xC0 /* Reset EOM latch */ |
| #define | EXT_INT_ENAB 0x1 /* Ext Int Enable */ |
| #define | TxINT_ENAB 0x2 /* Tx Int Enable */ |
| #define | PAR_SPEC 0x4 /* Parity is special condition */ |
| #define | RxINT_DISAB 0 /* Rx Int Disable */ |
| #define | RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */ |
| #define | INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */ |
| #define | INT_ERR_Rx 0x18 /* Int on error only */ |
| #define | RxINT_MASK 0x18 |
| #define | WT_RDY_RT 0x20 /* W/Req reflects recv if 1, xmit if 0 */ |
| #define | WT_FN_RDYFN 0x40 /* W/Req pin is DMA request if 1, wait if 0 */ |
| #define | WT_RDY_ENAB 0x80 /* Enable W/Req pin */ |
| #define | RxENABLE 0x1 /* Rx Enable */ |
| #define | SYNC_L_INH 0x2 /* Sync Character Load Inhibit */ |
| #define | ADD_SM 0x4 /* Address Search Mode (SDLC) */ |
| #define | RxCRC_ENAB 0x8 /* Rx CRC Enable */ |
| #define | ENT_HM 0x10 /* Enter Hunt Mode */ |
| #define | AUTO_ENAB 0x20 /* Auto Enables */ |
| #define | Rx5 0x0 /* Rx 5 Bits/Character */ |
| #define | Rx7 0x40 /* Rx 7 Bits/Character */ |
| #define | Rx6 0x80 /* Rx 6 Bits/Character */ |
| #define | Rx8 0xc0 /* Rx 8 Bits/Character */ |
| #define | RxN_MASK 0xc0 |
| #define | PAR_ENAB 0x1 /* Parity Enable */ |
| #define | PAR_EVEN 0x2 /* Parity Even/Odd* */ |
| #define | SYNC_ENAB 0 /* Sync Modes Enable */ |
| #define | SB1 0x4 /* 1 stop bit/char */ |
| #define | SB15 0x8 /* 1.5 stop bits/char */ |
| #define | SB2 0xc /* 2 stop bits/char */ |
| #define | SB_MASK 0xc |
| #define | MONSYNC 0 /* 8 Bit Sync character */ |
| #define | BISYNC 0x10 /* 16 bit sync character */ |
| #define | SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */ |
| #define | EXTSYNC 0x30 /* External Sync Mode */ |
| #define | X1CLK 0x0 /* x1 clock mode */ |
| #define | X16CLK 0x40 /* x16 clock mode */ |
| #define | X32CLK 0x80 /* x32 clock mode */ |
| #define | X64CLK 0xC0 /* x64 clock mode */ |
| #define | XCLK_MASK 0xC0 |
| #define | TxCRC_ENAB 0x1 /* Tx CRC Enable */ |
| #define | RTS 0x2 /* RTS */ |
| #define | SDLC_CRC 0x4 /* SDLC/CRC-16 */ |
| #define | TxENABLE 0x8 /* Tx Enable */ |
| #define | SND_BRK 0x10 /* Send Break */ |
| #define | Tx5 0x0 /* Tx 5 bits (or less)/character */ |
| #define | Tx7 0x20 /* Tx 7 bits/character */ |
| #define | Tx6 0x40 /* Tx 6 bits/character */ |
| #define | Tx8 0x60 /* Tx 8 bits/character */ |
| #define | TxN_MASK 0x60 |
| #define | DTR 0x80 /* DTR */ |
| #define | ENEXREAD 0x40 /* Enable read of some write registers */ |
| #define | VIS 1 /* Vector Includes Status */ |
| #define | NV 2 /* No Vector */ |
| #define | DLC 4 /* Disable Lower Chain */ |
| #define | MIE 8 /* Master Interrupt Enable */ |
| #define | STATHI 0x10 /* Status high */ |
| #define | NORESET 0 /* No reset on write to R9 */ |
| #define | CHRB 0x40 /* Reset channel B */ |
| #define | CHRA 0x80 /* Reset channel A */ |
| #define | FHWRES 0xc0 /* Force hardware reset */ |
| #define | BIT6 1 /* 6 bit/8bit sync */ |
| #define | LOOPMODE 2 /* SDLC Loop mode */ |
| #define | ABUNDER 4 /* Abort/flag on SDLC xmit underrun */ |
| #define | MARKIDLE 8 /* Mark/flag on idle */ |
| #define | GAOP 0x10 /* Go active on poll */ |
| #define | NRZ 0 /* NRZ mode */ |
| #define | NRZI 0x20 /* NRZI mode */ |
| #define | FM1 0x40 /* FM1 (transition = 1) */ |
| #define | FM0 0x60 /* FM0 (transition = 0) */ |
| #define | CRCPS 0x80 /* CRC Preset I/O */ |
| #define | TRxCXT 0 /* TRxC = Xtal output */ |
| #define | TRxCTC 1 /* TRxC = Transmit clock */ |
| #define | TRxCBR 2 /* TRxC = BR Generator Output */ |
| #define | TRxCDP 3 /* TRxC = DPLL output */ |
| #define | TRxCOI 4 /* TRxC O/I */ |
| #define | TCRTxCP 0 /* Transmit clock = RTxC pin */ |
| #define | TCTRxCP 8 /* Transmit clock = TRxC pin */ |
| #define | TCBR 0x10 /* Transmit clock = BR Generator output */ |
| #define | TCDPLL 0x18 /* Transmit clock = DPLL output */ |
| #define | RCRTxCP 0 /* Receive clock = RTxC pin */ |
| #define | RCTRxCP 0x20 /* Receive clock = TRxC pin */ |
| #define | RCBR 0x40 /* Receive clock = BR Generator output */ |
| #define | RCDPLL 0x60 /* Receive clock = DPLL output */ |
| #define | RTxCX 0x80 /* RTxC Xtal/No Xtal */ |
| #define | BRENAB 1 /* Baud rate generator enable */ |
| #define | BRSRC 2 /* Baud rate generator source */ |
| #define | DTRREQ 4 /* DTR/Request function */ |
| #define | AUTOECHO 8 /* Auto Echo */ |
| #define | LOOPBAK 0x10 /* Local loopback */ |
| #define | SEARCH 0x20 /* Enter search mode */ |
| #define | RMC 0x40 /* Reset missing clock */ |
| #define | DISDPLL 0x60 /* Disable DPLL */ |
| #define | SSBR 0x80 /* Set DPLL source = BR generator */ |
| #define | SSRTxC 0xa0 /* Set DPLL source = RTxC */ |
| #define | SFMM 0xc0 /* Set FM mode */ |
| #define | SNRZI 0xe0 /* Set NRZI mode */ |
| #define | EN85C30 1 /* Enable some 85c30-enhanced registers */ |
| #define | ZCIE 2 /* Zero count IE */ |
| #define | ENSTFIFO 4 /* Enable status FIFO (SDLC) */ |
| #define | DCDIE 8 /* DCD IE */ |
| #define | SYNCIE 0x10 /* Sync/hunt IE */ |
| #define | CTSIE 0x20 /* CTS IE */ |
| #define | TxUIE 0x40 /* Tx Underrun/EOM IE */ |
| #define | BRKIE 0x80 /* Break/Abort IE */ |
| #define | Rx_CH_AV 0x1 /* Rx Character Available */ |
| #define | ZCOUNT 0x2 /* Zero count */ |
| #define | Tx_BUF_EMP 0x4 /* Tx Buffer empty */ |
| #define | DCD 0x8 /* DCD */ |
| #define | SYNC_HUNT 0x10 /* Sync/hunt */ |
| #define | CTS 0x20 /* CTS */ |
| #define | TxEOM 0x40 /* Tx underrun */ |
| #define | BRK_ABRT 0x80 /* Break/Abort */ |
| #define | ALL_SNT 0x1 /* All sent */ |
| #define | RES3 0x8 /* 0/3 */ |
| #define | RES4 0x4 /* 0/4 */ |
| #define | RES5 0xc /* 0/5 */ |
| #define | RES6 0x2 /* 0/6 */ |
| #define | RES7 0xa /* 0/7 */ |
| #define | RES8 0x6 /* 0/8 */ |
| #define | RES18 0xe /* 1/8 */ |
| #define | RES28 0x0 /* 2/8 */ |
| #define | PAR_ERR 0x10 /* Parity error */ |
| #define | Rx_OVR 0x20 /* Rx Overrun Error */ |
| #define | CRC_ERR 0x40 /* CRC/Framing Error */ |
| #define | END_FR 0x80 /* End of Frame (SDLC) */ |
| #define | CHB_Tx_EMPTY 0x00 |
| #define | CHB_EXT_STAT 0x02 |
| #define | CHB_Rx_AVAIL 0x04 |
| #define | CHB_SPECIAL 0x06 |
| #define | CHA_Tx_EMPTY 0x08 |
| #define | CHA_EXT_STAT 0x0a |
| #define | CHA_Rx_AVAIL 0x0c |
| #define | CHA_SPECIAL 0x0e |
| #define | STATUS_MASK 0x06 |
| #define | CHBEXT 0x1 /* Channel B Ext/Stat IP */ |
| #define | CHBTxIP 0x2 /* Channel B Tx IP */ |
| #define | CHBRxIP 0x4 /* Channel B Rx IP */ |
| #define | CHAEXT 0x8 /* Channel A Ext/Stat IP */ |
| #define | CHATxIP 0x10 /* Channel A Tx IP */ |
| #define | CHARxIP 0x20 /* Channel A Rx IP */ |
| #define | ONLOOP 2 /* On loop */ |
| #define | LOOPSEND 0x10 /* Loop sending */ |
| #define | CLK2MIS 0x40 /* Two clocks missing */ |
| #define | CLK1MIS 0x80 /* One clock missing */ |
| #define | ZS_CLEARERR(port) (write_zsreg(port, 0, ERR_RES)) |
| #define | ZS_CLEARFIFO(port) |
| #define | ZS_IS_CONS(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CONS) |
| #define | ZS_IS_KGDB(UP) ((UP)->flags & PMACZILOG_FLAG_IS_KGDB) |
| #define | ZS_IS_CHANNEL_A(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A) |
| #define | ZS_REGS_HELD(UP) ((UP)->flags & PMACZILOG_FLAG_REGS_HELD) |
| #define | ZS_TX_STOPPED(UP) ((UP)->flags & PMACZILOG_FLAG_TX_STOPPED) |
| #define | ZS_TX_ACTIVE(UP) ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE) |
| #define | ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS) |
| #define | ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA) |
| #define | ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM) |
| #define | ZS_HAS_DMA(UP) ((UP)->flags & PMACZILOG_FLAG_HAS_DMA) |
| #define | ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN) |
| #define | ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK) |
Definition at line 248 of file pmac_zilog.h.
| #define ADD_SM 0x4 /* Address Search Mode (SDLC) */ |
Definition at line 179 of file pmac_zilog.h.
| #define ALL_SNT 0x1 /* All sent */ |
Definition at line 313 of file pmac_zilog.h.
| #define AUTO_ENAB 0x20 /* Auto Enables */ |
Definition at line 182 of file pmac_zilog.h.
| #define AUTOECHO 8 /* Auto Echo */ |
Definition at line 281 of file pmac_zilog.h.
| #define BISYNC 0x10 /* 16 bit sync character */ |
Definition at line 201 of file pmac_zilog.h.
| #define BIT6 1 /* 6 bit/8bit sync */ |
Definition at line 246 of file pmac_zilog.h.
Definition at line 117 of file pmac_zilog.h.
Definition at line 278 of file pmac_zilog.h.
Definition at line 116 of file pmac_zilog.h.
| #define BRK_ABRT 0x80 /* Break/Abort */ |
Definition at line 310 of file pmac_zilog.h.
| #define BRKIE 0x80 /* Break/Abort IE */ |
Definition at line 299 of file pmac_zilog.h.
Definition at line 279 of file pmac_zilog.h.
| #define CHA_EXT_STAT 0x0a |
Definition at line 335 of file pmac_zilog.h.
| #define CHA_Rx_AVAIL 0x0c |
Definition at line 336 of file pmac_zilog.h.
| #define CHA_SPECIAL 0x0e |
Definition at line 337 of file pmac_zilog.h.
| #define CHA_Tx_EMPTY 0x08 |
Definition at line 334 of file pmac_zilog.h.
| #define CHAEXT 0x8 /* Channel A Ext/Stat IP */ |
Definition at line 344 of file pmac_zilog.h.
| #define CHARxIP 0x20 /* Channel A Rx IP */ |
Definition at line 346 of file pmac_zilog.h.
| #define CHATxIP 0x10 /* Channel A Tx IP */ |
Definition at line 345 of file pmac_zilog.h.
| #define CHB_EXT_STAT 0x02 |
Definition at line 331 of file pmac_zilog.h.
| #define CHB_Rx_AVAIL 0x04 |
Definition at line 332 of file pmac_zilog.h.
| #define CHB_SPECIAL 0x06 |
Definition at line 333 of file pmac_zilog.h.
| #define CHB_Tx_EMPTY 0x00 |
Definition at line 330 of file pmac_zilog.h.
| #define CHBEXT 0x1 /* Channel B Ext/Stat IP */ |
Definition at line 341 of file pmac_zilog.h.
| #define CHBRxIP 0x4 /* Channel B Rx IP */ |
Definition at line 343 of file pmac_zilog.h.
| #define CHBTxIP 0x2 /* Channel B Tx IP */ |
Definition at line 342 of file pmac_zilog.h.
| #define CHRA 0x80 /* Reset channel A */ |
Definition at line 242 of file pmac_zilog.h.
| #define CHRB 0x40 /* Reset channel B */ |
Definition at line 241 of file pmac_zilog.h.
| #define CLK1MIS 0x80 /* One clock missing */ |
Definition at line 354 of file pmac_zilog.h.
| #define CLK2MIS 0x40 /* Two clocks missing */ |
Definition at line 353 of file pmac_zilog.h.
| #define CRC_ERR 0x40 /* CRC/Framing Error */ |
Definition at line 326 of file pmac_zilog.h.
| #define CRCPS 0x80 /* CRC Preset I/O */ |
Definition at line 255 of file pmac_zilog.h.
| #define CTS 0x20 /* CTS */ |
Definition at line 308 of file pmac_zilog.h.
| #define CTSIE 0x20 /* CTS IE */ |
Definition at line 297 of file pmac_zilog.h.
| #define DCD 0x8 /* DCD */ |
Definition at line 306 of file pmac_zilog.h.
Definition at line 295 of file pmac_zilog.h.
| #define DISDPLL 0x60 /* Disable DPLL */ |
Definition at line 285 of file pmac_zilog.h.
| #define DLC 4 /* Disable Lower Chain */ |
Definition at line 237 of file pmac_zilog.h.
| #define DTR 0x80 /* DTR */ |
Definition at line 223 of file pmac_zilog.h.
Definition at line 280 of file pmac_zilog.h.
| #define EN85C30 1 /* Enable some 85c30-enhanced registers */ |
Definition at line 292 of file pmac_zilog.h.
| #define END_FR 0x80 /* End of Frame (SDLC) */ |
Definition at line 327 of file pmac_zilog.h.
| #define ENEXREAD 0x40 /* Enable read of some write registers */ |
Definition at line 230 of file pmac_zilog.h.
Definition at line 294 of file pmac_zilog.h.
| #define ENT_HM 0x10 /* Enter Hunt Mode */ |
Definition at line 181 of file pmac_zilog.h.
| #define ERR_RES 0x30 /* Error Reset */ |
Definition at line 150 of file pmac_zilog.h.
| #define EXT_INT_ENAB 0x1 /* Ext Int Enable */ |
Definition at line 159 of file pmac_zilog.h.
| #define EXTSYNC 0x30 /* External Sync Mode */ |
Definition at line 203 of file pmac_zilog.h.
| #define FHWRES 0xc0 /* Force hardware reset */ |
Definition at line 243 of file pmac_zilog.h.
| #define FLAG 0x7e |
Definition at line 123 of file pmac_zilog.h.
| #define FM0 0x60 /* FM0 (transition = 0) */ |
Definition at line 254 of file pmac_zilog.h.
| #define FM1 0x40 /* FM1 (transition = 1) */ |
Definition at line 253 of file pmac_zilog.h.
| #define GAOP 0x10 /* Go active on poll */ |
Definition at line 250 of file pmac_zilog.h.
| #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */ |
Definition at line 165 of file pmac_zilog.h.
| #define INT_ERR_Rx 0x18 /* Int on error only */ |
Definition at line 166 of file pmac_zilog.h.
| #define LOOPBAK 0x10 /* Local loopback */ |
Definition at line 282 of file pmac_zilog.h.
Definition at line 247 of file pmac_zilog.h.
| #define LOOPSEND 0x10 /* Loop sending */ |
Definition at line 352 of file pmac_zilog.h.
Definition at line 249 of file pmac_zilog.h.
| #define MAX_ZS_PORTS 4 |
Definition at line 7 of file pmac_zilog.h.
| #define MIE 8 /* Master Interrupt Enable */ |
Definition at line 238 of file pmac_zilog.h.
Definition at line 200 of file pmac_zilog.h.
| #define NRZ 0 /* NRZ mode */ |
Definition at line 251 of file pmac_zilog.h.
| #define NRZI 0x20 /* NRZI mode */ |
Definition at line 252 of file pmac_zilog.h.
Definition at line 144 of file pmac_zilog.h.
| #define NUM_ZSREGS 17 |
Definition at line 12 of file pmac_zilog.h.
| #define NV 2 /* No Vector */ |
Definition at line 236 of file pmac_zilog.h.
| #define ONLOOP 2 /* On loop */ |
Definition at line 351 of file pmac_zilog.h.
| #define PAR_ENAB 0x1 /* Parity Enable */ |
Definition at line 191 of file pmac_zilog.h.
| #define PAR_ERR 0x10 /* Parity error */ |
Definition at line 324 of file pmac_zilog.h.
| #define PAR_EVEN 0x2 /* Parity Even/Odd* */ |
Definition at line 192 of file pmac_zilog.h.
| #define PAR_SPEC 0x4 /* Parity is special condition */ |
Definition at line 161 of file pmac_zilog.h.
| #define PMACZILOG_FLAG_BREAK 0x00010000 |
Definition at line 49 of file pmac_zilog.h.
| #define PMACZILOG_FLAG_HAS_DMA 0x00000400 |
Definition at line 45 of file pmac_zilog.h.
| #define PMACZILOG_FLAG_IS_CHANNEL_A 0x00000008 |
Definition at line 39 of file pmac_zilog.h.
| #define PMACZILOG_FLAG_IS_CONS 0x00000001 |
Definition at line 36 of file pmac_zilog.h.
| #define PMACZILOG_FLAG_IS_EXTCLK 0x00008000 |
Definition at line 48 of file pmac_zilog.h.
| #define PMACZILOG_FLAG_IS_INTMODEM 0x00000200 |
Definition at line 44 of file pmac_zilog.h.
| #define PMACZILOG_FLAG_IS_IRDA 0x00000100 |
Definition at line 43 of file pmac_zilog.h.
| #define PMACZILOG_FLAG_IS_KGDB 0x00000002 |
Definition at line 37 of file pmac_zilog.h.
| #define PMACZILOG_FLAG_IS_OPEN 0x00002000 |
Definition at line 47 of file pmac_zilog.h.
| #define PMACZILOG_FLAG_MODEM_STATUS 0x00000004 |
Definition at line 38 of file pmac_zilog.h.
| #define PMACZILOG_FLAG_REGS_HELD 0x00000010 |
Definition at line 40 of file pmac_zilog.h.
| #define PMACZILOG_FLAG_RSRC_REQUESTED 0x00000800 |
Definition at line 46 of file pmac_zilog.h.
| #define PMACZILOG_FLAG_TX_ACTIVE 0x00000040 |
Definition at line 42 of file pmac_zilog.h.
| #define PMACZILOG_FLAG_TX_STOPPED 0x00000020 |
Definition at line 41 of file pmac_zilog.h.
| #define POINT_HIGH 0x8 /* Select upper half of registers */ |
Definition at line 145 of file pmac_zilog.h.
| #define R0 0 /* Register selects */ |
Definition at line 126 of file pmac_zilog.h.
| #define R1 1 |
Definition at line 127 of file pmac_zilog.h.
| #define R10 10 |
Definition at line 136 of file pmac_zilog.h.
| #define R11 11 |
Definition at line 137 of file pmac_zilog.h.
| #define R12 12 |
Definition at line 138 of file pmac_zilog.h.
| #define R13 13 |
Definition at line 139 of file pmac_zilog.h.
| #define R14 14 |
Definition at line 140 of file pmac_zilog.h.
| #define R15 15 |
Definition at line 141 of file pmac_zilog.h.
| #define R2 2 |
Definition at line 128 of file pmac_zilog.h.
| #define R3 3 |
Definition at line 129 of file pmac_zilog.h.
| #define R4 4 |
Definition at line 130 of file pmac_zilog.h.
| #define R5 5 |
Definition at line 131 of file pmac_zilog.h.
| #define R6 6 |
Definition at line 132 of file pmac_zilog.h.
| #define R7 7 |
Definition at line 133 of file pmac_zilog.h.
| #define R7P 16 |
Definition at line 142 of file pmac_zilog.h.
| #define R8 8 |
Definition at line 134 of file pmac_zilog.h.
| #define R9 9 |
Definition at line 135 of file pmac_zilog.h.
| #define RCBR 0x40 /* Receive clock = BR Generator output */ |
Definition at line 269 of file pmac_zilog.h.
| #define RCDPLL 0x60 /* Receive clock = DPLL output */ |
Definition at line 270 of file pmac_zilog.h.
Definition at line 267 of file pmac_zilog.h.
| #define RCTRxCP 0x20 /* Receive clock = TRxC pin */ |
Definition at line 268 of file pmac_zilog.h.
| #define RES18 0xe /* 1/8 */ |
Definition at line 321 of file pmac_zilog.h.
| #define RES28 0x0 /* 2/8 */ |
Definition at line 322 of file pmac_zilog.h.
| #define RES3 0x8 /* 0/3 */ |
Definition at line 315 of file pmac_zilog.h.
| #define RES4 0x4 /* 0/4 */ |
Definition at line 316 of file pmac_zilog.h.
| #define RES5 0xc /* 0/5 */ |
Definition at line 317 of file pmac_zilog.h.
| #define RES6 0x2 /* 0/6 */ |
Definition at line 318 of file pmac_zilog.h.
| #define RES7 0xa /* 0/7 */ |
Definition at line 319 of file pmac_zilog.h.
| #define RES8 0x6 /* 0/8 */ |
Definition at line 320 of file pmac_zilog.h.
| #define RES_EOM_L 0xC0 /* Reset EOM latch */ |
Definition at line 155 of file pmac_zilog.h.
| #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ |
Definition at line 146 of file pmac_zilog.h.
| #define RES_H_IUS 0x38 /* Reset highest IUS */ |
Definition at line 151 of file pmac_zilog.h.
| #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ |
Definition at line 153 of file pmac_zilog.h.
| #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ |
Definition at line 148 of file pmac_zilog.h.
| #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ |
Definition at line 154 of file pmac_zilog.h.
| #define RES_Tx_P 0x28 /* Reset TxINT Pending */ |
Definition at line 149 of file pmac_zilog.h.
| #define RMC 0x40 /* Reset missing clock */ |
Definition at line 284 of file pmac_zilog.h.
| #define RTS 0x2 /* RTS */ |
Definition at line 214 of file pmac_zilog.h.
| #define RTxCX 0x80 /* RTxC Xtal/No Xtal */ |
Definition at line 271 of file pmac_zilog.h.
| #define Rx5 0x0 /* Rx 5 Bits/Character */ |
Definition at line 183 of file pmac_zilog.h.
| #define Rx6 0x80 /* Rx 6 Bits/Character */ |
Definition at line 185 of file pmac_zilog.h.
| #define Rx7 0x40 /* Rx 7 Bits/Character */ |
Definition at line 184 of file pmac_zilog.h.
| #define Rx8 0xc0 /* Rx 8 Bits/Character */ |
Definition at line 186 of file pmac_zilog.h.
| #define Rx_CH_AV 0x1 /* Rx Character Available */ |
Definition at line 303 of file pmac_zilog.h.
| #define Rx_OVR 0x20 /* Rx Overrun Error */ |
Definition at line 325 of file pmac_zilog.h.
| #define RxCRC_ENAB 0x8 /* Rx CRC Enable */ |
Definition at line 180 of file pmac_zilog.h.
| #define RxENABLE 0x1 /* Rx Enable */ |
Definition at line 177 of file pmac_zilog.h.
| #define RxINT_DISAB 0 /* Rx Int Disable */ |
Definition at line 163 of file pmac_zilog.h.
| #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */ |
Definition at line 164 of file pmac_zilog.h.
| #define RxINT_MASK 0x18 |
Definition at line 167 of file pmac_zilog.h.
| #define RxN_MASK 0xc0 |
Definition at line 187 of file pmac_zilog.h.
| #define SB1 0x4 /* 1 stop bit/char */ |
Definition at line 195 of file pmac_zilog.h.
| #define SB15 0x8 /* 1.5 stop bits/char */ |
Definition at line 196 of file pmac_zilog.h.
| #define SB2 0xc /* 2 stop bits/char */ |
Definition at line 197 of file pmac_zilog.h.
| #define SB_MASK 0xc |
Definition at line 198 of file pmac_zilog.h.
| #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */ |
Definition at line 202 of file pmac_zilog.h.
| #define SDLC_CRC 0x4 /* SDLC/CRC-16 */ |
Definition at line 215 of file pmac_zilog.h.
| #define SEARCH 0x20 /* Enter search mode */ |
Definition at line 283 of file pmac_zilog.h.
| #define SEND_ABORT 0x18 /* HDLC Abort */ |
Definition at line 147 of file pmac_zilog.h.
| #define SFMM 0xc0 /* Set FM mode */ |
Definition at line 288 of file pmac_zilog.h.
| #define SND_BRK 0x10 /* Send Break */ |
Definition at line 217 of file pmac_zilog.h.
| #define SNRZI 0xe0 /* Set NRZI mode */ |
Definition at line 289 of file pmac_zilog.h.
| #define SSBR 0x80 /* Set DPLL source = BR generator */ |
Definition at line 286 of file pmac_zilog.h.
| #define SSRTxC 0xa0 /* Set DPLL source = RTxC */ |
Definition at line 287 of file pmac_zilog.h.
| #define STATHI 0x10 /* Status high */ |
Definition at line 239 of file pmac_zilog.h.
| #define STATUS_MASK 0x06 |
Definition at line 338 of file pmac_zilog.h.
| #define SYNC_ENAB 0 /* Sync Modes Enable */ |
Definition at line 194 of file pmac_zilog.h.
| #define SYNC_HUNT 0x10 /* Sync/hunt */ |
Definition at line 307 of file pmac_zilog.h.
| #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */ |
Definition at line 178 of file pmac_zilog.h.
| #define SYNCIE 0x10 /* Sync/hunt IE */ |
Definition at line 296 of file pmac_zilog.h.
| #define TCBR 0x10 /* Transmit clock = BR Generator output */ |
Definition at line 265 of file pmac_zilog.h.
| #define TCDPLL 0x18 /* Transmit clock = DPLL output */ |
Definition at line 266 of file pmac_zilog.h.
Definition at line 263 of file pmac_zilog.h.
Definition at line 264 of file pmac_zilog.h.
| #define to_pmz | ( | p | ) | ((struct uart_pmac_port *)(p)) |
Definition at line 69 of file pmac_zilog.h.
Definition at line 260 of file pmac_zilog.h.
Definition at line 261 of file pmac_zilog.h.
| #define TRxCOI 4 /* TRxC O/I */ |
Definition at line 262 of file pmac_zilog.h.
Definition at line 259 of file pmac_zilog.h.
| #define TRxCXT 0 /* TRxC = Xtal output */ |
Definition at line 258 of file pmac_zilog.h.
| #define Tx5 0x0 /* Tx 5 bits (or less)/character */ |
Definition at line 218 of file pmac_zilog.h.
| #define Tx6 0x40 /* Tx 6 bits/character */ |
Definition at line 220 of file pmac_zilog.h.
| #define Tx7 0x20 /* Tx 7 bits/character */ |
Definition at line 219 of file pmac_zilog.h.
| #define Tx8 0x60 /* Tx 8 bits/character */ |
Definition at line 221 of file pmac_zilog.h.
| #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */ |
Definition at line 305 of file pmac_zilog.h.
| #define TxCRC_ENAB 0x1 /* Tx CRC Enable */ |
Definition at line 213 of file pmac_zilog.h.
| #define TxENABLE 0x8 /* Tx Enable */ |
Definition at line 216 of file pmac_zilog.h.
| #define TxEOM 0x40 /* Tx underrun */ |
Definition at line 309 of file pmac_zilog.h.
| #define TxINT_ENAB 0x2 /* Tx Int Enable */ |
Definition at line 160 of file pmac_zilog.h.
| #define TxN_MASK 0x60 |
Definition at line 222 of file pmac_zilog.h.
| #define TxUIE 0x40 /* Tx Underrun/EOM IE */ |
Definition at line 298 of file pmac_zilog.h.
| #define VIS 1 /* Vector Includes Status */ |
Definition at line 235 of file pmac_zilog.h.
| #define WT_FN_RDYFN 0x40 /* W/Req pin is DMA request if 1, wait if 0 */ |
Definition at line 170 of file pmac_zilog.h.
| #define WT_RDY_ENAB 0x80 /* Enable W/Req pin */ |
Definition at line 171 of file pmac_zilog.h.
| #define WT_RDY_RT 0x20 /* W/Req reflects recv if 1, xmit if 0 */ |
Definition at line 169 of file pmac_zilog.h.
| #define X16CLK 0x40 /* x16 clock mode */ |
Definition at line 206 of file pmac_zilog.h.
| #define X1CLK 0x0 /* x1 clock mode */ |
Definition at line 205 of file pmac_zilog.h.
| #define X32CLK 0x80 /* x32 clock mode */ |
Definition at line 207 of file pmac_zilog.h.
| #define X64CLK 0xC0 /* x64 clock mode */ |
Definition at line 208 of file pmac_zilog.h.
| #define XCLK_MASK 0xC0 |
Definition at line 209 of file pmac_zilog.h.
Definition at line 293 of file pmac_zilog.h.
| #define ZCOUNT 0x2 /* Zero count */ |
Definition at line 304 of file pmac_zilog.h.
Definition at line 363 of file pmac_zilog.h.
| #define ZS_CLEARFIFO | ( | port | ) |
Definition at line 364 of file pmac_zilog.h.
Definition at line 119 of file pmac_zilog.h.
| #define ZS_HAS_DMA | ( | UP | ) | ((UP)->flags & PMACZILOG_FLAG_HAS_DMA) |
Definition at line 379 of file pmac_zilog.h.
| #define ZS_IS_CHANNEL_A | ( | UP | ) | ((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A) |
Definition at line 372 of file pmac_zilog.h.
| #define ZS_IS_CONS | ( | UP | ) | ((UP)->flags & PMACZILOG_FLAG_IS_CONS) |
Definition at line 370 of file pmac_zilog.h.
| #define ZS_IS_EXTCLK | ( | UP | ) | ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK) |
Definition at line 381 of file pmac_zilog.h.
| #define ZS_IS_INTMODEM | ( | UP | ) | ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM) |
Definition at line 378 of file pmac_zilog.h.
| #define ZS_IS_IRDA | ( | UP | ) | ((UP)->flags & PMACZILOG_FLAG_IS_IRDA) |
Definition at line 377 of file pmac_zilog.h.
| #define ZS_IS_KGDB | ( | UP | ) | ((UP)->flags & PMACZILOG_FLAG_IS_KGDB) |
Definition at line 371 of file pmac_zilog.h.
| #define ZS_IS_OPEN | ( | UP | ) | ((UP)->flags & PMACZILOG_FLAG_IS_OPEN) |
Definition at line 380 of file pmac_zilog.h.
| #define ZS_REGS_HELD | ( | UP | ) | ((UP)->flags & PMACZILOG_FLAG_REGS_HELD) |
Definition at line 373 of file pmac_zilog.h.
| #define ZS_TX_ACTIVE | ( | UP | ) | ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE) |
Definition at line 375 of file pmac_zilog.h.
| #define ZS_TX_STOPPED | ( | UP | ) | ((UP)->flags & PMACZILOG_FLAG_TX_STOPPED) |
Definition at line 374 of file pmac_zilog.h.
| #define ZS_WANTS_MODEM_STATUS | ( | UP | ) | ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS) |
Definition at line 376 of file pmac_zilog.h.
1.8.2