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#define | _QLCNIC_LINUX_MAJOR 5 |
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#define | _QLCNIC_LINUX_MINOR 0 |
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#define | _QLCNIC_LINUX_SUBVERSION 29 |
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#define | QLCNIC_LINUX_VERSIONID "5.0.29" |
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#define | QLCNIC_DRV_IDC_VER 0x01 |
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#define | QLCNIC_DRIVER_VERSION |
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#define | QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) |
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#define | _major(v) (((v) >> 24) & 0xff) |
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#define | _minor(v) (((v) >> 16) & 0xff) |
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#define | _build(v) ((v) & 0xffff) |
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#define | QLCNIC_DECODE_VERSION(v) QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) |
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#define | QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) |
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#define | QLCNIC_NUM_FLASH_SECTORS (64) |
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#define | QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) |
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#define | QLCNIC_FLASH_TOTAL_SIZE |
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#define | RCV_DESC_RINGSIZE(rds_ring) (sizeof(struct rcv_desc) * (rds_ring)->num_desc) |
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#define | RCV_BUFF_RINGSIZE(rds_ring) (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) |
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#define | STATUS_DESC_RINGSIZE(sds_ring) (sizeof(struct status_desc) * (sds_ring)->num_desc) |
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#define | TX_BUFF_RINGSIZE(tx_ring) (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) |
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#define | TX_DESC_RINGSIZE(tx_ring) (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) |
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#define | QLCNIC_P3P_A0 0x50 |
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#define | QLCNIC_P3P_C0 0x58 |
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#define | QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) |
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#define | FIRST_PAGE_GROUP_START 0 |
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#define | FIRST_PAGE_GROUP_END 0x100000 |
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#define | P3P_MAX_MTU (9600) |
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#define | P3P_MIN_MTU (68) |
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#define | QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ |
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#define | QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) |
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#define | QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) |
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#define | QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 |
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#define | QLCNIC_LRO_BUFFER_EXTRA 2048 |
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#define | TX_ETHER_PKT 0x01 |
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#define | TX_TCP_PKT 0x02 |
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#define | TX_UDP_PKT 0x03 |
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#define | TX_IP_PKT 0x04 |
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#define | TX_TCP_LSO 0x05 |
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#define | TX_TCP_LSO6 0x06 |
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#define | TX_TCPV6_PKT 0x0b |
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#define | TX_UDPV6_PKT 0x0c |
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#define | QLCNIC_MAX_FRAGS_PER_TX 14 |
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#define | MAX_TSO_HEADER_DESC 2 |
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#define | MGMT_CMD_DESC_RESV 4 |
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#define | TX_STOP_THRESH |
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#define | QLCNIC_MAX_TX_TIMEOUTS 2 |
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#define | PHAN_INITIALIZE_FAILED 0xffff |
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#define | PHAN_INITIALIZE_COMPLETE 0xff01 |
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#define | PHAN_INITIALIZE_ACK 0xf00f |
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#define | PHAN_PEG_RCV_INITIALIZED 0xff01 |
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#define | NUM_RCV_DESC_RINGS 3 |
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#define | RCV_RING_NORMAL 0 |
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#define | RCV_RING_JUMBO 1 |
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#define | MIN_CMD_DESCRIPTORS 64 |
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#define | MIN_RCV_DESCRIPTORS 64 |
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#define | MIN_JUMBO_DESCRIPTORS 32 |
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#define | MAX_CMD_DESCRIPTORS 1024 |
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#define | MAX_RCV_DESCRIPTORS_1G 4096 |
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#define | MAX_RCV_DESCRIPTORS_10G 8192 |
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#define | MAX_RCV_DESCRIPTORS_VF 2048 |
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#define | MAX_JUMBO_RCV_DESCRIPTORS_1G 512 |
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#define | MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 |
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#define | DEFAULT_RCV_DESCRIPTORS_1G 2048 |
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#define | DEFAULT_RCV_DESCRIPTORS_10G 4096 |
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#define | DEFAULT_RCV_DESCRIPTORS_VF 1024 |
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#define | MAX_RDS_RINGS 2 |
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#define | get_next_index(index, length) (((index) + 1) & ((length) - 1)) |
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#define | FLAGS_VLAN_TAGGED 0x10 |
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#define | FLAGS_VLAN_OOB 0x40 |
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#define | qlcnic_set_tx_vlan_tci(cmd_desc, v) (cmd_desc)->vlan_TCI = cpu_to_le16(v); |
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#define | qlcnic_set_cmd_desc_port(cmd_desc, var) ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) |
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#define | qlcnic_set_cmd_desc_ctxid(cmd_desc, var) ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0)) |
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#define | qlcnic_set_tx_port(_desc, _port) ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)) |
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#define | qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) |
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#define | qlcnic_set_tx_frags_len(_desc, _frags, _len) |
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#define | QLCNIC_SYN_OFFLOAD 0x03 |
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#define | QLCNIC_RXPKT_DESC 0x04 |
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#define | QLCNIC_OLD_RXPKT_DESC 0x3f |
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#define | QLCNIC_RESPONSE_DESC 0x05 |
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#define | QLCNIC_LRO_DESC 0x12 |
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#define | STATUS_CKSUM_LOOP 0 |
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#define | STATUS_CKSUM_OK 2 |
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#define | STATUS_OWNER_HOST (0x1ULL << 56) |
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#define | STATUS_OWNER_PHANTOM (0x2ULL << 56) |
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#define | qlcnic_get_sts_port(sts_data) ((sts_data) & 0x0F) |
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#define | qlcnic_get_sts_status(sts_data) (((sts_data) >> 4) & 0x0F) |
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#define | qlcnic_get_sts_type(sts_data) (((sts_data) >> 8) & 0x0F) |
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#define | qlcnic_get_sts_totallength(sts_data) (((sts_data) >> 12) & 0xFFFF) |
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#define | qlcnic_get_sts_refhandle(sts_data) (((sts_data) >> 28) & 0xFFFF) |
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#define | qlcnic_get_sts_prot(sts_data) (((sts_data) >> 44) & 0x0F) |
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#define | qlcnic_get_sts_pkt_offset(sts_data) (((sts_data) >> 48) & 0x1F) |
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#define | qlcnic_get_sts_desc_cnt(sts_data) (((sts_data) >> 53) & 0x7) |
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#define | qlcnic_get_sts_opcode(sts_data) (((sts_data) >> 58) & 0x03F) |
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#define | qlcnic_get_lro_sts_refhandle(sts_data) ((sts_data) & 0x0FFFF) |
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#define | qlcnic_get_lro_sts_length(sts_data) (((sts_data) >> 16) & 0x0FFFF) |
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#define | qlcnic_get_lro_sts_l2_hdr_offset(sts_data) (((sts_data) >> 32) & 0x0FF) |
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#define | qlcnic_get_lro_sts_l4_hdr_offset(sts_data) (((sts_data) >> 40) & 0x0FF) |
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#define | qlcnic_get_lro_sts_timestamp(sts_data) (((sts_data) >> 48) & 0x1) |
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#define | qlcnic_get_lro_sts_type(sts_data) (((sts_data) >> 49) & 0x7) |
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#define | qlcnic_get_lro_sts_push_flag(sts_data) (((sts_data) >> 52) & 0x1) |
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#define | qlcnic_get_lro_sts_seq_number(sts_data) ((sts_data) & 0x0FFFFFFFF) |
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#define | qlcnic_get_lro_sts_mss(sts_data1) ((sts_data1 >> 32) & 0x0FFFF) |
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#define | QLCNIC_UNI_FW_MIN_SIZE 0xc8000 |
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#define | QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 |
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#define | QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 |
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#define | QLCNIC_UNI_DIR_SECT_FW 0x7 |
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#define | QLCNIC_UNI_CHIP_REV_OFF 10 |
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#define | QLCNIC_UNI_FLAGS_OFF 11 |
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#define | QLCNIC_UNI_BIOS_VERSION_OFF 12 |
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#define | QLCNIC_UNI_BOOTLD_IDX_OFF 27 |
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#define | QLCNIC_UNI_FIRMWARE_IDX_OFF 29 |
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#define | QLCNIC_FLT_LOCATION 0x3F1000 |
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#define | QLCNIC_B0_FW_IMAGE_REGION 0x74 |
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#define | QLCNIC_C0_FW_IMAGE_REGION 0x97 |
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#define | QLCNIC_BOOTLD_REGION 0X72 |
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#define | QLCNIC_BDINFO_MAGIC 0x12345678 |
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#define | QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 |
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#define | QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 |
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#define | QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 |
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#define | QLCNIC_BRDTYPE_P3P_4_GB 0x0024 |
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#define | QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 |
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#define | QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 |
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#define | QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 |
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#define | QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 |
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#define | QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 |
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#define | QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a |
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#define | QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b |
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#define | QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 |
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#define | QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 |
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#define | QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 |
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#define | QLCNIC_MSIX_TABLE_OFFSET 0x44 |
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#define | QLCNIC_BRDCFG_START 0x4000 /* board config */ |
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#define | QLCNIC_BOOTLD_START 0x10000 /* bootld */ |
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#define | QLCNIC_IMAGE_START 0x43000 /* compressed image */ |
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#define | QLCNIC_USER_START 0x3E8000 /* Firmare info */ |
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#define | QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) |
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#define | QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) |
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#define | QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) |
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#define | QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) |
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#define | QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) |
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#define | QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) |
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#define | QLCNIC_FW_MIN_SIZE (0x3fffff) |
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#define | QLCNIC_UNIFIED_ROMIMAGE 0 |
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#define | QLCNIC_FLASH_ROMIMAGE 1 |
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#define | QLCNIC_UNKNOWN_ROMIMAGE 0xff |
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#define | QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" |
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#define | QLCNIC_FLASH_ROMIMAGE_NAME "flash" |
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#define | MAX_STATUS_HANDLE (64) |
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#define | QLCNIC_BUFFER_FREE 0 |
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#define | QLCNIC_BUFFER_BUSY 1 |
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#define | QLCNIC_GBE 0x01 |
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#define | QLCNIC_XGBE 0x02 |
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#define | QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3 |
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#define | QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256 |
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#define | QLCNIC_INTR_DEFAULT 0x04 |
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#define | QLCNIC_CONFIG_INTR_COALESCE 3 |
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#define | QLCNIC_OS_CRB_RETRY_COUNT 4000 |
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#define | QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16)) |
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#define | QLCNIC_CDRP_CMD_BIT 0x80000000 |
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#define | QLCNIC_CDRP_FORM_RSP(rsp) (rsp) |
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#define | QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) |
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#define | QLCNIC_CDRP_RSP_OK 0x00000001 |
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#define | QLCNIC_CDRP_RSP_FAIL 0x00000002 |
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#define | QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 |
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#define | QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) |
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#define | QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0) |
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#define | QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 |
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#define | QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 |
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#define | QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 |
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#define | QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 |
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#define | QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 |
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#define | QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 |
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#define | QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007 |
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#define | QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008 |
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#define | QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009 |
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#define | QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a |
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#define | QLCNIC_CDRP_CMD_INTRPT_TEST 0x00000011 |
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#define | QLCNIC_CDRP_CMD_SET_MTU 0x00000012 |
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#define | QLCNIC_CDRP_CMD_READ_PHY 0x00000013 |
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#define | QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014 |
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#define | QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015 |
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#define | QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016 |
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#define | QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017 |
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#define | QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018 |
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#define | QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019 |
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#define | QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f |
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#define | QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020 |
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#define | QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021 |
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#define | QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022 |
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#define | QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024 |
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#define | QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025 |
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#define | QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026 |
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#define | QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027 |
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#define | QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028 |
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#define | QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029 |
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#define | QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a |
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#define | QLCNIC_CDRP_CMD_CONFIG_PORT 0x0000002E |
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#define | QLCNIC_CDRP_CMD_TEMP_SIZE 0x0000002f |
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#define | QLCNIC_CDRP_CMD_GET_TEMP_HDR 0x00000030 |
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#define | QLCNIC_CDRP_CMD_GET_MAC_STATS 0x00000037 |
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#define | QLCNIC_RCODE_SUCCESS 0 |
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#define | QLCNIC_RCODE_INVALID_ARGS 6 |
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#define | QLCNIC_RCODE_NOT_SUPPORTED 9 |
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#define | QLCNIC_RCODE_NOT_PERMITTED 10 |
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#define | QLCNIC_RCODE_NOT_IMPL 15 |
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#define | QLCNIC_RCODE_INVALID 16 |
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#define | QLCNIC_RCODE_TIMEOUT 17 |
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#define | QLCNIC_DESTROY_CTX_RESET 0 |
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#define | QLCNIC_CAP0_LEGACY_CONTEXT (1) |
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#define | QLCNIC_CAP0_LEGACY_MN (1 << 2) |
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#define | QLCNIC_CAP0_LSO (1 << 6) |
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#define | QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) |
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#define | QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) |
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#define | QLCNIC_CAP0_VALIDOFF (1 << 11) |
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#define | QLCNIC_CAP0_LRO_MSS (1 << 21) |
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#define | QLCNIC_HOST_CTX_STATE_FREED 0 |
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#define | QLCNIC_HOST_CTX_STATE_ACTIVE 2 |
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#define | SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) |
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#define | SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) |
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#define | SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) |
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#define | SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) |
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#define | QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 |
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#define | QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 |
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#define | QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 |
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#define | QLCNIC_HOST_RDS_CRB_MODE_MAX 3 |
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#define | QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 |
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#define | QLCNIC_HOST_INT_CRB_MODE_SHARED 1 |
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#define | QLCNIC_HOST_INT_CRB_MODE_NORX 2 |
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#define | QLCNIC_HOST_INT_CRB_MODE_NOTX 3 |
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#define | QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 |
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#define | MC_COUNT_P3P 38 |
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#define | QLCNIC_MAC_NOOP 0 |
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#define | QLCNIC_MAC_ADD 1 |
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#define | QLCNIC_MAC_DEL 2 |
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#define | QLCNIC_MAC_VLAN_ADD 3 |
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#define | QLCNIC_MAC_VLAN_DEL 4 |
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#define | QLCNIC_HOST_REQUEST 0x13 |
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#define | QLCNIC_REQUEST 0x14 |
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#define | QLCNIC_MAC_EVENT 0x1 |
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#define | QLCNIC_IP_UP 2 |
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#define | QLCNIC_IP_DOWN 3 |
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#define | QLCNIC_ILB_MODE 0x1 |
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#define | QLCNIC_ELB_MODE 0x2 |
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#define | QLCNIC_LINKEVENT 0x1 |
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#define | QLCNIC_LB_RESPONSE 0x2 |
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#define | QLCNIC_IS_LB_CONFIGURED(VAL) (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) |
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#define | QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 |
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#define | QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 |
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#define | QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 |
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#define | QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 |
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#define | QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc |
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#define | QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 |
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#define | QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 |
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#define | QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 |
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#define | QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 |
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#define | QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 |
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#define | QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f |
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#define | QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141 |
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#define | VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ |
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#define | VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ |
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#define | VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ |
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#define | QLCNIC_LRO_REQUEST_CLEANUP 4 |
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#define | QLCNIC_FW_CAPABILITY_TSO BIT_1 |
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#define | QLCNIC_FW_CAPABILITY_BDG BIT_8 |
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#define | QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 |
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#define | QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 |
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#define | QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 |
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#define | QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 |
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#define | QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 |
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#define | LINKEVENT_MODULE_NOT_PRESENT 1 |
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#define | LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 |
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#define | LINKEVENT_MODULE_OPTICAL_SRLR 3 |
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#define | LINKEVENT_MODULE_OPTICAL_LRM 4 |
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#define | LINKEVENT_MODULE_OPTICAL_SFP_1G 5 |
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#define | LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 |
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#define | LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 |
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#define | LINKEVENT_MODULE_TWINAX 8 |
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#define | LINKSPEED_10GBPS 10000 |
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#define | LINKSPEED_1GBPS 1000 |
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#define | LINKSPEED_100MBPS 100 |
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#define | LINKSPEED_10MBPS 10 |
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#define | LINKSPEED_ENCODED_10MBPS 0 |
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#define | LINKSPEED_ENCODED_100MBPS 1 |
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#define | LINKSPEED_ENCODED_1GBPS 2 |
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#define | LINKEVENT_AUTONEG_DISABLED 0 |
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#define | LINKEVENT_AUTONEG_ENABLED 1 |
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#define | LINKEVENT_HALF_DUPLEX 0 |
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#define | LINKEVENT_FULL_DUPLEX 1 |
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#define | LINKEVENT_LINKSPEED_MBPS 0 |
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#define | LINKEVENT_LINKSPEED_ENCODED 1 |
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#define | qlcnic_get_nic_msg_opcode(msg_hdr) ((msg_hdr >> 32) & 0xFF) |
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#define | QLCNIC_MSI_ENABLED 0x02 |
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#define | QLCNIC_MSIX_ENABLED 0x04 |
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#define | QLCNIC_LRO_ENABLED 0x08 |
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#define | QLCNIC_LRO_DISABLED 0x00 |
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#define | QLCNIC_BRIDGE_ENABLED 0X10 |
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#define | QLCNIC_DIAG_ENABLED 0x20 |
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#define | QLCNIC_ESWITCH_ENABLED 0x40 |
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#define | QLCNIC_ADAPTER_INITIALIZED 0x80 |
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#define | QLCNIC_TAGGING_ENABLED 0x100 |
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#define | QLCNIC_MACSPOOF 0x200 |
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#define | QLCNIC_MAC_OVERRIDE_DISABLED 0x400 |
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#define | QLCNIC_PROMISC_DISABLED 0x800 |
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#define | QLCNIC_NEED_FLR 0x1000 |
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#define | QLCNIC_FW_RESET_OWNER 0x2000 |
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#define | QLCNIC_FW_HANG 0x4000 |
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#define | QLCNIC_FW_LRO_MSS_CAP 0x8000 |
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#define | QLCNIC_IS_MSI_FAMILY(adapter) ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) |
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#define | QLCNIC_DEF_NUM_STS_DESC_RINGS 4 |
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#define | QLCNIC_MSIX_TBL_SPACE 8192 |
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#define | QLCNIC_PCI_REG_MSIX_TBL 0x44 |
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#define | QLCNIC_MSIX_TBL_PGSIZE 4096 |
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#define | QLCNIC_NETDEV_WEIGHT 128 |
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#define | QLCNIC_ADAPTER_UP_MAGIC 777 |
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#define | __QLCNIC_FW_ATTACHED 0 |
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#define | __QLCNIC_DEV_UP 1 |
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#define | __QLCNIC_RESETTING 2 |
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#define | __QLCNIC_START_FW 4 |
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#define | __QLCNIC_AER 5 |
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#define | __QLCNIC_DIAG_RES_ALLOC 6 |
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#define | __QLCNIC_LED_ENABLE 7 |
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#define | QLCNIC_INTERRUPT_TEST 1 |
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#define | QLCNIC_LOOPBACK_TEST 2 |
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#define | QLCNIC_LED_TEST 3 |
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#define | QLCNIC_FILTER_AGE 80 |
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#define | QLCNIC_READD_AGE 20 |
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#define | QLCNIC_LB_MAX_FILTERS 64 |
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#define | QLCNIC_FW_NOT_RESPOND 51 |
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#define | QLCNIC_TEST_IN_PROGRESS 52 |
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#define | QLCNIC_UNDEFINED_ERROR 53 |
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#define | QLCNIC_LB_CABLE_NOT_CONN 54 |
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#define | QLCNIC_SWITCH_ENABLE BIT_1 |
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#define | QLCNIC_SWITCH_VLAN_FILTERING BIT_2 |
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#define | QLCNIC_SWITCH_PROMISC_MODE BIT_3 |
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#define | QLCNIC_SWITCH_PORT_MIRRORING BIT_4 |
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#define | QL_STATUS_INVALID_PARAM -1 |
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#define | MAX_BW 100 /* % of link speed */ |
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#define | MAX_VLAN_ID 4095 |
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#define | MIN_VLAN_ID 2 |
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#define | DEFAULT_MAC_LEARN 1 |
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#define | IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) |
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#define | IS_VALID_BW(bw) (bw <= MAX_BW) |
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#define | QLCNIC_STATS_VERSION 1 |
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#define | QLCNIC_STATS_PORT 1 |
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#define | QLCNIC_STATS_ESWITCH 2 |
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#define | QLCNIC_QUERY_RX_COUNTER 0 |
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#define | QLCNIC_QUERY_TX_COUNTER 1 |
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#define | QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL |
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#define | QLCNIC_FILL_STATS(VAL1) (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) |
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#define | QLCNIC_MAC_STATS 1 |
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#define | QLCNIC_ESW_STATS 2 |
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#define | QLCNIC_ADD_ESW_STATS(VAL1, VAL2) |
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#define | QLCNIC_DUMP_WCRB BIT_0 |
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#define | QLCNIC_DUMP_RWCRB BIT_1 |
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#define | QLCNIC_DUMP_ANDCRB BIT_2 |
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#define | QLCNIC_DUMP_ORCRB BIT_3 |
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#define | QLCNIC_DUMP_POLLCRB BIT_4 |
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#define | QLCNIC_DUMP_RD_SAVE BIT_5 |
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#define | QLCNIC_DUMP_WRT_SAVED BIT_6 |
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#define | QLCNIC_DUMP_MOD_SAVE_ST BIT_7 |
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#define | QLCNIC_DUMP_SKIP BIT_7 |
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#define | QLCNIC_DUMP_MASK_MIN 3 |
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#define | QLCNIC_DUMP_MASK_DEF 0x1f |
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#define | QLCNIC_DUMP_MASK_MAX 0xff |
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#define | QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed |
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#define | QLCNIC_ENABLE_FW_DUMP 0xaddfeed |
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#define | QLCNIC_DISABLE_FW_DUMP 0xbadfeed |
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#define | QLCNIC_FORCE_FW_RESET 0xdeaddead |
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#define | QLCNIC_SET_QUIESCENT 0xadd00010 |
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#define | QLCNIC_RESET_QUIESCENT 0xadd00020 |
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#define | ADDR_IN_RANGE(addr, low, high) (((addr) < (high)) && ((addr) >= (low))) |
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#define | QLCRD32(adapter, off) (qlcnic_hw_read_wx_2M(adapter, off)) |
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#define | QLCWR32(adapter, off, val) (qlcnic_hw_write_wx_2M(adapter, off, val)) |
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#define | qlcnic_rom_lock(a) qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) |
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#define | qlcnic_rom_unlock(a) qlcnic_pcie_sem_unlock((a), 2) |
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#define | qlcnic_phy_lock(a) qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) |
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#define | qlcnic_phy_unlock(a) qlcnic_pcie_sem_unlock((a), 3) |
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#define | qlcnic_api_lock(a) qlcnic_pcie_sem_lock((a), 5, 0) |
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#define | qlcnic_api_unlock(a) qlcnic_pcie_sem_unlock((a), 5) |
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#define | qlcnic_sw_lock(a) qlcnic_pcie_sem_lock((a), 6, 0) |
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#define | qlcnic_sw_unlock(a) qlcnic_pcie_sem_unlock((a), 6) |
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#define | crb_win_lock(a) qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) |
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#define | crb_win_unlock(a) qlcnic_pcie_sem_unlock((a), 7) |
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#define | __QLCNIC_MAX_LED_RATE 0xf |
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#define | __QLCNIC_MAX_LED_STATE 0x2 |
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#define | QLCNIC_MAX_BOARD_NAME_LEN 100 |
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#define | NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards) |
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#define | QLCDB(adapter, lvl, _fmt, _args...) |
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