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radeon_combios.c
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1 /*
2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3  * Copyright 2007-8 Advanced Micro Devices, Inc.
4  * Copyright 2008 Red Hat Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  * Alex Deucher
26  */
27 #include <drm/drmP.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon.h"
30 #include "atom.h"
31 
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
36 #include <asm/prom.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
39 
40 /* from radeon_encoder.c */
41 extern uint32_t
42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43  uint8_t dac);
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
45 
46 /* from radeon_connector.c */
47 extern void
48 radeon_add_legacy_connector(struct drm_device *dev,
49  uint32_t connector_id,
50  uint32_t supported_device,
51  int connector_type,
52  struct radeon_i2c_bus_rec *i2c_bus,
53  uint16_t connector_object_id,
54  struct radeon_hpd *hpd);
55 
56 /* from radeon_legacy_encoder.c */
57 extern void
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
59  uint32_t supported_device);
60 
61 /* old legacy ATI BIOS routines */
62 
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65  /* absolute offset tables */
66  COMBIOS_ASIC_INIT_1_TABLE,
67  COMBIOS_BIOS_SUPPORT_TABLE,
68  COMBIOS_DAC_PROGRAMMING_TABLE,
69  COMBIOS_MAX_COLOR_DEPTH_TABLE,
70  COMBIOS_CRTC_INFO_TABLE,
71  COMBIOS_PLL_INFO_TABLE,
72  COMBIOS_TV_INFO_TABLE,
73  COMBIOS_DFP_INFO_TABLE,
74  COMBIOS_HW_CONFIG_INFO_TABLE,
75  COMBIOS_MULTIMEDIA_INFO_TABLE,
76  COMBIOS_TV_STD_PATCH_TABLE,
77  COMBIOS_LCD_INFO_TABLE,
78  COMBIOS_MOBILE_INFO_TABLE,
79  COMBIOS_PLL_INIT_TABLE,
80  COMBIOS_MEM_CONFIG_TABLE,
81  COMBIOS_SAVE_MASK_TABLE,
82  COMBIOS_HARDCODED_EDID_TABLE,
83  COMBIOS_ASIC_INIT_2_TABLE,
84  COMBIOS_CONNECTOR_INFO_TABLE,
85  COMBIOS_DYN_CLK_1_TABLE,
86  COMBIOS_RESERVED_MEM_TABLE,
87  COMBIOS_EXT_TMDS_INFO_TABLE,
88  COMBIOS_MEM_CLK_INFO_TABLE,
89  COMBIOS_EXT_DAC_INFO_TABLE,
90  COMBIOS_MISC_INFO_TABLE,
91  COMBIOS_CRT_INFO_TABLE,
92  COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93  COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94  COMBIOS_FAN_SPEED_INFO_TABLE,
95  COMBIOS_OVERDRIVE_INFO_TABLE,
96  COMBIOS_OEM_INFO_TABLE,
97  COMBIOS_DYN_CLK_2_TABLE,
98  COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99  COMBIOS_I2C_INFO_TABLE,
100  /* relative offset tables */
101  COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102  COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103  COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104  COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105  COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106  COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107  COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108  COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109  COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110  COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111  COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112 };
113 
114 enum radeon_combios_ddc {
115  DDC_NONE_DETECTED,
116  DDC_MONID,
117  DDC_DVI,
118  DDC_VGA,
119  DDC_CRT2,
120  DDC_LCD,
121  DDC_GPIO,
122 };
123 
124 enum radeon_combios_connector {
125  CONNECTOR_NONE_LEGACY,
126  CONNECTOR_PROPRIETARY_LEGACY,
127  CONNECTOR_CRT_LEGACY,
128  CONNECTOR_DVI_I_LEGACY,
129  CONNECTOR_DVI_D_LEGACY,
130  CONNECTOR_CTV_LEGACY,
131  CONNECTOR_STV_LEGACY,
132  CONNECTOR_UNSUPPORTED_LEGACY
133 };
134 
135 const int legacy_connector_convert[] = {
136  DRM_MODE_CONNECTOR_Unknown,
137  DRM_MODE_CONNECTOR_DVID,
138  DRM_MODE_CONNECTOR_VGA,
139  DRM_MODE_CONNECTOR_DVII,
140  DRM_MODE_CONNECTOR_DVID,
141  DRM_MODE_CONNECTOR_Composite,
142  DRM_MODE_CONNECTOR_SVIDEO,
143  DRM_MODE_CONNECTOR_Unknown,
144 };
145 
146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147  enum radeon_combios_table_offset table)
148 {
149  struct radeon_device *rdev = dev->dev_private;
150  int rev;
151  uint16_t offset = 0, check_offset;
152 
153  if (!rdev->bios)
154  return 0;
155 
156  switch (table) {
157  /* absolute offset tables */
158  case COMBIOS_ASIC_INIT_1_TABLE:
159  check_offset = RBIOS16(rdev->bios_header_start + 0xc);
160  if (check_offset)
161  offset = check_offset;
162  break;
163  case COMBIOS_BIOS_SUPPORT_TABLE:
164  check_offset = RBIOS16(rdev->bios_header_start + 0x14);
165  if (check_offset)
166  offset = check_offset;
167  break;
168  case COMBIOS_DAC_PROGRAMMING_TABLE:
169  check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
170  if (check_offset)
171  offset = check_offset;
172  break;
173  case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174  check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
175  if (check_offset)
176  offset = check_offset;
177  break;
178  case COMBIOS_CRTC_INFO_TABLE:
179  check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
180  if (check_offset)
181  offset = check_offset;
182  break;
183  case COMBIOS_PLL_INFO_TABLE:
184  check_offset = RBIOS16(rdev->bios_header_start + 0x30);
185  if (check_offset)
186  offset = check_offset;
187  break;
188  case COMBIOS_TV_INFO_TABLE:
189  check_offset = RBIOS16(rdev->bios_header_start + 0x32);
190  if (check_offset)
191  offset = check_offset;
192  break;
193  case COMBIOS_DFP_INFO_TABLE:
194  check_offset = RBIOS16(rdev->bios_header_start + 0x34);
195  if (check_offset)
196  offset = check_offset;
197  break;
198  case COMBIOS_HW_CONFIG_INFO_TABLE:
199  check_offset = RBIOS16(rdev->bios_header_start + 0x36);
200  if (check_offset)
201  offset = check_offset;
202  break;
203  case COMBIOS_MULTIMEDIA_INFO_TABLE:
204  check_offset = RBIOS16(rdev->bios_header_start + 0x38);
205  if (check_offset)
206  offset = check_offset;
207  break;
208  case COMBIOS_TV_STD_PATCH_TABLE:
209  check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
210  if (check_offset)
211  offset = check_offset;
212  break;
213  case COMBIOS_LCD_INFO_TABLE:
214  check_offset = RBIOS16(rdev->bios_header_start + 0x40);
215  if (check_offset)
216  offset = check_offset;
217  break;
218  case COMBIOS_MOBILE_INFO_TABLE:
219  check_offset = RBIOS16(rdev->bios_header_start + 0x42);
220  if (check_offset)
221  offset = check_offset;
222  break;
223  case COMBIOS_PLL_INIT_TABLE:
224  check_offset = RBIOS16(rdev->bios_header_start + 0x46);
225  if (check_offset)
226  offset = check_offset;
227  break;
228  case COMBIOS_MEM_CONFIG_TABLE:
229  check_offset = RBIOS16(rdev->bios_header_start + 0x48);
230  if (check_offset)
231  offset = check_offset;
232  break;
233  case COMBIOS_SAVE_MASK_TABLE:
234  check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
235  if (check_offset)
236  offset = check_offset;
237  break;
238  case COMBIOS_HARDCODED_EDID_TABLE:
239  check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
240  if (check_offset)
241  offset = check_offset;
242  break;
243  case COMBIOS_ASIC_INIT_2_TABLE:
244  check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
245  if (check_offset)
246  offset = check_offset;
247  break;
248  case COMBIOS_CONNECTOR_INFO_TABLE:
249  check_offset = RBIOS16(rdev->bios_header_start + 0x50);
250  if (check_offset)
251  offset = check_offset;
252  break;
253  case COMBIOS_DYN_CLK_1_TABLE:
254  check_offset = RBIOS16(rdev->bios_header_start + 0x52);
255  if (check_offset)
256  offset = check_offset;
257  break;
258  case COMBIOS_RESERVED_MEM_TABLE:
259  check_offset = RBIOS16(rdev->bios_header_start + 0x54);
260  if (check_offset)
261  offset = check_offset;
262  break;
263  case COMBIOS_EXT_TMDS_INFO_TABLE:
264  check_offset = RBIOS16(rdev->bios_header_start + 0x58);
265  if (check_offset)
266  offset = check_offset;
267  break;
268  case COMBIOS_MEM_CLK_INFO_TABLE:
269  check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
270  if (check_offset)
271  offset = check_offset;
272  break;
273  case COMBIOS_EXT_DAC_INFO_TABLE:
274  check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
275  if (check_offset)
276  offset = check_offset;
277  break;
278  case COMBIOS_MISC_INFO_TABLE:
279  check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
280  if (check_offset)
281  offset = check_offset;
282  break;
283  case COMBIOS_CRT_INFO_TABLE:
284  check_offset = RBIOS16(rdev->bios_header_start + 0x60);
285  if (check_offset)
286  offset = check_offset;
287  break;
288  case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289  check_offset = RBIOS16(rdev->bios_header_start + 0x62);
290  if (check_offset)
291  offset = check_offset;
292  break;
293  case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294  check_offset = RBIOS16(rdev->bios_header_start + 0x64);
295  if (check_offset)
296  offset = check_offset;
297  break;
298  case COMBIOS_FAN_SPEED_INFO_TABLE:
299  check_offset = RBIOS16(rdev->bios_header_start + 0x66);
300  if (check_offset)
301  offset = check_offset;
302  break;
303  case COMBIOS_OVERDRIVE_INFO_TABLE:
304  check_offset = RBIOS16(rdev->bios_header_start + 0x68);
305  if (check_offset)
306  offset = check_offset;
307  break;
308  case COMBIOS_OEM_INFO_TABLE:
309  check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
310  if (check_offset)
311  offset = check_offset;
312  break;
313  case COMBIOS_DYN_CLK_2_TABLE:
314  check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
315  if (check_offset)
316  offset = check_offset;
317  break;
318  case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319  check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
320  if (check_offset)
321  offset = check_offset;
322  break;
323  case COMBIOS_I2C_INFO_TABLE:
324  check_offset = RBIOS16(rdev->bios_header_start + 0x70);
325  if (check_offset)
326  offset = check_offset;
327  break;
328  /* relative offset tables */
329  case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
330  check_offset =
331  combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
332  if (check_offset) {
333  rev = RBIOS8(check_offset);
334  if (rev > 0) {
335  check_offset = RBIOS16(check_offset + 0x3);
336  if (check_offset)
337  offset = check_offset;
338  }
339  }
340  break;
341  case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
342  check_offset =
343  combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
344  if (check_offset) {
345  rev = RBIOS8(check_offset);
346  if (rev > 0) {
347  check_offset = RBIOS16(check_offset + 0x5);
348  if (check_offset)
349  offset = check_offset;
350  }
351  }
352  break;
353  case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
354  check_offset =
355  combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
356  if (check_offset) {
357  rev = RBIOS8(check_offset);
358  if (rev > 0) {
359  check_offset = RBIOS16(check_offset + 0x7);
360  if (check_offset)
361  offset = check_offset;
362  }
363  }
364  break;
365  case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
366  check_offset =
367  combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
368  if (check_offset) {
369  rev = RBIOS8(check_offset);
370  if (rev == 2) {
371  check_offset = RBIOS16(check_offset + 0x9);
372  if (check_offset)
373  offset = check_offset;
374  }
375  }
376  break;
377  case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
378  check_offset =
379  combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
380  if (check_offset) {
381  while (RBIOS8(check_offset++));
382  check_offset += 2;
383  if (check_offset)
384  offset = check_offset;
385  }
386  break;
387  case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
388  check_offset =
389  combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
390  if (check_offset) {
391  check_offset = RBIOS16(check_offset + 0x11);
392  if (check_offset)
393  offset = check_offset;
394  }
395  break;
396  case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
397  check_offset =
398  combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
399  if (check_offset) {
400  check_offset = RBIOS16(check_offset + 0x13);
401  if (check_offset)
402  offset = check_offset;
403  }
404  break;
405  case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
406  check_offset =
407  combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
408  if (check_offset) {
409  check_offset = RBIOS16(check_offset + 0x15);
410  if (check_offset)
411  offset = check_offset;
412  }
413  break;
414  case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
415  check_offset =
416  combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
417  if (check_offset) {
418  check_offset = RBIOS16(check_offset + 0x17);
419  if (check_offset)
420  offset = check_offset;
421  }
422  break;
423  case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
424  check_offset =
425  combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
426  if (check_offset) {
427  check_offset = RBIOS16(check_offset + 0x2);
428  if (check_offset)
429  offset = check_offset;
430  }
431  break;
432  case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
433  check_offset =
434  combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
435  if (check_offset) {
436  check_offset = RBIOS16(check_offset + 0x4);
437  if (check_offset)
438  offset = check_offset;
439  }
440  break;
441  default:
442  break;
443  }
444 
445  return offset;
446 
447 }
448 
449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
450 {
451  int edid_info, size;
452  struct edid *edid;
453  unsigned char *raw;
454  edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
455  if (!edid_info)
456  return false;
457 
458  raw = rdev->bios + edid_info;
459  size = EDID_LENGTH * (raw[0x7e] + 1);
460  edid = kmalloc(size, GFP_KERNEL);
461  if (edid == NULL)
462  return false;
463 
464  memcpy((unsigned char *)edid, raw, size);
465 
466  if (!drm_edid_is_valid(edid)) {
467  kfree(edid);
468  return false;
469  }
470 
471  rdev->mode_info.bios_hardcoded_edid = edid;
472  rdev->mode_info.bios_hardcoded_edid_size = size;
473  return true;
474 }
475 
476 /* this is used for atom LCDs as well */
477 struct edid *
478 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
479 {
480  struct edid *edid;
481 
482  if (rdev->mode_info.bios_hardcoded_edid) {
483  edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
484  if (edid) {
485  memcpy((unsigned char *)edid,
486  (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
487  rdev->mode_info.bios_hardcoded_edid_size);
488  return edid;
489  }
490  }
491  return NULL;
492 }
493 
494 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
495  enum radeon_combios_ddc ddc,
496  u32 clk_mask,
497  u32 data_mask)
498 {
499  struct radeon_i2c_bus_rec i2c;
500  int ddc_line = 0;
501 
502  /* ddc id = mask reg
503  * DDC_NONE_DETECTED = none
504  * DDC_DVI = RADEON_GPIO_DVI_DDC
505  * DDC_VGA = RADEON_GPIO_VGA_DDC
506  * DDC_LCD = RADEON_GPIOPAD_MASK
507  * DDC_GPIO = RADEON_MDGPIO_MASK
508  * r1xx
509  * DDC_MONID = RADEON_GPIO_MONID
510  * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
511  * r200
512  * DDC_MONID = RADEON_GPIO_MONID
513  * DDC_CRT2 = RADEON_GPIO_DVI_DDC
514  * r300/r350
515  * DDC_MONID = RADEON_GPIO_DVI_DDC
516  * DDC_CRT2 = RADEON_GPIO_DVI_DDC
517  * rv2xx/rv3xx
518  * DDC_MONID = RADEON_GPIO_MONID
519  * DDC_CRT2 = RADEON_GPIO_MONID
520  * rs3xx/rs4xx
521  * DDC_MONID = RADEON_GPIOPAD_MASK
522  * DDC_CRT2 = RADEON_GPIO_MONID
523  */
524  switch (ddc) {
525  case DDC_NONE_DETECTED:
526  default:
527  ddc_line = 0;
528  break;
529  case DDC_DVI:
530  ddc_line = RADEON_GPIO_DVI_DDC;
531  break;
532  case DDC_VGA:
533  ddc_line = RADEON_GPIO_VGA_DDC;
534  break;
535  case DDC_LCD:
536  ddc_line = RADEON_GPIOPAD_MASK;
537  break;
538  case DDC_GPIO:
539  ddc_line = RADEON_MDGPIO_MASK;
540  break;
541  case DDC_MONID:
542  if (rdev->family == CHIP_RS300 ||
543  rdev->family == CHIP_RS400 ||
544  rdev->family == CHIP_RS480)
545  ddc_line = RADEON_GPIOPAD_MASK;
546  else if (rdev->family == CHIP_R300 ||
547  rdev->family == CHIP_R350) {
548  ddc_line = RADEON_GPIO_DVI_DDC;
549  ddc = DDC_DVI;
550  } else
551  ddc_line = RADEON_GPIO_MONID;
552  break;
553  case DDC_CRT2:
554  if (rdev->family == CHIP_R200 ||
555  rdev->family == CHIP_R300 ||
556  rdev->family == CHIP_R350) {
557  ddc_line = RADEON_GPIO_DVI_DDC;
558  ddc = DDC_DVI;
559  } else if (rdev->family == CHIP_RS300 ||
560  rdev->family == CHIP_RS400 ||
561  rdev->family == CHIP_RS480)
562  ddc_line = RADEON_GPIO_MONID;
563  else if (rdev->family >= CHIP_RV350) {
564  ddc_line = RADEON_GPIO_MONID;
565  ddc = DDC_MONID;
566  } else
567  ddc_line = RADEON_GPIO_CRT2_DDC;
568  break;
569  }
570 
571  if (ddc_line == RADEON_GPIOPAD_MASK) {
572  i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
573  i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
574  i2c.a_clk_reg = RADEON_GPIOPAD_A;
575  i2c.a_data_reg = RADEON_GPIOPAD_A;
576  i2c.en_clk_reg = RADEON_GPIOPAD_EN;
577  i2c.en_data_reg = RADEON_GPIOPAD_EN;
578  i2c.y_clk_reg = RADEON_GPIOPAD_Y;
579  i2c.y_data_reg = RADEON_GPIOPAD_Y;
580  } else if (ddc_line == RADEON_MDGPIO_MASK) {
581  i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
582  i2c.mask_data_reg = RADEON_MDGPIO_MASK;
583  i2c.a_clk_reg = RADEON_MDGPIO_A;
584  i2c.a_data_reg = RADEON_MDGPIO_A;
585  i2c.en_clk_reg = RADEON_MDGPIO_EN;
586  i2c.en_data_reg = RADEON_MDGPIO_EN;
587  i2c.y_clk_reg = RADEON_MDGPIO_Y;
588  i2c.y_data_reg = RADEON_MDGPIO_Y;
589  } else {
590  i2c.mask_clk_reg = ddc_line;
591  i2c.mask_data_reg = ddc_line;
592  i2c.a_clk_reg = ddc_line;
593  i2c.a_data_reg = ddc_line;
594  i2c.en_clk_reg = ddc_line;
595  i2c.en_data_reg = ddc_line;
596  i2c.y_clk_reg = ddc_line;
597  i2c.y_data_reg = ddc_line;
598  }
599 
600  if (clk_mask && data_mask) {
601  /* system specific masks */
602  i2c.mask_clk_mask = clk_mask;
603  i2c.mask_data_mask = data_mask;
604  i2c.a_clk_mask = clk_mask;
605  i2c.a_data_mask = data_mask;
606  i2c.en_clk_mask = clk_mask;
607  i2c.en_data_mask = data_mask;
608  i2c.y_clk_mask = clk_mask;
609  i2c.y_data_mask = data_mask;
610  } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
611  (ddc_line == RADEON_MDGPIO_MASK)) {
612  /* default gpiopad masks */
613  i2c.mask_clk_mask = (0x20 << 8);
614  i2c.mask_data_mask = 0x80;
615  i2c.a_clk_mask = (0x20 << 8);
616  i2c.a_data_mask = 0x80;
617  i2c.en_clk_mask = (0x20 << 8);
618  i2c.en_data_mask = 0x80;
619  i2c.y_clk_mask = (0x20 << 8);
620  i2c.y_data_mask = 0x80;
621  } else {
622  /* default masks for ddc pads */
623  i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
624  i2c.mask_data_mask = RADEON_GPIO_MASK_0;
625  i2c.a_clk_mask = RADEON_GPIO_A_1;
626  i2c.a_data_mask = RADEON_GPIO_A_0;
627  i2c.en_clk_mask = RADEON_GPIO_EN_1;
628  i2c.en_data_mask = RADEON_GPIO_EN_0;
629  i2c.y_clk_mask = RADEON_GPIO_Y_1;
630  i2c.y_data_mask = RADEON_GPIO_Y_0;
631  }
632 
633  switch (rdev->family) {
634  case CHIP_R100:
635  case CHIP_RV100:
636  case CHIP_RS100:
637  case CHIP_RV200:
638  case CHIP_RS200:
639  case CHIP_RS300:
640  switch (ddc_line) {
641  case RADEON_GPIO_DVI_DDC:
642  i2c.hw_capable = true;
643  break;
644  default:
645  i2c.hw_capable = false;
646  break;
647  }
648  break;
649  case CHIP_R200:
650  switch (ddc_line) {
651  case RADEON_GPIO_DVI_DDC:
652  case RADEON_GPIO_MONID:
653  i2c.hw_capable = true;
654  break;
655  default:
656  i2c.hw_capable = false;
657  break;
658  }
659  break;
660  case CHIP_RV250:
661  case CHIP_RV280:
662  switch (ddc_line) {
663  case RADEON_GPIO_VGA_DDC:
664  case RADEON_GPIO_DVI_DDC:
665  case RADEON_GPIO_CRT2_DDC:
666  i2c.hw_capable = true;
667  break;
668  default:
669  i2c.hw_capable = false;
670  break;
671  }
672  break;
673  case CHIP_R300:
674  case CHIP_R350:
675  switch (ddc_line) {
676  case RADEON_GPIO_VGA_DDC:
677  case RADEON_GPIO_DVI_DDC:
678  i2c.hw_capable = true;
679  break;
680  default:
681  i2c.hw_capable = false;
682  break;
683  }
684  break;
685  case CHIP_RV350:
686  case CHIP_RV380:
687  case CHIP_RS400:
688  case CHIP_RS480:
689  switch (ddc_line) {
690  case RADEON_GPIO_VGA_DDC:
691  case RADEON_GPIO_DVI_DDC:
692  i2c.hw_capable = true;
693  break;
694  case RADEON_GPIO_MONID:
695  /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
696  * reliably on some pre-r4xx hardware; not sure why.
697  */
698  i2c.hw_capable = false;
699  break;
700  default:
701  i2c.hw_capable = false;
702  break;
703  }
704  break;
705  default:
706  i2c.hw_capable = false;
707  break;
708  }
709  i2c.mm_i2c = false;
710 
711  i2c.i2c_id = ddc;
712  i2c.hpd = RADEON_HPD_NONE;
713 
714  if (ddc_line)
715  i2c.valid = true;
716  else
717  i2c.valid = false;
718 
719  return i2c;
720 }
721 
722 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
723 {
724  struct drm_device *dev = rdev->ddev;
725  struct radeon_i2c_bus_rec i2c;
726  u16 offset;
727  u8 id, blocks, clk, data;
728  int i;
729 
730  i2c.valid = false;
731 
732  offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
733  if (offset) {
734  blocks = RBIOS8(offset + 2);
735  for (i = 0; i < blocks; i++) {
736  id = RBIOS8(offset + 3 + (i * 5) + 0);
737  if (id == 136) {
738  clk = RBIOS8(offset + 3 + (i * 5) + 3);
739  data = RBIOS8(offset + 3 + (i * 5) + 4);
740  /* gpiopad */
741  i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
742  (1 << clk), (1 << data));
743  break;
744  }
745  }
746  }
747  return i2c;
748 }
749 
750 void radeon_combios_i2c_init(struct radeon_device *rdev)
751 {
752  struct drm_device *dev = rdev->ddev;
753  struct radeon_i2c_bus_rec i2c;
754 
755  /* actual hw pads
756  * r1xx/rs2xx/rs3xx
757  * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
758  * r200
759  * 0x60, 0x64, 0x68, mm
760  * r300/r350
761  * 0x60, 0x64, mm
762  * rv2xx/rv3xx/rs4xx
763  * 0x60, 0x64, 0x68, gpiopads, mm
764  */
765 
766  /* 0x60 */
767  i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
768  rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
769  /* 0x64 */
770  i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
771  rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
772 
773  /* mm i2c */
774  i2c.valid = true;
775  i2c.hw_capable = true;
776  i2c.mm_i2c = true;
777  i2c.i2c_id = 0xa0;
778  rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
779 
780  if (rdev->family == CHIP_R300 ||
781  rdev->family == CHIP_R350) {
782  /* only 2 sw i2c pads */
783  } else if (rdev->family == CHIP_RS300 ||
784  rdev->family == CHIP_RS400 ||
785  rdev->family == CHIP_RS480) {
786  /* 0x68 */
787  i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
788  rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
789 
790  /* gpiopad */
791  i2c = radeon_combios_get_i2c_info_from_table(rdev);
792  if (i2c.valid)
793  rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
794  } else if ((rdev->family == CHIP_R200) ||
795  (rdev->family >= CHIP_R300)) {
796  /* 0x68 */
797  i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
798  rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
799  } else {
800  /* 0x68 */
801  i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
802  rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
803  /* 0x6c */
804  i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
805  rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
806  }
807 }
808 
809 bool radeon_combios_get_clock_info(struct drm_device *dev)
810 {
811  struct radeon_device *rdev = dev->dev_private;
812  uint16_t pll_info;
813  struct radeon_pll *p1pll = &rdev->clock.p1pll;
814  struct radeon_pll *p2pll = &rdev->clock.p2pll;
815  struct radeon_pll *spll = &rdev->clock.spll;
816  struct radeon_pll *mpll = &rdev->clock.mpll;
817  int8_t rev;
818  uint16_t sclk, mclk;
819 
820  pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
821  if (pll_info) {
822  rev = RBIOS8(pll_info);
823 
824  /* pixel clocks */
825  p1pll->reference_freq = RBIOS16(pll_info + 0xe);
826  p1pll->reference_div = RBIOS16(pll_info + 0x10);
827  p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
828  p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
829  p1pll->lcd_pll_out_min = p1pll->pll_out_min;
830  p1pll->lcd_pll_out_max = p1pll->pll_out_max;
831 
832  if (rev > 9) {
833  p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
834  p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
835  } else {
836  p1pll->pll_in_min = 40;
837  p1pll->pll_in_max = 500;
838  }
839  *p2pll = *p1pll;
840 
841  /* system clock */
842  spll->reference_freq = RBIOS16(pll_info + 0x1a);
843  spll->reference_div = RBIOS16(pll_info + 0x1c);
844  spll->pll_out_min = RBIOS32(pll_info + 0x1e);
845  spll->pll_out_max = RBIOS32(pll_info + 0x22);
846 
847  if (rev > 10) {
848  spll->pll_in_min = RBIOS32(pll_info + 0x48);
849  spll->pll_in_max = RBIOS32(pll_info + 0x4c);
850  } else {
851  /* ??? */
852  spll->pll_in_min = 40;
853  spll->pll_in_max = 500;
854  }
855 
856  /* memory clock */
857  mpll->reference_freq = RBIOS16(pll_info + 0x26);
858  mpll->reference_div = RBIOS16(pll_info + 0x28);
859  mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
860  mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
861 
862  if (rev > 10) {
863  mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
864  mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
865  } else {
866  /* ??? */
867  mpll->pll_in_min = 40;
868  mpll->pll_in_max = 500;
869  }
870 
871  /* default sclk/mclk */
872  sclk = RBIOS16(pll_info + 0xa);
873  mclk = RBIOS16(pll_info + 0x8);
874  if (sclk == 0)
875  sclk = 200 * 100;
876  if (mclk == 0)
877  mclk = 200 * 100;
878 
879  rdev->clock.default_sclk = sclk;
880  rdev->clock.default_mclk = mclk;
881 
882  if (RBIOS32(pll_info + 0x16))
883  rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
884  else
885  rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
886 
887  return true;
888  }
889  return false;
890 }
891 
892 bool radeon_combios_sideport_present(struct radeon_device *rdev)
893 {
894  struct drm_device *dev = rdev->ddev;
895  u16 igp_info;
896 
897  /* sideport is AMD only */
898  if (rdev->family == CHIP_RS400)
899  return false;
900 
901  igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
902 
903  if (igp_info) {
904  if (RBIOS16(igp_info + 0x4))
905  return true;
906  }
907  return false;
908 }
909 
910 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
911  0x00000808, /* r100 */
912  0x00000808, /* rv100 */
913  0x00000808, /* rs100 */
914  0x00000808, /* rv200 */
915  0x00000808, /* rs200 */
916  0x00000808, /* r200 */
917  0x00000808, /* rv250 */
918  0x00000000, /* rs300 */
919  0x00000808, /* rv280 */
920  0x00000808, /* r300 */
921  0x00000808, /* r350 */
922  0x00000808, /* rv350 */
923  0x00000808, /* rv380 */
924  0x00000808, /* r420 */
925  0x00000808, /* r423 */
926  0x00000808, /* rv410 */
927  0x00000000, /* rs400 */
928  0x00000000, /* rs480 */
929 };
930 
931 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
932  struct radeon_encoder_primary_dac *p_dac)
933 {
934  p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
935  return;
936 }
937 
938 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
939  radeon_encoder
940  *encoder)
941 {
942  struct drm_device *dev = encoder->base.dev;
943  struct radeon_device *rdev = dev->dev_private;
944  uint16_t dac_info;
945  uint8_t rev, bg, dac;
946  struct radeon_encoder_primary_dac *p_dac = NULL;
947  int found = 0;
948 
949  p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
950  GFP_KERNEL);
951 
952  if (!p_dac)
953  return NULL;
954 
955  /* check CRT table */
956  dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
957  if (dac_info) {
958  rev = RBIOS8(dac_info) & 0x3;
959  if (rev < 2) {
960  bg = RBIOS8(dac_info + 0x2) & 0xf;
961  dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
962  p_dac->ps2_pdac_adj = (bg << 8) | (dac);
963  } else {
964  bg = RBIOS8(dac_info + 0x2) & 0xf;
965  dac = RBIOS8(dac_info + 0x3) & 0xf;
966  p_dac->ps2_pdac_adj = (bg << 8) | (dac);
967  }
968  /* if the values are all zeros, use the table */
969  if (p_dac->ps2_pdac_adj)
970  found = 1;
971  }
972 
973  if (!found) /* fallback to defaults */
974  radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
975 
976  return p_dac;
977 }
978 
979 enum radeon_tv_std
980 radeon_combios_get_tv_info(struct radeon_device *rdev)
981 {
982  struct drm_device *dev = rdev->ddev;
983  uint16_t tv_info;
984  enum radeon_tv_std tv_std = TV_STD_NTSC;
985 
986  tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
987  if (tv_info) {
988  if (RBIOS8(tv_info + 6) == 'T') {
989  switch (RBIOS8(tv_info + 7) & 0xf) {
990  case 1:
991  tv_std = TV_STD_NTSC;
992  DRM_DEBUG_KMS("Default TV standard: NTSC\n");
993  break;
994  case 2:
995  tv_std = TV_STD_PAL;
996  DRM_DEBUG_KMS("Default TV standard: PAL\n");
997  break;
998  case 3:
999  tv_std = TV_STD_PAL_M;
1000  DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1001  break;
1002  case 4:
1003  tv_std = TV_STD_PAL_60;
1004  DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1005  break;
1006  case 5:
1007  tv_std = TV_STD_NTSC_J;
1008  DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1009  break;
1010  case 6:
1011  tv_std = TV_STD_SCART_PAL;
1012  DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
1013  break;
1014  default:
1015  tv_std = TV_STD_NTSC;
1016  DRM_DEBUG_KMS
1017  ("Unknown TV standard; defaulting to NTSC\n");
1018  break;
1019  }
1020 
1021  switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
1022  case 0:
1023  DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
1024  break;
1025  case 1:
1026  DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
1027  break;
1028  case 2:
1029  DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
1030  break;
1031  case 3:
1032  DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
1033  break;
1034  default:
1035  break;
1036  }
1037  }
1038  }
1039  return tv_std;
1040 }
1041 
1042 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
1043  0x00000000, /* r100 */
1044  0x00280000, /* rv100 */
1045  0x00000000, /* rs100 */
1046  0x00880000, /* rv200 */
1047  0x00000000, /* rs200 */
1048  0x00000000, /* r200 */
1049  0x00770000, /* rv250 */
1050  0x00290000, /* rs300 */
1051  0x00560000, /* rv280 */
1052  0x00780000, /* r300 */
1053  0x00770000, /* r350 */
1054  0x00780000, /* rv350 */
1055  0x00780000, /* rv380 */
1056  0x01080000, /* r420 */
1057  0x01080000, /* r423 */
1058  0x01080000, /* rv410 */
1059  0x00780000, /* rs400 */
1060  0x00780000, /* rs480 */
1061 };
1062 
1063 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1064  struct radeon_encoder_tv_dac *tv_dac)
1065 {
1066  tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1067  if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1068  tv_dac->ps2_tvdac_adj = 0x00880000;
1069  tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1070  tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1071  return;
1072 }
1073 
1074 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1075  radeon_encoder
1076  *encoder)
1077 {
1078  struct drm_device *dev = encoder->base.dev;
1079  struct radeon_device *rdev = dev->dev_private;
1080  uint16_t dac_info;
1081  uint8_t rev, bg, dac;
1082  struct radeon_encoder_tv_dac *tv_dac = NULL;
1083  int found = 0;
1084 
1085  tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1086  if (!tv_dac)
1087  return NULL;
1088 
1089  /* first check TV table */
1090  dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1091  if (dac_info) {
1092  rev = RBIOS8(dac_info + 0x3);
1093  if (rev > 4) {
1094  bg = RBIOS8(dac_info + 0xc) & 0xf;
1095  dac = RBIOS8(dac_info + 0xd) & 0xf;
1096  tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1097 
1098  bg = RBIOS8(dac_info + 0xe) & 0xf;
1099  dac = RBIOS8(dac_info + 0xf) & 0xf;
1100  tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1101 
1102  bg = RBIOS8(dac_info + 0x10) & 0xf;
1103  dac = RBIOS8(dac_info + 0x11) & 0xf;
1104  tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1105  /* if the values are all zeros, use the table */
1106  if (tv_dac->ps2_tvdac_adj)
1107  found = 1;
1108  } else if (rev > 1) {
1109  bg = RBIOS8(dac_info + 0xc) & 0xf;
1110  dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1111  tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1112 
1113  bg = RBIOS8(dac_info + 0xd) & 0xf;
1114  dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1115  tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1116 
1117  bg = RBIOS8(dac_info + 0xe) & 0xf;
1118  dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1119  tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1120  /* if the values are all zeros, use the table */
1121  if (tv_dac->ps2_tvdac_adj)
1122  found = 1;
1123  }
1124  tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1125  }
1126  if (!found) {
1127  /* then check CRT table */
1128  dac_info =
1129  combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1130  if (dac_info) {
1131  rev = RBIOS8(dac_info) & 0x3;
1132  if (rev < 2) {
1133  bg = RBIOS8(dac_info + 0x3) & 0xf;
1134  dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1135  tv_dac->ps2_tvdac_adj =
1136  (bg << 16) | (dac << 20);
1137  tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1138  tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1139  /* if the values are all zeros, use the table */
1140  if (tv_dac->ps2_tvdac_adj)
1141  found = 1;
1142  } else {
1143  bg = RBIOS8(dac_info + 0x4) & 0xf;
1144  dac = RBIOS8(dac_info + 0x5) & 0xf;
1145  tv_dac->ps2_tvdac_adj =
1146  (bg << 16) | (dac << 20);
1147  tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1148  tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1149  /* if the values are all zeros, use the table */
1150  if (tv_dac->ps2_tvdac_adj)
1151  found = 1;
1152  }
1153  } else {
1154  DRM_INFO("No TV DAC info found in BIOS\n");
1155  }
1156  }
1157 
1158  if (!found) /* fallback to defaults */
1159  radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1160 
1161  return tv_dac;
1162 }
1163 
1164 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1165  radeon_device
1166  *rdev)
1167 {
1168  struct radeon_encoder_lvds *lvds = NULL;
1169  uint32_t fp_vert_stretch, fp_horz_stretch;
1170  uint32_t ppll_div_sel, ppll_val;
1171  uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1172 
1173  lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1174 
1175  if (!lvds)
1176  return NULL;
1177 
1178  fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1179  fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1180 
1181  /* These should be fail-safe defaults, fingers crossed */
1182  lvds->panel_pwr_delay = 200;
1183  lvds->panel_vcc_delay = 2000;
1184 
1185  lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1186  lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1187  lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1188 
1189  if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1190  lvds->native_mode.vdisplay =
1191  ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1192  RADEON_VERT_PANEL_SHIFT) + 1;
1193  else
1194  lvds->native_mode.vdisplay =
1195  (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1196 
1197  if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1198  lvds->native_mode.hdisplay =
1199  (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1200  RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1201  else
1202  lvds->native_mode.hdisplay =
1203  ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1204 
1205  if ((lvds->native_mode.hdisplay < 640) ||
1206  (lvds->native_mode.vdisplay < 480)) {
1207  lvds->native_mode.hdisplay = 640;
1208  lvds->native_mode.vdisplay = 480;
1209  }
1210 
1211  ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1212  ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1213  if ((ppll_val & 0x000707ff) == 0x1bb)
1214  lvds->use_bios_dividers = false;
1215  else {
1216  lvds->panel_ref_divider =
1217  RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1218  lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1219  lvds->panel_fb_divider = ppll_val & 0x7ff;
1220 
1221  if ((lvds->panel_ref_divider != 0) &&
1222  (lvds->panel_fb_divider > 3))
1223  lvds->use_bios_dividers = true;
1224  }
1225  lvds->panel_vcc_delay = 200;
1226 
1227  DRM_INFO("Panel info derived from registers\n");
1228  DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1229  lvds->native_mode.vdisplay);
1230 
1231  return lvds;
1232 }
1233 
1234 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1235  *encoder)
1236 {
1237  struct drm_device *dev = encoder->base.dev;
1238  struct radeon_device *rdev = dev->dev_private;
1239  uint16_t lcd_info;
1240  uint32_t panel_setup;
1241  char stmp[30];
1242  int tmp, i;
1243  struct radeon_encoder_lvds *lvds = NULL;
1244 
1245  lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1246 
1247  if (lcd_info) {
1248  lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1249 
1250  if (!lvds)
1251  return NULL;
1252 
1253  for (i = 0; i < 24; i++)
1254  stmp[i] = RBIOS8(lcd_info + i + 1);
1255  stmp[24] = 0;
1256 
1257  DRM_INFO("Panel ID String: %s\n", stmp);
1258 
1259  lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1260  lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1261 
1262  DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1263  lvds->native_mode.vdisplay);
1264 
1265  lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1266  lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1267 
1268  lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1269  lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1270  lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1271 
1272  lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1273  lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1274  lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1275  if ((lvds->panel_ref_divider != 0) &&
1276  (lvds->panel_fb_divider > 3))
1277  lvds->use_bios_dividers = true;
1278 
1279  panel_setup = RBIOS32(lcd_info + 0x39);
1280  lvds->lvds_gen_cntl = 0xff00;
1281  if (panel_setup & 0x1)
1282  lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1283 
1284  if ((panel_setup >> 4) & 0x1)
1285  lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1286 
1287  switch ((panel_setup >> 8) & 0x7) {
1288  case 0:
1289  lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1290  break;
1291  case 1:
1292  lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1293  break;
1294  case 2:
1295  lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1296  break;
1297  default:
1298  break;
1299  }
1300 
1301  if ((panel_setup >> 16) & 0x1)
1302  lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1303 
1304  if ((panel_setup >> 17) & 0x1)
1305  lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1306 
1307  if ((panel_setup >> 18) & 0x1)
1308  lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1309 
1310  if ((panel_setup >> 23) & 0x1)
1311  lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1312 
1313  lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1314 
1315  for (i = 0; i < 32; i++) {
1316  tmp = RBIOS16(lcd_info + 64 + i * 2);
1317  if (tmp == 0)
1318  break;
1319 
1320  if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1321  (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1322  lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1323  (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1324  lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1325  (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1326  lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1327  (RBIOS8(tmp + 23) * 8);
1328 
1329  lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1330  (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1331  lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1332  ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1333  lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1334  ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1335 
1336  lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1337  lvds->native_mode.flags = 0;
1338  /* set crtc values */
1339  drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1340 
1341  }
1342  }
1343  } else {
1344  DRM_INFO("No panel info found in BIOS\n");
1345  lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1346  }
1347 
1348  if (lvds)
1349  encoder->native_mode = lvds->native_mode;
1350  return lvds;
1351 }
1352 
1353 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1354  {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1355  {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1356  {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1357  {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1358  {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1359  {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1360  {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1361  {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1362  {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1363  {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1364  {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1365  {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1366  {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1367  {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1368  {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1369  {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1370  { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1371  { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1372 };
1373 
1374 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1375  struct radeon_encoder_int_tmds *tmds)
1376 {
1377  struct drm_device *dev = encoder->base.dev;
1378  struct radeon_device *rdev = dev->dev_private;
1379  int i;
1380 
1381  for (i = 0; i < 4; i++) {
1382  tmds->tmds_pll[i].value =
1383  default_tmds_pll[rdev->family][i].value;
1384  tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1385  }
1386 
1387  return true;
1388 }
1389 
1390 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1391  struct radeon_encoder_int_tmds *tmds)
1392 {
1393  struct drm_device *dev = encoder->base.dev;
1394  struct radeon_device *rdev = dev->dev_private;
1395  uint16_t tmds_info;
1396  int i, n;
1397  uint8_t ver;
1398 
1399  tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1400 
1401  if (tmds_info) {
1402  ver = RBIOS8(tmds_info);
1403  DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1404  if (ver == 3) {
1405  n = RBIOS8(tmds_info + 5) + 1;
1406  if (n > 4)
1407  n = 4;
1408  for (i = 0; i < n; i++) {
1409  tmds->tmds_pll[i].value =
1410  RBIOS32(tmds_info + i * 10 + 0x08);
1411  tmds->tmds_pll[i].freq =
1412  RBIOS16(tmds_info + i * 10 + 0x10);
1413  DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1414  tmds->tmds_pll[i].freq,
1415  tmds->tmds_pll[i].value);
1416  }
1417  } else if (ver == 4) {
1418  int stride = 0;
1419  n = RBIOS8(tmds_info + 5) + 1;
1420  if (n > 4)
1421  n = 4;
1422  for (i = 0; i < n; i++) {
1423  tmds->tmds_pll[i].value =
1424  RBIOS32(tmds_info + stride + 0x08);
1425  tmds->tmds_pll[i].freq =
1426  RBIOS16(tmds_info + stride + 0x10);
1427  if (i == 0)
1428  stride += 10;
1429  else
1430  stride += 6;
1431  DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1432  tmds->tmds_pll[i].freq,
1433  tmds->tmds_pll[i].value);
1434  }
1435  }
1436  } else {
1437  DRM_INFO("No TMDS info found in BIOS\n");
1438  return false;
1439  }
1440  return true;
1441 }
1442 
1443 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1444  struct radeon_encoder_ext_tmds *tmds)
1445 {
1446  struct drm_device *dev = encoder->base.dev;
1447  struct radeon_device *rdev = dev->dev_private;
1448  struct radeon_i2c_bus_rec i2c_bus;
1449 
1450  /* default for macs */
1451  i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1452  tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1453 
1454  /* XXX some macs have duallink chips */
1455  switch (rdev->mode_info.connector_table) {
1456  case CT_POWERBOOK_EXTERNAL:
1457  case CT_MINI_EXTERNAL:
1458  default:
1459  tmds->dvo_chip = DVO_SIL164;
1460  tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1461  break;
1462  }
1463 
1464  return true;
1465 }
1466 
1467 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1468  struct radeon_encoder_ext_tmds *tmds)
1469 {
1470  struct drm_device *dev = encoder->base.dev;
1471  struct radeon_device *rdev = dev->dev_private;
1472  uint16_t offset;
1473  uint8_t ver;
1474  enum radeon_combios_ddc gpio;
1475  struct radeon_i2c_bus_rec i2c_bus;
1476 
1477  tmds->i2c_bus = NULL;
1478  if (rdev->flags & RADEON_IS_IGP) {
1479  i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1480  tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1481  tmds->dvo_chip = DVO_SIL164;
1482  tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1483  } else {
1484  offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1485  if (offset) {
1486  ver = RBIOS8(offset);
1487  DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1488  tmds->slave_addr = RBIOS8(offset + 4 + 2);
1489  tmds->slave_addr >>= 1; /* 7 bit addressing */
1490  gpio = RBIOS8(offset + 4 + 3);
1491  if (gpio == DDC_LCD) {
1492  /* MM i2c */
1493  i2c_bus.valid = true;
1494  i2c_bus.hw_capable = true;
1495  i2c_bus.mm_i2c = true;
1496  i2c_bus.i2c_id = 0xa0;
1497  } else
1498  i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1499  tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1500  }
1501  }
1502 
1503  if (!tmds->i2c_bus) {
1504  DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1505  return false;
1506  }
1507 
1508  return true;
1509 }
1510 
1511 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1512 {
1513  struct radeon_device *rdev = dev->dev_private;
1514  struct radeon_i2c_bus_rec ddc_i2c;
1515  struct radeon_hpd hpd;
1516 
1517  rdev->mode_info.connector_table = radeon_connector_table;
1518  if (rdev->mode_info.connector_table == CT_NONE) {
1519 #ifdef CONFIG_PPC_PMAC
1520  if (of_machine_is_compatible("PowerBook3,3")) {
1521  /* powerbook with VGA */
1522  rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1523  } else if (of_machine_is_compatible("PowerBook3,4") ||
1524  of_machine_is_compatible("PowerBook3,5")) {
1525  /* powerbook with internal tmds */
1526  rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1527  } else if (of_machine_is_compatible("PowerBook5,1") ||
1528  of_machine_is_compatible("PowerBook5,2") ||
1529  of_machine_is_compatible("PowerBook5,3") ||
1530  of_machine_is_compatible("PowerBook5,4") ||
1531  of_machine_is_compatible("PowerBook5,5")) {
1532  /* powerbook with external single link tmds (sil164) */
1533  rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1534  } else if (of_machine_is_compatible("PowerBook5,6")) {
1535  /* powerbook with external dual or single link tmds */
1536  rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1537  } else if (of_machine_is_compatible("PowerBook5,7") ||
1538  of_machine_is_compatible("PowerBook5,8") ||
1539  of_machine_is_compatible("PowerBook5,9")) {
1540  /* PowerBook6,2 ? */
1541  /* powerbook with external dual link tmds (sil1178?) */
1542  rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1543  } else if (of_machine_is_compatible("PowerBook4,1") ||
1544  of_machine_is_compatible("PowerBook4,2") ||
1545  of_machine_is_compatible("PowerBook4,3") ||
1546  of_machine_is_compatible("PowerBook6,3") ||
1547  of_machine_is_compatible("PowerBook6,5") ||
1548  of_machine_is_compatible("PowerBook6,7")) {
1549  /* ibook */
1550  rdev->mode_info.connector_table = CT_IBOOK;
1551  } else if (of_machine_is_compatible("PowerMac4,4")) {
1552  /* emac */
1553  rdev->mode_info.connector_table = CT_EMAC;
1554  } else if (of_machine_is_compatible("PowerMac10,1")) {
1555  /* mini with internal tmds */
1556  rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1557  } else if (of_machine_is_compatible("PowerMac10,2")) {
1558  /* mini with external tmds */
1559  rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1560  } else if (of_machine_is_compatible("PowerMac12,1")) {
1561  /* PowerMac8,1 ? */
1562  /* imac g5 isight */
1563  rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1564  } else if ((rdev->pdev->device == 0x4a48) &&
1565  (rdev->pdev->subsystem_vendor == 0x1002) &&
1566  (rdev->pdev->subsystem_device == 0x4a48)) {
1567  /* Mac X800 */
1568  rdev->mode_info.connector_table = CT_MAC_X800;
1569  } else if ((of_machine_is_compatible("PowerMac7,2") ||
1570  of_machine_is_compatible("PowerMac7,3")) &&
1571  (rdev->pdev->device == 0x4150) &&
1572  (rdev->pdev->subsystem_vendor == 0x1002) &&
1573  (rdev->pdev->subsystem_device == 0x4150)) {
1574  /* Mac G5 tower 9600 */
1575  rdev->mode_info.connector_table = CT_MAC_G5_9600;
1576  } else if ((rdev->pdev->device == 0x4c66) &&
1577  (rdev->pdev->subsystem_vendor == 0x1002) &&
1578  (rdev->pdev->subsystem_device == 0x4c66)) {
1579  /* SAM440ep RV250 embedded board */
1580  rdev->mode_info.connector_table = CT_SAM440EP;
1581  } else
1582 #endif /* CONFIG_PPC_PMAC */
1583 #ifdef CONFIG_PPC64
1584  if (ASIC_IS_RN50(rdev))
1585  rdev->mode_info.connector_table = CT_RN50_POWER;
1586  else
1587 #endif
1588  rdev->mode_info.connector_table = CT_GENERIC;
1589  }
1590 
1591  switch (rdev->mode_info.connector_table) {
1592  case CT_GENERIC:
1593  DRM_INFO("Connector Table: %d (generic)\n",
1594  rdev->mode_info.connector_table);
1595  /* these are the most common settings */
1596  if (rdev->flags & RADEON_SINGLE_CRTC) {
1597  /* VGA - primary dac */
1598  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1599  hpd.hpd = RADEON_HPD_NONE;
1600  radeon_add_legacy_encoder(dev,
1601  radeon_get_encoder_enum(dev,
1602  ATOM_DEVICE_CRT1_SUPPORT,
1603  1),
1604  ATOM_DEVICE_CRT1_SUPPORT);
1605  radeon_add_legacy_connector(dev, 0,
1606  ATOM_DEVICE_CRT1_SUPPORT,
1607  DRM_MODE_CONNECTOR_VGA,
1608  &ddc_i2c,
1609  CONNECTOR_OBJECT_ID_VGA,
1610  &hpd);
1611  } else if (rdev->flags & RADEON_IS_MOBILITY) {
1612  /* LVDS */
1613  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1614  hpd.hpd = RADEON_HPD_NONE;
1615  radeon_add_legacy_encoder(dev,
1616  radeon_get_encoder_enum(dev,
1617  ATOM_DEVICE_LCD1_SUPPORT,
1618  0),
1619  ATOM_DEVICE_LCD1_SUPPORT);
1620  radeon_add_legacy_connector(dev, 0,
1621  ATOM_DEVICE_LCD1_SUPPORT,
1622  DRM_MODE_CONNECTOR_LVDS,
1623  &ddc_i2c,
1624  CONNECTOR_OBJECT_ID_LVDS,
1625  &hpd);
1626 
1627  /* VGA - primary dac */
1628  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1629  hpd.hpd = RADEON_HPD_NONE;
1630  radeon_add_legacy_encoder(dev,
1631  radeon_get_encoder_enum(dev,
1632  ATOM_DEVICE_CRT1_SUPPORT,
1633  1),
1634  ATOM_DEVICE_CRT1_SUPPORT);
1635  radeon_add_legacy_connector(dev, 1,
1636  ATOM_DEVICE_CRT1_SUPPORT,
1637  DRM_MODE_CONNECTOR_VGA,
1638  &ddc_i2c,
1639  CONNECTOR_OBJECT_ID_VGA,
1640  &hpd);
1641  } else {
1642  /* DVI-I - tv dac, int tmds */
1643  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1644  hpd.hpd = RADEON_HPD_1;
1645  radeon_add_legacy_encoder(dev,
1646  radeon_get_encoder_enum(dev,
1647  ATOM_DEVICE_DFP1_SUPPORT,
1648  0),
1649  ATOM_DEVICE_DFP1_SUPPORT);
1650  radeon_add_legacy_encoder(dev,
1651  radeon_get_encoder_enum(dev,
1652  ATOM_DEVICE_CRT2_SUPPORT,
1653  2),
1654  ATOM_DEVICE_CRT2_SUPPORT);
1655  radeon_add_legacy_connector(dev, 0,
1656  ATOM_DEVICE_DFP1_SUPPORT |
1657  ATOM_DEVICE_CRT2_SUPPORT,
1658  DRM_MODE_CONNECTOR_DVII,
1659  &ddc_i2c,
1660  CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1661  &hpd);
1662 
1663  /* VGA - primary dac */
1664  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1665  hpd.hpd = RADEON_HPD_NONE;
1666  radeon_add_legacy_encoder(dev,
1667  radeon_get_encoder_enum(dev,
1668  ATOM_DEVICE_CRT1_SUPPORT,
1669  1),
1670  ATOM_DEVICE_CRT1_SUPPORT);
1671  radeon_add_legacy_connector(dev, 1,
1672  ATOM_DEVICE_CRT1_SUPPORT,
1673  DRM_MODE_CONNECTOR_VGA,
1674  &ddc_i2c,
1675  CONNECTOR_OBJECT_ID_VGA,
1676  &hpd);
1677  }
1678 
1679  if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1680  /* TV - tv dac */
1681  ddc_i2c.valid = false;
1682  hpd.hpd = RADEON_HPD_NONE;
1683  radeon_add_legacy_encoder(dev,
1684  radeon_get_encoder_enum(dev,
1685  ATOM_DEVICE_TV1_SUPPORT,
1686  2),
1687  ATOM_DEVICE_TV1_SUPPORT);
1688  radeon_add_legacy_connector(dev, 2,
1689  ATOM_DEVICE_TV1_SUPPORT,
1690  DRM_MODE_CONNECTOR_SVIDEO,
1691  &ddc_i2c,
1692  CONNECTOR_OBJECT_ID_SVIDEO,
1693  &hpd);
1694  }
1695  break;
1696  case CT_IBOOK:
1697  DRM_INFO("Connector Table: %d (ibook)\n",
1698  rdev->mode_info.connector_table);
1699  /* LVDS */
1700  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1701  hpd.hpd = RADEON_HPD_NONE;
1702  radeon_add_legacy_encoder(dev,
1703  radeon_get_encoder_enum(dev,
1704  ATOM_DEVICE_LCD1_SUPPORT,
1705  0),
1706  ATOM_DEVICE_LCD1_SUPPORT);
1707  radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1708  DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1709  CONNECTOR_OBJECT_ID_LVDS,
1710  &hpd);
1711  /* VGA - TV DAC */
1712  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1713  hpd.hpd = RADEON_HPD_NONE;
1714  radeon_add_legacy_encoder(dev,
1715  radeon_get_encoder_enum(dev,
1716  ATOM_DEVICE_CRT2_SUPPORT,
1717  2),
1718  ATOM_DEVICE_CRT2_SUPPORT);
1719  radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1720  DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1721  CONNECTOR_OBJECT_ID_VGA,
1722  &hpd);
1723  /* TV - TV DAC */
1724  ddc_i2c.valid = false;
1725  hpd.hpd = RADEON_HPD_NONE;
1726  radeon_add_legacy_encoder(dev,
1727  radeon_get_encoder_enum(dev,
1728  ATOM_DEVICE_TV1_SUPPORT,
1729  2),
1730  ATOM_DEVICE_TV1_SUPPORT);
1731  radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1732  DRM_MODE_CONNECTOR_SVIDEO,
1733  &ddc_i2c,
1734  CONNECTOR_OBJECT_ID_SVIDEO,
1735  &hpd);
1736  break;
1737  case CT_POWERBOOK_EXTERNAL:
1738  DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1739  rdev->mode_info.connector_table);
1740  /* LVDS */
1741  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1742  hpd.hpd = RADEON_HPD_NONE;
1743  radeon_add_legacy_encoder(dev,
1744  radeon_get_encoder_enum(dev,
1745  ATOM_DEVICE_LCD1_SUPPORT,
1746  0),
1747  ATOM_DEVICE_LCD1_SUPPORT);
1748  radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1749  DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1750  CONNECTOR_OBJECT_ID_LVDS,
1751  &hpd);
1752  /* DVI-I - primary dac, ext tmds */
1753  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1754  hpd.hpd = RADEON_HPD_2; /* ??? */
1755  radeon_add_legacy_encoder(dev,
1756  radeon_get_encoder_enum(dev,
1757  ATOM_DEVICE_DFP2_SUPPORT,
1758  0),
1759  ATOM_DEVICE_DFP2_SUPPORT);
1760  radeon_add_legacy_encoder(dev,
1761  radeon_get_encoder_enum(dev,
1762  ATOM_DEVICE_CRT1_SUPPORT,
1763  1),
1764  ATOM_DEVICE_CRT1_SUPPORT);
1765  /* XXX some are SL */
1766  radeon_add_legacy_connector(dev, 1,
1767  ATOM_DEVICE_DFP2_SUPPORT |
1768  ATOM_DEVICE_CRT1_SUPPORT,
1769  DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1770  CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1771  &hpd);
1772  /* TV - TV DAC */
1773  ddc_i2c.valid = false;
1774  hpd.hpd = RADEON_HPD_NONE;
1775  radeon_add_legacy_encoder(dev,
1776  radeon_get_encoder_enum(dev,
1777  ATOM_DEVICE_TV1_SUPPORT,
1778  2),
1779  ATOM_DEVICE_TV1_SUPPORT);
1780  radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1781  DRM_MODE_CONNECTOR_SVIDEO,
1782  &ddc_i2c,
1783  CONNECTOR_OBJECT_ID_SVIDEO,
1784  &hpd);
1785  break;
1786  case CT_POWERBOOK_INTERNAL:
1787  DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1788  rdev->mode_info.connector_table);
1789  /* LVDS */
1790  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1791  hpd.hpd = RADEON_HPD_NONE;
1792  radeon_add_legacy_encoder(dev,
1793  radeon_get_encoder_enum(dev,
1794  ATOM_DEVICE_LCD1_SUPPORT,
1795  0),
1796  ATOM_DEVICE_LCD1_SUPPORT);
1797  radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1798  DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1799  CONNECTOR_OBJECT_ID_LVDS,
1800  &hpd);
1801  /* DVI-I - primary dac, int tmds */
1802  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1803  hpd.hpd = RADEON_HPD_1; /* ??? */
1804  radeon_add_legacy_encoder(dev,
1805  radeon_get_encoder_enum(dev,
1806  ATOM_DEVICE_DFP1_SUPPORT,
1807  0),
1808  ATOM_DEVICE_DFP1_SUPPORT);
1809  radeon_add_legacy_encoder(dev,
1810  radeon_get_encoder_enum(dev,
1811  ATOM_DEVICE_CRT1_SUPPORT,
1812  1),
1813  ATOM_DEVICE_CRT1_SUPPORT);
1814  radeon_add_legacy_connector(dev, 1,
1815  ATOM_DEVICE_DFP1_SUPPORT |
1816  ATOM_DEVICE_CRT1_SUPPORT,
1817  DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1818  CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1819  &hpd);
1820  /* TV - TV DAC */
1821  ddc_i2c.valid = false;
1822  hpd.hpd = RADEON_HPD_NONE;
1823  radeon_add_legacy_encoder(dev,
1824  radeon_get_encoder_enum(dev,
1825  ATOM_DEVICE_TV1_SUPPORT,
1826  2),
1827  ATOM_DEVICE_TV1_SUPPORT);
1828  radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1829  DRM_MODE_CONNECTOR_SVIDEO,
1830  &ddc_i2c,
1831  CONNECTOR_OBJECT_ID_SVIDEO,
1832  &hpd);
1833  break;
1834  case CT_POWERBOOK_VGA:
1835  DRM_INFO("Connector Table: %d (powerbook vga)\n",
1836  rdev->mode_info.connector_table);
1837  /* LVDS */
1838  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1839  hpd.hpd = RADEON_HPD_NONE;
1840  radeon_add_legacy_encoder(dev,
1841  radeon_get_encoder_enum(dev,
1842  ATOM_DEVICE_LCD1_SUPPORT,
1843  0),
1844  ATOM_DEVICE_LCD1_SUPPORT);
1845  radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1846  DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1847  CONNECTOR_OBJECT_ID_LVDS,
1848  &hpd);
1849  /* VGA - primary dac */
1850  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1851  hpd.hpd = RADEON_HPD_NONE;
1852  radeon_add_legacy_encoder(dev,
1853  radeon_get_encoder_enum(dev,
1854  ATOM_DEVICE_CRT1_SUPPORT,
1855  1),
1856  ATOM_DEVICE_CRT1_SUPPORT);
1857  radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1858  DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1859  CONNECTOR_OBJECT_ID_VGA,
1860  &hpd);
1861  /* TV - TV DAC */
1862  ddc_i2c.valid = false;
1863  hpd.hpd = RADEON_HPD_NONE;
1864  radeon_add_legacy_encoder(dev,
1865  radeon_get_encoder_enum(dev,
1866  ATOM_DEVICE_TV1_SUPPORT,
1867  2),
1868  ATOM_DEVICE_TV1_SUPPORT);
1869  radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1870  DRM_MODE_CONNECTOR_SVIDEO,
1871  &ddc_i2c,
1872  CONNECTOR_OBJECT_ID_SVIDEO,
1873  &hpd);
1874  break;
1875  case CT_MINI_EXTERNAL:
1876  DRM_INFO("Connector Table: %d (mini external tmds)\n",
1877  rdev->mode_info.connector_table);
1878  /* DVI-I - tv dac, ext tmds */
1879  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1880  hpd.hpd = RADEON_HPD_2; /* ??? */
1881  radeon_add_legacy_encoder(dev,
1882  radeon_get_encoder_enum(dev,
1883  ATOM_DEVICE_DFP2_SUPPORT,
1884  0),
1885  ATOM_DEVICE_DFP2_SUPPORT);
1886  radeon_add_legacy_encoder(dev,
1887  radeon_get_encoder_enum(dev,
1888  ATOM_DEVICE_CRT2_SUPPORT,
1889  2),
1890  ATOM_DEVICE_CRT2_SUPPORT);
1891  /* XXX are any DL? */
1892  radeon_add_legacy_connector(dev, 0,
1893  ATOM_DEVICE_DFP2_SUPPORT |
1894  ATOM_DEVICE_CRT2_SUPPORT,
1895  DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1896  CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1897  &hpd);
1898  /* TV - TV DAC */
1899  ddc_i2c.valid = false;
1900  hpd.hpd = RADEON_HPD_NONE;
1901  radeon_add_legacy_encoder(dev,
1902  radeon_get_encoder_enum(dev,
1903  ATOM_DEVICE_TV1_SUPPORT,
1904  2),
1905  ATOM_DEVICE_TV1_SUPPORT);
1906  radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1907  DRM_MODE_CONNECTOR_SVIDEO,
1908  &ddc_i2c,
1909  CONNECTOR_OBJECT_ID_SVIDEO,
1910  &hpd);
1911  break;
1912  case CT_MINI_INTERNAL:
1913  DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1914  rdev->mode_info.connector_table);
1915  /* DVI-I - tv dac, int tmds */
1916  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1917  hpd.hpd = RADEON_HPD_1; /* ??? */
1918  radeon_add_legacy_encoder(dev,
1919  radeon_get_encoder_enum(dev,
1920  ATOM_DEVICE_DFP1_SUPPORT,
1921  0),
1922  ATOM_DEVICE_DFP1_SUPPORT);
1923  radeon_add_legacy_encoder(dev,
1924  radeon_get_encoder_enum(dev,
1925  ATOM_DEVICE_CRT2_SUPPORT,
1926  2),
1927  ATOM_DEVICE_CRT2_SUPPORT);
1928  radeon_add_legacy_connector(dev, 0,
1929  ATOM_DEVICE_DFP1_SUPPORT |
1930  ATOM_DEVICE_CRT2_SUPPORT,
1931  DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1932  CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1933  &hpd);
1934  /* TV - TV DAC */
1935  ddc_i2c.valid = false;
1936  hpd.hpd = RADEON_HPD_NONE;
1937  radeon_add_legacy_encoder(dev,
1938  radeon_get_encoder_enum(dev,
1939  ATOM_DEVICE_TV1_SUPPORT,
1940  2),
1941  ATOM_DEVICE_TV1_SUPPORT);
1942  radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1943  DRM_MODE_CONNECTOR_SVIDEO,
1944  &ddc_i2c,
1945  CONNECTOR_OBJECT_ID_SVIDEO,
1946  &hpd);
1947  break;
1948  case CT_IMAC_G5_ISIGHT:
1949  DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1950  rdev->mode_info.connector_table);
1951  /* DVI-D - int tmds */
1952  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1953  hpd.hpd = RADEON_HPD_1; /* ??? */
1954  radeon_add_legacy_encoder(dev,
1955  radeon_get_encoder_enum(dev,
1956  ATOM_DEVICE_DFP1_SUPPORT,
1957  0),
1958  ATOM_DEVICE_DFP1_SUPPORT);
1959  radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1960  DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1961  CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1962  &hpd);
1963  /* VGA - tv dac */
1964  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1965  hpd.hpd = RADEON_HPD_NONE;
1966  radeon_add_legacy_encoder(dev,
1967  radeon_get_encoder_enum(dev,
1968  ATOM_DEVICE_CRT2_SUPPORT,
1969  2),
1970  ATOM_DEVICE_CRT2_SUPPORT);
1971  radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1972  DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1973  CONNECTOR_OBJECT_ID_VGA,
1974  &hpd);
1975  /* TV - TV DAC */
1976  ddc_i2c.valid = false;
1977  hpd.hpd = RADEON_HPD_NONE;
1978  radeon_add_legacy_encoder(dev,
1979  radeon_get_encoder_enum(dev,
1980  ATOM_DEVICE_TV1_SUPPORT,
1981  2),
1982  ATOM_DEVICE_TV1_SUPPORT);
1983  radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1984  DRM_MODE_CONNECTOR_SVIDEO,
1985  &ddc_i2c,
1986  CONNECTOR_OBJECT_ID_SVIDEO,
1987  &hpd);
1988  break;
1989  case CT_EMAC:
1990  DRM_INFO("Connector Table: %d (emac)\n",
1991  rdev->mode_info.connector_table);
1992  /* VGA - primary dac */
1993  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1994  hpd.hpd = RADEON_HPD_NONE;
1995  radeon_add_legacy_encoder(dev,
1996  radeon_get_encoder_enum(dev,
1997  ATOM_DEVICE_CRT1_SUPPORT,
1998  1),
1999  ATOM_DEVICE_CRT1_SUPPORT);
2000  radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2001  DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2002  CONNECTOR_OBJECT_ID_VGA,
2003  &hpd);
2004  /* VGA - tv dac */
2005  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2006  hpd.hpd = RADEON_HPD_NONE;
2007  radeon_add_legacy_encoder(dev,
2008  radeon_get_encoder_enum(dev,
2009  ATOM_DEVICE_CRT2_SUPPORT,
2010  2),
2011  ATOM_DEVICE_CRT2_SUPPORT);
2012  radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2013  DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2014  CONNECTOR_OBJECT_ID_VGA,
2015  &hpd);
2016  /* TV - TV DAC */
2017  ddc_i2c.valid = false;
2018  hpd.hpd = RADEON_HPD_NONE;
2019  radeon_add_legacy_encoder(dev,
2020  radeon_get_encoder_enum(dev,
2021  ATOM_DEVICE_TV1_SUPPORT,
2022  2),
2023  ATOM_DEVICE_TV1_SUPPORT);
2024  radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2025  DRM_MODE_CONNECTOR_SVIDEO,
2026  &ddc_i2c,
2027  CONNECTOR_OBJECT_ID_SVIDEO,
2028  &hpd);
2029  break;
2030  case CT_RN50_POWER:
2031  DRM_INFO("Connector Table: %d (rn50-power)\n",
2032  rdev->mode_info.connector_table);
2033  /* VGA - primary dac */
2034  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2035  hpd.hpd = RADEON_HPD_NONE;
2036  radeon_add_legacy_encoder(dev,
2037  radeon_get_encoder_enum(dev,
2038  ATOM_DEVICE_CRT1_SUPPORT,
2039  1),
2040  ATOM_DEVICE_CRT1_SUPPORT);
2041  radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2042  DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2043  CONNECTOR_OBJECT_ID_VGA,
2044  &hpd);
2045  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2046  hpd.hpd = RADEON_HPD_NONE;
2047  radeon_add_legacy_encoder(dev,
2048  radeon_get_encoder_enum(dev,
2049  ATOM_DEVICE_CRT2_SUPPORT,
2050  2),
2051  ATOM_DEVICE_CRT2_SUPPORT);
2052  radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2053  DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2054  CONNECTOR_OBJECT_ID_VGA,
2055  &hpd);
2056  break;
2057  case CT_MAC_X800:
2058  DRM_INFO("Connector Table: %d (mac x800)\n",
2059  rdev->mode_info.connector_table);
2060  /* DVI - primary dac, internal tmds */
2061  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2062  hpd.hpd = RADEON_HPD_1; /* ??? */
2063  radeon_add_legacy_encoder(dev,
2064  radeon_get_encoder_enum(dev,
2065  ATOM_DEVICE_DFP1_SUPPORT,
2066  0),
2067  ATOM_DEVICE_DFP1_SUPPORT);
2068  radeon_add_legacy_encoder(dev,
2069  radeon_get_encoder_enum(dev,
2070  ATOM_DEVICE_CRT1_SUPPORT,
2071  1),
2072  ATOM_DEVICE_CRT1_SUPPORT);
2073  radeon_add_legacy_connector(dev, 0,
2074  ATOM_DEVICE_DFP1_SUPPORT |
2075  ATOM_DEVICE_CRT1_SUPPORT,
2076  DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2077  CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2078  &hpd);
2079  /* DVI - tv dac, dvo */
2080  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2081  hpd.hpd = RADEON_HPD_2; /* ??? */
2082  radeon_add_legacy_encoder(dev,
2083  radeon_get_encoder_enum(dev,
2084  ATOM_DEVICE_DFP2_SUPPORT,
2085  0),
2086  ATOM_DEVICE_DFP2_SUPPORT);
2087  radeon_add_legacy_encoder(dev,
2088  radeon_get_encoder_enum(dev,
2089  ATOM_DEVICE_CRT2_SUPPORT,
2090  2),
2091  ATOM_DEVICE_CRT2_SUPPORT);
2092  radeon_add_legacy_connector(dev, 1,
2093  ATOM_DEVICE_DFP2_SUPPORT |
2094  ATOM_DEVICE_CRT2_SUPPORT,
2095  DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2096  CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2097  &hpd);
2098  break;
2099  case CT_MAC_G5_9600:
2100  DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2101  rdev->mode_info.connector_table);
2102  /* DVI - tv dac, dvo */
2103  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2104  hpd.hpd = RADEON_HPD_1; /* ??? */
2105  radeon_add_legacy_encoder(dev,
2106  radeon_get_encoder_enum(dev,
2107  ATOM_DEVICE_DFP2_SUPPORT,
2108  0),
2109  ATOM_DEVICE_DFP2_SUPPORT);
2110  radeon_add_legacy_encoder(dev,
2111  radeon_get_encoder_enum(dev,
2112  ATOM_DEVICE_CRT2_SUPPORT,
2113  2),
2114  ATOM_DEVICE_CRT2_SUPPORT);
2115  radeon_add_legacy_connector(dev, 0,
2116  ATOM_DEVICE_DFP2_SUPPORT |
2117  ATOM_DEVICE_CRT2_SUPPORT,
2118  DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2119  CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2120  &hpd);
2121  /* ADC - primary dac, internal tmds */
2122  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2123  hpd.hpd = RADEON_HPD_2; /* ??? */
2124  radeon_add_legacy_encoder(dev,
2125  radeon_get_encoder_enum(dev,
2126  ATOM_DEVICE_DFP1_SUPPORT,
2127  0),
2128  ATOM_DEVICE_DFP1_SUPPORT);
2129  radeon_add_legacy_encoder(dev,
2130  radeon_get_encoder_enum(dev,
2131  ATOM_DEVICE_CRT1_SUPPORT,
2132  1),
2133  ATOM_DEVICE_CRT1_SUPPORT);
2134  radeon_add_legacy_connector(dev, 1,
2135  ATOM_DEVICE_DFP1_SUPPORT |
2136  ATOM_DEVICE_CRT1_SUPPORT,
2137  DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2138  CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2139  &hpd);
2140  /* TV - TV DAC */
2141  ddc_i2c.valid = false;
2142  hpd.hpd = RADEON_HPD_NONE;
2143  radeon_add_legacy_encoder(dev,
2144  radeon_get_encoder_enum(dev,
2145  ATOM_DEVICE_TV1_SUPPORT,
2146  2),
2147  ATOM_DEVICE_TV1_SUPPORT);
2148  radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2149  DRM_MODE_CONNECTOR_SVIDEO,
2150  &ddc_i2c,
2151  CONNECTOR_OBJECT_ID_SVIDEO,
2152  &hpd);
2153  break;
2154  case CT_SAM440EP:
2155  DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2156  rdev->mode_info.connector_table);
2157  /* LVDS */
2158  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2159  hpd.hpd = RADEON_HPD_NONE;
2160  radeon_add_legacy_encoder(dev,
2161  radeon_get_encoder_enum(dev,
2162  ATOM_DEVICE_LCD1_SUPPORT,
2163  0),
2164  ATOM_DEVICE_LCD1_SUPPORT);
2165  radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2166  DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2167  CONNECTOR_OBJECT_ID_LVDS,
2168  &hpd);
2169  /* DVI-I - secondary dac, int tmds */
2170  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2171  hpd.hpd = RADEON_HPD_1; /* ??? */
2172  radeon_add_legacy_encoder(dev,
2173  radeon_get_encoder_enum(dev,
2174  ATOM_DEVICE_DFP1_SUPPORT,
2175  0),
2176  ATOM_DEVICE_DFP1_SUPPORT);
2177  radeon_add_legacy_encoder(dev,
2178  radeon_get_encoder_enum(dev,
2179  ATOM_DEVICE_CRT2_SUPPORT,
2180  2),
2181  ATOM_DEVICE_CRT2_SUPPORT);
2182  radeon_add_legacy_connector(dev, 1,
2183  ATOM_DEVICE_DFP1_SUPPORT |
2184  ATOM_DEVICE_CRT2_SUPPORT,
2185  DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2186  CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2187  &hpd);
2188  /* VGA - primary dac */
2189  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2190  hpd.hpd = RADEON_HPD_NONE;
2191  radeon_add_legacy_encoder(dev,
2192  radeon_get_encoder_enum(dev,
2193  ATOM_DEVICE_CRT1_SUPPORT,
2194  1),
2195  ATOM_DEVICE_CRT1_SUPPORT);
2196  radeon_add_legacy_connector(dev, 2,
2197  ATOM_DEVICE_CRT1_SUPPORT,
2198  DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2199  CONNECTOR_OBJECT_ID_VGA,
2200  &hpd);
2201  /* TV - TV DAC */
2202  ddc_i2c.valid = false;
2203  hpd.hpd = RADEON_HPD_NONE;
2204  radeon_add_legacy_encoder(dev,
2205  radeon_get_encoder_enum(dev,
2206  ATOM_DEVICE_TV1_SUPPORT,
2207  2),
2208  ATOM_DEVICE_TV1_SUPPORT);
2209  radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2210  DRM_MODE_CONNECTOR_SVIDEO,
2211  &ddc_i2c,
2212  CONNECTOR_OBJECT_ID_SVIDEO,
2213  &hpd);
2214  break;
2215  default:
2216  DRM_INFO("Connector table: %d (invalid)\n",
2217  rdev->mode_info.connector_table);
2218  return false;
2219  }
2220 
2221  radeon_link_encoder_connector(dev);
2222 
2223  return true;
2224 }
2225 
2226 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2227  int bios_index,
2228  enum radeon_combios_connector
2229  *legacy_connector,
2230  struct radeon_i2c_bus_rec *ddc_i2c,
2231  struct radeon_hpd *hpd)
2232 {
2233 
2234  /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2235  one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2236  if (dev->pdev->device == 0x515e &&
2237  dev->pdev->subsystem_vendor == 0x1014) {
2238  if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2239  ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2240  return false;
2241  }
2242 
2243  /* X300 card with extra non-existent DVI port */
2244  if (dev->pdev->device == 0x5B60 &&
2245  dev->pdev->subsystem_vendor == 0x17af &&
2246  dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2247  if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2248  return false;
2249  }
2250 
2251  return true;
2252 }
2253 
2254 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2255 {
2256  /* Acer 5102 has non-existent TV port */
2257  if (dev->pdev->device == 0x5975 &&
2258  dev->pdev->subsystem_vendor == 0x1025 &&
2259  dev->pdev->subsystem_device == 0x009f)
2260  return false;
2261 
2262  /* HP dc5750 has non-existent TV port */
2263  if (dev->pdev->device == 0x5974 &&
2264  dev->pdev->subsystem_vendor == 0x103c &&
2265  dev->pdev->subsystem_device == 0x280a)
2266  return false;
2267 
2268  /* MSI S270 has non-existent TV port */
2269  if (dev->pdev->device == 0x5955 &&
2270  dev->pdev->subsystem_vendor == 0x1462 &&
2271  dev->pdev->subsystem_device == 0x0131)
2272  return false;
2273 
2274  return true;
2275 }
2276 
2277 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2278 {
2279  struct radeon_device *rdev = dev->dev_private;
2280  uint32_t ext_tmds_info;
2281 
2282  if (rdev->flags & RADEON_IS_IGP) {
2283  if (is_dvi_d)
2284  return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2285  else
2286  return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2287  }
2288  ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2289  if (ext_tmds_info) {
2290  uint8_t rev = RBIOS8(ext_tmds_info);
2291  uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2292  if (rev >= 3) {
2293  if (is_dvi_d)
2294  return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2295  else
2296  return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2297  } else {
2298  if (flags & 1) {
2299  if (is_dvi_d)
2300  return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2301  else
2302  return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2303  }
2304  }
2305  }
2306  if (is_dvi_d)
2307  return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2308  else
2309  return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2310 }
2311 
2312 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2313 {
2314  struct radeon_device *rdev = dev->dev_private;
2315  uint32_t conn_info, entry, devices;
2316  uint16_t tmp, connector_object_id;
2317  enum radeon_combios_ddc ddc_type;
2318  enum radeon_combios_connector connector;
2319  int i = 0;
2320  struct radeon_i2c_bus_rec ddc_i2c;
2321  struct radeon_hpd hpd;
2322 
2323  conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2324  if (conn_info) {
2325  for (i = 0; i < 4; i++) {
2326  entry = conn_info + 2 + i * 2;
2327 
2328  if (!RBIOS16(entry))
2329  break;
2330 
2331  tmp = RBIOS16(entry);
2332 
2333  connector = (tmp >> 12) & 0xf;
2334 
2335  ddc_type = (tmp >> 8) & 0xf;
2336  if (ddc_type == 5)
2337  ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2338  else
2339  ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2340 
2341  switch (connector) {
2342  case CONNECTOR_PROPRIETARY_LEGACY:
2343  case CONNECTOR_DVI_I_LEGACY:
2344  case CONNECTOR_DVI_D_LEGACY:
2345  if ((tmp >> 4) & 0x1)
2346  hpd.hpd = RADEON_HPD_2;
2347  else
2348  hpd.hpd = RADEON_HPD_1;
2349  break;
2350  default:
2351  hpd.hpd = RADEON_HPD_NONE;
2352  break;
2353  }
2354 
2355  if (!radeon_apply_legacy_quirks(dev, i, &connector,
2356  &ddc_i2c, &hpd))
2357  continue;
2358 
2359  switch (connector) {
2360  case CONNECTOR_PROPRIETARY_LEGACY:
2361  if ((tmp >> 4) & 0x1)
2362  devices = ATOM_DEVICE_DFP2_SUPPORT;
2363  else
2364  devices = ATOM_DEVICE_DFP1_SUPPORT;
2365  radeon_add_legacy_encoder(dev,
2366  radeon_get_encoder_enum
2367  (dev, devices, 0),
2368  devices);
2369  radeon_add_legacy_connector(dev, i, devices,
2370  legacy_connector_convert
2371  [connector],
2372  &ddc_i2c,
2373  CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2374  &hpd);
2375  break;
2376  case CONNECTOR_CRT_LEGACY:
2377  if (tmp & 0x1) {
2378  devices = ATOM_DEVICE_CRT2_SUPPORT;
2379  radeon_add_legacy_encoder(dev,
2380  radeon_get_encoder_enum
2381  (dev,
2382  ATOM_DEVICE_CRT2_SUPPORT,
2383  2),
2384  ATOM_DEVICE_CRT2_SUPPORT);
2385  } else {
2386  devices = ATOM_DEVICE_CRT1_SUPPORT;
2387  radeon_add_legacy_encoder(dev,
2388  radeon_get_encoder_enum
2389  (dev,
2390  ATOM_DEVICE_CRT1_SUPPORT,
2391  1),
2392  ATOM_DEVICE_CRT1_SUPPORT);
2393  }
2394  radeon_add_legacy_connector(dev,
2395  i,
2396  devices,
2397  legacy_connector_convert
2398  [connector],
2399  &ddc_i2c,
2400  CONNECTOR_OBJECT_ID_VGA,
2401  &hpd);
2402  break;
2403  case CONNECTOR_DVI_I_LEGACY:
2404  devices = 0;
2405  if (tmp & 0x1) {
2406  devices |= ATOM_DEVICE_CRT2_SUPPORT;
2407  radeon_add_legacy_encoder(dev,
2408  radeon_get_encoder_enum
2409  (dev,
2410  ATOM_DEVICE_CRT2_SUPPORT,
2411  2),
2412  ATOM_DEVICE_CRT2_SUPPORT);
2413  } else {
2414  devices |= ATOM_DEVICE_CRT1_SUPPORT;
2415  radeon_add_legacy_encoder(dev,
2416  radeon_get_encoder_enum
2417  (dev,
2418  ATOM_DEVICE_CRT1_SUPPORT,
2419  1),
2420  ATOM_DEVICE_CRT1_SUPPORT);
2421  }
2422  if ((tmp >> 4) & 0x1) {
2423  devices |= ATOM_DEVICE_DFP2_SUPPORT;
2424  radeon_add_legacy_encoder(dev,
2425  radeon_get_encoder_enum
2426  (dev,
2427  ATOM_DEVICE_DFP2_SUPPORT,
2428  0),
2429  ATOM_DEVICE_DFP2_SUPPORT);
2430  connector_object_id = combios_check_dl_dvi(dev, 0);
2431  } else {
2432  devices |= ATOM_DEVICE_DFP1_SUPPORT;
2433  radeon_add_legacy_encoder(dev,
2434  radeon_get_encoder_enum
2435  (dev,
2436  ATOM_DEVICE_DFP1_SUPPORT,
2437  0),
2438  ATOM_DEVICE_DFP1_SUPPORT);
2439  connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2440  }
2441  radeon_add_legacy_connector(dev,
2442  i,
2443  devices,
2444  legacy_connector_convert
2445  [connector],
2446  &ddc_i2c,
2447  connector_object_id,
2448  &hpd);
2449  break;
2450  case CONNECTOR_DVI_D_LEGACY:
2451  if ((tmp >> 4) & 0x1) {
2452  devices = ATOM_DEVICE_DFP2_SUPPORT;
2453  connector_object_id = combios_check_dl_dvi(dev, 1);
2454  } else {
2455  devices = ATOM_DEVICE_DFP1_SUPPORT;
2456  connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2457  }
2458  radeon_add_legacy_encoder(dev,
2459  radeon_get_encoder_enum
2460  (dev, devices, 0),
2461  devices);
2462  radeon_add_legacy_connector(dev, i, devices,
2463  legacy_connector_convert
2464  [connector],
2465  &ddc_i2c,
2466  connector_object_id,
2467  &hpd);
2468  break;
2469  case CONNECTOR_CTV_LEGACY:
2470  case CONNECTOR_STV_LEGACY:
2471  radeon_add_legacy_encoder(dev,
2472  radeon_get_encoder_enum
2473  (dev,
2474  ATOM_DEVICE_TV1_SUPPORT,
2475  2),
2476  ATOM_DEVICE_TV1_SUPPORT);
2477  radeon_add_legacy_connector(dev, i,
2478  ATOM_DEVICE_TV1_SUPPORT,
2479  legacy_connector_convert
2480  [connector],
2481  &ddc_i2c,
2482  CONNECTOR_OBJECT_ID_SVIDEO,
2483  &hpd);
2484  break;
2485  default:
2486  DRM_ERROR("Unknown connector type: %d\n",
2487  connector);
2488  continue;
2489  }
2490 
2491  }
2492  } else {
2493  uint16_t tmds_info =
2494  combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2495  if (tmds_info) {
2496  DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2497 
2498  radeon_add_legacy_encoder(dev,
2499  radeon_get_encoder_enum(dev,
2500  ATOM_DEVICE_CRT1_SUPPORT,
2501  1),
2502  ATOM_DEVICE_CRT1_SUPPORT);
2503  radeon_add_legacy_encoder(dev,
2504  radeon_get_encoder_enum(dev,
2505  ATOM_DEVICE_DFP1_SUPPORT,
2506  0),
2507  ATOM_DEVICE_DFP1_SUPPORT);
2508 
2509  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2510  hpd.hpd = RADEON_HPD_1;
2511  radeon_add_legacy_connector(dev,
2512  0,
2513  ATOM_DEVICE_CRT1_SUPPORT |
2514  ATOM_DEVICE_DFP1_SUPPORT,
2515  DRM_MODE_CONNECTOR_DVII,
2516  &ddc_i2c,
2517  CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2518  &hpd);
2519  } else {
2520  uint16_t crt_info =
2521  combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2522  DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2523  if (crt_info) {
2524  radeon_add_legacy_encoder(dev,
2525  radeon_get_encoder_enum(dev,
2526  ATOM_DEVICE_CRT1_SUPPORT,
2527  1),
2528  ATOM_DEVICE_CRT1_SUPPORT);
2529  ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2530  hpd.hpd = RADEON_HPD_NONE;
2531  radeon_add_legacy_connector(dev,
2532  0,
2533  ATOM_DEVICE_CRT1_SUPPORT,
2534  DRM_MODE_CONNECTOR_VGA,
2535  &ddc_i2c,
2536  CONNECTOR_OBJECT_ID_VGA,
2537  &hpd);
2538  } else {
2539  DRM_DEBUG_KMS("No connector info found\n");
2540  return false;
2541  }
2542  }
2543  }
2544 
2545  if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2546  uint16_t lcd_info =
2547  combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2548  if (lcd_info) {
2549  uint16_t lcd_ddc_info =
2550  combios_get_table_offset(dev,
2551  COMBIOS_LCD_DDC_INFO_TABLE);
2552 
2553  radeon_add_legacy_encoder(dev,
2554  radeon_get_encoder_enum(dev,
2555  ATOM_DEVICE_LCD1_SUPPORT,
2556  0),
2557  ATOM_DEVICE_LCD1_SUPPORT);
2558 
2559  if (lcd_ddc_info) {
2560  ddc_type = RBIOS8(lcd_ddc_info + 2);
2561  switch (ddc_type) {
2562  case DDC_LCD:
2563  ddc_i2c =
2564  combios_setup_i2c_bus(rdev,
2565  DDC_LCD,
2566  RBIOS32(lcd_ddc_info + 3),
2567  RBIOS32(lcd_ddc_info + 7));
2568  radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2569  break;
2570  case DDC_GPIO:
2571  ddc_i2c =
2572  combios_setup_i2c_bus(rdev,
2573  DDC_GPIO,
2574  RBIOS32(lcd_ddc_info + 3),
2575  RBIOS32(lcd_ddc_info + 7));
2576  radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2577  break;
2578  default:
2579  ddc_i2c =
2580  combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2581  break;
2582  }
2583  DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2584  } else
2585  ddc_i2c.valid = false;
2586 
2587  hpd.hpd = RADEON_HPD_NONE;
2588  radeon_add_legacy_connector(dev,
2589  5,
2590  ATOM_DEVICE_LCD1_SUPPORT,
2591  DRM_MODE_CONNECTOR_LVDS,
2592  &ddc_i2c,
2593  CONNECTOR_OBJECT_ID_LVDS,
2594  &hpd);
2595  }
2596  }
2597 
2598  /* check TV table */
2599  if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2600  uint32_t tv_info =
2601  combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2602  if (tv_info) {
2603  if (RBIOS8(tv_info + 6) == 'T') {
2604  if (radeon_apply_legacy_tv_quirks(dev)) {
2605  hpd.hpd = RADEON_HPD_NONE;
2606  ddc_i2c.valid = false;
2607  radeon_add_legacy_encoder(dev,
2608  radeon_get_encoder_enum
2609  (dev,
2610  ATOM_DEVICE_TV1_SUPPORT,
2611  2),
2612  ATOM_DEVICE_TV1_SUPPORT);
2613  radeon_add_legacy_connector(dev, 6,
2614  ATOM_DEVICE_TV1_SUPPORT,
2615  DRM_MODE_CONNECTOR_SVIDEO,
2616  &ddc_i2c,
2617  CONNECTOR_OBJECT_ID_SVIDEO,
2618  &hpd);
2619  }
2620  }
2621  }
2622  }
2623 
2624  radeon_link_encoder_connector(dev);
2625 
2626  return true;
2627 }
2628 
2629 static const char *thermal_controller_names[] = {
2630  "NONE",
2631  "lm63",
2632  "adm1032",
2633 };
2634 
2635 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2636 {
2637  struct drm_device *dev = rdev->ddev;
2638  u16 offset, misc, misc2 = 0;
2639  u8 rev, blocks, tmp;
2640  int state_index = 0;
2641  struct radeon_i2c_bus_rec i2c_bus;
2642 
2643  rdev->pm.default_power_state_index = -1;
2644 
2645  /* allocate 2 power states */
2646  rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2647  if (rdev->pm.power_state) {
2648  /* allocate 1 clock mode per state */
2649  rdev->pm.power_state[0].clock_info =
2650  kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2651  rdev->pm.power_state[1].clock_info =
2652  kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2653  if (!rdev->pm.power_state[0].clock_info ||
2654  !rdev->pm.power_state[1].clock_info)
2655  goto pm_failed;
2656  } else
2657  goto pm_failed;
2658 
2659  /* check for a thermal chip */
2660  offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2661  if (offset) {
2662  u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2663 
2664  rev = RBIOS8(offset);
2665 
2666  if (rev == 0) {
2667  thermal_controller = RBIOS8(offset + 3);
2668  gpio = RBIOS8(offset + 4) & 0x3f;
2669  i2c_addr = RBIOS8(offset + 5);
2670  } else if (rev == 1) {
2671  thermal_controller = RBIOS8(offset + 4);
2672  gpio = RBIOS8(offset + 5) & 0x3f;
2673  i2c_addr = RBIOS8(offset + 6);
2674  } else if (rev == 2) {
2675  thermal_controller = RBIOS8(offset + 4);
2676  gpio = RBIOS8(offset + 5) & 0x3f;
2677  i2c_addr = RBIOS8(offset + 6);
2678  clk_bit = RBIOS8(offset + 0xa);
2679  data_bit = RBIOS8(offset + 0xb);
2680  }
2681  if ((thermal_controller > 0) && (thermal_controller < 3)) {
2682  DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2683  thermal_controller_names[thermal_controller],
2684  i2c_addr >> 1);
2685  if (gpio == DDC_LCD) {
2686  /* MM i2c */
2687  i2c_bus.valid = true;
2688  i2c_bus.hw_capable = true;
2689  i2c_bus.mm_i2c = true;
2690  i2c_bus.i2c_id = 0xa0;
2691  } else if (gpio == DDC_GPIO)
2692  i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2693  else
2694  i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2695  rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2696  if (rdev->pm.i2c_bus) {
2697  struct i2c_board_info info = { };
2698  const char *name = thermal_controller_names[thermal_controller];
2699  info.addr = i2c_addr >> 1;
2700  strlcpy(info.type, name, sizeof(info.type));
2701  i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2702  }
2703  }
2704  } else {
2705  /* boards with a thermal chip, but no overdrive table */
2706 
2707  /* Asus 9600xt has an f75375 on the monid bus */
2708  if ((dev->pdev->device == 0x4152) &&
2709  (dev->pdev->subsystem_vendor == 0x1043) &&
2710  (dev->pdev->subsystem_device == 0xc002)) {
2711  i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2712  rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2713  if (rdev->pm.i2c_bus) {
2714  struct i2c_board_info info = { };
2715  const char *name = "f75375";
2716  info.addr = 0x28;
2717  strlcpy(info.type, name, sizeof(info.type));
2718  i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2719  DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2720  name, info.addr);
2721  }
2722  }
2723  }
2724 
2725  if (rdev->flags & RADEON_IS_MOBILITY) {
2726  offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2727  if (offset) {
2728  rev = RBIOS8(offset);
2729  blocks = RBIOS8(offset + 0x2);
2730  /* power mode 0 tends to be the only valid one */
2731  rdev->pm.power_state[state_index].num_clock_modes = 1;
2732  rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2733  rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2734  if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2735  (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2736  goto default_mode;
2737  rdev->pm.power_state[state_index].type =
2738  POWER_STATE_TYPE_BATTERY;
2739  misc = RBIOS16(offset + 0x5 + 0x0);
2740  if (rev > 4)
2741  misc2 = RBIOS16(offset + 0x5 + 0xe);
2742  rdev->pm.power_state[state_index].misc = misc;
2743  rdev->pm.power_state[state_index].misc2 = misc2;
2744  if (misc & 0x4) {
2745  rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2746  if (misc & 0x8)
2747  rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2748  true;
2749  else
2750  rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2751  false;
2752  rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2753  if (rev < 6) {
2754  rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2755  RBIOS16(offset + 0x5 + 0xb) * 4;
2756  tmp = RBIOS8(offset + 0x5 + 0xd);
2757  rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2758  } else {
2759  u8 entries = RBIOS8(offset + 0x5 + 0xb);
2760  u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2761  if (entries && voltage_table_offset) {
2762  rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2763  RBIOS16(voltage_table_offset) * 4;
2764  tmp = RBIOS8(voltage_table_offset + 0x2);
2765  rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2766  } else
2767  rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2768  }
2769  switch ((misc2 & 0x700) >> 8) {
2770  case 0:
2771  default:
2772  rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2773  break;
2774  case 1:
2775  rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2776  break;
2777  case 2:
2778  rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2779  break;
2780  case 3:
2781  rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2782  break;
2783  case 4:
2784  rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2785  break;
2786  }
2787  } else
2788  rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2789  if (rev > 6)
2790  rdev->pm.power_state[state_index].pcie_lanes =
2791  RBIOS8(offset + 0x5 + 0x10);
2792  rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2793  state_index++;
2794  } else {
2795  /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2796  }
2797  } else {
2798  /* XXX figure out some good default low power mode for desktop cards */
2799  }
2800 
2801 default_mode:
2802  /* add the default mode */
2803  rdev->pm.power_state[state_index].type =
2804  POWER_STATE_TYPE_DEFAULT;
2805  rdev->pm.power_state[state_index].num_clock_modes = 1;
2806  rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2807  rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2808  rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2809  if ((state_index > 0) &&
2810  (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2811  rdev->pm.power_state[state_index].clock_info[0].voltage =
2812  rdev->pm.power_state[0].clock_info[0].voltage;
2813  else
2814  rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2815  rdev->pm.power_state[state_index].pcie_lanes = 16;
2816  rdev->pm.power_state[state_index].flags = 0;
2817  rdev->pm.default_power_state_index = state_index;
2818  rdev->pm.num_power_states = state_index + 1;
2819 
2820  rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2821  rdev->pm.current_clock_mode_index = 0;
2822  return;
2823 
2824 pm_failed:
2825  rdev->pm.default_power_state_index = state_index;
2826  rdev->pm.num_power_states = 0;
2827 
2828  rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2829  rdev->pm.current_clock_mode_index = 0;
2830 }
2831 
2832 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2833 {
2834  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2835  struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2836 
2837  if (!tmds)
2838  return;
2839 
2840  switch (tmds->dvo_chip) {
2841  case DVO_SIL164:
2842  /* sil 164 */
2843  radeon_i2c_put_byte(tmds->i2c_bus,
2844  tmds->slave_addr,
2845  0x08, 0x30);
2846  radeon_i2c_put_byte(tmds->i2c_bus,
2847  tmds->slave_addr,
2848  0x09, 0x00);
2849  radeon_i2c_put_byte(tmds->i2c_bus,
2850  tmds->slave_addr,
2851  0x0a, 0x90);
2852  radeon_i2c_put_byte(tmds->i2c_bus,
2853  tmds->slave_addr,
2854  0x0c, 0x89);
2855  radeon_i2c_put_byte(tmds->i2c_bus,
2856  tmds->slave_addr,
2857  0x08, 0x3b);
2858  break;
2859  case DVO_SIL1178:
2860  /* sil 1178 - untested */
2861  /*
2862  * 0x0f, 0x44
2863  * 0x0f, 0x4c
2864  * 0x0e, 0x01
2865  * 0x0a, 0x80
2866  * 0x09, 0x30
2867  * 0x0c, 0xc9
2868  * 0x0d, 0x70
2869  * 0x08, 0x32
2870  * 0x08, 0x33
2871  */
2872  break;
2873  default:
2874  break;
2875  }
2876 
2877 }
2878 
2879 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2880 {
2881  struct drm_device *dev = encoder->dev;
2882  struct radeon_device *rdev = dev->dev_private;
2883  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2884  uint16_t offset;
2885  uint8_t blocks, slave_addr, rev;
2886  uint32_t index, id;
2887  uint32_t reg, val, and_mask, or_mask;
2888  struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2889 
2890  if (!tmds)
2891  return false;
2892 
2893  if (rdev->flags & RADEON_IS_IGP) {
2894  offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2895  rev = RBIOS8(offset);
2896  if (offset) {
2897  rev = RBIOS8(offset);
2898  if (rev > 1) {
2899  blocks = RBIOS8(offset + 3);
2900  index = offset + 4;
2901  while (blocks > 0) {
2902  id = RBIOS16(index);
2903  index += 2;
2904  switch (id >> 13) {
2905  case 0:
2906  reg = (id & 0x1fff) * 4;
2907  val = RBIOS32(index);
2908  index += 4;
2909  WREG32(reg, val);
2910  break;
2911  case 2:
2912  reg = (id & 0x1fff) * 4;
2913  and_mask = RBIOS32(index);
2914  index += 4;
2915  or_mask = RBIOS32(index);
2916  index += 4;
2917  val = RREG32(reg);
2918  val = (val & and_mask) | or_mask;
2919  WREG32(reg, val);
2920  break;
2921  case 3:
2922  val = RBIOS16(index);
2923  index += 2;
2924  udelay(val);
2925  break;
2926  case 4:
2927  val = RBIOS16(index);
2928  index += 2;
2929  mdelay(val);
2930  break;
2931  case 6:
2932  slave_addr = id & 0xff;
2933  slave_addr >>= 1; /* 7 bit addressing */
2934  index++;
2935  reg = RBIOS8(index);
2936  index++;
2937  val = RBIOS8(index);
2938  index++;
2939  radeon_i2c_put_byte(tmds->i2c_bus,
2940  slave_addr,
2941  reg, val);
2942  break;
2943  default:
2944  DRM_ERROR("Unknown id %d\n", id >> 13);
2945  break;
2946  }
2947  blocks--;
2948  }
2949  return true;
2950  }
2951  }
2952  } else {
2953  offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2954  if (offset) {
2955  index = offset + 10;
2956  id = RBIOS16(index);
2957  while (id != 0xffff) {
2958  index += 2;
2959  switch (id >> 13) {
2960  case 0:
2961  reg = (id & 0x1fff) * 4;
2962  val = RBIOS32(index);
2963  WREG32(reg, val);
2964  break;
2965  case 2:
2966  reg = (id & 0x1fff) * 4;
2967  and_mask = RBIOS32(index);
2968  index += 4;
2969  or_mask = RBIOS32(index);
2970  index += 4;
2971  val = RREG32(reg);
2972  val = (val & and_mask) | or_mask;
2973  WREG32(reg, val);
2974  break;
2975  case 4:
2976  val = RBIOS16(index);
2977  index += 2;
2978  udelay(val);
2979  break;
2980  case 5:
2981  reg = id & 0x1fff;
2982  and_mask = RBIOS32(index);
2983  index += 4;
2984  or_mask = RBIOS32(index);
2985  index += 4;
2986  val = RREG32_PLL(reg);
2987  val = (val & and_mask) | or_mask;
2988  WREG32_PLL(reg, val);
2989  break;
2990  case 6:
2991  reg = id & 0x1fff;
2992  val = RBIOS8(index);
2993  index += 1;
2994  radeon_i2c_put_byte(tmds->i2c_bus,
2995  tmds->slave_addr,
2996  reg, val);
2997  break;
2998  default:
2999  DRM_ERROR("Unknown id %d\n", id >> 13);
3000  break;
3001  }
3002  id = RBIOS16(index);
3003  }
3004  return true;
3005  }
3006  }
3007  return false;
3008 }
3009 
3010 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3011 {
3012  struct radeon_device *rdev = dev->dev_private;
3013 
3014  if (offset) {
3015  while (RBIOS16(offset)) {
3016  uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3017  uint32_t addr = (RBIOS16(offset) & 0x1fff);
3018  uint32_t val, and_mask, or_mask;
3019  uint32_t tmp;
3020 
3021  offset += 2;
3022  switch (cmd) {
3023  case 0:
3024  val = RBIOS32(offset);
3025  offset += 4;
3026  WREG32(addr, val);
3027  break;
3028  case 1:
3029  val = RBIOS32(offset);
3030  offset += 4;
3031  WREG32(addr, val);
3032  break;
3033  case 2:
3034  and_mask = RBIOS32(offset);
3035  offset += 4;
3036  or_mask = RBIOS32(offset);
3037  offset += 4;
3038  tmp = RREG32(addr);
3039  tmp &= and_mask;
3040  tmp |= or_mask;
3041  WREG32(addr, tmp);
3042  break;
3043  case 3:
3044  and_mask = RBIOS32(offset);
3045  offset += 4;
3046  or_mask = RBIOS32(offset);
3047  offset += 4;
3048  tmp = RREG32(addr);
3049  tmp &= and_mask;
3050  tmp |= or_mask;
3051  WREG32(addr, tmp);
3052  break;
3053  case 4:
3054  val = RBIOS16(offset);
3055  offset += 2;
3056  udelay(val);
3057  break;
3058  case 5:
3059  val = RBIOS16(offset);
3060  offset += 2;
3061  switch (addr) {
3062  case 8:
3063  while (val--) {
3064  if (!
3065  (RREG32_PLL
3066  (RADEON_CLK_PWRMGT_CNTL) &
3067  RADEON_MC_BUSY))
3068  break;
3069  }
3070  break;
3071  case 9:
3072  while (val--) {
3073  if ((RREG32(RADEON_MC_STATUS) &
3074  RADEON_MC_IDLE))
3075  break;
3076  }
3077  break;
3078  default:
3079  break;
3080  }
3081  break;
3082  default:
3083  break;
3084  }
3085  }
3086  }
3087 }
3088 
3089 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3090 {
3091  struct radeon_device *rdev = dev->dev_private;
3092 
3093  if (offset) {
3094  while (RBIOS8(offset)) {
3095  uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3096  uint8_t addr = (RBIOS8(offset) & 0x3f);
3097  uint32_t val, shift, tmp;
3098  uint32_t and_mask, or_mask;
3099 
3100  offset++;
3101  switch (cmd) {
3102  case 0:
3103  val = RBIOS32(offset);
3104  offset += 4;
3105  WREG32_PLL(addr, val);
3106  break;
3107  case 1:
3108  shift = RBIOS8(offset) * 8;
3109  offset++;
3110  and_mask = RBIOS8(offset) << shift;
3111  and_mask |= ~(0xff << shift);
3112  offset++;
3113  or_mask = RBIOS8(offset) << shift;
3114  offset++;
3115  tmp = RREG32_PLL(addr);
3116  tmp &= and_mask;
3117  tmp |= or_mask;
3118  WREG32_PLL(addr, tmp);
3119  break;
3120  case 2:
3121  case 3:
3122  tmp = 1000;
3123  switch (addr) {
3124  case 1:
3125  udelay(150);
3126  break;
3127  case 2:
3128  mdelay(1);
3129  break;
3130  case 3:
3131  while (tmp--) {
3132  if (!
3133  (RREG32_PLL
3134  (RADEON_CLK_PWRMGT_CNTL) &
3135  RADEON_MC_BUSY))
3136  break;
3137  }
3138  break;
3139  case 4:
3140  while (tmp--) {
3141  if (RREG32_PLL
3142  (RADEON_CLK_PWRMGT_CNTL) &
3143  RADEON_DLL_READY)
3144  break;
3145  }
3146  break;
3147  case 5:
3148  tmp =
3149  RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3150  if (tmp & RADEON_CG_NO1_DEBUG_0) {
3151 #if 0
3152  uint32_t mclk_cntl =
3153  RREG32_PLL
3154  (RADEON_MCLK_CNTL);
3155  mclk_cntl &= 0xffff0000;
3156  /*mclk_cntl |= 0x00001111;*//* ??? */
3157  WREG32_PLL(RADEON_MCLK_CNTL,
3158  mclk_cntl);
3159  mdelay(10);
3160 #endif
3161  WREG32_PLL
3162  (RADEON_CLK_PWRMGT_CNTL,
3163  tmp &
3164  ~RADEON_CG_NO1_DEBUG_0);
3165  mdelay(10);
3166  }
3167  break;
3168  default:
3169  break;
3170  }
3171  break;
3172  default:
3173  break;
3174  }
3175  }
3176  }
3177 }
3178 
3179 static void combios_parse_ram_reset_table(struct drm_device *dev,
3180  uint16_t offset)
3181 {
3182  struct radeon_device *rdev = dev->dev_private;
3183  uint32_t tmp;
3184 
3185  if (offset) {
3186  uint8_t val = RBIOS8(offset);
3187  while (val != 0xff) {
3188  offset++;
3189 
3190  if (val == 0x0f) {
3191  uint32_t channel_complete_mask;
3192 
3193  if (ASIC_IS_R300(rdev))
3194  channel_complete_mask =
3195  R300_MEM_PWRUP_COMPLETE;
3196  else
3197  channel_complete_mask =
3198  RADEON_MEM_PWRUP_COMPLETE;
3199  tmp = 20000;
3200  while (tmp--) {
3201  if ((RREG32(RADEON_MEM_STR_CNTL) &
3202  channel_complete_mask) ==
3203  channel_complete_mask)
3204  break;
3205  }
3206  } else {
3207  uint32_t or_mask = RBIOS16(offset);
3208  offset += 2;
3209 
3210  tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3211  tmp &= RADEON_SDRAM_MODE_MASK;
3212  tmp |= or_mask;
3213  WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3214 
3215  or_mask = val << 24;
3216  tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3217  tmp &= RADEON_B3MEM_RESET_MASK;
3218  tmp |= or_mask;
3219  WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3220  }
3221  val = RBIOS8(offset);
3222  }
3223  }
3224 }
3225 
3226 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3227  int mem_addr_mapping)
3228 {
3229  struct radeon_device *rdev = dev->dev_private;
3230  uint32_t mem_cntl;
3231  uint32_t mem_size;
3232  uint32_t addr = 0;
3233 
3234  mem_cntl = RREG32(RADEON_MEM_CNTL);
3235  if (mem_cntl & RV100_HALF_MODE)
3236  ram /= 2;
3237  mem_size = ram;
3238  mem_cntl &= ~(0xff << 8);
3239  mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3240  WREG32(RADEON_MEM_CNTL, mem_cntl);
3241  RREG32(RADEON_MEM_CNTL);
3242 
3243  /* sdram reset ? */
3244 
3245  /* something like this???? */
3246  while (ram--) {
3247  addr = ram * 1024 * 1024;
3248  /* write to each page */
3249  WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3250  WREG32(RADEON_MM_DATA, 0xdeadbeef);
3251  /* read back and verify */
3252  WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3253  if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3254  return 0;
3255  }
3256 
3257  return mem_size;
3258 }
3259 
3260 static void combios_write_ram_size(struct drm_device *dev)
3261 {
3262  struct radeon_device *rdev = dev->dev_private;
3263  uint8_t rev;
3264  uint16_t offset;
3265  uint32_t mem_size = 0;
3266  uint32_t mem_cntl = 0;
3267 
3268  /* should do something smarter here I guess... */
3269  if (rdev->flags & RADEON_IS_IGP)
3270  return;
3271 
3272  /* first check detected mem table */
3273  offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3274  if (offset) {
3275  rev = RBIOS8(offset);
3276  if (rev < 3) {
3277  mem_cntl = RBIOS32(offset + 1);
3278  mem_size = RBIOS16(offset + 5);
3279  if ((rdev->family < CHIP_R200) &&
3280  !ASIC_IS_RN50(rdev))
3281  WREG32(RADEON_MEM_CNTL, mem_cntl);
3282  }
3283  }
3284 
3285  if (!mem_size) {
3286  offset =
3287  combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3288  if (offset) {
3289  rev = RBIOS8(offset - 1);
3290  if (rev < 1) {
3291  if ((rdev->family < CHIP_R200)
3292  && !ASIC_IS_RN50(rdev)) {
3293  int ram = 0;
3294  int mem_addr_mapping = 0;
3295 
3296  while (RBIOS8(offset)) {
3297  ram = RBIOS8(offset);
3298  mem_addr_mapping =
3299  RBIOS8(offset + 1);
3300  if (mem_addr_mapping != 0x25)
3301  ram *= 2;
3302  mem_size =
3303  combios_detect_ram(dev, ram,
3304  mem_addr_mapping);
3305  if (mem_size)
3306  break;
3307  offset += 2;
3308  }
3309  } else
3310  mem_size = RBIOS8(offset);
3311  } else {
3312  mem_size = RBIOS8(offset);
3313  mem_size *= 2; /* convert to MB */
3314  }
3315  }
3316  }
3317 
3318  mem_size *= (1024 * 1024); /* convert to bytes */
3319  WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3320 }
3321 
3322 void radeon_combios_asic_init(struct drm_device *dev)
3323 {
3324  struct radeon_device *rdev = dev->dev_private;
3325  uint16_t table;
3326 
3327  /* port hardcoded mac stuff from radeonfb */
3328  if (rdev->bios == NULL)
3329  return;
3330 
3331  /* ASIC INIT 1 */
3332  table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3333  if (table)
3334  combios_parse_mmio_table(dev, table);
3335 
3336  /* PLL INIT */
3337  table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3338  if (table)
3339  combios_parse_pll_table(dev, table);
3340 
3341  /* ASIC INIT 2 */
3342  table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3343  if (table)
3344  combios_parse_mmio_table(dev, table);
3345 
3346  if (!(rdev->flags & RADEON_IS_IGP)) {
3347  /* ASIC INIT 4 */
3348  table =
3349  combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3350  if (table)
3351  combios_parse_mmio_table(dev, table);
3352 
3353  /* RAM RESET */
3354  table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3355  if (table)
3356  combios_parse_ram_reset_table(dev, table);
3357 
3358  /* ASIC INIT 3 */
3359  table =
3360  combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3361  if (table)
3362  combios_parse_mmio_table(dev, table);
3363 
3364  /* write CONFIG_MEMSIZE */
3365  combios_write_ram_size(dev);
3366  }
3367 
3368  /* quirk for rs4xx HP nx6125 laptop to make it resume
3369  * - it hangs on resume inside the dynclk 1 table.
3370  */
3371  if (rdev->family == CHIP_RS480 &&
3372  rdev->pdev->subsystem_vendor == 0x103c &&
3373  rdev->pdev->subsystem_device == 0x308b)
3374  return;
3375 
3376  /* quirk for rs4xx HP dv5000 laptop to make it resume
3377  * - it hangs on resume inside the dynclk 1 table.
3378  */
3379  if (rdev->family == CHIP_RS480 &&
3380  rdev->pdev->subsystem_vendor == 0x103c &&
3381  rdev->pdev->subsystem_device == 0x30a4)
3382  return;
3383 
3384  /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3385  * - it hangs on resume inside the dynclk 1 table.
3386  */
3387  if (rdev->family == CHIP_RS480 &&
3388  rdev->pdev->subsystem_vendor == 0x103c &&
3389  rdev->pdev->subsystem_device == 0x30ae)
3390  return;
3391 
3392  /* DYN CLK 1 */
3393  table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3394  if (table)
3395  combios_parse_pll_table(dev, table);
3396 
3397 }
3398 
3399 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3400 {
3401  struct radeon_device *rdev = dev->dev_private;
3402  uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3403 
3404  bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3405  bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3406  bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3407 
3408  /* let the bios control the backlight */
3409  bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3410 
3411  /* tell the bios not to handle mode switching */
3412  bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3413  RADEON_ACC_MODE_CHANGE);
3414 
3415  /* tell the bios a driver is loaded */
3416  bios_7_scratch |= RADEON_DRV_LOADED;
3417 
3418  WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3419  WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3420  WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3421 }
3422 
3423 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3424 {
3425  struct drm_device *dev = encoder->dev;
3426  struct radeon_device *rdev = dev->dev_private;
3427  uint32_t bios_6_scratch;
3428 
3429  bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3430 
3431  if (lock)
3432  bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3433  else
3434  bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3435 
3436  WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3437 }
3438 
3439 void
3440 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3441  struct drm_encoder *encoder,
3442  bool connected)
3443 {
3444  struct drm_device *dev = connector->dev;
3445  struct radeon_device *rdev = dev->dev_private;
3446  struct radeon_connector *radeon_connector =
3447  to_radeon_connector(connector);
3448  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3449  uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3450  uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3451 
3452  if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3453  (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3454  if (connected) {
3455  DRM_DEBUG_KMS("TV1 connected\n");
3456  /* fix me */
3457  bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3458  /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3459  bios_5_scratch |= RADEON_TV1_ON;
3460  bios_5_scratch |= RADEON_ACC_REQ_TV1;
3461  } else {
3462  DRM_DEBUG_KMS("TV1 disconnected\n");
3463  bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3464  bios_5_scratch &= ~RADEON_TV1_ON;
3465  bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3466  }
3467  }
3468  if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3469  (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3470  if (connected) {
3471  DRM_DEBUG_KMS("LCD1 connected\n");
3472  bios_4_scratch |= RADEON_LCD1_ATTACHED;
3473  bios_5_scratch |= RADEON_LCD1_ON;
3474  bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3475  } else {
3476  DRM_DEBUG_KMS("LCD1 disconnected\n");
3477  bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3478  bios_5_scratch &= ~RADEON_LCD1_ON;
3479  bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3480  }
3481  }
3482  if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3483  (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3484  if (connected) {
3485  DRM_DEBUG_KMS("CRT1 connected\n");
3486  bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3487  bios_5_scratch |= RADEON_CRT1_ON;
3488  bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3489  } else {
3490  DRM_DEBUG_KMS("CRT1 disconnected\n");
3491  bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3492  bios_5_scratch &= ~RADEON_CRT1_ON;
3493  bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3494  }
3495  }
3496  if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3497  (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3498  if (connected) {
3499  DRM_DEBUG_KMS("CRT2 connected\n");
3500  bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3501  bios_5_scratch |= RADEON_CRT2_ON;
3502  bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3503  } else {
3504  DRM_DEBUG_KMS("CRT2 disconnected\n");
3505  bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3506  bios_5_scratch &= ~RADEON_CRT2_ON;
3507  bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3508  }
3509  }
3510  if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3511  (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3512  if (connected) {
3513  DRM_DEBUG_KMS("DFP1 connected\n");
3514  bios_4_scratch |= RADEON_DFP1_ATTACHED;
3515  bios_5_scratch |= RADEON_DFP1_ON;
3516  bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3517  } else {
3518  DRM_DEBUG_KMS("DFP1 disconnected\n");
3519  bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3520  bios_5_scratch &= ~RADEON_DFP1_ON;
3521  bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3522  }
3523  }
3524  if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3525  (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3526  if (connected) {
3527  DRM_DEBUG_KMS("DFP2 connected\n");
3528  bios_4_scratch |= RADEON_DFP2_ATTACHED;
3529  bios_5_scratch |= RADEON_DFP2_ON;
3530  bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3531  } else {
3532  DRM_DEBUG_KMS("DFP2 disconnected\n");
3533  bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3534  bios_5_scratch &= ~RADEON_DFP2_ON;
3535  bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3536  }
3537  }
3538  WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3539  WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3540 }
3541 
3542 void
3543 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3544 {
3545  struct drm_device *dev = encoder->dev;
3546  struct radeon_device *rdev = dev->dev_private;
3547  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3548  uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3549 
3550  if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3551  bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3552  bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3553  }
3554  if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3555  bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3556  bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3557  }
3558  if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3559  bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3560  bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3561  }
3562  if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3563  bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3564  bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3565  }
3566  if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3567  bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3568  bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3569  }
3570  if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3571  bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3572  bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3573  }
3574  WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3575 }
3576 
3577 void
3578 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3579 {
3580  struct drm_device *dev = encoder->dev;
3581  struct radeon_device *rdev = dev->dev_private;
3582  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3583  uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3584 
3585  if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3586  if (on)
3587  bios_6_scratch |= RADEON_TV_DPMS_ON;
3588  else
3589  bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3590  }
3591  if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3592  if (on)
3593  bios_6_scratch |= RADEON_CRT_DPMS_ON;
3594  else
3595  bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3596  }
3597  if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3598  if (on)
3599  bios_6_scratch |= RADEON_LCD_DPMS_ON;
3600  else
3601  bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3602  }
3603  if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3604  if (on)
3605  bios_6_scratch |= RADEON_DFP_DPMS_ON;
3606  else
3607  bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3608  }
3609  WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3610 }
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