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Data Structures | Macros
sunzilog.h File Reference

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Data Structures

struct  zilog_channel
 
struct  zilog_layout
 

Macros

#define NUM_ZSREGS   17
 
#define R7p   16 /* Written as R7 with P15 bit 0 set */
 
#define BRG_TO_BPS(brg, freq)   ((freq) / 2 / ((brg) + 2))
 
#define BPS_TO_BRG(bps, freq)   ((((freq) + (bps)) / (2 * (bps))) - 2)
 
#define FLAG   0x7e
 
#define R0   0 /* Register selects */
 
#define R1   1
 
#define R2   2
 
#define R3   3
 
#define R4   4
 
#define R5   5
 
#define R6   6
 
#define R7   7
 
#define R8   8
 
#define R9   9
 
#define R10   10
 
#define R11   11
 
#define R12   12
 
#define R13   13
 
#define R14   14
 
#define R15   15
 
#define NULLCODE   0 /* Null Code */
 
#define POINT_HIGH   0x8 /* Select upper half of registers */
 
#define RES_EXT_INT   0x10 /* Reset Ext. Status Interrupts */
 
#define SEND_ABORT   0x18 /* HDLC Abort */
 
#define RES_RxINT_FC   0x20 /* Reset RxINT on First Character */
 
#define RES_Tx_P   0x28 /* Reset TxINT Pending */
 
#define ERR_RES   0x30 /* Error Reset */
 
#define RES_H_IUS   0x38 /* Reset highest IUS */
 
#define RES_Rx_CRC   0x40 /* Reset Rx CRC Checker */
 
#define RES_Tx_CRC   0x80 /* Reset Tx CRC Checker */
 
#define RES_EOM_L   0xC0 /* Reset EOM latch */
 
#define EXT_INT_ENAB   0x1 /* Ext Int Enable */
 
#define TxINT_ENAB   0x2 /* Tx Int Enable */
 
#define PAR_SPEC   0x4 /* Parity is special condition */
 
#define RxINT_DISAB   0 /* Rx Int Disable */
 
#define RxINT_FCERR   0x8 /* Rx Int on First Character Only or Error */
 
#define INT_ALL_Rx   0x10 /* Int on all Rx Characters or error */
 
#define INT_ERR_Rx   0x18 /* Int on error only */
 
#define RxINT_MASK   0x18
 
#define WT_RDY_RT   0x20 /* Wait/Ready on R/T */
 
#define WT_FN_RDYFN   0x40 /* Wait/FN/Ready FN */
 
#define WT_RDY_ENAB   0x80 /* Wait/Ready Enable */
 
#define RxENAB   0x1 /* Rx Enable */
 
#define SYNC_L_INH   0x2 /* Sync Character Load Inhibit */
 
#define ADD_SM   0x4 /* Address Search Mode (SDLC) */
 
#define RxCRC_ENAB   0x8 /* Rx CRC Enable */
 
#define ENT_HM   0x10 /* Enter Hunt Mode */
 
#define AUTO_ENAB   0x20 /* Auto Enables */
 
#define Rx5   0x0 /* Rx 5 Bits/Character */
 
#define Rx7   0x40 /* Rx 7 Bits/Character */
 
#define Rx6   0x80 /* Rx 6 Bits/Character */
 
#define Rx8   0xc0 /* Rx 8 Bits/Character */
 
#define RxN_MASK   0xc0
 
#define PAR_ENAB   0x1 /* Parity Enable */
 
#define PAR_EVEN   0x2 /* Parity Even/Odd* */
 
#define SYNC_ENAB   0 /* Sync Modes Enable */
 
#define SB1   0x4 /* 1 stop bit/char */
 
#define SB15   0x8 /* 1.5 stop bits/char */
 
#define SB2   0xc /* 2 stop bits/char */
 
#define MONSYNC   0 /* 8 Bit Sync character */
 
#define BISYNC   0x10 /* 16 bit sync character */
 
#define SDLC   0x20 /* SDLC Mode (01111110 Sync Flag) */
 
#define EXTSYNC   0x30 /* External Sync Mode */
 
#define X1CLK   0x0 /* x1 clock mode */
 
#define X16CLK   0x40 /* x16 clock mode */
 
#define X32CLK   0x80 /* x32 clock mode */
 
#define X64CLK   0xC0 /* x64 clock mode */
 
#define XCLK_MASK   0xC0
 
#define TxCRC_ENAB   0x1 /* Tx CRC Enable */
 
#define RTS   0x2 /* RTS */
 
#define SDLC_CRC   0x4 /* SDLC/CRC-16 */
 
#define TxENAB   0x8 /* Tx Enable */
 
#define SND_BRK   0x10 /* Send Break */
 
#define Tx5   0x0 /* Tx 5 bits (or less)/character */
 
#define Tx7   0x20 /* Tx 7 bits/character */
 
#define Tx6   0x40 /* Tx 6 bits/character */
 
#define Tx8   0x60 /* Tx 8 bits/character */
 
#define TxN_MASK   0x60
 
#define DTR   0x80 /* DTR */
 
#define AUTO_TxFLAG   1 /* Automatic Tx SDLC Flag */
 
#define AUTO_EOM_RST   2 /* Automatic EOM Reset */
 
#define AUTOnRTS   4 /* Automatic /RTS pin deactivation */
 
#define RxFIFO_LVL   8 /* Receive FIFO interrupt level */
 
#define nDTRnREQ   0x10 /* /DTR/REQ timing */
 
#define TxFIFO_LVL   0x20 /* Transmit FIFO interrupt level */
 
#define EXT_RD_EN   0x40 /* Extended read register enable */
 
#define VIS   1 /* Vector Includes Status */
 
#define NV   2 /* No Vector */
 
#define DLC   4 /* Disable Lower Chain */
 
#define MIE   8 /* Master Interrupt Enable */
 
#define STATHI   0x10 /* Status high */
 
#define SWIACK   0x20 /* Software Interrupt Ack (not on NMOS) */
 
#define NORESET   0 /* No reset on write to R9 */
 
#define CHRB   0x40 /* Reset channel B */
 
#define CHRA   0x80 /* Reset channel A */
 
#define FHWRES   0xc0 /* Force hardware reset */
 
#define BIT6   1 /* 6 bit/8bit sync */
 
#define LOOPMODE   2 /* SDLC Loop mode */
 
#define ABUNDER   4 /* Abort/flag on SDLC xmit underrun */
 
#define MARKIDLE   8 /* Mark/flag on idle */
 
#define GAOP   0x10 /* Go active on poll */
 
#define NRZ   0 /* NRZ mode */
 
#define NRZI   0x20 /* NRZI mode */
 
#define FM1   0x40 /* FM1 (transition = 1) */
 
#define FM0   0x60 /* FM0 (transition = 0) */
 
#define CRCPS   0x80 /* CRC Preset I/O */
 
#define TRxCXT   0 /* TRxC = Xtal output */
 
#define TRxCTC   1 /* TRxC = Transmit clock */
 
#define TRxCBR   2 /* TRxC = BR Generator Output */
 
#define TRxCDP   3 /* TRxC = DPLL output */
 
#define TRxCOI   4 /* TRxC O/I */
 
#define TCRTxCP   0 /* Transmit clock = RTxC pin */
 
#define TCTRxCP   8 /* Transmit clock = TRxC pin */
 
#define TCBR   0x10 /* Transmit clock = BR Generator output */
 
#define TCDPLL   0x18 /* Transmit clock = DPLL output */
 
#define RCRTxCP   0 /* Receive clock = RTxC pin */
 
#define RCTRxCP   0x20 /* Receive clock = TRxC pin */
 
#define RCBR   0x40 /* Receive clock = BR Generator output */
 
#define RCDPLL   0x60 /* Receive clock = DPLL output */
 
#define RTxCX   0x80 /* RTxC Xtal/No Xtal */
 
#define BRENAB   1 /* Baud rate generator enable */
 
#define BRSRC   2 /* Baud rate generator source */
 
#define DTRREQ   4 /* DTR/Request function */
 
#define AUTOECHO   8 /* Auto Echo */
 
#define LOOPBAK   0x10 /* Local loopback */
 
#define SEARCH   0x20 /* Enter search mode */
 
#define RMC   0x40 /* Reset missing clock */
 
#define DISDPLL   0x60 /* Disable DPLL */
 
#define SSBR   0x80 /* Set DPLL source = BR generator */
 
#define SSRTxC   0xa0 /* Set DPLL source = RTxC */
 
#define SFMM   0xc0 /* Set FM mode */
 
#define SNRZI   0xe0 /* Set NRZI mode */
 
#define WR7pEN   1 /* WR7' Enable (ESCC only) */
 
#define ZCIE   2 /* Zero count IE */
 
#define FIFOEN   4 /* FIFO Enable (ESCC only) */
 
#define DCDIE   8 /* DCD IE */
 
#define SYNCIE   0x10 /* Sync/hunt IE */
 
#define CTSIE   0x20 /* CTS IE */
 
#define TxUIE   0x40 /* Tx Underrun/EOM IE */
 
#define BRKIE   0x80 /* Break/Abort IE */
 
#define Rx_CH_AV   0x1 /* Rx Character Available */
 
#define ZCOUNT   0x2 /* Zero count */
 
#define Tx_BUF_EMP   0x4 /* Tx Buffer empty */
 
#define DCD   0x8 /* DCD */
 
#define SYNC   0x10 /* Sync/hunt */
 
#define CTS   0x20 /* CTS */
 
#define TxEOM   0x40 /* Tx underrun */
 
#define BRK_ABRT   0x80 /* Break/Abort */
 
#define ALL_SNT   0x1 /* All sent */
 
#define RES3   0x8 /* 0/3 */
 
#define RES4   0x4 /* 0/4 */
 
#define RES5   0xc /* 0/5 */
 
#define RES6   0x2 /* 0/6 */
 
#define RES7   0xa /* 0/7 */
 
#define RES8   0x6 /* 0/8 */
 
#define RES18   0xe /* 1/8 */
 
#define RES28   0x0 /* 2/8 */
 
#define PAR_ERR   0x10 /* Parity error */
 
#define Rx_OVR   0x20 /* Rx Overrun Error */
 
#define CRC_ERR   0x40 /* CRC/Framing Error */
 
#define END_FR   0x80 /* End of Frame (SDLC) */
 
#define CHB_Tx_EMPTY   0x00
 
#define CHB_EXT_STAT   0x02
 
#define CHB_Rx_AVAIL   0x04
 
#define CHB_SPECIAL   0x06
 
#define CHA_Tx_EMPTY   0x08
 
#define CHA_EXT_STAT   0x0a
 
#define CHA_Rx_AVAIL   0x0c
 
#define CHA_SPECIAL   0x0e
 
#define STATUS_MASK   0x0e
 
#define CHBEXT   0x1 /* Channel B Ext/Stat IP */
 
#define CHBTxIP   0x2 /* Channel B Tx IP */
 
#define CHBRxIP   0x4 /* Channel B Rx IP */
 
#define CHAEXT   0x8 /* Channel A Ext/Stat IP */
 
#define CHATxIP   0x10 /* Channel A Tx IP */
 
#define CHARxIP   0x20 /* Channel A Rx IP */
 
#define ONLOOP   2 /* On loop */
 
#define LOOPSEND   0x10 /* Loop sending */
 
#define CLK2MIS   0x40 /* Two clocks missing */
 
#define CLK1MIS   0x80 /* One clock missing */
 
#define ZS_CLEARERR(channel)
 
#define ZS_CLEARSTAT(channel)
 
#define ZS_CLEARFIFO(channel)
 

Macro Definition Documentation

#define ABUNDER   4 /* Abort/flag on SDLC xmit underrun */

Definition at line 157 of file sunzilog.h.

#define ADD_SM   0x4 /* Address Search Mode (SDLC) */

Definition at line 82 of file sunzilog.h.

#define ALL_SNT   0x1 /* All sent */

Definition at line 222 of file sunzilog.h.

#define AUTO_ENAB   0x20 /* Auto Enables */

Definition at line 85 of file sunzilog.h.

#define AUTO_EOM_RST   2 /* Automatic EOM Reset */

Definition at line 133 of file sunzilog.h.

#define AUTO_TxFLAG   1 /* Automatic Tx SDLC Flag */

Definition at line 132 of file sunzilog.h.

#define AUTOECHO   8 /* Auto Echo */

Definition at line 190 of file sunzilog.h.

#define AUTOnRTS   4 /* Automatic /RTS pin deactivation */

Definition at line 134 of file sunzilog.h.

#define BISYNC   0x10 /* 16 bit sync character */

Definition at line 103 of file sunzilog.h.

#define BIT6   1 /* 6 bit/8bit sync */

Definition at line 155 of file sunzilog.h.

#define BPS_TO_BRG (   bps,
  freq 
)    ((((freq) + (bps)) / (2 * (bps))) - 2)

Definition at line 23 of file sunzilog.h.

#define BRENAB   1 /* Baud rate generator enable */

Definition at line 187 of file sunzilog.h.

#define BRG_TO_BPS (   brg,
  freq 
)    ((freq) / 2 / ((brg) + 2))

Definition at line 22 of file sunzilog.h.

#define BRK_ABRT   0x80 /* Break/Abort */

Definition at line 219 of file sunzilog.h.

#define BRKIE   0x80 /* Break/Abort IE */

Definition at line 208 of file sunzilog.h.

#define BRSRC   2 /* Baud rate generator source */

Definition at line 188 of file sunzilog.h.

#define CHA_EXT_STAT   0x0a

Definition at line 244 of file sunzilog.h.

#define CHA_Rx_AVAIL   0x0c

Definition at line 245 of file sunzilog.h.

#define CHA_SPECIAL   0x0e

Definition at line 246 of file sunzilog.h.

#define CHA_Tx_EMPTY   0x08

Definition at line 243 of file sunzilog.h.

#define CHAEXT   0x8 /* Channel A Ext/Stat IP */

Definition at line 253 of file sunzilog.h.

#define CHARxIP   0x20 /* Channel A Rx IP */

Definition at line 255 of file sunzilog.h.

#define CHATxIP   0x10 /* Channel A Tx IP */

Definition at line 254 of file sunzilog.h.

#define CHB_EXT_STAT   0x02

Definition at line 240 of file sunzilog.h.

#define CHB_Rx_AVAIL   0x04

Definition at line 241 of file sunzilog.h.

#define CHB_SPECIAL   0x06

Definition at line 242 of file sunzilog.h.

#define CHB_Tx_EMPTY   0x00

Definition at line 239 of file sunzilog.h.

#define CHBEXT   0x1 /* Channel B Ext/Stat IP */

Definition at line 250 of file sunzilog.h.

#define CHBRxIP   0x4 /* Channel B Rx IP */

Definition at line 252 of file sunzilog.h.

#define CHBTxIP   0x2 /* Channel B Tx IP */

Definition at line 251 of file sunzilog.h.

#define CHRA   0x80 /* Reset channel A */

Definition at line 151 of file sunzilog.h.

#define CHRB   0x40 /* Reset channel B */

Definition at line 150 of file sunzilog.h.

#define CLK1MIS   0x80 /* One clock missing */

Definition at line 267 of file sunzilog.h.

#define CLK2MIS   0x40 /* Two clocks missing */

Definition at line 266 of file sunzilog.h.

#define CRC_ERR   0x40 /* CRC/Framing Error */

Definition at line 235 of file sunzilog.h.

#define CRCPS   0x80 /* CRC Preset I/O */

Definition at line 164 of file sunzilog.h.

#define CTS   0x20 /* CTS */

Definition at line 217 of file sunzilog.h.

#define CTSIE   0x20 /* CTS IE */

Definition at line 206 of file sunzilog.h.

#define DCD   0x8 /* DCD */

Definition at line 215 of file sunzilog.h.

#define DCDIE   8 /* DCD IE */

Definition at line 204 of file sunzilog.h.

#define DISDPLL   0x60 /* Disable DPLL */

Definition at line 194 of file sunzilog.h.

#define DLC   4 /* Disable Lower Chain */

Definition at line 145 of file sunzilog.h.

#define DTR   0x80 /* DTR */

Definition at line 125 of file sunzilog.h.

#define DTRREQ   4 /* DTR/Request function */

Definition at line 189 of file sunzilog.h.

#define END_FR   0x80 /* End of Frame (SDLC) */

Definition at line 236 of file sunzilog.h.

#define ENT_HM   0x10 /* Enter Hunt Mode */

Definition at line 84 of file sunzilog.h.

#define ERR_RES   0x30 /* Error Reset */

Definition at line 53 of file sunzilog.h.

#define EXT_INT_ENAB   0x1 /* Ext Int Enable */

Definition at line 62 of file sunzilog.h.

#define EXT_RD_EN   0x40 /* Extended read register enable */

Definition at line 138 of file sunzilog.h.

#define EXTSYNC   0x30 /* External Sync Mode */

Definition at line 105 of file sunzilog.h.

#define FHWRES   0xc0 /* Force hardware reset */

Definition at line 152 of file sunzilog.h.

#define FIFOEN   4 /* FIFO Enable (ESCC only) */

Definition at line 203 of file sunzilog.h.

#define FLAG   0x7e

Definition at line 27 of file sunzilog.h.

#define FM0   0x60 /* FM0 (transition = 0) */

Definition at line 163 of file sunzilog.h.

#define FM1   0x40 /* FM1 (transition = 1) */

Definition at line 162 of file sunzilog.h.

#define GAOP   0x10 /* Go active on poll */

Definition at line 159 of file sunzilog.h.

#define INT_ALL_Rx   0x10 /* Int on all Rx Characters or error */

Definition at line 68 of file sunzilog.h.

#define INT_ERR_Rx   0x18 /* Int on error only */

Definition at line 69 of file sunzilog.h.

#define LOOPBAK   0x10 /* Local loopback */

Definition at line 191 of file sunzilog.h.

#define LOOPMODE   2 /* SDLC Loop mode */

Definition at line 156 of file sunzilog.h.

#define LOOPSEND   0x10 /* Loop sending */

Definition at line 265 of file sunzilog.h.

#define MARKIDLE   8 /* Mark/flag on idle */

Definition at line 158 of file sunzilog.h.

#define MIE   8 /* Master Interrupt Enable */

Definition at line 146 of file sunzilog.h.

#define MONSYNC   0 /* 8 Bit Sync character */

Definition at line 102 of file sunzilog.h.

#define nDTRnREQ   0x10 /* /DTR/REQ timing */

Definition at line 136 of file sunzilog.h.

#define NORESET   0 /* No reset on write to R9 */

Definition at line 149 of file sunzilog.h.

#define NRZ   0 /* NRZ mode */

Definition at line 160 of file sunzilog.h.

#define NRZI   0x20 /* NRZI mode */

Definition at line 161 of file sunzilog.h.

#define NULLCODE   0 /* Null Code */

Definition at line 47 of file sunzilog.h.

#define NUM_ZSREGS   17

Definition at line 16 of file sunzilog.h.

#define NV   2 /* No Vector */

Definition at line 144 of file sunzilog.h.

#define ONLOOP   2 /* On loop */

Definition at line 264 of file sunzilog.h.

#define PAR_ENAB   0x1 /* Parity Enable */

Definition at line 94 of file sunzilog.h.

#define PAR_ERR   0x10 /* Parity error */

Definition at line 233 of file sunzilog.h.

#define PAR_EVEN   0x2 /* Parity Even/Odd* */

Definition at line 95 of file sunzilog.h.

#define PAR_SPEC   0x4 /* Parity is special condition */

Definition at line 64 of file sunzilog.h.

#define POINT_HIGH   0x8 /* Select upper half of registers */

Definition at line 48 of file sunzilog.h.

#define R0   0 /* Register selects */

Definition at line 30 of file sunzilog.h.

#define R1   1

Definition at line 31 of file sunzilog.h.

#define R10   10

Definition at line 40 of file sunzilog.h.

#define R11   11

Definition at line 41 of file sunzilog.h.

#define R12   12

Definition at line 42 of file sunzilog.h.

#define R13   13

Definition at line 43 of file sunzilog.h.

#define R14   14

Definition at line 44 of file sunzilog.h.

#define R15   15

Definition at line 45 of file sunzilog.h.

#define R2   2

Definition at line 32 of file sunzilog.h.

#define R3   3

Definition at line 33 of file sunzilog.h.

#define R4   4

Definition at line 34 of file sunzilog.h.

#define R5   5

Definition at line 35 of file sunzilog.h.

#define R6   6

Definition at line 36 of file sunzilog.h.

#define R7   7

Definition at line 37 of file sunzilog.h.

#define R7p   16 /* Written as R7 with P15 bit 0 set */

Definition at line 17 of file sunzilog.h.

#define R8   8

Definition at line 38 of file sunzilog.h.

#define R9   9

Definition at line 39 of file sunzilog.h.

#define RCBR   0x40 /* Receive clock = BR Generator output */

Definition at line 178 of file sunzilog.h.

#define RCDPLL   0x60 /* Receive clock = DPLL output */

Definition at line 179 of file sunzilog.h.

#define RCRTxCP   0 /* Receive clock = RTxC pin */

Definition at line 176 of file sunzilog.h.

#define RCTRxCP   0x20 /* Receive clock = TRxC pin */

Definition at line 177 of file sunzilog.h.

#define RES18   0xe /* 1/8 */

Definition at line 230 of file sunzilog.h.

#define RES28   0x0 /* 2/8 */

Definition at line 231 of file sunzilog.h.

#define RES3   0x8 /* 0/3 */

Definition at line 224 of file sunzilog.h.

#define RES4   0x4 /* 0/4 */

Definition at line 225 of file sunzilog.h.

#define RES5   0xc /* 0/5 */

Definition at line 226 of file sunzilog.h.

#define RES6   0x2 /* 0/6 */

Definition at line 227 of file sunzilog.h.

#define RES7   0xa /* 0/7 */

Definition at line 228 of file sunzilog.h.

#define RES8   0x6 /* 0/8 */

Definition at line 229 of file sunzilog.h.

#define RES_EOM_L   0xC0 /* Reset EOM latch */

Definition at line 58 of file sunzilog.h.

#define RES_EXT_INT   0x10 /* Reset Ext. Status Interrupts */

Definition at line 49 of file sunzilog.h.

#define RES_H_IUS   0x38 /* Reset highest IUS */

Definition at line 54 of file sunzilog.h.

#define RES_Rx_CRC   0x40 /* Reset Rx CRC Checker */

Definition at line 56 of file sunzilog.h.

#define RES_RxINT_FC   0x20 /* Reset RxINT on First Character */

Definition at line 51 of file sunzilog.h.

#define RES_Tx_CRC   0x80 /* Reset Tx CRC Checker */

Definition at line 57 of file sunzilog.h.

#define RES_Tx_P   0x28 /* Reset TxINT Pending */

Definition at line 52 of file sunzilog.h.

#define RMC   0x40 /* Reset missing clock */

Definition at line 193 of file sunzilog.h.

#define RTS   0x2 /* RTS */

Definition at line 116 of file sunzilog.h.

#define RTxCX   0x80 /* RTxC Xtal/No Xtal */

Definition at line 180 of file sunzilog.h.

#define Rx5   0x0 /* Rx 5 Bits/Character */

Definition at line 86 of file sunzilog.h.

#define Rx6   0x80 /* Rx 6 Bits/Character */

Definition at line 88 of file sunzilog.h.

#define Rx7   0x40 /* Rx 7 Bits/Character */

Definition at line 87 of file sunzilog.h.

#define Rx8   0xc0 /* Rx 8 Bits/Character */

Definition at line 89 of file sunzilog.h.

#define Rx_CH_AV   0x1 /* Rx Character Available */

Definition at line 212 of file sunzilog.h.

#define Rx_OVR   0x20 /* Rx Overrun Error */

Definition at line 234 of file sunzilog.h.

#define RxCRC_ENAB   0x8 /* Rx CRC Enable */

Definition at line 83 of file sunzilog.h.

#define RxENAB   0x1 /* Rx Enable */

Definition at line 80 of file sunzilog.h.

#define RxFIFO_LVL   8 /* Receive FIFO interrupt level */

Definition at line 135 of file sunzilog.h.

#define RxINT_DISAB   0 /* Rx Int Disable */

Definition at line 66 of file sunzilog.h.

#define RxINT_FCERR   0x8 /* Rx Int on First Character Only or Error */

Definition at line 67 of file sunzilog.h.

#define RxINT_MASK   0x18

Definition at line 70 of file sunzilog.h.

#define RxN_MASK   0xc0

Definition at line 90 of file sunzilog.h.

#define SB1   0x4 /* 1 stop bit/char */

Definition at line 98 of file sunzilog.h.

#define SB15   0x8 /* 1.5 stop bits/char */

Definition at line 99 of file sunzilog.h.

#define SB2   0xc /* 2 stop bits/char */

Definition at line 100 of file sunzilog.h.

#define SDLC   0x20 /* SDLC Mode (01111110 Sync Flag) */

Definition at line 104 of file sunzilog.h.

#define SDLC_CRC   0x4 /* SDLC/CRC-16 */

Definition at line 117 of file sunzilog.h.

#define SEARCH   0x20 /* Enter search mode */

Definition at line 192 of file sunzilog.h.

#define SEND_ABORT   0x18 /* HDLC Abort */

Definition at line 50 of file sunzilog.h.

#define SFMM   0xc0 /* Set FM mode */

Definition at line 197 of file sunzilog.h.

#define SND_BRK   0x10 /* Send Break */

Definition at line 119 of file sunzilog.h.

#define SNRZI   0xe0 /* Set NRZI mode */

Definition at line 198 of file sunzilog.h.

#define SSBR   0x80 /* Set DPLL source = BR generator */

Definition at line 195 of file sunzilog.h.

#define SSRTxC   0xa0 /* Set DPLL source = RTxC */

Definition at line 196 of file sunzilog.h.

#define STATHI   0x10 /* Status high */

Definition at line 147 of file sunzilog.h.

#define STATUS_MASK   0x0e

Definition at line 247 of file sunzilog.h.

#define SWIACK   0x20 /* Software Interrupt Ack (not on NMOS) */

Definition at line 148 of file sunzilog.h.

#define SYNC   0x10 /* Sync/hunt */

Definition at line 216 of file sunzilog.h.

#define SYNC_ENAB   0 /* Sync Modes Enable */

Definition at line 97 of file sunzilog.h.

#define SYNC_L_INH   0x2 /* Sync Character Load Inhibit */

Definition at line 81 of file sunzilog.h.

#define SYNCIE   0x10 /* Sync/hunt IE */

Definition at line 205 of file sunzilog.h.

#define TCBR   0x10 /* Transmit clock = BR Generator output */

Definition at line 174 of file sunzilog.h.

#define TCDPLL   0x18 /* Transmit clock = DPLL output */

Definition at line 175 of file sunzilog.h.

#define TCRTxCP   0 /* Transmit clock = RTxC pin */

Definition at line 172 of file sunzilog.h.

#define TCTRxCP   8 /* Transmit clock = TRxC pin */

Definition at line 173 of file sunzilog.h.

#define TRxCBR   2 /* TRxC = BR Generator Output */

Definition at line 169 of file sunzilog.h.

#define TRxCDP   3 /* TRxC = DPLL output */

Definition at line 170 of file sunzilog.h.

#define TRxCOI   4 /* TRxC O/I */

Definition at line 171 of file sunzilog.h.

#define TRxCTC   1 /* TRxC = Transmit clock */

Definition at line 168 of file sunzilog.h.

#define TRxCXT   0 /* TRxC = Xtal output */

Definition at line 167 of file sunzilog.h.

#define Tx5   0x0 /* Tx 5 bits (or less)/character */

Definition at line 120 of file sunzilog.h.

#define Tx6   0x40 /* Tx 6 bits/character */

Definition at line 122 of file sunzilog.h.

#define Tx7   0x20 /* Tx 7 bits/character */

Definition at line 121 of file sunzilog.h.

#define Tx8   0x60 /* Tx 8 bits/character */

Definition at line 123 of file sunzilog.h.

#define Tx_BUF_EMP   0x4 /* Tx Buffer empty */

Definition at line 214 of file sunzilog.h.

#define TxCRC_ENAB   0x1 /* Tx CRC Enable */

Definition at line 115 of file sunzilog.h.

#define TxENAB   0x8 /* Tx Enable */

Definition at line 118 of file sunzilog.h.

#define TxEOM   0x40 /* Tx underrun */

Definition at line 218 of file sunzilog.h.

#define TxFIFO_LVL   0x20 /* Transmit FIFO interrupt level */

Definition at line 137 of file sunzilog.h.

#define TxINT_ENAB   0x2 /* Tx Int Enable */

Definition at line 63 of file sunzilog.h.

#define TxN_MASK   0x60

Definition at line 124 of file sunzilog.h.

#define TxUIE   0x40 /* Tx Underrun/EOM IE */

Definition at line 207 of file sunzilog.h.

#define VIS   1 /* Vector Includes Status */

Definition at line 143 of file sunzilog.h.

#define WR7pEN   1 /* WR7' Enable (ESCC only) */

Definition at line 201 of file sunzilog.h.

#define WT_FN_RDYFN   0x40 /* Wait/FN/Ready FN */

Definition at line 73 of file sunzilog.h.

#define WT_RDY_ENAB   0x80 /* Wait/Ready Enable */

Definition at line 74 of file sunzilog.h.

#define WT_RDY_RT   0x20 /* Wait/Ready on R/T */

Definition at line 72 of file sunzilog.h.

#define X16CLK   0x40 /* x16 clock mode */

Definition at line 108 of file sunzilog.h.

#define X1CLK   0x0 /* x1 clock mode */

Definition at line 107 of file sunzilog.h.

#define X32CLK   0x80 /* x32 clock mode */

Definition at line 109 of file sunzilog.h.

#define X64CLK   0xC0 /* x64 clock mode */

Definition at line 110 of file sunzilog.h.

#define XCLK_MASK   0xC0

Definition at line 111 of file sunzilog.h.

#define ZCIE   2 /* Zero count IE */

Definition at line 202 of file sunzilog.h.

#define ZCOUNT   0x2 /* Zero count */

Definition at line 213 of file sunzilog.h.

#define ZS_CLEARERR (   channel)
Value:
do { sbus_writeb(ERR_RES, &channel->control); \
udelay(5); } while(0)

Definition at line 276 of file sunzilog.h.

#define ZS_CLEARFIFO (   channel)
Value:
do { sbus_readb(&channel->data); \
udelay(2); \
sbus_readb(&channel->data); \
udelay(2); \
sbus_readb(&channel->data); \
udelay(2); } while(0)

Definition at line 282 of file sunzilog.h.

#define ZS_CLEARSTAT (   channel)
Value:
do { sbus_writeb(RES_EXT_INT, &channel->control); \
udelay(5); } while(0)

Definition at line 279 of file sunzilog.h.