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vt8623fb.c
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1 /*
2  * linux/drivers/video/vt8623fb.c - fbdev driver for
3  * integrated graphic core in VIA VT8623 [CLE266] chipset
4  *
5  * Copyright (c) 2006-2007 Ondrej Zajicek <[email protected]>
6  *
7  * This file is subject to the terms and conditions of the GNU General Public
8  * License. See the file COPYING in the main directory of this archive for
9  * more details.
10  *
11  * Code is based on s3fb, some parts are from David Boucher's viafb
12  * (http://davesdomain.org.uk/viafb/)
13  */
14 
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/tty.h>
21 #include <linux/delay.h>
22 #include <linux/fb.h>
23 #include <linux/svga.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
27 #include <video/vga.h>
28 
29 #ifdef CONFIG_MTRR
30 #include <asm/mtrr.h>
31 #endif
32 
33 struct vt8623fb_info {
34  char __iomem *mmio_base;
35  int mtrr_reg;
36  struct vgastate state;
37  struct mutex open_lock;
38  unsigned int ref_count;
39  u32 pseudo_palette[16];
40 };
41 
42 
43 
44 /* ------------------------------------------------------------------------- */
45 
46 static const struct svga_fb_format vt8623fb_formats[] = {
47  { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
48  FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP8, FB_VISUAL_PSEUDOCOLOR, 16, 16},
49  { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
50  FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 16, 16},
51  { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
52  FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 16, 16},
53  { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
54  FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 8},
55 /* {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
56  FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4}, */
57  {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
58  FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
59  {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
60  FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 2},
61  SVGA_FORMAT_END
62 };
63 
64 static const struct svga_pll vt8623_pll = {2, 127, 2, 7, 0, 3,
65  60000, 300000, 14318};
66 
67 /* CRT timing register sets */
68 
69 static struct vga_regset vt8623_h_total_regs[] = {{0x00, 0, 7}, {0x36, 3, 3}, VGA_REGSET_END};
70 static struct vga_regset vt8623_h_display_regs[] = {{0x01, 0, 7}, VGA_REGSET_END};
71 static struct vga_regset vt8623_h_blank_start_regs[] = {{0x02, 0, 7}, VGA_REGSET_END};
72 static struct vga_regset vt8623_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, {0x33, 5, 5}, VGA_REGSET_END};
73 static struct vga_regset vt8623_h_sync_start_regs[] = {{0x04, 0, 7}, {0x33, 4, 4}, VGA_REGSET_END};
74 static struct vga_regset vt8623_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
75 
76 static struct vga_regset vt8623_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x35, 0, 0}, VGA_REGSET_END};
77 static struct vga_regset vt8623_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x35, 2, 2}, VGA_REGSET_END};
78 static struct vga_regset vt8623_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x35, 3, 3}, VGA_REGSET_END};
79 static struct vga_regset vt8623_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
80 static struct vga_regset vt8623_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x35, 1, 1}, VGA_REGSET_END};
81 static struct vga_regset vt8623_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
82 
83 static struct vga_regset vt8623_offset_regs[] = {{0x13, 0, 7}, {0x35, 5, 7}, VGA_REGSET_END};
84 static struct vga_regset vt8623_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x33, 0, 2}, {0x35, 4, 4}, VGA_REGSET_END};
85 static struct vga_regset vt8623_fetch_count_regs[] = {{0x1C, 0, 7}, {0x1D, 0, 1}, VGA_REGSET_END};
86 static struct vga_regset vt8623_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x34, 0, 7}, {0x48, 0, 1}, VGA_REGSET_END};
87 
88 static struct svga_timing_regs vt8623_timing_regs = {
89  vt8623_h_total_regs, vt8623_h_display_regs, vt8623_h_blank_start_regs,
90  vt8623_h_blank_end_regs, vt8623_h_sync_start_regs, vt8623_h_sync_end_regs,
91  vt8623_v_total_regs, vt8623_v_display_regs, vt8623_v_blank_start_regs,
92  vt8623_v_blank_end_regs, vt8623_v_sync_start_regs, vt8623_v_sync_end_regs,
93 };
94 
95 
96 /* ------------------------------------------------------------------------- */
97 
98 
99 /* Module parameters */
100 
101 static char *mode_option = "640x480-8@60";
102 
103 #ifdef CONFIG_MTRR
104 static int mtrr = 1;
105 #endif
106 
107 MODULE_AUTHOR("(c) 2006 Ondrej Zajicek <[email protected]>");
108 MODULE_LICENSE("GPL");
109 MODULE_DESCRIPTION("fbdev driver for integrated graphics core in VIA VT8623 [CLE266]");
110 
111 module_param(mode_option, charp, 0644);
112 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
113 module_param_named(mode, mode_option, charp, 0);
114 MODULE_PARM_DESC(mode, "Default video mode e.g. '648x480-8@60' (deprecated)");
115 
116 #ifdef CONFIG_MTRR
117 module_param(mtrr, int, 0444);
118 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
119 #endif
120 
121 
122 /* ------------------------------------------------------------------------- */
123 
124 static void vt8623fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
125 {
126  struct vt8623fb_info *par = info->par;
127 
128  svga_tilecursor(par->state.vgabase, info, cursor);
129 }
130 
131 static struct fb_tile_ops vt8623fb_tile_ops = {
132  .fb_settile = svga_settile,
133  .fb_tilecopy = svga_tilecopy,
134  .fb_tilefill = svga_tilefill,
135  .fb_tileblit = svga_tileblit,
136  .fb_tilecursor = vt8623fb_tilecursor,
137  .fb_get_tilemax = svga_get_tilemax,
138 };
139 
140 
141 /* ------------------------------------------------------------------------- */
142 
143 
144 /* image data is MSB-first, fb structure is MSB-first too */
145 static inline u32 expand_color(u32 c)
146 {
147  return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
148 }
149 
150 /* vt8623fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
151 static void vt8623fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
152 {
153  u32 fg = expand_color(image->fg_color);
154  u32 bg = expand_color(image->bg_color);
155  const u8 *src1, *src;
156  u8 __iomem *dst1;
157  u32 __iomem *dst;
158  u32 val;
159  int x, y;
160 
161  src1 = image->data;
162  dst1 = info->screen_base + (image->dy * info->fix.line_length)
163  + ((image->dx / 8) * 4);
164 
165  for (y = 0; y < image->height; y++) {
166  src = src1;
167  dst = (u32 __iomem *) dst1;
168  for (x = 0; x < image->width; x += 8) {
169  val = *(src++) * 0x01010101;
170  val = (val & fg) | (~val & bg);
171  fb_writel(val, dst++);
172  }
173  src1 += image->width / 8;
174  dst1 += info->fix.line_length;
175  }
176 }
177 
178 /* vt8623fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
179 static void vt8623fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
180 {
181  u32 fg = expand_color(rect->color);
182  u8 __iomem *dst1;
183  u32 __iomem *dst;
184  int x, y;
185 
186  dst1 = info->screen_base + (rect->dy * info->fix.line_length)
187  + ((rect->dx / 8) * 4);
188 
189  for (y = 0; y < rect->height; y++) {
190  dst = (u32 __iomem *) dst1;
191  for (x = 0; x < rect->width; x += 8) {
192  fb_writel(fg, dst++);
193  }
194  dst1 += info->fix.line_length;
195  }
196 }
197 
198 
199 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
200 static inline u32 expand_pixel(u32 c)
201 {
202  return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
203  ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
204 }
205 
206 /* vt8623fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
207 static void vt8623fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
208 {
209  u32 fg = image->fg_color * 0x11111111;
210  u32 bg = image->bg_color * 0x11111111;
211  const u8 *src1, *src;
212  u8 __iomem *dst1;
213  u32 __iomem *dst;
214  u32 val;
215  int x, y;
216 
217  src1 = image->data;
218  dst1 = info->screen_base + (image->dy * info->fix.line_length)
219  + ((image->dx / 8) * 4);
220 
221  for (y = 0; y < image->height; y++) {
222  src = src1;
223  dst = (u32 __iomem *) dst1;
224  for (x = 0; x < image->width; x += 8) {
225  val = expand_pixel(*(src++));
226  val = (val & fg) | (~val & bg);
227  fb_writel(val, dst++);
228  }
229  src1 += image->width / 8;
230  dst1 += info->fix.line_length;
231  }
232 }
233 
234 static void vt8623fb_imageblit(struct fb_info *info, const struct fb_image *image)
235 {
236  if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
237  && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
238  if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
239  vt8623fb_iplan_imageblit(info, image);
240  else
241  vt8623fb_cfb4_imageblit(info, image);
242  } else
243  cfb_imageblit(info, image);
244 }
245 
246 static void vt8623fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
247 {
248  if ((info->var.bits_per_pixel == 4)
249  && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
250  && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
251  vt8623fb_iplan_fillrect(info, rect);
252  else
253  cfb_fillrect(info, rect);
254 }
255 
256 
257 /* ------------------------------------------------------------------------- */
258 
259 
260 static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock)
261 {
262  struct vt8623fb_info *par = info->par;
263  u16 m, n, r;
264  u8 regval;
265  int rv;
266 
267  rv = svga_compute_pll(&vt8623_pll, 1000000000 / pixclock, &m, &n, &r, info->node);
268  if (rv < 0) {
269  printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);
270  return;
271  }
272 
273  /* Set VGA misc register */
274  regval = vga_r(par->state.vgabase, VGA_MIS_R);
275  vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
276 
277  /* Set clock registers */
278  vga_wseq(par->state.vgabase, 0x46, (n | (r << 6)));
279  vga_wseq(par->state.vgabase, 0x47, m);
280 
281  udelay(1000);
282 
283  /* PLL reset */
284  svga_wseq_mask(par->state.vgabase, 0x40, 0x02, 0x02);
285  svga_wseq_mask(par->state.vgabase, 0x40, 0x00, 0x02);
286 }
287 
288 
289 static int vt8623fb_open(struct fb_info *info, int user)
290 {
291  struct vt8623fb_info *par = info->par;
292 
293  mutex_lock(&(par->open_lock));
294  if (par->ref_count == 0) {
295  void __iomem *vgabase = par->state.vgabase;
296 
297  memset(&(par->state), 0, sizeof(struct vgastate));
298  par->state.vgabase = vgabase;
299  par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
300  par->state.num_crtc = 0xA2;
301  par->state.num_seq = 0x50;
302  save_vga(&(par->state));
303  }
304 
305  par->ref_count++;
306  mutex_unlock(&(par->open_lock));
307 
308  return 0;
309 }
310 
311 static int vt8623fb_release(struct fb_info *info, int user)
312 {
313  struct vt8623fb_info *par = info->par;
314 
315  mutex_lock(&(par->open_lock));
316  if (par->ref_count == 0) {
317  mutex_unlock(&(par->open_lock));
318  return -EINVAL;
319  }
320 
321  if (par->ref_count == 1)
322  restore_vga(&(par->state));
323 
324  par->ref_count--;
325  mutex_unlock(&(par->open_lock));
326 
327  return 0;
328 }
329 
330 static int vt8623fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
331 {
332  int rv, mem, step;
333 
334  /* Find appropriate format */
335  rv = svga_match_format (vt8623fb_formats, var, NULL);
336  if (rv < 0)
337  {
338  printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
339  return rv;
340  }
341 
342  /* Do not allow to have real resoulution larger than virtual */
343  if (var->xres > var->xres_virtual)
344  var->xres_virtual = var->xres;
345 
346  if (var->yres > var->yres_virtual)
347  var->yres_virtual = var->yres;
348 
349  /* Round up xres_virtual to have proper alignment of lines */
350  step = vt8623fb_formats[rv].xresstep - 1;
351  var->xres_virtual = (var->xres_virtual+step) & ~step;
352 
353  /* Check whether have enough memory */
354  mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
355  if (mem > info->screen_size)
356  {
357  printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
358  return -EINVAL;
359  }
360 
361  /* Text mode is limited to 256 kB of memory */
362  if ((var->bits_per_pixel == 0) && (mem > (256*1024)))
363  {
364  printk(KERN_ERR "fb%d: text framebuffer size too large (%d kB requested, 256 kB possible)\n", info->node, mem >> 10);
365  return -EINVAL;
366  }
367 
368  rv = svga_check_timings (&vt8623_timing_regs, var, info->node);
369  if (rv < 0)
370  {
371  printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
372  return rv;
373  }
374 
375  /* Interlaced mode not supported */
376  if (var->vmode & FB_VMODE_INTERLACED)
377  return -EINVAL;
378 
379  return 0;
380 }
381 
382 
383 static int vt8623fb_set_par(struct fb_info *info)
384 {
385  u32 mode, offset_value, fetch_value, screen_size;
386  struct vt8623fb_info *par = info->par;
387  u32 bpp = info->var.bits_per_pixel;
388 
389  if (bpp != 0) {
390  info->fix.ypanstep = 1;
391  info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
392 
393  info->flags &= ~FBINFO_MISC_TILEBLITTING;
394  info->tileops = NULL;
395 
396  /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
397  info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
398  info->pixmap.blit_y = ~(u32)0;
399 
400  offset_value = (info->var.xres_virtual * bpp) / 64;
401  fetch_value = ((info->var.xres * bpp) / 128) + 4;
402 
403  if (bpp == 4)
404  fetch_value = (info->var.xres / 8) + 8; /* + 0 is OK */
405 
406  screen_size = info->var.yres_virtual * info->fix.line_length;
407  } else {
408  info->fix.ypanstep = 16;
409  info->fix.line_length = 0;
410 
411  info->flags |= FBINFO_MISC_TILEBLITTING;
412  info->tileops = &vt8623fb_tile_ops;
413 
414  /* supports 8x16 tiles only */
415  info->pixmap.blit_x = 1 << (8 - 1);
416  info->pixmap.blit_y = 1 << (16 - 1);
417 
418  offset_value = info->var.xres_virtual / 16;
419  fetch_value = (info->var.xres / 8) + 8;
420  screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
421  }
422 
423  info->var.xoffset = 0;
424  info->var.yoffset = 0;
425  info->var.activate = FB_ACTIVATE_NOW;
426 
427  /* Unlock registers */
428  svga_wseq_mask(par->state.vgabase, 0x10, 0x01, 0x01);
429  svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
430  svga_wcrt_mask(par->state.vgabase, 0x47, 0x00, 0x01);
431 
432  /* Device, screen and sync off */
433  svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
434  svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30);
435  svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
436 
437  /* Set default values */
438  svga_set_default_gfx_regs(par->state.vgabase);
439  svga_set_default_atc_regs(par->state.vgabase);
440  svga_set_default_seq_regs(par->state.vgabase);
441  svga_set_default_crt_regs(par->state.vgabase);
442  svga_wcrt_multi(par->state.vgabase, vt8623_line_compare_regs, 0xFFFFFFFF);
443  svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, 0);
444 
445  svga_wcrt_multi(par->state.vgabase, vt8623_offset_regs, offset_value);
446  svga_wseq_multi(par->state.vgabase, vt8623_fetch_count_regs, fetch_value);
447 
448  /* Clear H/V Skew */
449  svga_wcrt_mask(par->state.vgabase, 0x03, 0x00, 0x60);
450  svga_wcrt_mask(par->state.vgabase, 0x05, 0x00, 0x60);
451 
452  if (info->var.vmode & FB_VMODE_DOUBLE)
453  svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
454  else
455  svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
456 
457  svga_wseq_mask(par->state.vgabase, 0x1E, 0xF0, 0xF0); // DI/DVP bus
458  svga_wseq_mask(par->state.vgabase, 0x2A, 0x0F, 0x0F); // DI/DVP bus
459  svga_wseq_mask(par->state.vgabase, 0x16, 0x08, 0xBF); // FIFO read threshold
460  vga_wseq(par->state.vgabase, 0x17, 0x1F); // FIFO depth
461  vga_wseq(par->state.vgabase, 0x18, 0x4E);
462  svga_wseq_mask(par->state.vgabase, 0x1A, 0x08, 0x08); // enable MMIO ?
463 
464  vga_wcrt(par->state.vgabase, 0x32, 0x00);
465  vga_wcrt(par->state.vgabase, 0x34, 0x00);
466  vga_wcrt(par->state.vgabase, 0x6A, 0x80);
467  vga_wcrt(par->state.vgabase, 0x6A, 0xC0);
468 
469  vga_wgfx(par->state.vgabase, 0x20, 0x00);
470  vga_wgfx(par->state.vgabase, 0x21, 0x00);
471  vga_wgfx(par->state.vgabase, 0x22, 0x00);
472 
473  /* Set SR15 according to number of bits per pixel */
474  mode = svga_match_format(vt8623fb_formats, &(info->var), &(info->fix));
475  switch (mode) {
476  case 0:
477  pr_debug("fb%d: text mode\n", info->node);
478  svga_set_textmode_vga_regs(par->state.vgabase);
479  svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
480  svga_wcrt_mask(par->state.vgabase, 0x11, 0x60, 0x70);
481  break;
482  case 1:
483  pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
484  vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
485  svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE);
486  svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70);
487  break;
488  case 2:
489  pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
490  svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
491  svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70);
492  break;
493  case 3:
494  pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
495  svga_wseq_mask(par->state.vgabase, 0x15, 0x22, 0xFE);
496  break;
497  case 4:
498  pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
499  svga_wseq_mask(par->state.vgabase, 0x15, 0xB6, 0xFE);
500  break;
501  case 5:
502  pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
503  svga_wseq_mask(par->state.vgabase, 0x15, 0xAE, 0xFE);
504  break;
505  default:
506  printk(KERN_ERR "vt8623fb: unsupported mode - bug\n");
507  return (-EINVAL);
508  }
509 
510  vt8623_set_pixclock(info, info->var.pixclock);
511  svga_set_timings(par->state.vgabase, &vt8623_timing_regs, &(info->var), 1, 1,
512  (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, 1,
513  1, info->node);
514 
515  memset_io(info->screen_base, 0x00, screen_size);
516 
517  /* Device and screen back on */
518  svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
519  svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
520  svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
521 
522  return 0;
523 }
524 
525 
526 static int vt8623fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
527  u_int transp, struct fb_info *fb)
528 {
529  switch (fb->var.bits_per_pixel) {
530  case 0:
531  case 4:
532  if (regno >= 16)
533  return -EINVAL;
534 
535  outb(0x0F, VGA_PEL_MSK);
536  outb(regno, VGA_PEL_IW);
537  outb(red >> 10, VGA_PEL_D);
538  outb(green >> 10, VGA_PEL_D);
539  outb(blue >> 10, VGA_PEL_D);
540  break;
541  case 8:
542  if (regno >= 256)
543  return -EINVAL;
544 
545  outb(0xFF, VGA_PEL_MSK);
546  outb(regno, VGA_PEL_IW);
547  outb(red >> 10, VGA_PEL_D);
548  outb(green >> 10, VGA_PEL_D);
549  outb(blue >> 10, VGA_PEL_D);
550  break;
551  case 16:
552  if (regno >= 16)
553  return 0;
554 
555  if (fb->var.green.length == 5)
556  ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
557  ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
558  else if (fb->var.green.length == 6)
559  ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
560  ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
561  else
562  return -EINVAL;
563  break;
564  case 24:
565  case 32:
566  if (regno >= 16)
567  return 0;
568 
569  /* ((transp & 0xFF00) << 16) */
570  ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
571  (green & 0xFF00) | ((blue & 0xFF00) >> 8);
572  break;
573  default:
574  return -EINVAL;
575  }
576 
577  return 0;
578 }
579 
580 
581 static int vt8623fb_blank(int blank_mode, struct fb_info *info)
582 {
583  struct vt8623fb_info *par = info->par;
584 
585  switch (blank_mode) {
586  case FB_BLANK_UNBLANK:
587  pr_debug("fb%d: unblank\n", info->node);
588  svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
589  svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
590  break;
591  case FB_BLANK_NORMAL:
592  pr_debug("fb%d: blank\n", info->node);
593  svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
594  svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
595  break;
596  case FB_BLANK_HSYNC_SUSPEND:
597  pr_debug("fb%d: DPMS standby (hsync off)\n", info->node);
598  svga_wcrt_mask(par->state.vgabase, 0x36, 0x10, 0x30);
599  svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
600  break;
601  case FB_BLANK_VSYNC_SUSPEND:
602  pr_debug("fb%d: DPMS suspend (vsync off)\n", info->node);
603  svga_wcrt_mask(par->state.vgabase, 0x36, 0x20, 0x30);
604  svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
605  break;
606  case FB_BLANK_POWERDOWN:
607  pr_debug("fb%d: DPMS off (no sync)\n", info->node);
608  svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30);
609  svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
610  break;
611  }
612 
613  return 0;
614 }
615 
616 
617 static int vt8623fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
618 {
619  struct vt8623fb_info *par = info->par;
620  unsigned int offset;
621 
622  /* Calculate the offset */
623  if (info->var.bits_per_pixel == 0) {
624  offset = (var->yoffset / 16) * info->var.xres_virtual
625  + var->xoffset;
626  offset = offset >> 3;
627  } else {
628  offset = (var->yoffset * info->fix.line_length) +
629  (var->xoffset * info->var.bits_per_pixel / 8);
630  offset = offset >> ((info->var.bits_per_pixel == 4) ? 2 : 1);
631  }
632 
633  /* Set the offset */
634  svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, offset);
635 
636  return 0;
637 }
638 
639 
640 /* ------------------------------------------------------------------------- */
641 
642 
643 /* Frame buffer operations */
644 
645 static struct fb_ops vt8623fb_ops = {
646  .owner = THIS_MODULE,
647  .fb_open = vt8623fb_open,
648  .fb_release = vt8623fb_release,
649  .fb_check_var = vt8623fb_check_var,
650  .fb_set_par = vt8623fb_set_par,
651  .fb_setcolreg = vt8623fb_setcolreg,
652  .fb_blank = vt8623fb_blank,
653  .fb_pan_display = vt8623fb_pan_display,
654  .fb_fillrect = vt8623fb_fillrect,
655  .fb_copyarea = cfb_copyarea,
656  .fb_imageblit = vt8623fb_imageblit,
657  .fb_get_caps = svga_get_caps,
658 };
659 
660 
661 /* PCI probe */
662 
663 static int __devinit vt8623_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
664 {
665  struct pci_bus_region bus_reg;
666  struct resource vga_res;
667  struct fb_info *info;
668  struct vt8623fb_info *par;
669  unsigned int memsize1, memsize2;
670  int rc;
671 
672  /* Ignore secondary VGA device because there is no VGA arbitration */
673  if (! svga_primary_device(dev)) {
674  dev_info(&(dev->dev), "ignoring secondary device\n");
675  return -ENODEV;
676  }
677 
678  /* Allocate and fill driver data structure */
679  info = framebuffer_alloc(sizeof(struct vt8623fb_info), &(dev->dev));
680  if (! info) {
681  dev_err(&(dev->dev), "cannot allocate memory\n");
682  return -ENOMEM;
683  }
684 
685  par = info->par;
686  mutex_init(&par->open_lock);
687 
688  info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
689  info->fbops = &vt8623fb_ops;
690 
691  /* Prepare PCI device */
692 
693  rc = pci_enable_device(dev);
694  if (rc < 0) {
695  dev_err(info->device, "cannot enable PCI device\n");
696  goto err_enable_device;
697  }
698 
699  rc = pci_request_regions(dev, "vt8623fb");
700  if (rc < 0) {
701  dev_err(info->device, "cannot reserve framebuffer region\n");
702  goto err_request_regions;
703  }
704 
705  info->fix.smem_start = pci_resource_start(dev, 0);
706  info->fix.smem_len = pci_resource_len(dev, 0);
707  info->fix.mmio_start = pci_resource_start(dev, 1);
708  info->fix.mmio_len = pci_resource_len(dev, 1);
709 
710  /* Map physical IO memory address into kernel space */
711  info->screen_base = pci_iomap(dev, 0, 0);
712  if (! info->screen_base) {
713  rc = -ENOMEM;
714  dev_err(info->device, "iomap for framebuffer failed\n");
715  goto err_iomap_1;
716  }
717 
718  par->mmio_base = pci_iomap(dev, 1, 0);
719  if (! par->mmio_base) {
720  rc = -ENOMEM;
721  dev_err(info->device, "iomap for MMIO failed\n");
722  goto err_iomap_2;
723  }
724 
725  bus_reg.start = 0;
726  bus_reg.end = 64 * 1024;
727 
728  vga_res.flags = IORESOURCE_IO;
729 
730  pcibios_bus_to_resource(dev, &vga_res, &bus_reg);
731 
732  par->state.vgabase = (void __iomem *) vga_res.start;
733 
734  /* Find how many physical memory there is on card */
735  memsize1 = (vga_rseq(par->state.vgabase, 0x34) + 1) >> 1;
736  memsize2 = vga_rseq(par->state.vgabase, 0x39) << 2;
737 
738  if ((16 <= memsize1) && (memsize1 <= 64) && (memsize1 == memsize2))
739  info->screen_size = memsize1 << 20;
740  else {
741  dev_err(info->device, "memory size detection failed (%x %x), suppose 16 MB\n", memsize1, memsize2);
742  info->screen_size = 16 << 20;
743  }
744 
745  info->fix.smem_len = info->screen_size;
746  strcpy(info->fix.id, "VIA VT8623");
747  info->fix.type = FB_TYPE_PACKED_PIXELS;
748  info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
749  info->fix.ypanstep = 0;
750  info->fix.accel = FB_ACCEL_NONE;
751  info->pseudo_palette = (void*)par->pseudo_palette;
752 
753  /* Prepare startup mode */
754 
755  kparam_block_sysfs_write(mode_option);
756  rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
757  kparam_unblock_sysfs_write(mode_option);
758  if (! ((rc == 1) || (rc == 2))) {
759  rc = -EINVAL;
760  dev_err(info->device, "mode %s not found\n", mode_option);
761  goto err_find_mode;
762  }
763 
764  rc = fb_alloc_cmap(&info->cmap, 256, 0);
765  if (rc < 0) {
766  dev_err(info->device, "cannot allocate colormap\n");
767  goto err_alloc_cmap;
768  }
769 
770  rc = register_framebuffer(info);
771  if (rc < 0) {
772  dev_err(info->device, "cannot register framebugger\n");
773  goto err_reg_fb;
774  }
775 
776  printk(KERN_INFO "fb%d: %s on %s, %d MB RAM\n", info->node, info->fix.id,
777  pci_name(dev), info->fix.smem_len >> 20);
778 
779  /* Record a reference to the driver data */
780  pci_set_drvdata(dev, info);
781 
782 #ifdef CONFIG_MTRR
783  if (mtrr) {
784  par->mtrr_reg = -1;
785  par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
786  }
787 #endif
788 
789  return 0;
790 
791  /* Error handling */
792 err_reg_fb:
793  fb_dealloc_cmap(&info->cmap);
794 err_alloc_cmap:
795 err_find_mode:
796  pci_iounmap(dev, par->mmio_base);
797 err_iomap_2:
798  pci_iounmap(dev, info->screen_base);
799 err_iomap_1:
800  pci_release_regions(dev);
801 err_request_regions:
802 /* pci_disable_device(dev); */
803 err_enable_device:
804  framebuffer_release(info);
805  return rc;
806 }
807 
808 /* PCI remove */
809 
810 static void __devexit vt8623_pci_remove(struct pci_dev *dev)
811 {
812  struct fb_info *info = pci_get_drvdata(dev);
813 
814  if (info) {
815  struct vt8623fb_info *par = info->par;
816 
817 #ifdef CONFIG_MTRR
818  if (par->mtrr_reg >= 0) {
819  mtrr_del(par->mtrr_reg, 0, 0);
820  par->mtrr_reg = -1;
821  }
822 #endif
823 
824  unregister_framebuffer(info);
825  fb_dealloc_cmap(&info->cmap);
826 
827  pci_iounmap(dev, info->screen_base);
828  pci_iounmap(dev, par->mmio_base);
829  pci_release_regions(dev);
830 /* pci_disable_device(dev); */
831 
832  pci_set_drvdata(dev, NULL);
833  framebuffer_release(info);
834  }
835 }
836 
837 
838 #ifdef CONFIG_PM
839 /* PCI suspend */
840 
841 static int vt8623_pci_suspend(struct pci_dev* dev, pm_message_t state)
842 {
843  struct fb_info *info = pci_get_drvdata(dev);
844  struct vt8623fb_info *par = info->par;
845 
846  dev_info(info->device, "suspend\n");
847 
848  console_lock();
849  mutex_lock(&(par->open_lock));
850 
851  if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
852  mutex_unlock(&(par->open_lock));
853  console_unlock();
854  return 0;
855  }
856 
857  fb_set_suspend(info, 1);
858 
859  pci_save_state(dev);
860  pci_disable_device(dev);
861  pci_set_power_state(dev, pci_choose_state(dev, state));
862 
863  mutex_unlock(&(par->open_lock));
864  console_unlock();
865 
866  return 0;
867 }
868 
869 
870 /* PCI resume */
871 
872 static int vt8623_pci_resume(struct pci_dev* dev)
873 {
874  struct fb_info *info = pci_get_drvdata(dev);
875  struct vt8623fb_info *par = info->par;
876 
877  dev_info(info->device, "resume\n");
878 
879  console_lock();
880  mutex_lock(&(par->open_lock));
881 
882  if (par->ref_count == 0)
883  goto fail;
884 
885  pci_set_power_state(dev, PCI_D0);
886  pci_restore_state(dev);
887 
888  if (pci_enable_device(dev))
889  goto fail;
890 
891  pci_set_master(dev);
892 
893  vt8623fb_set_par(info);
894  fb_set_suspend(info, 0);
895 
896 fail:
897  mutex_unlock(&(par->open_lock));
898  console_unlock();
899 
900  return 0;
901 }
902 #else
903 #define vt8623_pci_suspend NULL
904 #define vt8623_pci_resume NULL
905 #endif /* CONFIG_PM */
906 
907 /* List of boards that we are trying to support */
908 
909 static struct pci_device_id vt8623_devices[] __devinitdata = {
910  {PCI_DEVICE(PCI_VENDOR_ID_VIA, 0x3122)},
911  {0, 0, 0, 0, 0, 0, 0}
912 };
913 
914 MODULE_DEVICE_TABLE(pci, vt8623_devices);
915 
916 static struct pci_driver vt8623fb_pci_driver = {
917  .name = "vt8623fb",
918  .id_table = vt8623_devices,
919  .probe = vt8623_pci_probe,
920  .remove = __devexit_p(vt8623_pci_remove),
921  .suspend = vt8623_pci_suspend,
922  .resume = vt8623_pci_resume,
923 };
924 
925 /* Cleanup */
926 
927 static void __exit vt8623fb_cleanup(void)
928 {
929  pr_debug("vt8623fb: cleaning up\n");
930  pci_unregister_driver(&vt8623fb_pci_driver);
931 }
932 
933 /* Driver Initialisation */
934 
935 static int __init vt8623fb_init(void)
936 {
937 
938 #ifndef MODULE
939  char *option = NULL;
940 
941  if (fb_get_options("vt8623fb", &option))
942  return -ENODEV;
943 
944  if (option && *option)
945  mode_option = option;
946 #endif
947 
948  pr_debug("vt8623fb: initializing\n");
949  return pci_register_driver(&vt8623fb_pci_driver);
950 }
951 
952 /* ------------------------------------------------------------------------- */
953 
954 /* Modularization */
955 
956 module_init(vt8623fb_init);
957 module_exit(vt8623fb_cleanup);
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