#include <SIRegisterInfo.h>

Inheritance diagram for llvm::SIRegisterInfo:

Collaboration diagram for llvm::SIRegisterInfo:

Public Types
enum	PreloadedValue { TGID_X, TGID_Y, TGID_Z, SCRATCH_WAVE_OFFSET, SCRATCH_PTR }
Public Member Functions
	SIRegisterInfo (const AMDGPUSubtarget &st)
BitVector	getReservedRegs (const MachineFunction &MF) const override
unsigned	getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const override
bool	requiresRegisterScavenging (const MachineFunction &Fn) const override
void	eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
const TargetRegisterClass *	getCFGStructurizerRegClass (MVT VT) const override
	get the register class of the specified type to use in the CFGStructurizer
unsigned	getHWRegIndex (unsigned Reg) const override
const TargetRegisterClass *	getPhysRegClass (unsigned Reg) const
	Return the 'base' register class for this register. e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.
bool	isSGPRClass (const TargetRegisterClass *RC) const
bool	hasVGPRs (const TargetRegisterClass *RC) const
const TargetRegisterClass *	getEquivalentVGPRClass (const TargetRegisterClass *SRC) const
const TargetRegisterClass *	getSubRegClass (const TargetRegisterClass *RC, unsigned SubIdx) const
unsigned	getPhysRegSubReg (unsigned Reg, const TargetRegisterClass *SubRC, unsigned Channel) const
bool	regClassCanUseImmediate (int RCID) const
bool	regClassCanUseImmediate (const TargetRegisterClass *RC) const
unsigned	getPreloadedValue (const MachineFunction &MF, enum PreloadedValue Value) const
	Returns the physical register that `Value` is stored in.

Detailed Description

Definition at line 23 of file SIRegisterInfo.h.

Member Enumeration Documentation

enum llvm::SIRegisterInfo::PreloadedValue

Enumerator:

TGID_X
TGID_Y
TGID_Z
SCRATCH_WAVE_OFFSET
SCRATCH_PTR

Definition at line 78 of file SIRegisterInfo.h.

Constructor & Destructor Documentation

SIRegisterInfo::SIRegisterInfo ( const AMDGPUSubtarget & st )

Definition at line 28 of file SIRegisterInfo.cpp.

Member Function Documentation

void SIRegisterInfo::eliminateFrameIndex	(	MachineBasicBlock::iterator	MI,
		int	SPAdj,
		unsigned	FIOperandNum,
		RegScavenger *	RS
	)		const `[override]`

Reimplemented from llvm::AMDGPURegisterInfo.

Definition at line 71 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), llvm::LLVMContext::emitError(), llvm::MachineInstr::eraseFromParent(), llvm::Function::getContext(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getIndex(), llvm::MachineFunction::getInfo(), llvm::AMDGPUSubtarget::getInstrInfo(), getNumSubRegsForSpillOp(), llvm::MachineBasicBlock::getParent(), getPhysRegSubReg(), llvm::SIMachineFunctionInfo::getSpilledReg(), llvm::SIInstrInfo::insertNOPs(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::SIMachineFunctionInfo::SpilledReg::Lane, llvm::RegScavenger::scavengeRegister(), llvm::AMDGPURegisterInfo::ST, TII, and llvm::SIMachineFunctionInfo::SpilledReg::VGPR.

const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass ( MVT VT ) const [override, virtual]

get the register class of the specified type to use in the CFGStructurizer

Reimplemented from llvm::AMDGPURegisterInfo.

Definition at line 156 of file SIRegisterInfo.cpp.

References llvm::MVT::i32, and llvm::MVT::SimpleTy.

const TargetRegisterClass * SIRegisterInfo::getEquivalentVGPRClass ( const TargetRegisterClass * SRC ) const

Returns:: A VGPR reg class with the same width as SRC

Definition at line 204 of file SIRegisterInfo.cpp.

References hasVGPRs().

Referenced by llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOpWithMove(), and llvm::SIInstrInfo::moveToVALU().

unsigned SIRegisterInfo::getHWRegIndex ( unsigned Reg ) const [override, virtual]

Reimplemented from llvm::AMDGPURegisterInfo.

Definition at line 164 of file SIRegisterInfo.cpp.

Referenced by getPhysRegSubReg().

const TargetRegisterClass * SIRegisterInfo::getPhysRegClass ( unsigned Reg ) const

Return the 'base' register class for this register. e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.

Definition at line 168 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterInfo::isVirtualRegister().

Referenced by isVGPR().

unsigned SIRegisterInfo::getPhysRegSubReg	(	unsigned	Reg,
		const TargetRegisterClass *	SubRC,
		unsigned	Channel
	)		const

Channel This is the register channel (e.g. a value from 0-16), not the SubReg index.

Returns:: The sub-register of Reg that is in Channel.

Definition at line 238 of file SIRegisterInfo.cpp.

References getHWRegIndex(), llvm::TargetRegisterClass::getRegister(), and llvm_unreachable.

Referenced by eliminateFrameIndex().

unsigned SIRegisterInfo::getPreloadedValue	(	const MachineFunction &	MF,
		enum PreloadedValue	Value
	)		const

Returns the physical register that Value is stored in.

Definition at line 294 of file SIRegisterInfo.cpp.

References llvm::MachineFunction::getInfo(), llvm_unreachable, llvm::SIMachineFunctionInfo::NumUserSGPRs, SCRATCH_PTR, SCRATCH_WAVE_OFFSET, TGID_X, TGID_Y, and TGID_Z.

unsigned SIRegisterInfo::getRegPressureLimit	(	const TargetRegisterClass *	RC,
		MachineFunction &	MF
	)		const `[override]`

Definition at line 40 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterClass::getNumRegs().

BitVector SIRegisterInfo::getReservedRegs ( const MachineFunction & MF ) const [override]

Reimplemented from llvm::AMDGPURegisterInfo.

Definition at line 32 of file SIRegisterInfo.cpp.

References llvm::BitVector::set().

const TargetRegisterClass * SIRegisterInfo::getSubRegClass	(	const TargetRegisterClass *	RC,
		unsigned	SubIdx
	)		const

Returns:: The register class that is used for a sub-register of RC for the given SubIdx. If SubIdx equals NoSubRegister, RC will be returned.

Definition at line 224 of file SIRegisterInfo.cpp.

References isSGPRClass().

bool SIRegisterInfo::hasVGPRs ( const TargetRegisterClass * RC ) const