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drxk_hard.c
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1 /*
2  * drxk_hard: DRX-K DVB-C/T demodulator driver
3  *
4  * Copyright (C) 2010-2011 Digital Devices GmbH
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * version 2 only, as published by the Free Software Foundation.
9  *
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20  * 02110-1301, USA
21  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22  */
23 
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <linux/hardirq.h>
32 #include <asm/div64.h>
33 
34 #include "dvb_frontend.h"
35 #include "drxk.h"
36 #include "drxk_hard.h"
37 
38 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
39 static int PowerDownQAM(struct drxk_state *state);
40 static int SetDVBTStandard(struct drxk_state *state,
41  enum OperationMode oMode);
42 static int SetQAMStandard(struct drxk_state *state,
43  enum OperationMode oMode);
44 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
45  s32 tunerFreqOffset);
46 static int SetDVBTStandard(struct drxk_state *state,
47  enum OperationMode oMode);
48 static int DVBTStart(struct drxk_state *state);
49 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
50  s32 tunerFreqOffset);
51 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
52 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
53 static int SwitchAntennaToQAM(struct drxk_state *state);
54 static int SwitchAntennaToDVBT(struct drxk_state *state);
55 
56 static bool IsDVBT(struct drxk_state *state)
57 {
58  return state->m_OperationMode == OM_DVBT;
59 }
60 
61 static bool IsQAM(struct drxk_state *state)
62 {
63  return state->m_OperationMode == OM_QAM_ITU_A ||
64  state->m_OperationMode == OM_QAM_ITU_B ||
65  state->m_OperationMode == OM_QAM_ITU_C;
66 }
67 
68 bool IsA1WithPatchCode(struct drxk_state *state)
69 {
70  return state->m_DRXK_A1_PATCH_CODE;
71 }
72 
73 bool IsA1WithRomCode(struct drxk_state *state)
74 {
75  return state->m_DRXK_A1_ROM_CODE;
76 }
77 
78 #define NOA1ROM 0
79 
80 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
81 #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
82 
83 #define DEFAULT_MER_83 165
84 #define DEFAULT_MER_93 250
85 
86 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
87 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
88 #endif
89 
90 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
91 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
92 #endif
93 
94 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
95 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
96 
97 #ifndef DRXK_KI_RAGC_ATV
98 #define DRXK_KI_RAGC_ATV 4
99 #endif
100 #ifndef DRXK_KI_IAGC_ATV
101 #define DRXK_KI_IAGC_ATV 6
102 #endif
103 #ifndef DRXK_KI_DAGC_ATV
104 #define DRXK_KI_DAGC_ATV 7
105 #endif
106 
107 #ifndef DRXK_KI_RAGC_QAM
108 #define DRXK_KI_RAGC_QAM 3
109 #endif
110 #ifndef DRXK_KI_IAGC_QAM
111 #define DRXK_KI_IAGC_QAM 4
112 #endif
113 #ifndef DRXK_KI_DAGC_QAM
114 #define DRXK_KI_DAGC_QAM 7
115 #endif
116 #ifndef DRXK_KI_RAGC_DVBT
117 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
118 #endif
119 #ifndef DRXK_KI_IAGC_DVBT
120 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
121 #endif
122 #ifndef DRXK_KI_DAGC_DVBT
123 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
124 #endif
125 
126 #ifndef DRXK_AGC_DAC_OFFSET
127 #define DRXK_AGC_DAC_OFFSET (0x800)
128 #endif
129 
130 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
131 #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
132 #endif
133 
134 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
135 #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
136 #endif
137 
138 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
139 #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
140 #endif
141 
142 #ifndef DRXK_QAM_SYMBOLRATE_MAX
143 #define DRXK_QAM_SYMBOLRATE_MAX (7233000)
144 #endif
145 
146 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
147 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
148 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
149 #define DRXK_BL_ROM_OFFSET_TAPS_BG 24
150 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
151 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
152 #define DRXK_BL_ROM_OFFSET_TAPS_FM 48
153 #define DRXK_BL_ROM_OFFSET_UCODE 0
154 
155 #define DRXK_BLC_TIMEOUT 100
156 
157 #define DRXK_BLCC_NR_ELEMENTS_TAPS 2
158 #define DRXK_BLCC_NR_ELEMENTS_UCODE 6
159 
160 #define DRXK_BLDC_NR_ELEMENTS_TAPS 28
161 
162 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
163 #define DRXK_OFDM_NE_NOTCH_WIDTH (4)
164 #endif
165 
166 #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
167 #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
168 #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
169 #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
170 #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
171 
172 static unsigned int debug;
173 module_param(debug, int, 0644);
174 MODULE_PARM_DESC(debug, "enable debug messages");
175 
176 #define dprintk(level, fmt, arg...) do { \
177 if (debug >= level) \
178  printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \
179 } while (0)
180 
181 
182 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
183 {
184  u64 tmp64;
185 
186  tmp64 = (u64) a * (u64) b;
187  do_div(tmp64, c);
188 
189  return (u32) tmp64;
190 }
191 
192 inline u32 Frac28a(u32 a, u32 c)
193 {
194  int i = 0;
195  u32 Q1 = 0;
196  u32 R0 = 0;
197 
198  R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
199  Q1 = a / c; /* integer part, only the 4 least significant bits
200  will be visible in the result */
201 
202  /* division using radix 16, 7 nibbles in the result */
203  for (i = 0; i < 7; i++) {
204  Q1 = (Q1 << 4) | (R0 / c);
205  R0 = (R0 % c) << 4;
206  }
207  /* rounding */
208  if ((R0 >> 3) >= c)
209  Q1++;
210 
211  return Q1;
212 }
213 
214 static u32 Log10Times100(u32 x)
215 {
216  static const u8 scale = 15;
217  static const u8 indexWidth = 5;
218  u8 i = 0;
219  u32 y = 0;
220  u32 d = 0;
221  u32 k = 0;
222  u32 r = 0;
223  /*
224  log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
225  0 <= n < ((1<<INDEXWIDTH)+1)
226  */
227 
228  static const u32 log2lut[] = {
229  0, /* 0.000000 */
230  290941, /* 290941.300628 */
231  573196, /* 573196.476418 */
232  847269, /* 847269.179851 */
233  1113620, /* 1113620.489452 */
234  1372674, /* 1372673.576986 */
235  1624818, /* 1624817.752104 */
236  1870412, /* 1870411.981536 */
237  2109788, /* 2109787.962654 */
238  2343253, /* 2343252.817465 */
239  2571091, /* 2571091.461923 */
240  2793569, /* 2793568.696416 */
241  3010931, /* 3010931.055901 */
242  3223408, /* 3223408.452106 */
243  3431216, /* 3431215.635215 */
244  3634553, /* 3634553.498355 */
245  3833610, /* 3833610.244726 */
246  4028562, /* 4028562.434393 */
247  4219576, /* 4219575.925308 */
248  4406807, /* 4406806.721144 */
249  4590402, /* 4590401.736809 */
250  4770499, /* 4770499.491025 */
251  4947231, /* 4947230.734179 */
252  5120719, /* 5120719.018555 */
253  5291081, /* 5291081.217197 */
254  5458428, /* 5458427.996830 */
255  5622864, /* 5622864.249668 */
256  5784489, /* 5784489.488298 */
257  5943398, /* 5943398.207380 */
258  6099680, /* 6099680.215452 */
259  6253421, /* 6253420.939751 */
260  6404702, /* 6404701.706649 */
261  6553600, /* 6553600.000000 */
262  };
263 
264 
265  if (x == 0)
266  return 0;
267 
268  /* Scale x (normalize) */
269  /* computing y in log(x/y) = log(x) - log(y) */
270  if ((x & ((0xffffffff) << (scale + 1))) == 0) {
271  for (k = scale; k > 0; k--) {
272  if (x & (((u32) 1) << scale))
273  break;
274  x <<= 1;
275  }
276  } else {
277  for (k = scale; k < 31; k++) {
278  if ((x & (((u32) (-1)) << (scale + 1))) == 0)
279  break;
280  x >>= 1;
281  }
282  }
283  /*
284  Now x has binary point between bit[scale] and bit[scale-1]
285  and 1.0 <= x < 2.0 */
286 
287  /* correction for divison: log(x) = log(x/y)+log(y) */
288  y = k * ((((u32) 1) << scale) * 200);
289 
290  /* remove integer part */
291  x &= ((((u32) 1) << scale) - 1);
292  /* get index */
293  i = (u8) (x >> (scale - indexWidth));
294  /* compute delta (x - a) */
295  d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
296  /* compute log, multiplication (d* (..)) must be within range ! */
297  y += log2lut[i] +
298  ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
299  /* Conver to log10() */
300  y /= 108853; /* (log2(10) << scale) */
301  r = (y >> 1);
302  /* rounding */
303  if (y & ((u32) 1))
304  r++;
305  return r;
306 }
307 
308 /****************************************************************************/
309 /* I2C **********************************************************************/
310 /****************************************************************************/
311 
312 static int drxk_i2c_lock(struct drxk_state *state)
313 {
314  i2c_lock_adapter(state->i2c);
315  state->drxk_i2c_exclusive_lock = true;
316 
317  return 0;
318 }
319 
320 static void drxk_i2c_unlock(struct drxk_state *state)
321 {
322  if (!state->drxk_i2c_exclusive_lock)
323  return;
324 
325  i2c_unlock_adapter(state->i2c);
326  state->drxk_i2c_exclusive_lock = false;
327 }
328 
329 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
330  unsigned len)
331 {
332  if (state->drxk_i2c_exclusive_lock)
333  return __i2c_transfer(state->i2c, msgs, len);
334  else
335  return i2c_transfer(state->i2c, msgs, len);
336 }
337 
338 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
339 {
340  struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
341  .buf = val, .len = 1}
342  };
343 
344  return drxk_i2c_transfer(state, msgs, 1);
345 }
346 
347 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
348 {
349  int status;
350  struct i2c_msg msg = {
351  .addr = adr, .flags = 0, .buf = data, .len = len };
352 
353  dprintk(3, ":");
354  if (debug > 2) {
355  int i;
356  for (i = 0; i < len; i++)
357  printk(KERN_CONT " %02x", data[i]);
358  printk(KERN_CONT "\n");
359  }
360  status = drxk_i2c_transfer(state, &msg, 1);
361  if (status >= 0 && status != 1)
362  status = -EIO;
363 
364  if (status < 0)
365  printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
366 
367  return status;
368 }
369 
370 static int i2c_read(struct drxk_state *state,
371  u8 adr, u8 *msg, int len, u8 *answ, int alen)
372 {
373  int status;
374  struct i2c_msg msgs[2] = {
375  {.addr = adr, .flags = 0,
376  .buf = msg, .len = len},
377  {.addr = adr, .flags = I2C_M_RD,
378  .buf = answ, .len = alen}
379  };
380 
381  status = drxk_i2c_transfer(state, msgs, 2);
382  if (status != 2) {
383  if (debug > 2)
384  printk(KERN_CONT ": ERROR!\n");
385  if (status >= 0)
386  status = -EIO;
387 
388  printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
389  return status;
390  }
391  if (debug > 2) {
392  int i;
393  dprintk(2, ": read from");
394  for (i = 0; i < len; i++)
395  printk(KERN_CONT " %02x", msg[i]);
396  printk(KERN_CONT ", value = ");
397  for (i = 0; i < alen; i++)
398  printk(KERN_CONT " %02x", answ[i]);
399  printk(KERN_CONT "\n");
400  }
401  return 0;
402 }
403 
404 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
405 {
406  int status;
407  u8 adr = state->demod_address, mm1[4], mm2[2], len;
408 
409  if (state->single_master)
410  flags |= 0xC0;
411 
412  if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
413  mm1[0] = (((reg << 1) & 0xFF) | 0x01);
414  mm1[1] = ((reg >> 16) & 0xFF);
415  mm1[2] = ((reg >> 24) & 0xFF) | flags;
416  mm1[3] = ((reg >> 7) & 0xFF);
417  len = 4;
418  } else {
419  mm1[0] = ((reg << 1) & 0xFF);
420  mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
421  len = 2;
422  }
423  dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
424  status = i2c_read(state, adr, mm1, len, mm2, 2);
425  if (status < 0)
426  return status;
427  if (data)
428  *data = mm2[0] | (mm2[1] << 8);
429 
430  return 0;
431 }
432 
433 static int read16(struct drxk_state *state, u32 reg, u16 *data)
434 {
435  return read16_flags(state, reg, data, 0);
436 }
437 
438 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
439 {
440  int status;
441  u8 adr = state->demod_address, mm1[4], mm2[4], len;
442 
443  if (state->single_master)
444  flags |= 0xC0;
445 
446  if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
447  mm1[0] = (((reg << 1) & 0xFF) | 0x01);
448  mm1[1] = ((reg >> 16) & 0xFF);
449  mm1[2] = ((reg >> 24) & 0xFF) | flags;
450  mm1[3] = ((reg >> 7) & 0xFF);
451  len = 4;
452  } else {
453  mm1[0] = ((reg << 1) & 0xFF);
454  mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
455  len = 2;
456  }
457  dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
458  status = i2c_read(state, adr, mm1, len, mm2, 4);
459  if (status < 0)
460  return status;
461  if (data)
462  *data = mm2[0] | (mm2[1] << 8) |
463  (mm2[2] << 16) | (mm2[3] << 24);
464 
465  return 0;
466 }
467 
468 static int read32(struct drxk_state *state, u32 reg, u32 *data)
469 {
470  return read32_flags(state, reg, data, 0);
471 }
472 
473 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
474 {
475  u8 adr = state->demod_address, mm[6], len;
476 
477  if (state->single_master)
478  flags |= 0xC0;
479  if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
480  mm[0] = (((reg << 1) & 0xFF) | 0x01);
481  mm[1] = ((reg >> 16) & 0xFF);
482  mm[2] = ((reg >> 24) & 0xFF) | flags;
483  mm[3] = ((reg >> 7) & 0xFF);
484  len = 4;
485  } else {
486  mm[0] = ((reg << 1) & 0xFF);
487  mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
488  len = 2;
489  }
490  mm[len] = data & 0xff;
491  mm[len + 1] = (data >> 8) & 0xff;
492 
493  dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
494  return i2c_write(state, adr, mm, len + 2);
495 }
496 
497 static int write16(struct drxk_state *state, u32 reg, u16 data)
498 {
499  return write16_flags(state, reg, data, 0);
500 }
501 
502 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
503 {
504  u8 adr = state->demod_address, mm[8], len;
505 
506  if (state->single_master)
507  flags |= 0xC0;
508  if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
509  mm[0] = (((reg << 1) & 0xFF) | 0x01);
510  mm[1] = ((reg >> 16) & 0xFF);
511  mm[2] = ((reg >> 24) & 0xFF) | flags;
512  mm[3] = ((reg >> 7) & 0xFF);
513  len = 4;
514  } else {
515  mm[0] = ((reg << 1) & 0xFF);
516  mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
517  len = 2;
518  }
519  mm[len] = data & 0xff;
520  mm[len + 1] = (data >> 8) & 0xff;
521  mm[len + 2] = (data >> 16) & 0xff;
522  mm[len + 3] = (data >> 24) & 0xff;
523  dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
524 
525  return i2c_write(state, adr, mm, len + 4);
526 }
527 
528 static int write32(struct drxk_state *state, u32 reg, u32 data)
529 {
530  return write32_flags(state, reg, data, 0);
531 }
532 
533 static int write_block(struct drxk_state *state, u32 Address,
534  const int BlockSize, const u8 pBlock[])
535 {
536  int status = 0, BlkSize = BlockSize;
537  u8 Flags = 0;
538 
539  if (state->single_master)
540  Flags |= 0xC0;
541 
542  while (BlkSize > 0) {
543  int Chunk = BlkSize > state->m_ChunkSize ?
544  state->m_ChunkSize : BlkSize;
545  u8 *AdrBuf = &state->Chunk[0];
546  u32 AdrLength = 0;
547 
548  if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
549  AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
550  AdrBuf[1] = ((Address >> 16) & 0xFF);
551  AdrBuf[2] = ((Address >> 24) & 0xFF);
552  AdrBuf[3] = ((Address >> 7) & 0xFF);
553  AdrBuf[2] |= Flags;
554  AdrLength = 4;
555  if (Chunk == state->m_ChunkSize)
556  Chunk -= 2;
557  } else {
558  AdrBuf[0] = ((Address << 1) & 0xFF);
559  AdrBuf[1] = (((Address >> 16) & 0x0F) |
560  ((Address >> 18) & 0xF0));
561  AdrLength = 2;
562  }
563  memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
564  dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
565  if (debug > 1) {
566  int i;
567  if (pBlock)
568  for (i = 0; i < Chunk; i++)
569  printk(KERN_CONT " %02x", pBlock[i]);
570  printk(KERN_CONT "\n");
571  }
572  status = i2c_write(state, state->demod_address,
573  &state->Chunk[0], Chunk + AdrLength);
574  if (status < 0) {
575  printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
576  __func__, Address);
577  break;
578  }
579  pBlock += Chunk;
580  Address += (Chunk >> 1);
581  BlkSize -= Chunk;
582  }
583  return status;
584 }
585 
586 #ifndef DRXK_MAX_RETRIES_POWERUP
587 #define DRXK_MAX_RETRIES_POWERUP 20
588 #endif
589 
590 int PowerUpDevice(struct drxk_state *state)
591 {
592  int status;
593  u8 data = 0;
594  u16 retryCount = 0;
595 
596  dprintk(1, "\n");
597 
598  status = i2c_read1(state, state->demod_address, &data);
599  if (status < 0) {
600  do {
601  data = 0;
602  status = i2c_write(state, state->demod_address,
603  &data, 1);
604  msleep(10);
605  retryCount++;
606  if (status < 0)
607  continue;
608  status = i2c_read1(state, state->demod_address,
609  &data);
610  } while (status < 0 &&
611  (retryCount < DRXK_MAX_RETRIES_POWERUP));
612  if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
613  goto error;
614  }
615 
616  /* Make sure all clk domains are active */
617  status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
618  if (status < 0)
619  goto error;
620  status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
621  if (status < 0)
622  goto error;
623  /* Enable pll lock tests */
624  status = write16(state, SIO_CC_PLL_LOCK__A, 1);
625  if (status < 0)
626  goto error;
627 
628  state->m_currentPowerMode = DRX_POWER_UP;
629 
630 error:
631  if (status < 0)
632  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
633 
634  return status;
635 }
636 
637 
638 static int init_state(struct drxk_state *state)
639 {
640  /*
641  * FIXME: most (all?) of the values bellow should be moved into
642  * struct drxk_config, as they are probably board-specific
643  */
644  u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
645  u32 ulVSBIfAgcOutputLevel = 0;
646  u32 ulVSBIfAgcMinLevel = 0;
647  u32 ulVSBIfAgcMaxLevel = 0x7FFF;
648  u32 ulVSBIfAgcSpeed = 3;
649 
650  u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
651  u32 ulVSBRfAgcOutputLevel = 0;
652  u32 ulVSBRfAgcMinLevel = 0;
653  u32 ulVSBRfAgcMaxLevel = 0x7FFF;
654  u32 ulVSBRfAgcSpeed = 3;
655  u32 ulVSBRfAgcTop = 9500;
656  u32 ulVSBRfAgcCutOffCurrent = 4000;
657 
658  u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
659  u32 ulATVIfAgcOutputLevel = 0;
660  u32 ulATVIfAgcMinLevel = 0;
661  u32 ulATVIfAgcMaxLevel = 0;
662  u32 ulATVIfAgcSpeed = 3;
663 
664  u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
665  u32 ulATVRfAgcOutputLevel = 0;
666  u32 ulATVRfAgcMinLevel = 0;
667  u32 ulATVRfAgcMaxLevel = 0;
668  u32 ulATVRfAgcTop = 9500;
669  u32 ulATVRfAgcCutOffCurrent = 4000;
670  u32 ulATVRfAgcSpeed = 3;
671 
672  u32 ulQual83 = DEFAULT_MER_83;
673  u32 ulQual93 = DEFAULT_MER_93;
674 
675  u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
676  u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
677 
678  /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
679  /* io_pad_cfg_mode output mode is drive always */
680  /* io_pad_cfg_drive is set to power 2 (23 mA) */
681  u32 ulGPIOCfg = 0x0113;
682  u32 ulInvertTSClock = 0;
683  u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
684  u32 ulDVBTBitrate = 50000000;
685  u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
686 
687  u32 ulInsertRSByte = 0;
688 
689  u32 ulRfMirror = 1;
690  u32 ulPowerDown = 0;
691 
692  dprintk(1, "\n");
693 
694  state->m_hasLNA = false;
695  state->m_hasDVBT = false;
696  state->m_hasDVBC = false;
697  state->m_hasATV = false;
698  state->m_hasOOB = false;
699  state->m_hasAudio = false;
700 
701  if (!state->m_ChunkSize)
702  state->m_ChunkSize = 124;
703 
704  state->m_oscClockFreq = 0;
705  state->m_smartAntInverted = false;
706  state->m_bPDownOpenBridge = false;
707 
708  /* real system clock frequency in kHz */
709  state->m_sysClockFreq = 151875;
710  /* Timing div, 250ns/Psys */
711  /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
712  state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
713  HI_I2C_DELAY) / 1000;
714  /* Clipping */
715  if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
716  state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
717  state->m_HICfgWakeUpKey = (state->demod_address << 1);
718  /* port/bridge/power down ctrl */
719  state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
720 
721  state->m_bPowerDown = (ulPowerDown != 0);
722 
723  state->m_DRXK_A1_PATCH_CODE = false;
724  state->m_DRXK_A1_ROM_CODE = false;
725  state->m_DRXK_A2_ROM_CODE = false;
726  state->m_DRXK_A3_ROM_CODE = false;
727  state->m_DRXK_A2_PATCH_CODE = false;
728  state->m_DRXK_A3_PATCH_CODE = false;
729 
730  /* Init AGC and PGA parameters */
731  /* VSB IF */
732  state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
733  state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
734  state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
735  state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
736  state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
737  state->m_vsbPgaCfg = 140;
738 
739  /* VSB RF */
740  state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
741  state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
742  state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
743  state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
744  state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
745  state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
746  state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
747  state->m_vsbPreSawCfg.reference = 0x07;
748  state->m_vsbPreSawCfg.usePreSaw = true;
749 
750  state->m_Quality83percent = DEFAULT_MER_83;
751  state->m_Quality93percent = DEFAULT_MER_93;
752  if (ulQual93 <= 500 && ulQual83 < ulQual93) {
753  state->m_Quality83percent = ulQual83;
754  state->m_Quality93percent = ulQual93;
755  }
756 
757  /* ATV IF */
758  state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
759  state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
760  state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
761  state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
762  state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
763 
764  /* ATV RF */
765  state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
766  state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
767  state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
768  state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
769  state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
770  state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
771  state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
772  state->m_atvPreSawCfg.reference = 0x04;
773  state->m_atvPreSawCfg.usePreSaw = true;
774 
775 
776  /* DVBT RF */
777  state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
778  state->m_dvbtRfAgcCfg.outputLevel = 0;
779  state->m_dvbtRfAgcCfg.minOutputLevel = 0;
780  state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
781  state->m_dvbtRfAgcCfg.top = 0x2100;
782  state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
783  state->m_dvbtRfAgcCfg.speed = 1;
784 
785 
786  /* DVBT IF */
787  state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
788  state->m_dvbtIfAgcCfg.outputLevel = 0;
789  state->m_dvbtIfAgcCfg.minOutputLevel = 0;
790  state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
791  state->m_dvbtIfAgcCfg.top = 13424;
792  state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
793  state->m_dvbtIfAgcCfg.speed = 3;
794  state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
795  state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
796  /* state->m_dvbtPgaCfg = 140; */
797 
798  state->m_dvbtPreSawCfg.reference = 4;
799  state->m_dvbtPreSawCfg.usePreSaw = false;
800 
801  /* QAM RF */
802  state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
803  state->m_qamRfAgcCfg.outputLevel = 0;
804  state->m_qamRfAgcCfg.minOutputLevel = 6023;
805  state->m_qamRfAgcCfg.maxOutputLevel = 27000;
806  state->m_qamRfAgcCfg.top = 0x2380;
807  state->m_qamRfAgcCfg.cutOffCurrent = 4000;
808  state->m_qamRfAgcCfg.speed = 3;
809 
810  /* QAM IF */
811  state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
812  state->m_qamIfAgcCfg.outputLevel = 0;
813  state->m_qamIfAgcCfg.minOutputLevel = 0;
814  state->m_qamIfAgcCfg.maxOutputLevel = 9000;
815  state->m_qamIfAgcCfg.top = 0x0511;
816  state->m_qamIfAgcCfg.cutOffCurrent = 0;
817  state->m_qamIfAgcCfg.speed = 3;
818  state->m_qamIfAgcCfg.IngainTgtMax = 5119;
819  state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
820 
821  state->m_qamPgaCfg = 140;
822  state->m_qamPreSawCfg.reference = 4;
823  state->m_qamPreSawCfg.usePreSaw = false;
824 
825  state->m_OperationMode = OM_NONE;
826  state->m_DrxkState = DRXK_UNINITIALIZED;
827 
828  /* MPEG output configuration */
829  state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
830  state->m_insertRSByte = false; /* If TRUE; insert RS byte */
831  state->m_invertDATA = false; /* If TRUE; invert DATA signals */
832  state->m_invertERR = false; /* If TRUE; invert ERR signal */
833  state->m_invertSTR = false; /* If TRUE; invert STR signals */
834  state->m_invertVAL = false; /* If TRUE; invert VAL signals */
835  state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
836 
837  /* If TRUE; static MPEG clockrate will be used;
838  otherwise clockrate will adapt to the bitrate of the TS */
839 
840  state->m_DVBTBitrate = ulDVBTBitrate;
841  state->m_DVBCBitrate = ulDVBCBitrate;
842 
843  state->m_TSDataStrength = (ulTSDataStrength & 0x07);
844 
845  /* Maximum bitrate in b/s in case static clockrate is selected */
846  state->m_mpegTsStaticBitrate = 19392658;
847  state->m_disableTEIhandling = false;
848 
849  if (ulInsertRSByte)
850  state->m_insertRSByte = true;
851 
852  state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
853  if (ulMpegLockTimeOut < 10000)
854  state->m_MpegLockTimeOut = ulMpegLockTimeOut;
855  state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
856  if (ulDemodLockTimeOut < 10000)
857  state->m_DemodLockTimeOut = ulDemodLockTimeOut;
858 
859  /* QAM defaults */
860  state->m_Constellation = DRX_CONSTELLATION_AUTO;
861  state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
862  state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */
863  state->m_fecRsPrescale = 1;
864 
865  state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
866  state->m_agcFastClipCtrlDelay = 0;
867 
868  state->m_GPIOCfg = (ulGPIOCfg);
869 
870  state->m_bPowerDown = false;
871  state->m_currentPowerMode = DRX_POWER_DOWN;
872 
873  state->m_rfmirror = (ulRfMirror == 0);
874  state->m_IfAgcPol = false;
875  return 0;
876 }
877 
878 static int DRXX_Open(struct drxk_state *state)
879 {
880  int status = 0;
881  u32 jtag = 0;
882  u16 bid = 0;
883  u16 key = 0;
884 
885  dprintk(1, "\n");
886  /* stop lock indicator process */
887  status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
888  if (status < 0)
889  goto error;
890  /* Check device id */
891  status = read16(state, SIO_TOP_COMM_KEY__A, &key);
892  if (status < 0)
893  goto error;
894  status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
895  if (status < 0)
896  goto error;
897  status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
898  if (status < 0)
899  goto error;
900  status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
901  if (status < 0)
902  goto error;
903  status = write16(state, SIO_TOP_COMM_KEY__A, key);
904 error:
905  if (status < 0)
906  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
907  return status;
908 }
909 
910 static int GetDeviceCapabilities(struct drxk_state *state)
911 {
912  u16 sioPdrOhwCfg = 0;
913  u32 sioTopJtagidLo = 0;
914  int status;
915  const char *spin = "";
916 
917  dprintk(1, "\n");
918 
919  /* driver 0.9.0 */
920  /* stop lock indicator process */
921  status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
922  if (status < 0)
923  goto error;
924  status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
925  if (status < 0)
926  goto error;
927  status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
928  if (status < 0)
929  goto error;
930  status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
931  if (status < 0)
932  goto error;
933 
934  switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
935  case 0:
936  /* ignore (bypass ?) */
937  break;
938  case 1:
939  /* 27 MHz */
940  state->m_oscClockFreq = 27000;
941  break;
942  case 2:
943  /* 20.25 MHz */
944  state->m_oscClockFreq = 20250;
945  break;
946  case 3:
947  /* 4 MHz */
948  state->m_oscClockFreq = 20250;
949  break;
950  default:
951  printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n");
952  return -EINVAL;
953  }
954  /*
955  Determine device capabilities
956  Based on pinning v14
957  */
958  status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
959  if (status < 0)
960  goto error;
961 
962  printk(KERN_INFO "drxk: status = 0x%08x\n", sioTopJtagidLo);
963 
964  /* driver 0.9.0 */
965  switch ((sioTopJtagidLo >> 29) & 0xF) {
966  case 0:
967  state->m_deviceSpin = DRXK_SPIN_A1;
968  spin = "A1";
969  break;
970  case 2:
971  state->m_deviceSpin = DRXK_SPIN_A2;
972  spin = "A2";
973  break;
974  case 3:
975  state->m_deviceSpin = DRXK_SPIN_A3;
976  spin = "A3";
977  break;
978  default:
979  state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
980  status = -EINVAL;
981  printk(KERN_ERR "drxk: Spin %d unknown\n",
982  (sioTopJtagidLo >> 29) & 0xF);
983  goto error2;
984  }
985  switch ((sioTopJtagidLo >> 12) & 0xFF) {
986  case 0x13:
987  /* typeId = DRX3913K_TYPE_ID */
988  state->m_hasLNA = false;
989  state->m_hasOOB = false;
990  state->m_hasATV = false;
991  state->m_hasAudio = false;
992  state->m_hasDVBT = true;
993  state->m_hasDVBC = true;
994  state->m_hasSAWSW = true;
995  state->m_hasGPIO2 = false;
996  state->m_hasGPIO1 = false;
997  state->m_hasIRQN = false;
998  break;
999  case 0x15:
1000  /* typeId = DRX3915K_TYPE_ID */
1001  state->m_hasLNA = false;
1002  state->m_hasOOB = false;
1003  state->m_hasATV = true;
1004  state->m_hasAudio = false;
1005  state->m_hasDVBT = true;
1006  state->m_hasDVBC = false;
1007  state->m_hasSAWSW = true;
1008  state->m_hasGPIO2 = true;
1009  state->m_hasGPIO1 = true;
1010  state->m_hasIRQN = false;
1011  break;
1012  case 0x16:
1013  /* typeId = DRX3916K_TYPE_ID */
1014  state->m_hasLNA = false;
1015  state->m_hasOOB = false;
1016  state->m_hasATV = true;
1017  state->m_hasAudio = false;
1018  state->m_hasDVBT = true;
1019  state->m_hasDVBC = false;
1020  state->m_hasSAWSW = true;
1021  state->m_hasGPIO2 = true;
1022  state->m_hasGPIO1 = true;
1023  state->m_hasIRQN = false;
1024  break;
1025  case 0x18:
1026  /* typeId = DRX3918K_TYPE_ID */
1027  state->m_hasLNA = false;
1028  state->m_hasOOB = false;
1029  state->m_hasATV = true;
1030  state->m_hasAudio = true;
1031  state->m_hasDVBT = true;
1032  state->m_hasDVBC = false;
1033  state->m_hasSAWSW = true;
1034  state->m_hasGPIO2 = true;
1035  state->m_hasGPIO1 = true;
1036  state->m_hasIRQN = false;
1037  break;
1038  case 0x21:
1039  /* typeId = DRX3921K_TYPE_ID */
1040  state->m_hasLNA = false;
1041  state->m_hasOOB = false;
1042  state->m_hasATV = true;
1043  state->m_hasAudio = true;
1044  state->m_hasDVBT = true;
1045  state->m_hasDVBC = true;
1046  state->m_hasSAWSW = true;
1047  state->m_hasGPIO2 = true;
1048  state->m_hasGPIO1 = true;
1049  state->m_hasIRQN = false;
1050  break;
1051  case 0x23:
1052  /* typeId = DRX3923K_TYPE_ID */
1053  state->m_hasLNA = false;
1054  state->m_hasOOB = false;
1055  state->m_hasATV = true;
1056  state->m_hasAudio = true;
1057  state->m_hasDVBT = true;
1058  state->m_hasDVBC = true;
1059  state->m_hasSAWSW = true;
1060  state->m_hasGPIO2 = true;
1061  state->m_hasGPIO1 = true;
1062  state->m_hasIRQN = false;
1063  break;
1064  case 0x25:
1065  /* typeId = DRX3925K_TYPE_ID */
1066  state->m_hasLNA = false;
1067  state->m_hasOOB = false;
1068  state->m_hasATV = true;
1069  state->m_hasAudio = true;
1070  state->m_hasDVBT = true;
1071  state->m_hasDVBC = true;
1072  state->m_hasSAWSW = true;
1073  state->m_hasGPIO2 = true;
1074  state->m_hasGPIO1 = true;
1075  state->m_hasIRQN = false;
1076  break;
1077  case 0x26:
1078  /* typeId = DRX3926K_TYPE_ID */
1079  state->m_hasLNA = false;
1080  state->m_hasOOB = false;
1081  state->m_hasATV = true;
1082  state->m_hasAudio = false;
1083  state->m_hasDVBT = true;
1084  state->m_hasDVBC = true;
1085  state->m_hasSAWSW = true;
1086  state->m_hasGPIO2 = true;
1087  state->m_hasGPIO1 = true;
1088  state->m_hasIRQN = false;
1089  break;
1090  default:
1091  printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
1092  ((sioTopJtagidLo >> 12) & 0xFF));
1093  status = -EINVAL;
1094  goto error2;
1095  }
1096 
1097  printk(KERN_INFO
1098  "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1099  ((sioTopJtagidLo >> 12) & 0xFF), spin,
1100  state->m_oscClockFreq / 1000,
1101  state->m_oscClockFreq % 1000);
1102 
1103 error:
1104  if (status < 0)
1105  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1106 
1107 error2:
1108  return status;
1109 }
1110 
1111 static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1112 {
1113  int status;
1114  bool powerdown_cmd;
1115 
1116  dprintk(1, "\n");
1117 
1118  /* Write command */
1119  status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1120  if (status < 0)
1121  goto error;
1122  if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1123  msleep(1);
1124 
1125  powerdown_cmd =
1126  (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1127  ((state->m_HICfgCtrl) &
1128  SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1129  SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1130  if (powerdown_cmd == false) {
1131  /* Wait until command rdy */
1132  u32 retryCount = 0;
1133  u16 waitCmd;
1134 
1135  do {
1136  msleep(1);
1137  retryCount += 1;
1138  status = read16(state, SIO_HI_RA_RAM_CMD__A,
1139  &waitCmd);
1140  } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1141  && (waitCmd != 0));
1142  if (status < 0)
1143  goto error;
1144  status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
1145  }
1146 error:
1147  if (status < 0)
1148  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1149 
1150  return status;
1151 }
1152 
1153 static int HI_CfgCommand(struct drxk_state *state)
1154 {
1155  int status;
1156 
1157  dprintk(1, "\n");
1158 
1159  mutex_lock(&state->mutex);
1160 
1161  status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1162  if (status < 0)
1163  goto error;
1164  status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1165  if (status < 0)
1166  goto error;
1167  status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1168  if (status < 0)
1169  goto error;
1170  status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1171  if (status < 0)
1172  goto error;
1173  status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1174  if (status < 0)
1175  goto error;
1176  status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1177  if (status < 0)
1178  goto error;
1179  status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1180  if (status < 0)
1181  goto error;
1182 
1183  state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1184 error:
1185  mutex_unlock(&state->mutex);
1186  if (status < 0)
1187  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1188  return status;
1189 }
1190 
1191 static int InitHI(struct drxk_state *state)
1192 {
1193  dprintk(1, "\n");
1194 
1195  state->m_HICfgWakeUpKey = (state->demod_address << 1);
1196  state->m_HICfgTimeout = 0x96FF;
1197  /* port/bridge/power down ctrl */
1198  state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1199 
1200  return HI_CfgCommand(state);
1201 }
1202 
1203 static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1204 {
1205  int status = -1;
1206  u16 sioPdrMclkCfg = 0;
1207  u16 sioPdrMdxCfg = 0;
1208  u16 err_cfg = 0;
1209 
1210  dprintk(1, ": mpeg %s, %s mode\n",
1211  mpegEnable ? "enable" : "disable",
1212  state->m_enableParallel ? "parallel" : "serial");
1213 
1214  /* stop lock indicator process */
1215  status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1216  if (status < 0)
1217  goto error;
1218 
1219  /* MPEG TS pad configuration */
1220  status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1221  if (status < 0)
1222  goto error;
1223 
1224  if (mpegEnable == false) {
1225  /* Set MPEG TS pads to inputmode */
1226  status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1227  if (status < 0)
1228  goto error;
1229  status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1230  if (status < 0)
1231  goto error;
1232  status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1233  if (status < 0)
1234  goto error;
1235  status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1236  if (status < 0)
1237  goto error;
1238  status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1239  if (status < 0)
1240  goto error;
1241  status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1242  if (status < 0)
1243  goto error;
1244  status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1245  if (status < 0)
1246  goto error;
1247  status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1248  if (status < 0)
1249  goto error;
1250  status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1251  if (status < 0)
1252  goto error;
1253  status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1254  if (status < 0)
1255  goto error;
1256  status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1257  if (status < 0)
1258  goto error;
1259  status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1260  if (status < 0)
1261  goto error;
1262  } else {
1263  /* Enable MPEG output */
1264  sioPdrMdxCfg =
1265  ((state->m_TSDataStrength <<
1266  SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1267  sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1268  SIO_PDR_MCLK_CFG_DRIVE__B) |
1269  0x0003);
1270 
1271  status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1272  if (status < 0)
1273  goto error;
1274 
1275  if (state->enable_merr_cfg)
1276  err_cfg = sioPdrMdxCfg;
1277 
1278  status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1279  if (status < 0)
1280  goto error;
1281  status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1282  if (status < 0)
1283  goto error;
1284 
1285  if (state->m_enableParallel == true) {
1286  /* paralel -> enable MD1 to MD7 */
1287  status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1288  if (status < 0)
1289  goto error;
1290  status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1291  if (status < 0)
1292  goto error;
1293  status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1294  if (status < 0)
1295  goto error;
1296  status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1297  if (status < 0)
1298  goto error;
1299  status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1300  if (status < 0)
1301  goto error;
1302  status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1303  if (status < 0)
1304  goto error;
1305  status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1306  if (status < 0)
1307  goto error;
1308  } else {
1309  sioPdrMdxCfg = ((state->m_TSDataStrength <<
1310  SIO_PDR_MD0_CFG_DRIVE__B)
1311  | 0x0003);
1312  /* serial -> disable MD1 to MD7 */
1313  status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1314  if (status < 0)
1315  goto error;
1316  status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1317  if (status < 0)
1318  goto error;
1319  status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1320  if (status < 0)
1321  goto error;
1322  status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1323  if (status < 0)
1324  goto error;
1325  status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1326  if (status < 0)
1327  goto error;
1328  status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1329  if (status < 0)
1330  goto error;
1331  status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1332  if (status < 0)
1333  goto error;
1334  }
1335  status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1336  if (status < 0)
1337  goto error;
1338  status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1339  if (status < 0)
1340  goto error;
1341  }
1342  /* Enable MB output over MPEG pads and ctl input */
1343  status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1344  if (status < 0)
1345  goto error;
1346  /* Write nomagic word to enable pdr reg write */
1347  status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1348 error:
1349  if (status < 0)
1350  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1351  return status;
1352 }
1353 
1354 static int MPEGTSDisable(struct drxk_state *state)
1355 {
1356  dprintk(1, "\n");
1357 
1358  return MPEGTSConfigurePins(state, false);
1359 }
1360 
1361 static int BLChainCmd(struct drxk_state *state,
1362  u16 romOffset, u16 nrOfElements, u32 timeOut)
1363 {
1364  u16 blStatus = 0;
1365  int status;
1366  unsigned long end;
1367 
1368  dprintk(1, "\n");
1369  mutex_lock(&state->mutex);
1370  status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1371  if (status < 0)
1372  goto error;
1373  status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1374  if (status < 0)
1375  goto error;
1376  status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1377  if (status < 0)
1378  goto error;
1379  status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1380  if (status < 0)
1381  goto error;
1382 
1383  end = jiffies + msecs_to_jiffies(timeOut);
1384  do {
1385  msleep(1);
1386  status = read16(state, SIO_BL_STATUS__A, &blStatus);
1387  if (status < 0)
1388  goto error;
1389  } while ((blStatus == 0x1) &&
1390  ((time_is_after_jiffies(end))));
1391 
1392  if (blStatus == 0x1) {
1393  printk(KERN_ERR "drxk: SIO not ready\n");
1394  status = -EINVAL;
1395  goto error2;
1396  }
1397 error:
1398  if (status < 0)
1399  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1400 error2:
1401  mutex_unlock(&state->mutex);
1402  return status;
1403 }
1404 
1405 
1406 static int DownloadMicrocode(struct drxk_state *state,
1407  const u8 pMCImage[], u32 Length)
1408 {
1409  const u8 *pSrc = pMCImage;
1410  u32 Address;
1411  u16 nBlocks;
1412  u16 BlockSize;
1413  u32 offset = 0;
1414  u32 i;
1415  int status = 0;
1416 
1417  dprintk(1, "\n");
1418 
1419  /* down the drain (we don't care about MAGIC_WORD) */
1420 #if 0
1421  /* For future reference */
1422  Drain = (pSrc[0] << 8) | pSrc[1];
1423 #endif
1424  pSrc += sizeof(u16);
1425  offset += sizeof(u16);
1426  nBlocks = (pSrc[0] << 8) | pSrc[1];
1427  pSrc += sizeof(u16);
1428  offset += sizeof(u16);
1429 
1430  for (i = 0; i < nBlocks; i += 1) {
1431  Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
1432  (pSrc[2] << 8) | pSrc[3];
1433  pSrc += sizeof(u32);
1434  offset += sizeof(u32);
1435 
1436  BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
1437  pSrc += sizeof(u16);
1438  offset += sizeof(u16);
1439 
1440 #if 0
1441  /* For future reference */
1442  Flags = (pSrc[0] << 8) | pSrc[1];
1443 #endif
1444  pSrc += sizeof(u16);
1445  offset += sizeof(u16);
1446 
1447 #if 0
1448  /* For future reference */
1449  BlockCRC = (pSrc[0] << 8) | pSrc[1];
1450 #endif
1451  pSrc += sizeof(u16);
1452  offset += sizeof(u16);
1453 
1454  if (offset + BlockSize > Length) {
1455  printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1456  return -EINVAL;
1457  }
1458 
1459  status = write_block(state, Address, BlockSize, pSrc);
1460  if (status < 0) {
1461  printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
1462  break;
1463  }
1464  pSrc += BlockSize;
1465  offset += BlockSize;
1466  }
1467  return status;
1468 }
1469 
1470 static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1471 {
1472  int status;
1473  u16 data = 0;
1474  u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1475  u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1476  unsigned long end;
1477 
1478  dprintk(1, "\n");
1479 
1480  if (enable == false) {
1481  desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1482  desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1483  }
1484 
1485  status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1486  if (status >= 0 && data == desiredStatus) {
1487  /* tokenring already has correct status */
1488  return status;
1489  }
1490  /* Disable/enable dvbt tokenring bridge */
1491  status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1492 
1493  end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1494  do {
1495  status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1496  if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
1497  break;
1498  msleep(1);
1499  } while (1);
1500  if (data != desiredStatus) {
1501  printk(KERN_ERR "drxk: SIO not ready\n");
1502  return -EINVAL;
1503  }
1504  return status;
1505 }
1506 
1507 static int MPEGTSStop(struct drxk_state *state)
1508 {
1509  int status = 0;
1510  u16 fecOcSncMode = 0;
1511  u16 fecOcIprMode = 0;
1512 
1513  dprintk(1, "\n");
1514 
1515  /* Gracefull shutdown (byte boundaries) */
1516  status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1517  if (status < 0)
1518  goto error;
1519  fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1520  status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1521  if (status < 0)
1522  goto error;
1523 
1524  /* Suppress MCLK during absence of data */
1525  status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1526  if (status < 0)
1527  goto error;
1528  fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1529  status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1530 
1531 error:
1532  if (status < 0)
1533  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1534 
1535  return status;
1536 }
1537 
1538 static int scu_command(struct drxk_state *state,
1539  u16 cmd, u8 parameterLen,
1540  u16 *parameter, u8 resultLen, u16 *result)
1541 {
1542 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1543 #error DRXK register mapping no longer compatible with this routine!
1544 #endif
1545  u16 curCmd = 0;
1546  int status = -EINVAL;
1547  unsigned long end;
1548  u8 buffer[34];
1549  int cnt = 0, ii;
1550  const char *p;
1551  char errname[30];
1552 
1553  dprintk(1, "\n");
1554 
1555  if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1556  ((resultLen > 0) && (result == NULL))) {
1557  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1558  return status;
1559  }
1560 
1561  mutex_lock(&state->mutex);
1562 
1563  /* assume that the command register is ready
1564  since it is checked afterwards */
1565  for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1566  buffer[cnt++] = (parameter[ii] & 0xFF);
1567  buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1568  }
1569  buffer[cnt++] = (cmd & 0xFF);
1570  buffer[cnt++] = ((cmd >> 8) & 0xFF);
1571 
1572  write_block(state, SCU_RAM_PARAM_0__A -
1573  (parameterLen - 1), cnt, buffer);
1574  /* Wait until SCU has processed command */
1575  end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1576  do {
1577  msleep(1);
1578  status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1579  if (status < 0)
1580  goto error;
1581  } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1582  if (curCmd != DRX_SCU_READY) {
1583  printk(KERN_ERR "drxk: SCU not ready\n");
1584  status = -EIO;
1585  goto error2;
1586  }
1587  /* read results */
1588  if ((resultLen > 0) && (result != NULL)) {
1589  s16 err;
1590  int ii;
1591 
1592  for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1593  status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1594  if (status < 0)
1595  goto error;
1596  }
1597 
1598  /* Check if an error was reported by SCU */
1599  err = (s16)result[0];
1600  if (err >= 0)
1601  goto error;
1602 
1603  /* check for the known error codes */
1604  switch (err) {
1605  case SCU_RESULT_UNKCMD:
1606  p = "SCU_RESULT_UNKCMD";
1607  break;
1608  case SCU_RESULT_UNKSTD:
1609  p = "SCU_RESULT_UNKSTD";
1610  break;
1611  case SCU_RESULT_SIZE:
1612  p = "SCU_RESULT_SIZE";
1613  break;
1614  case SCU_RESULT_INVPAR:
1615  p = "SCU_RESULT_INVPAR";
1616  break;
1617  default: /* Other negative values are errors */
1618  sprintf(errname, "ERROR: %d\n", err);
1619  p = errname;
1620  }
1621  printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
1622  print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1623  status = -EINVAL;
1624  goto error2;
1625  }
1626 
1627 error:
1628  if (status < 0)
1629  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1630 error2:
1631  mutex_unlock(&state->mutex);
1632  return status;
1633 }
1634 
1635 static int SetIqmAf(struct drxk_state *state, bool active)
1636 {
1637  u16 data = 0;
1638  int status;
1639 
1640  dprintk(1, "\n");
1641 
1642  /* Configure IQM */
1643  status = read16(state, IQM_AF_STDBY__A, &data);
1644  if (status < 0)
1645  goto error;
1646 
1647  if (!active) {
1648  data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1649  | IQM_AF_STDBY_STDBY_AMP_STANDBY
1650  | IQM_AF_STDBY_STDBY_PD_STANDBY
1651  | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1652  | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1653  } else {
1654  data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1655  & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1656  & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1657  & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1658  & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1659  );
1660  }
1661  status = write16(state, IQM_AF_STDBY__A, data);
1662 
1663 error:
1664  if (status < 0)
1665  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1666  return status;
1667 }
1668 
1669 static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1670 {
1671  int status = 0;
1672  u16 sioCcPwdMode = 0;
1673 
1674  dprintk(1, "\n");
1675 
1676  /* Check arguments */
1677  if (mode == NULL)
1678  return -EINVAL;
1679 
1680  switch (*mode) {
1681  case DRX_POWER_UP:
1682  sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1683  break;
1684  case DRXK_POWER_DOWN_OFDM:
1685  sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1686  break;
1687  case DRXK_POWER_DOWN_CORE:
1688  sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1689  break;
1690  case DRXK_POWER_DOWN_PLL:
1691  sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1692  break;
1693  case DRX_POWER_DOWN:
1694  sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1695  break;
1696  default:
1697  /* Unknow sleep mode */
1698  return -EINVAL;
1699  }
1700 
1701  /* If already in requested power mode, do nothing */
1702  if (state->m_currentPowerMode == *mode)
1703  return 0;
1704 
1705  /* For next steps make sure to start from DRX_POWER_UP mode */
1706  if (state->m_currentPowerMode != DRX_POWER_UP) {
1707  status = PowerUpDevice(state);
1708  if (status < 0)
1709  goto error;
1710  status = DVBTEnableOFDMTokenRing(state, true);
1711  if (status < 0)
1712  goto error;
1713  }
1714 
1715  if (*mode == DRX_POWER_UP) {
1716  /* Restore analog & pin configuartion */
1717  } else {
1718  /* Power down to requested mode */
1719  /* Backup some register settings */
1720  /* Set pins with possible pull-ups connected
1721  to them in input mode */
1722  /* Analog power down */
1723  /* ADC power down */
1724  /* Power down device */
1725  /* stop all comm_exec */
1726  /* Stop and power down previous standard */
1727  switch (state->m_OperationMode) {
1728  case OM_DVBT:
1729  status = MPEGTSStop(state);
1730  if (status < 0)
1731  goto error;
1732  status = PowerDownDVBT(state, false);
1733  if (status < 0)
1734  goto error;
1735  break;
1736  case OM_QAM_ITU_A:
1737  case OM_QAM_ITU_C:
1738  status = MPEGTSStop(state);
1739  if (status < 0)
1740  goto error;
1741  status = PowerDownQAM(state);
1742  if (status < 0)
1743  goto error;
1744  break;
1745  default:
1746  break;
1747  }
1748  status = DVBTEnableOFDMTokenRing(state, false);
1749  if (status < 0)
1750  goto error;
1751  status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1752  if (status < 0)
1753  goto error;
1754  status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1755  if (status < 0)
1756  goto error;
1757 
1758  if (*mode != DRXK_POWER_DOWN_OFDM) {
1759  state->m_HICfgCtrl |=
1760  SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1761  status = HI_CfgCommand(state);
1762  if (status < 0)
1763  goto error;
1764  }
1765  }
1766  state->m_currentPowerMode = *mode;
1767 
1768 error:
1769  if (status < 0)
1770  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1771 
1772  return status;
1773 }
1774 
1775 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1776 {
1777  enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
1778  u16 cmdResult = 0;
1779  u16 data = 0;
1780  int status;
1781 
1782  dprintk(1, "\n");
1783 
1784  status = read16(state, SCU_COMM_EXEC__A, &data);
1785  if (status < 0)
1786  goto error;
1787  if (data == SCU_COMM_EXEC_ACTIVE) {
1788  /* Send OFDM stop command */
1789  status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1790  if (status < 0)
1791  goto error;
1792  /* Send OFDM reset command */
1793  status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1794  if (status < 0)
1795  goto error;
1796  }
1797 
1798  /* Reset datapath for OFDM, processors first */
1799  status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1800  if (status < 0)
1801  goto error;
1802  status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1803  if (status < 0)
1804  goto error;
1805  status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1806  if (status < 0)
1807  goto error;
1808 
1809  /* powerdown AFE */
1810  status = SetIqmAf(state, false);
1811  if (status < 0)
1812  goto error;
1813 
1814  /* powerdown to OFDM mode */
1815  if (setPowerMode) {
1816  status = CtrlPowerMode(state, &powerMode);
1817  if (status < 0)
1818  goto error;
1819  }
1820 error:
1821  if (status < 0)
1822  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1823  return status;
1824 }
1825 
1826 static int SetOperationMode(struct drxk_state *state,
1827  enum OperationMode oMode)
1828 {
1829  int status = 0;
1830 
1831  dprintk(1, "\n");
1832  /*
1833  Stop and power down previous standard
1834  TODO investigate total power down instead of partial
1835  power down depending on "previous" standard.
1836  */
1837 
1838  /* disable HW lock indicator */
1839  status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1840  if (status < 0)
1841  goto error;
1842 
1843  /* Device is already at the required mode */
1844  if (state->m_OperationMode == oMode)
1845  return 0;
1846 
1847  switch (state->m_OperationMode) {
1848  /* OM_NONE was added for start up */
1849  case OM_NONE:
1850  break;
1851  case OM_DVBT:
1852  status = MPEGTSStop(state);
1853  if (status < 0)
1854  goto error;
1855  status = PowerDownDVBT(state, true);
1856  if (status < 0)
1857  goto error;
1858  state->m_OperationMode = OM_NONE;
1859  break;
1860  case OM_QAM_ITU_A: /* fallthrough */
1861  case OM_QAM_ITU_C:
1862  status = MPEGTSStop(state);
1863  if (status < 0)
1864  goto error;
1865  status = PowerDownQAM(state);
1866  if (status < 0)
1867  goto error;
1868  state->m_OperationMode = OM_NONE;
1869  break;
1870  case OM_QAM_ITU_B:
1871  default:
1872  status = -EINVAL;
1873  goto error;
1874  }
1875 
1876  /*
1877  Power up new standard
1878  */
1879  switch (oMode) {
1880  case OM_DVBT:
1881  dprintk(1, ": DVB-T\n");
1882  state->m_OperationMode = oMode;
1883  status = SetDVBTStandard(state, oMode);
1884  if (status < 0)
1885  goto error;
1886  break;
1887  case OM_QAM_ITU_A: /* fallthrough */
1888  case OM_QAM_ITU_C:
1889  dprintk(1, ": DVB-C Annex %c\n",
1890  (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C');
1891  state->m_OperationMode = oMode;
1892  status = SetQAMStandard(state, oMode);
1893  if (status < 0)
1894  goto error;
1895  break;
1896  case OM_QAM_ITU_B:
1897  default:
1898  status = -EINVAL;
1899  }
1900 error:
1901  if (status < 0)
1902  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1903  return status;
1904 }
1905 
1906 static int Start(struct drxk_state *state, s32 offsetFreq,
1907  s32 IntermediateFrequency)
1908 {
1909  int status = -EINVAL;
1910 
1911  u16 IFreqkHz;
1912  s32 OffsetkHz = offsetFreq / 1000;
1913 
1914  dprintk(1, "\n");
1915  if (state->m_DrxkState != DRXK_STOPPED &&
1916  state->m_DrxkState != DRXK_DTV_STARTED)
1917  goto error;
1918 
1919  state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1920 
1921  if (IntermediateFrequency < 0) {
1922  state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
1923  IntermediateFrequency = -IntermediateFrequency;
1924  }
1925 
1926  switch (state->m_OperationMode) {
1927  case OM_QAM_ITU_A:
1928  case OM_QAM_ITU_C:
1929  IFreqkHz = (IntermediateFrequency / 1000);
1930  status = SetQAM(state, IFreqkHz, OffsetkHz);
1931  if (status < 0)
1932  goto error;
1933  state->m_DrxkState = DRXK_DTV_STARTED;
1934  break;
1935  case OM_DVBT:
1936  IFreqkHz = (IntermediateFrequency / 1000);
1937  status = MPEGTSStop(state);
1938  if (status < 0)
1939  goto error;
1940  status = SetDVBT(state, IFreqkHz, OffsetkHz);
1941  if (status < 0)
1942  goto error;
1943  status = DVBTStart(state);
1944  if (status < 0)
1945  goto error;
1946  state->m_DrxkState = DRXK_DTV_STARTED;
1947  break;
1948  default:
1949  break;
1950  }
1951 error:
1952  if (status < 0)
1953  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1954  return status;
1955 }
1956 
1957 static int ShutDown(struct drxk_state *state)
1958 {
1959  dprintk(1, "\n");
1960 
1961  MPEGTSStop(state);
1962  return 0;
1963 }
1964 
1965 static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1966  u32 Time)
1967 {
1968  int status = -EINVAL;
1969 
1970  dprintk(1, "\n");
1971 
1972  if (pLockStatus == NULL)
1973  goto error;
1974 
1975  *pLockStatus = NOT_LOCKED;
1976 
1977  /* define the SCU command code */
1978  switch (state->m_OperationMode) {
1979  case OM_QAM_ITU_A:
1980  case OM_QAM_ITU_B:
1981  case OM_QAM_ITU_C:
1982  status = GetQAMLockStatus(state, pLockStatus);
1983  break;
1984  case OM_DVBT:
1985  status = GetDVBTLockStatus(state, pLockStatus);
1986  break;
1987  default:
1988  break;
1989  }
1990 error:
1991  if (status < 0)
1992  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1993  return status;
1994 }
1995 
1996 static int MPEGTSStart(struct drxk_state *state)
1997 {
1998  int status;
1999 
2000  u16 fecOcSncMode = 0;
2001 
2002  /* Allow OC to sync again */
2003  status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
2004  if (status < 0)
2005  goto error;
2006  fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
2007  status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
2008  if (status < 0)
2009  goto error;
2010  status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
2011 error:
2012  if (status < 0)
2013  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2014  return status;
2015 }
2016 
2017 static int MPEGTSDtoInit(struct drxk_state *state)
2018 {
2019  int status;
2020 
2021  dprintk(1, "\n");
2022 
2023  /* Rate integration settings */
2024  status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
2025  if (status < 0)
2026  goto error;
2027  status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
2028  if (status < 0)
2029  goto error;
2030  status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
2031  if (status < 0)
2032  goto error;
2033  status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
2034  if (status < 0)
2035  goto error;
2036  status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
2037  if (status < 0)
2038  goto error;
2039  status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
2040  if (status < 0)
2041  goto error;
2042  status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
2043  if (status < 0)
2044  goto error;
2045  status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
2046  if (status < 0)
2047  goto error;
2048 
2049  /* Additional configuration */
2050  status = write16(state, FEC_OC_OCR_INVERT__A, 0);
2051  if (status < 0)
2052  goto error;
2053  status = write16(state, FEC_OC_SNC_LWM__A, 2);
2054  if (status < 0)
2055  goto error;
2056  status = write16(state, FEC_OC_SNC_HWM__A, 12);
2057 error:
2058  if (status < 0)
2059  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2060 
2061  return status;
2062 }
2063 
2064 static int MPEGTSDtoSetup(struct drxk_state *state,
2065  enum OperationMode oMode)
2066 {
2067  int status;
2068 
2069  u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
2070  u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
2071  u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
2072  u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
2073  u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
2074  u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
2075  u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
2076  u16 fecOcTmdMode = 0;
2077  u16 fecOcTmdIntUpdRate = 0;
2078  u32 maxBitRate = 0;
2079  bool staticCLK = false;
2080 
2081  dprintk(1, "\n");
2082 
2083  /* Check insertion of the Reed-Solomon parity bytes */
2084  status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2085  if (status < 0)
2086  goto error;
2087  status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2088  if (status < 0)
2089  goto error;
2090  fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2091  fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2092  if (state->m_insertRSByte == true) {
2093  /* enable parity symbol forward */
2094  fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2095  /* MVAL disable during parity bytes */
2096  fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2097  /* TS burst length to 204 */
2098  fecOcDtoBurstLen = 204;
2099  }
2100 
2101  /* Check serial or parrallel output */
2102  fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2103  if (state->m_enableParallel == false) {
2104  /* MPEG data output is serial -> set ipr_mode[0] */
2105  fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2106  }
2107 
2108  switch (oMode) {
2109  case OM_DVBT:
2110  maxBitRate = state->m_DVBTBitrate;
2111  fecOcTmdMode = 3;
2112  fecOcRcnCtlRate = 0xC00000;
2113  staticCLK = state->m_DVBTStaticCLK;
2114  break;
2115  case OM_QAM_ITU_A: /* fallthrough */
2116  case OM_QAM_ITU_C:
2117  fecOcTmdMode = 0x0004;
2118  fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
2119  maxBitRate = state->m_DVBCBitrate;
2120  staticCLK = state->m_DVBCStaticCLK;
2121  break;
2122  default:
2123  status = -EINVAL;
2124  } /* switch (standard) */
2125  if (status < 0)
2126  goto error;
2127 
2128  /* Configure DTO's */
2129  if (staticCLK) {
2130  u32 bitRate = 0;
2131 
2132  /* Rational DTO for MCLK source (static MCLK rate),
2133  Dynamic DTO for optimal grouping
2134  (avoid intra-packet gaps),
2135  DTO offset enable to sync TS burst with MSTRT */
2136  fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2137  FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2138  fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2139  FEC_OC_FCT_MODE_VIRT_ENA__M);
2140 
2141  /* Check user defined bitrate */
2142  bitRate = maxBitRate;
2143  if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
2144  bitRate = 75900000UL;
2145  }
2146  /* Rational DTO period:
2147  dto_period = (Fsys / bitrate) - 2
2148 
2149  Result should be floored,
2150  to make sure >= requested bitrate
2151  */
2152  fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2153  * 1000) / bitRate);
2154  if (fecOcDtoPeriod <= 2)
2155  fecOcDtoPeriod = 0;
2156  else
2157  fecOcDtoPeriod -= 2;
2158  fecOcTmdIntUpdRate = 8;
2159  } else {
2160  /* (commonAttr->staticCLK == false) => dynamic mode */
2161  fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2162  fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2163  fecOcTmdIntUpdRate = 5;
2164  }
2165 
2166  /* Write appropriate registers with requested configuration */
2167  status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2168  if (status < 0)
2169  goto error;
2170  status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2171  if (status < 0)
2172  goto error;
2173  status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2174  if (status < 0)
2175  goto error;
2176  status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2177  if (status < 0)
2178  goto error;
2179  status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2180  if (status < 0)
2181  goto error;
2182  status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2183  if (status < 0)
2184  goto error;
2185 
2186  /* Rate integration settings */
2187  status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2188  if (status < 0)
2189  goto error;
2190  status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2191  if (status < 0)
2192  goto error;
2193  status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2194 error:
2195  if (status < 0)
2196  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2197  return status;
2198 }
2199 
2200 static int MPEGTSConfigurePolarity(struct drxk_state *state)
2201 {
2202  u16 fecOcRegIprInvert = 0;
2203 
2204  /* Data mask for the output data byte */
2205  u16 InvertDataMask =
2206  FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2207  FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2208  FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2209  FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2210 
2211  dprintk(1, "\n");
2212 
2213  /* Control selective inversion of output bits */
2214  fecOcRegIprInvert &= (~(InvertDataMask));
2215  if (state->m_invertDATA == true)
2216  fecOcRegIprInvert |= InvertDataMask;
2217  fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2218  if (state->m_invertERR == true)
2219  fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2220  fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2221  if (state->m_invertSTR == true)
2222  fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2223  fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2224  if (state->m_invertVAL == true)
2225  fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2226  fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2227  if (state->m_invertCLK == true)
2228  fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2229 
2230  return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2231 }
2232 
2233 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2234 
2235 static int SetAgcRf(struct drxk_state *state,
2236  struct SCfgAgc *pAgcCfg, bool isDTV)
2237 {
2238  int status = -EINVAL;
2239  u16 data = 0;
2240  struct SCfgAgc *pIfAgcSettings;
2241 
2242  dprintk(1, "\n");
2243 
2244  if (pAgcCfg == NULL)
2245  goto error;
2246 
2247  switch (pAgcCfg->ctrlMode) {
2248  case DRXK_AGC_CTRL_AUTO:
2249  /* Enable RF AGC DAC */
2250  status = read16(state, IQM_AF_STDBY__A, &data);
2251  if (status < 0)
2252  goto error;
2253  data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2254  status = write16(state, IQM_AF_STDBY__A, data);
2255  if (status < 0)
2256  goto error;
2257  status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2258  if (status < 0)
2259  goto error;
2260 
2261  /* Enable SCU RF AGC loop */
2262  data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2263 
2264  /* Polarity */
2265  if (state->m_RfAgcPol)
2266  data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2267  else
2268  data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2269  status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2270  if (status < 0)
2271  goto error;
2272 
2273  /* Set speed (using complementary reduction value) */
2274  status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2275  if (status < 0)
2276  goto error;
2277 
2278  data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2279  data |= (~(pAgcCfg->speed <<
2280  SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2281  & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2282 
2283  status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2284  if (status < 0)
2285  goto error;
2286 
2287  if (IsDVBT(state))
2288  pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2289  else if (IsQAM(state))
2290  pIfAgcSettings = &state->m_qamIfAgcCfg;
2291  else
2292  pIfAgcSettings = &state->m_atvIfAgcCfg;
2293  if (pIfAgcSettings == NULL) {
2294  status = -EINVAL;
2295  goto error;
2296  }
2297 
2298  /* Set TOP, only if IF-AGC is in AUTO mode */
2299  if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2300  status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2301  if (status < 0)
2302  goto error;
2303 
2304  /* Cut-Off current */
2305  status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2306  if (status < 0)
2307  goto error;
2308 
2309  /* Max. output level */
2310  status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2311  if (status < 0)
2312  goto error;
2313 
2314  break;
2315 
2316  case DRXK_AGC_CTRL_USER:
2317  /* Enable RF AGC DAC */
2318  status = read16(state, IQM_AF_STDBY__A, &data);
2319  if (status < 0)
2320  goto error;
2321  data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2322  status = write16(state, IQM_AF_STDBY__A, data);
2323  if (status < 0)
2324  goto error;
2325 
2326  /* Disable SCU RF AGC loop */
2327  status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2328  if (status < 0)
2329  goto error;
2330  data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2331  if (state->m_RfAgcPol)
2332  data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2333  else
2334  data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2335  status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2336  if (status < 0)
2337  goto error;
2338 
2339  /* SCU c.o.c. to 0, enabling full control range */
2340  status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2341  if (status < 0)
2342  goto error;
2343 
2344  /* Write value to output pin */
2345  status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2346  if (status < 0)
2347  goto error;
2348  break;
2349 
2350  case DRXK_AGC_CTRL_OFF:
2351  /* Disable RF AGC DAC */
2352  status = read16(state, IQM_AF_STDBY__A, &data);
2353  if (status < 0)
2354  goto error;
2355  data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2356  status = write16(state, IQM_AF_STDBY__A, data);
2357  if (status < 0)
2358  goto error;
2359 
2360  /* Disable SCU RF AGC loop */
2361  status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2362  if (status < 0)
2363  goto error;
2364  data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2365  status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2366  if (status < 0)
2367  goto error;
2368  break;
2369 
2370  default:
2371  status = -EINVAL;
2372 
2373  }
2374 error:
2375  if (status < 0)
2376  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2377  return status;
2378 }
2379 
2380 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2381 
2382 static int SetAgcIf(struct drxk_state *state,
2383  struct SCfgAgc *pAgcCfg, bool isDTV)
2384 {
2385  u16 data = 0;
2386  int status = 0;
2387  struct SCfgAgc *pRfAgcSettings;
2388 
2389  dprintk(1, "\n");
2390 
2391  switch (pAgcCfg->ctrlMode) {
2392  case DRXK_AGC_CTRL_AUTO:
2393 
2394  /* Enable IF AGC DAC */
2395  status = read16(state, IQM_AF_STDBY__A, &data);
2396  if (status < 0)
2397  goto error;
2398  data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2399  status = write16(state, IQM_AF_STDBY__A, data);
2400  if (status < 0)
2401  goto error;
2402 
2403  status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2404  if (status < 0)
2405  goto error;
2406 
2407  /* Enable SCU IF AGC loop */
2408  data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2409 
2410  /* Polarity */
2411  if (state->m_IfAgcPol)
2412  data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2413  else
2414  data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2415  status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2416  if (status < 0)
2417  goto error;
2418 
2419  /* Set speed (using complementary reduction value) */
2420  status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2421  if (status < 0)
2422  goto error;
2423  data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2424  data |= (~(pAgcCfg->speed <<
2425  SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2426  & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2427 
2428  status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2429  if (status < 0)
2430  goto error;
2431 
2432  if (IsQAM(state))
2433  pRfAgcSettings = &state->m_qamRfAgcCfg;
2434  else
2435  pRfAgcSettings = &state->m_atvRfAgcCfg;
2436  if (pRfAgcSettings == NULL)
2437  return -1;
2438  /* Restore TOP */
2439  status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2440  if (status < 0)
2441  goto error;
2442  break;
2443 
2444  case DRXK_AGC_CTRL_USER:
2445 
2446  /* Enable IF AGC DAC */
2447  status = read16(state, IQM_AF_STDBY__A, &data);
2448  if (status < 0)
2449  goto error;
2450  data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2451  status = write16(state, IQM_AF_STDBY__A, data);
2452  if (status < 0)
2453  goto error;
2454 
2455  status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2456  if (status < 0)
2457  goto error;
2458 
2459  /* Disable SCU IF AGC loop */
2460  data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2461 
2462  /* Polarity */
2463  if (state->m_IfAgcPol)
2464  data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2465  else
2466  data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2467  status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2468  if (status < 0)
2469  goto error;
2470 
2471  /* Write value to output pin */
2472  status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2473  if (status < 0)
2474  goto error;
2475  break;
2476 
2477  case DRXK_AGC_CTRL_OFF:
2478 
2479  /* Disable If AGC DAC */
2480  status = read16(state, IQM_AF_STDBY__A, &data);
2481  if (status < 0)
2482  goto error;
2483  data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2484  status = write16(state, IQM_AF_STDBY__A, data);
2485  if (status < 0)
2486  goto error;
2487 
2488  /* Disable SCU IF AGC loop */
2489  status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2490  if (status < 0)
2491  goto error;
2492  data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2493  status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2494  if (status < 0)
2495  goto error;
2496  break;
2497  } /* switch (agcSettingsIf->ctrlMode) */
2498 
2499  /* always set the top to support
2500  configurations without if-loop */
2501  status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2502 error:
2503  if (status < 0)
2504  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2505  return status;
2506 }
2507 
2508 static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2509 {
2510  u16 agcDacLvl;
2511  int status;
2512  u16 Level = 0;
2513 
2514  dprintk(1, "\n");
2515 
2516  status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2517  if (status < 0) {
2518  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2519  return status;
2520  }
2521 
2522  *pValue = 0;
2523 
2524  if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
2525  Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
2526  if (Level < 14000)
2527  *pValue = (14000 - Level) / 4;
2528  else
2529  *pValue = 0;
2530 
2531  return status;
2532 }
2533 
2534 static int GetQAMSignalToNoise(struct drxk_state *state,
2535  s32 *pSignalToNoise)
2536 {
2537  int status = 0;
2538  u16 qamSlErrPower = 0; /* accum. error between
2539  raw and sliced symbols */
2540  u32 qamSlSigPower = 0; /* used for MER, depends of
2541  QAM modulation */
2542  u32 qamSlMer = 0; /* QAM MER */
2543 
2544  dprintk(1, "\n");
2545 
2546  /* MER calculation */
2547 
2548  /* get the register value needed for MER */
2549  status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2550  if (status < 0) {
2551  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2552  return -EINVAL;
2553  }
2554 
2555  switch (state->props.modulation) {
2556  case QAM_16:
2557  qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2558  break;
2559  case QAM_32:
2560  qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2561  break;
2562  case QAM_64:
2563  qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2564  break;
2565  case QAM_128:
2566  qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2567  break;
2568  default:
2569  case QAM_256:
2570  qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2571  break;
2572  }
2573 
2574  if (qamSlErrPower > 0) {
2575  qamSlMer = Log10Times100(qamSlSigPower) -
2576  Log10Times100((u32) qamSlErrPower);
2577  }
2578  *pSignalToNoise = qamSlMer;
2579 
2580  return status;
2581 }
2582 
2583 static int GetDVBTSignalToNoise(struct drxk_state *state,
2584  s32 *pSignalToNoise)
2585 {
2586  int status;
2587  u16 regData = 0;
2588  u32 EqRegTdSqrErrI = 0;
2589  u32 EqRegTdSqrErrQ = 0;
2590  u16 EqRegTdSqrErrExp = 0;
2591  u16 EqRegTdTpsPwrOfs = 0;
2592  u16 EqRegTdReqSmbCnt = 0;
2593  u32 tpsCnt = 0;
2594  u32 SqrErrIQ = 0;
2595  u32 a = 0;
2596  u32 b = 0;
2597  u32 c = 0;
2598  u32 iMER = 0;
2599  u16 transmissionParams = 0;
2600 
2601  dprintk(1, "\n");
2602 
2603  status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2604  if (status < 0)
2605  goto error;
2606  status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2607  if (status < 0)
2608  goto error;
2609  status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2610  if (status < 0)
2611  goto error;
2612  status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData);
2613  if (status < 0)
2614  goto error;
2615  /* Extend SQR_ERR_I operational range */
2616  EqRegTdSqrErrI = (u32) regData;
2617  if ((EqRegTdSqrErrExp > 11) &&
2618  (EqRegTdSqrErrI < 0x00000FFFUL)) {
2619  EqRegTdSqrErrI += 0x00010000UL;
2620  }
2621  status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData);
2622  if (status < 0)
2623  goto error;
2624  /* Extend SQR_ERR_Q operational range */
2625  EqRegTdSqrErrQ = (u32) regData;
2626  if ((EqRegTdSqrErrExp > 11) &&
2627  (EqRegTdSqrErrQ < 0x00000FFFUL))
2628  EqRegTdSqrErrQ += 0x00010000UL;
2629 
2630  status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2631  if (status < 0)
2632  goto error;
2633 
2634  /* Check input data for MER */
2635 
2636  /* MER calculation (in 0.1 dB) without math.h */
2637  if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2638  iMER = 0;
2639  else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2640  /* No error at all, this must be the HW reset value
2641  * Apparently no first measurement yet
2642  * Set MER to 0.0 */
2643  iMER = 0;
2644  } else {
2645  SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2646  EqRegTdSqrErrExp;
2647  if ((transmissionParams &
2648  OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2649  == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2650  tpsCnt = 17;
2651  else
2652  tpsCnt = 68;
2653 
2654  /* IMER = 100 * log10 (x)
2655  where x = (EqRegTdTpsPwrOfs^2 *
2656  EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2657 
2658  => IMER = a + b -c
2659  where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2660  b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2661  c = 100 * log10 (SqrErrIQ)
2662  */
2663 
2664  /* log(x) x = 9bits * 9bits->18 bits */
2665  a = Log10Times100(EqRegTdTpsPwrOfs *
2666  EqRegTdTpsPwrOfs);
2667  /* log(x) x = 16bits * 7bits->23 bits */
2668  b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2669  /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2670  c = Log10Times100(SqrErrIQ);
2671 
2672  iMER = a + b;
2673  /* No negative MER, clip to zero */
2674  if (iMER > c)
2675  iMER -= c;
2676  else
2677  iMER = 0;
2678  }
2679  *pSignalToNoise = iMER;
2680 
2681 error:
2682  if (status < 0)
2683  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2684  return status;
2685 }
2686 
2687 static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2688 {
2689  dprintk(1, "\n");
2690 
2691  *pSignalToNoise = 0;
2692  switch (state->m_OperationMode) {
2693  case OM_DVBT:
2694  return GetDVBTSignalToNoise(state, pSignalToNoise);
2695  case OM_QAM_ITU_A:
2696  case OM_QAM_ITU_C:
2697  return GetQAMSignalToNoise(state, pSignalToNoise);
2698  default:
2699  break;
2700  }
2701  return 0;
2702 }
2703 
2704 #if 0
2705 static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2706 {
2707  /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2708  int status = 0;
2709 
2710  dprintk(1, "\n");
2711 
2712  static s32 QE_SN[] = {
2713  51, /* QPSK 1/2 */
2714  69, /* QPSK 2/3 */
2715  79, /* QPSK 3/4 */
2716  89, /* QPSK 5/6 */
2717  97, /* QPSK 7/8 */
2718  108, /* 16-QAM 1/2 */
2719  131, /* 16-QAM 2/3 */
2720  146, /* 16-QAM 3/4 */
2721  156, /* 16-QAM 5/6 */
2722  160, /* 16-QAM 7/8 */
2723  165, /* 64-QAM 1/2 */
2724  187, /* 64-QAM 2/3 */
2725  202, /* 64-QAM 3/4 */
2726  216, /* 64-QAM 5/6 */
2727  225, /* 64-QAM 7/8 */
2728  };
2729 
2730  *pQuality = 0;
2731 
2732  do {
2733  s32 SignalToNoise = 0;
2734  u16 Constellation = 0;
2735  u16 CodeRate = 0;
2736  u32 SignalToNoiseRel;
2737  u32 BERQuality;
2738 
2739  status = GetDVBTSignalToNoise(state, &SignalToNoise);
2740  if (status < 0)
2741  break;
2742  status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2743  if (status < 0)
2744  break;
2745  Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2746 
2747  status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2748  if (status < 0)
2749  break;
2750  CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2751 
2752  if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2753  CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2754  break;
2755  SignalToNoiseRel = SignalToNoise -
2756  QE_SN[Constellation * 5 + CodeRate];
2757  BERQuality = 100;
2758 
2759  if (SignalToNoiseRel < -70)
2760  *pQuality = 0;
2761  else if (SignalToNoiseRel < 30)
2762  *pQuality = ((SignalToNoiseRel + 70) *
2763  BERQuality) / 100;
2764  else
2765  *pQuality = BERQuality;
2766  } while (0);
2767  return 0;
2768 };
2769 
2770 static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2771 {
2772  int status = 0;
2773  *pQuality = 0;
2774 
2775  dprintk(1, "\n");
2776 
2777  do {
2778  u32 SignalToNoise = 0;
2779  u32 BERQuality = 100;
2780  u32 SignalToNoiseRel = 0;
2781 
2782  status = GetQAMSignalToNoise(state, &SignalToNoise);
2783  if (status < 0)
2784  break;
2785 
2786  switch (state->props.modulation) {
2787  case QAM_16:
2788  SignalToNoiseRel = SignalToNoise - 200;
2789  break;
2790  case QAM_32:
2791  SignalToNoiseRel = SignalToNoise - 230;
2792  break; /* Not in NorDig */
2793  case QAM_64:
2794  SignalToNoiseRel = SignalToNoise - 260;
2795  break;
2796  case QAM_128:
2797  SignalToNoiseRel = SignalToNoise - 290;
2798  break;
2799  default:
2800  case QAM_256:
2801  SignalToNoiseRel = SignalToNoise - 320;
2802  break;
2803  }
2804 
2805  if (SignalToNoiseRel < -70)
2806  *pQuality = 0;
2807  else if (SignalToNoiseRel < 30)
2808  *pQuality = ((SignalToNoiseRel + 70) *
2809  BERQuality) / 100;
2810  else
2811  *pQuality = BERQuality;
2812  } while (0);
2813 
2814  return status;
2815 }
2816 
2817 static int GetQuality(struct drxk_state *state, s32 *pQuality)
2818 {
2819  dprintk(1, "\n");
2820 
2821  switch (state->m_OperationMode) {
2822  case OM_DVBT:
2823  return GetDVBTQuality(state, pQuality);
2824  case OM_QAM_ITU_A:
2825  return GetDVBCQuality(state, pQuality);
2826  default:
2827  break;
2828  }
2829 
2830  return 0;
2831 }
2832 #endif
2833 
2834 /* Free data ram in SIO HI */
2835 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2836 #define SIO_HI_RA_RAM_USR_END__A 0x420060
2837 
2838 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2839 #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2840 #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2841 #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2842 
2843 #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2844 #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2845 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2846 
2847 static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2848 {
2849  int status = -EINVAL;
2850 
2851  dprintk(1, "\n");
2852 
2853  if (state->m_DrxkState == DRXK_UNINITIALIZED)
2854  return 0;
2855  if (state->m_DrxkState == DRXK_POWERED_DOWN)
2856  goto error;
2857 
2858  if (state->no_i2c_bridge)
2859  return 0;
2860 
2861  status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2862  if (status < 0)
2863  goto error;
2864  if (bEnableBridge) {
2865  status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2866  if (status < 0)
2867  goto error;
2868  } else {
2869  status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2870  if (status < 0)
2871  goto error;
2872  }
2873 
2874  status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2875 
2876 error:
2877  if (status < 0)
2878  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2879  return status;
2880 }
2881 
2882 static int SetPreSaw(struct drxk_state *state,
2883  struct SCfgPreSaw *pPreSawCfg)
2884 {
2885  int status = -EINVAL;
2886 
2887  dprintk(1, "\n");
2888 
2889  if ((pPreSawCfg == NULL)
2890  || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2891  goto error;
2892 
2893  status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2894 error:
2895  if (status < 0)
2896  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2897  return status;
2898 }
2899 
2900 static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2901  u16 romOffset, u16 nrOfElements, u32 timeOut)
2902 {
2903  u16 blStatus = 0;
2904  u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2905  u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2906  int status;
2907  unsigned long end;
2908 
2909  dprintk(1, "\n");
2910 
2911  mutex_lock(&state->mutex);
2912  status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2913  if (status < 0)
2914  goto error;
2915  status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2916  if (status < 0)
2917  goto error;
2918  status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2919  if (status < 0)
2920  goto error;
2921  status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2922  if (status < 0)
2923  goto error;
2924  status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2925  if (status < 0)
2926  goto error;
2927  status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2928  if (status < 0)
2929  goto error;
2930 
2931  end = jiffies + msecs_to_jiffies(timeOut);
2932  do {
2933  status = read16(state, SIO_BL_STATUS__A, &blStatus);
2934  if (status < 0)
2935  goto error;
2936  } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2937  if (blStatus == 0x1) {
2938  printk(KERN_ERR "drxk: SIO not ready\n");
2939  status = -EINVAL;
2940  goto error2;
2941  }
2942 error:
2943  if (status < 0)
2944  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2945 error2:
2946  mutex_unlock(&state->mutex);
2947  return status;
2948 
2949 }
2950 
2951 static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2952 {
2953  u16 data = 0;
2954  int status;
2955 
2956  dprintk(1, "\n");
2957 
2958  /* Start measurement */
2959  status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2960  if (status < 0)
2961  goto error;
2962  status = write16(state, IQM_AF_START_LOCK__A, 1);
2963  if (status < 0)
2964  goto error;
2965 
2966  *count = 0;
2967  status = read16(state, IQM_AF_PHASE0__A, &data);
2968  if (status < 0)
2969  goto error;
2970  if (data == 127)
2971  *count = *count + 1;
2972  status = read16(state, IQM_AF_PHASE1__A, &data);
2973  if (status < 0)
2974  goto error;
2975  if (data == 127)
2976  *count = *count + 1;
2977  status = read16(state, IQM_AF_PHASE2__A, &data);
2978  if (status < 0)
2979  goto error;
2980  if (data == 127)
2981  *count = *count + 1;
2982 
2983 error:
2984  if (status < 0)
2985  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2986  return status;
2987 }
2988 
2989 static int ADCSynchronization(struct drxk_state *state)
2990 {
2991  u16 count = 0;
2992  int status;
2993 
2994  dprintk(1, "\n");
2995 
2996  status = ADCSyncMeasurement(state, &count);
2997  if (status < 0)
2998  goto error;
2999 
3000  if (count == 1) {
3001  /* Try sampling on a diffrent edge */
3002  u16 clkNeg = 0;
3003 
3004  status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
3005  if (status < 0)
3006  goto error;
3007  if ((clkNeg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
3008  IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
3009  clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
3010  clkNeg |=
3011  IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
3012  } else {
3013  clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
3014  clkNeg |=
3015  IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
3016  }
3017  status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
3018  if (status < 0)
3019  goto error;
3020  status = ADCSyncMeasurement(state, &count);
3021  if (status < 0)
3022  goto error;
3023  }
3024 
3025  if (count < 2)
3026  status = -EINVAL;
3027 error:
3028  if (status < 0)
3029  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3030  return status;
3031 }
3032 
3033 static int SetFrequencyShifter(struct drxk_state *state,
3034  u16 intermediateFreqkHz,
3035  s32 tunerFreqOffset, bool isDTV)
3036 {
3037  bool selectPosImage = false;
3038  u32 rfFreqResidual = tunerFreqOffset;
3039  u32 fmFrequencyShift = 0;
3040  bool tunerMirror = !state->m_bMirrorFreqSpect;
3041  u32 adcFreq;
3042  bool adcFlip;
3043  int status;
3044  u32 ifFreqActual;
3045  u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
3046  u32 frequencyShift;
3047  bool imageToSelect;
3048 
3049  dprintk(1, "\n");
3050 
3051  /*
3052  Program frequency shifter
3053  No need to account for mirroring on RF
3054  */
3055  if (isDTV) {
3056  if ((state->m_OperationMode == OM_QAM_ITU_A) ||
3057  (state->m_OperationMode == OM_QAM_ITU_C) ||
3058  (state->m_OperationMode == OM_DVBT))
3059  selectPosImage = true;
3060  else
3061  selectPosImage = false;
3062  }
3063  if (tunerMirror)
3064  /* tuner doesn't mirror */
3065  ifFreqActual = intermediateFreqkHz +
3066  rfFreqResidual + fmFrequencyShift;
3067  else
3068  /* tuner mirrors */
3069  ifFreqActual = intermediateFreqkHz -
3070  rfFreqResidual - fmFrequencyShift;
3071  if (ifFreqActual > samplingFrequency / 2) {
3072  /* adc mirrors */
3073  adcFreq = samplingFrequency - ifFreqActual;
3074  adcFlip = true;
3075  } else {
3076  /* adc doesn't mirror */
3077  adcFreq = ifFreqActual;
3078  adcFlip = false;
3079  }
3080 
3081  frequencyShift = adcFreq;
3082  imageToSelect = state->m_rfmirror ^ tunerMirror ^
3083  adcFlip ^ selectPosImage;
3084  state->m_IqmFsRateOfs =
3085  Frac28a((frequencyShift), samplingFrequency);
3086 
3087  if (imageToSelect)
3088  state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
3089 
3090  /* Program frequency shifter with tuner offset compensation */
3091  /* frequencyShift += tunerFreqOffset; TODO */
3092  status = write32(state, IQM_FS_RATE_OFS_LO__A,
3093  state->m_IqmFsRateOfs);
3094  if (status < 0)
3095  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3096  return status;
3097 }
3098 
3099 static int InitAGC(struct drxk_state *state, bool isDTV)
3100 {
3101  u16 ingainTgt = 0;
3102  u16 ingainTgtMin = 0;
3103  u16 ingainTgtMax = 0;
3104  u16 clpCyclen = 0;
3105  u16 clpSumMin = 0;
3106  u16 clpDirTo = 0;
3107  u16 snsSumMin = 0;
3108  u16 snsSumMax = 0;
3109  u16 clpSumMax = 0;
3110  u16 snsDirTo = 0;
3111  u16 kiInnergainMin = 0;
3112  u16 ifIaccuHiTgt = 0;
3113  u16 ifIaccuHiTgtMin = 0;
3114  u16 ifIaccuHiTgtMax = 0;
3115  u16 data = 0;
3116  u16 fastClpCtrlDelay = 0;
3117  u16 clpCtrlMode = 0;
3118  int status = 0;
3119 
3120  dprintk(1, "\n");
3121 
3122  /* Common settings */
3123  snsSumMax = 1023;
3124  ifIaccuHiTgtMin = 2047;
3125  clpCyclen = 500;
3126  clpSumMax = 1023;
3127 
3128  /* AGCInit() not available for DVBT; init done in microcode */
3129  if (!IsQAM(state)) {
3130  printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode);
3131  return -EINVAL;
3132  }
3133 
3134  /* FIXME: Analog TV AGC require different settings */
3135 
3136  /* Standard specific settings */
3137  clpSumMin = 8;
3138  clpDirTo = (u16) -9;
3139  clpCtrlMode = 0;
3140  snsSumMin = 8;
3141  snsDirTo = (u16) -9;
3142  kiInnergainMin = (u16) -1030;
3143  ifIaccuHiTgtMax = 0x2380;
3144  ifIaccuHiTgt = 0x2380;
3145  ingainTgtMin = 0x0511;
3146  ingainTgt = 0x0511;
3147  ingainTgtMax = 5119;
3148  fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay;
3149 
3150  status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3151  if (status < 0)
3152  goto error;
3153 
3154  status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3155  if (status < 0)
3156  goto error;
3157  status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3158  if (status < 0)
3159  goto error;
3160  status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3161  if (status < 0)
3162  goto error;
3163  status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3164  if (status < 0)
3165  goto error;
3166  status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3167  if (status < 0)
3168  goto error;
3169  status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3170  if (status < 0)
3171  goto error;
3172  status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3173  if (status < 0)
3174  goto error;
3175  status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3176  if (status < 0)
3177  goto error;
3178  status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3179  if (status < 0)
3180  goto error;
3181  status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3182  if (status < 0)
3183  goto error;
3184  status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3185  if (status < 0)
3186  goto error;
3187  status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3188  if (status < 0)
3189  goto error;
3190 
3191  status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3192  if (status < 0)
3193  goto error;
3194  status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3195  if (status < 0)
3196  goto error;
3197  status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3198  if (status < 0)
3199  goto error;
3200 
3201  status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3202  if (status < 0)
3203  goto error;
3204  status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3205  if (status < 0)
3206  goto error;
3207  status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3208  if (status < 0)
3209  goto error;
3210 
3211  status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3212  if (status < 0)
3213  goto error;
3214  status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3215  if (status < 0)
3216  goto error;
3217  status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3218  if (status < 0)
3219  goto error;
3220  status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3221  if (status < 0)
3222  goto error;
3223  status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3224  if (status < 0)
3225  goto error;
3226  status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3227  if (status < 0)
3228  goto error;
3229  status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3230  if (status < 0)
3231  goto error;
3232  status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3233  if (status < 0)
3234  goto error;
3235  status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3236  if (status < 0)
3237  goto error;
3238  status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3239  if (status < 0)
3240  goto error;
3241  status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3242  if (status < 0)
3243  goto error;
3244  status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3245  if (status < 0)
3246  goto error;
3247  status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3248  if (status < 0)
3249  goto error;
3250  status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3251  if (status < 0)
3252  goto error;
3253  status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3254  if (status < 0)
3255  goto error;
3256  status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3257  if (status < 0)
3258  goto error;
3259  status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3260  if (status < 0)
3261  goto error;
3262  status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3263  if (status < 0)
3264  goto error;
3265  status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3266  if (status < 0)
3267  goto error;
3268 
3269  /* Initialize inner-loop KI gain factors */
3270  status = read16(state, SCU_RAM_AGC_KI__A, &data);
3271  if (status < 0)
3272  goto error;
3273 
3274  data = 0x0657;
3275  data &= ~SCU_RAM_AGC_KI_RF__M;
3276  data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3277  data &= ~SCU_RAM_AGC_KI_IF__M;
3278  data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3279 
3280  status = write16(state, SCU_RAM_AGC_KI__A, data);
3281 error:
3282  if (status < 0)
3283  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3284  return status;
3285 }
3286 
3287 static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
3288 {
3289  int status;
3290 
3291  dprintk(1, "\n");
3292  if (packetErr == NULL)
3293  status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3294  else
3295  status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3296  if (status < 0)
3297  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3298  return status;
3299 }
3300 
3301 static int DVBTScCommand(struct drxk_state *state,
3302  u16 cmd, u16 subcmd,
3303  u16 param0, u16 param1, u16 param2,
3304  u16 param3, u16 param4)
3305 {
3306  u16 curCmd = 0;
3307  u16 errCode = 0;
3308  u16 retryCnt = 0;
3309  u16 scExec = 0;
3310  int status;
3311 
3312  dprintk(1, "\n");
3313  status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
3314  if (scExec != 1) {
3315  /* SC is not running */
3316  status = -EINVAL;
3317  }
3318  if (status < 0)
3319  goto error;
3320 
3321  /* Wait until sc is ready to receive command */
3322  retryCnt = 0;
3323  do {
3324  msleep(1);
3325  status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3326  retryCnt++;
3327  } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3328  if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3329  goto error;
3330 
3331  /* Write sub-command */
3332  switch (cmd) {
3333  /* All commands using sub-cmd */
3334  case OFDM_SC_RA_RAM_CMD_PROC_START:
3335  case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3336  case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3337  status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3338  if (status < 0)
3339  goto error;
3340  break;
3341  default:
3342  /* Do nothing */
3343  break;
3344  }
3345 
3346  /* Write needed parameters and the command */
3347  switch (cmd) {
3348  /* All commands using 5 parameters */
3349  /* All commands using 4 parameters */
3350  /* All commands using 3 parameters */
3351  /* All commands using 2 parameters */
3352  case OFDM_SC_RA_RAM_CMD_PROC_START:
3353  case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3354  case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3355  status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3356  /* All commands using 1 parameters */
3357  case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3358  case OFDM_SC_RA_RAM_CMD_USER_IO:
3359  status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3360  /* All commands using 0 parameters */
3361  case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3362  case OFDM_SC_RA_RAM_CMD_NULL:
3363  /* Write command */
3364  status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3365  break;
3366  default:
3367  /* Unknown command */
3368  status = -EINVAL;
3369  }
3370  if (status < 0)
3371  goto error;
3372 
3373  /* Wait until sc is ready processing command */
3374  retryCnt = 0;
3375  do {
3376  msleep(1);
3377  status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3378  retryCnt++;
3379  } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3380  if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3381  goto error;
3382 
3383  /* Check for illegal cmd */
3384  status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
3385  if (errCode == 0xFFFF) {
3386  /* illegal command */
3387  status = -EINVAL;
3388  }
3389  if (status < 0)
3390  goto error;
3391 
3392  /* Retreive results parameters from SC */
3393  switch (cmd) {
3394  /* All commands yielding 5 results */
3395  /* All commands yielding 4 results */
3396  /* All commands yielding 3 results */
3397  /* All commands yielding 2 results */
3398  /* All commands yielding 1 result */
3399  case OFDM_SC_RA_RAM_CMD_USER_IO:
3400  case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3401  status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3402  /* All commands yielding 0 results */
3403  case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3404  case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3405  case OFDM_SC_RA_RAM_CMD_PROC_START:
3406  case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3407  case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3408  case OFDM_SC_RA_RAM_CMD_NULL:
3409  break;
3410  default:
3411  /* Unknown command */
3412  status = -EINVAL;
3413  break;
3414  } /* switch (cmd->cmd) */
3415 error:
3416  if (status < 0)
3417  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3418  return status;
3419 }
3420 
3421 static int PowerUpDVBT(struct drxk_state *state)
3422 {
3423  enum DRXPowerMode powerMode = DRX_POWER_UP;
3424  int status;
3425 
3426  dprintk(1, "\n");
3427  status = CtrlPowerMode(state, &powerMode);
3428  if (status < 0)
3429  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3430  return status;
3431 }
3432 
3433 static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3434 {
3435  int status;
3436 
3437  dprintk(1, "\n");
3438  if (*enabled == true)
3439  status = write16(state, IQM_CF_BYPASSDET__A, 0);
3440  else
3441  status = write16(state, IQM_CF_BYPASSDET__A, 1);
3442  if (status < 0)
3443  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3444  return status;
3445 }
3446 
3447 #define DEFAULT_FR_THRES_8K 4000
3448 static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3449 {
3450 
3451  int status;
3452 
3453  dprintk(1, "\n");
3454  if (*enabled == true) {
3455  /* write mask to 1 */
3456  status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3457  DEFAULT_FR_THRES_8K);
3458  } else {
3459  /* write mask to 0 */
3460  status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3461  }
3462  if (status < 0)
3463  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3464 
3465  return status;
3466 }
3467 
3468 static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3469  struct DRXKCfgDvbtEchoThres_t *echoThres)
3470 {
3471  u16 data = 0;
3472  int status;
3473 
3474  dprintk(1, "\n");
3475  status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3476  if (status < 0)
3477  goto error;
3478 
3479  switch (echoThres->fftMode) {
3480  case DRX_FFTMODE_2K:
3481  data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3482  data |= ((echoThres->threshold <<
3483  OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3484  & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3485  break;
3486  case DRX_FFTMODE_8K:
3487  data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3488  data |= ((echoThres->threshold <<
3489  OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3490  & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3491  break;
3492  default:
3493  return -EINVAL;
3494  }
3495 
3496  status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3497 error:
3498  if (status < 0)
3499  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3500  return status;
3501 }
3502 
3503 static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3504  enum DRXKCfgDvbtSqiSpeed *speed)
3505 {
3506  int status = -EINVAL;
3507 
3508  dprintk(1, "\n");
3509 
3510  switch (*speed) {
3511  case DRXK_DVBT_SQI_SPEED_FAST:
3512  case DRXK_DVBT_SQI_SPEED_MEDIUM:
3513  case DRXK_DVBT_SQI_SPEED_SLOW:
3514  break;
3515  default:
3516  goto error;
3517  }
3518  status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3519  (u16) *speed);
3520 error:
3521  if (status < 0)
3522  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3523  return status;
3524 }
3525 
3526 /*============================================================================*/
3527 
3536 static int DVBTActivatePresets(struct drxk_state *state)
3537 {
3538  int status;
3539  bool setincenable = false;
3540  bool setfrenable = true;
3541 
3542  struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3543  struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3544 
3545  dprintk(1, "\n");
3546  status = DVBTCtrlSetIncEnable(state, &setincenable);
3547  if (status < 0)
3548  goto error;
3549  status = DVBTCtrlSetFrEnable(state, &setfrenable);
3550  if (status < 0)
3551  goto error;
3552  status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3553  if (status < 0)
3554  goto error;
3555  status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3556  if (status < 0)
3557  goto error;
3558  status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3559 error:
3560  if (status < 0)
3561  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3562  return status;
3563 }
3564 
3565 /*============================================================================*/
3566 
3575 static int SetDVBTStandard(struct drxk_state *state,
3576  enum OperationMode oMode)
3577 {
3578  u16 cmdResult = 0;
3579  u16 data = 0;
3580  int status;
3581 
3582  dprintk(1, "\n");
3583 
3584  PowerUpDVBT(state);
3585  /* added antenna switch */
3586  SwitchAntennaToDVBT(state);
3587  /* send OFDM reset command */
3588  status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3589  if (status < 0)
3590  goto error;
3591 
3592  /* send OFDM setenv command */
3593  status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3594  if (status < 0)
3595  goto error;
3596 
3597  /* reset datapath for OFDM, processors first */
3598  status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3599  if (status < 0)
3600  goto error;
3601  status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3602  if (status < 0)
3603  goto error;
3604  status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3605  if (status < 0)
3606  goto error;
3607 
3608  /* IQM setup */
3609  /* synchronize on ofdstate->m_festart */
3610  status = write16(state, IQM_AF_UPD_SEL__A, 1);
3611  if (status < 0)
3612  goto error;
3613  /* window size for clipping ADC detection */
3614  status = write16(state, IQM_AF_CLP_LEN__A, 0);
3615  if (status < 0)
3616  goto error;
3617  /* window size for for sense pre-SAW detection */
3618  status = write16(state, IQM_AF_SNS_LEN__A, 0);
3619  if (status < 0)
3620  goto error;
3621  /* sense threshold for sense pre-SAW detection */
3622  status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3623  if (status < 0)
3624  goto error;
3625  status = SetIqmAf(state, true);
3626  if (status < 0)
3627  goto error;
3628 
3629  status = write16(state, IQM_AF_AGC_RF__A, 0);
3630  if (status < 0)
3631  goto error;
3632 
3633  /* Impulse noise cruncher setup */
3634  status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3635  if (status < 0)
3636  goto error;
3637  status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3638  if (status < 0)
3639  goto error;
3640  status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3641  if (status < 0)
3642  goto error;
3643 
3644  status = write16(state, IQM_RC_STRETCH__A, 16);
3645  if (status < 0)
3646  goto error;
3647  status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3648  if (status < 0)
3649  goto error;
3650  status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3651  if (status < 0)
3652  goto error;
3653  status = write16(state, IQM_CF_SCALE__A, 1600);
3654  if (status < 0)
3655  goto error;
3656  status = write16(state, IQM_CF_SCALE_SH__A, 0);
3657  if (status < 0)
3658  goto error;
3659 
3660  /* virtual clipping threshold for clipping ADC detection */
3661  status = write16(state, IQM_AF_CLP_TH__A, 448);
3662  if (status < 0)
3663  goto error;
3664  status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3665  if (status < 0)
3666  goto error;
3667 
3668  status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3669  if (status < 0)
3670  goto error;
3671 
3672  status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3673  if (status < 0)
3674  goto error;
3675  status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3676  if (status < 0)
3677  goto error;
3678  /* enable power measurement interrupt */
3679  status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3680  if (status < 0)
3681  goto error;
3682  status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3683  if (status < 0)
3684  goto error;
3685 
3686  /* IQM will not be reset from here, sync ADC and update/init AGC */
3687  status = ADCSynchronization(state);
3688  if (status < 0)
3689  goto error;
3690  status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3691  if (status < 0)
3692  goto error;
3693 
3694  /* Halt SCU to enable safe non-atomic accesses */
3695  status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3696  if (status < 0)
3697  goto error;
3698 
3699  status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3700  if (status < 0)
3701  goto error;
3702  status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3703  if (status < 0)
3704  goto error;
3705 
3706  /* Set Noise Estimation notch width and enable DC fix */
3707  status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3708  if (status < 0)
3709  goto error;
3710  data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3711  status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3712  if (status < 0)
3713  goto error;
3714 
3715  /* Activate SCU to enable SCU commands */
3716  status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3717  if (status < 0)
3718  goto error;
3719 
3720  if (!state->m_DRXK_A3_ROM_CODE) {
3721  /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3722  status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3723  if (status < 0)
3724  goto error;
3725  }
3726 
3727  /* OFDM_SC setup */
3728 #ifdef COMPILE_FOR_NONRT
3729  status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3730  if (status < 0)
3731  goto error;
3732  status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3733  if (status < 0)
3734  goto error;
3735 #endif
3736 
3737  /* FEC setup */
3738  status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3739  if (status < 0)
3740  goto error;
3741 
3742 
3743 #ifdef COMPILE_FOR_NONRT
3744  status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3745  if (status < 0)
3746  goto error;
3747 #else
3748  status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3749  if (status < 0)
3750  goto error;
3751 #endif
3752  status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3753  if (status < 0)
3754  goto error;
3755 
3756  /* Setup MPEG bus */
3757  status = MPEGTSDtoSetup(state, OM_DVBT);
3758  if (status < 0)
3759  goto error;
3760  /* Set DVBT Presets */
3761  status = DVBTActivatePresets(state);
3762  if (status < 0)
3763  goto error;
3764 
3765 error:
3766  if (status < 0)
3767  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3768  return status;
3769 }
3770 
3771 /*============================================================================*/
3777 static int DVBTStart(struct drxk_state *state)
3778 {
3779  u16 param1;
3780  int status;
3781  /* DRXKOfdmScCmd_t scCmd; */
3782 
3783  dprintk(1, "\n");
3784  /* Start correct processes to get in lock */
3785  /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3786  param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3787  status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3788  if (status < 0)
3789  goto error;
3790  /* Start FEC OC */
3791  status = MPEGTSStart(state);
3792  if (status < 0)
3793  goto error;
3794  status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3795  if (status < 0)
3796  goto error;
3797 error:
3798  if (status < 0)
3799  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3800  return status;
3801 }
3802 
3803 
3804 /*============================================================================*/
3805 
3812 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3813  s32 tunerFreqOffset)
3814 {
3815  u16 cmdResult = 0;
3816  u16 transmissionParams = 0;
3817  u16 operationMode = 0;
3818  u32 iqmRcRateOfs = 0;
3819  u32 bandwidth = 0;
3820  u16 param1;
3821  int status;
3822 
3823  dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset);
3824 
3825  status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3826  if (status < 0)
3827  goto error;
3828 
3829  /* Halt SCU to enable safe non-atomic accesses */
3830  status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3831  if (status < 0)
3832  goto error;
3833 
3834  /* Stop processors */
3835  status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3836  if (status < 0)
3837  goto error;
3838  status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3839  if (status < 0)
3840  goto error;
3841 
3842  /* Mandatory fix, always stop CP, required to set spl offset back to
3843  hardware default (is set to 0 by ucode during pilot detection */
3844  status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3845  if (status < 0)
3846  goto error;
3847 
3848  /*== Write channel settings to device =====================================*/
3849 
3850  /* mode */
3851  switch (state->props.transmission_mode) {
3852  case TRANSMISSION_MODE_AUTO:
3853  default:
3854  operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3855  /* fall through , try first guess DRX_FFTMODE_8K */
3856  case TRANSMISSION_MODE_8K:
3857  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3858  break;
3859  case TRANSMISSION_MODE_2K:
3860  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3861  break;
3862  }
3863 
3864  /* guard */
3865  switch (state->props.guard_interval) {
3866  default:
3867  case GUARD_INTERVAL_AUTO:
3868  operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3869  /* fall through , try first guess DRX_GUARD_1DIV4 */
3870  case GUARD_INTERVAL_1_4:
3871  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3872  break;
3873  case GUARD_INTERVAL_1_32:
3874  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3875  break;
3876  case GUARD_INTERVAL_1_16:
3877  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3878  break;
3879  case GUARD_INTERVAL_1_8:
3880  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3881  break;
3882  }
3883 
3884  /* hierarchy */
3885  switch (state->props.hierarchy) {
3886  case HIERARCHY_AUTO:
3887  case HIERARCHY_NONE:
3888  default:
3889  operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3890  /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3891  /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3892  /* break; */
3893  case HIERARCHY_1:
3894  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3895  break;
3896  case HIERARCHY_2:
3897  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3898  break;
3899  case HIERARCHY_4:
3900  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3901  break;
3902  }
3903 
3904 
3905  /* modulation */
3906  switch (state->props.modulation) {
3907  case QAM_AUTO:
3908  default:
3909  operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3910  /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3911  case QAM_64:
3912  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3913  break;
3914  case QPSK:
3915  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3916  break;
3917  case QAM_16:
3918  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3919  break;
3920  }
3921 #if 0
3922  /* No hierachical channels support in BDA */
3923  /* Priority (only for hierarchical channels) */
3924  switch (channel->priority) {
3925  case DRX_PRIORITY_LOW:
3926  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3927  WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3928  OFDM_EC_SB_PRIOR_LO);
3929  break;
3930  case DRX_PRIORITY_HIGH:
3931  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3932  WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3933  OFDM_EC_SB_PRIOR_HI));
3934  break;
3935  case DRX_PRIORITY_UNKNOWN: /* fall through */
3936  default:
3937  status = -EINVAL;
3938  goto error;
3939  }
3940 #else
3941  /* Set Priorty high */
3942  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3943  status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3944  if (status < 0)
3945  goto error;
3946 #endif
3947 
3948  /* coderate */
3949  switch (state->props.code_rate_HP) {
3950  case FEC_AUTO:
3951  default:
3952  operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3953  /* fall through , try first guess DRX_CODERATE_2DIV3 */
3954  case FEC_2_3:
3955  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3956  break;
3957  case FEC_1_2:
3958  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3959  break;
3960  case FEC_3_4:
3961  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3962  break;
3963  case FEC_5_6:
3964  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3965  break;
3966  case FEC_7_8:
3967  transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3968  break;
3969  }
3970 
3971  /* SAW filter selection: normaly not necesarry, but if wanted
3972  the application can select a SAW filter via the driver by using UIOs */
3973  /* First determine real bandwidth (Hz) */
3974  /* Also set delay for impulse noise cruncher */
3975  /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3976  by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3977  functions */
3978  switch (state->props.bandwidth_hz) {
3979  case 0:
3980  state->props.bandwidth_hz = 8000000;
3981  /* fall though */
3982  case 8000000:
3983  bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3984  status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3985  if (status < 0)
3986  goto error;
3987  /* cochannel protection for PAL 8 MHz */
3988  status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3989  if (status < 0)
3990  goto error;
3991  status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3992  if (status < 0)
3993  goto error;
3994  status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3995  if (status < 0)
3996  goto error;
3997  status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3998  if (status < 0)
3999  goto error;
4000  break;
4001  case 7000000:
4002  bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
4003  status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
4004  if (status < 0)
4005  goto error;
4006  /* cochannel protection for PAL 7 MHz */
4007  status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
4008  if (status < 0)
4009  goto error;
4010  status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
4011  if (status < 0)
4012  goto error;
4013  status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
4014  if (status < 0)
4015  goto error;
4016  status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
4017  if (status < 0)
4018  goto error;
4019  break;
4020  case 6000000:
4021  bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
4022  status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
4023  if (status < 0)
4024  goto error;
4025  /* cochannel protection for NTSC 6 MHz */
4026  status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
4027  if (status < 0)
4028  goto error;
4029  status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
4030  if (status < 0)
4031  goto error;
4032  status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
4033  if (status < 0)
4034  goto error;
4035  status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
4036  if (status < 0)
4037  goto error;
4038  break;
4039  default:
4040  status = -EINVAL;
4041  goto error;
4042  }
4043 
4044  if (iqmRcRateOfs == 0) {
4045  /* Now compute IQM_RC_RATE_OFS
4046  (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
4047  =>
4048  ((SysFreq / BandWidth) * (2^21)) - (2^23)
4049  */
4050  /* (SysFreq / BandWidth) * (2^28) */
4051  /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
4052  => assert(MAX(sysClk) < 16*MIN(bandwidth))
4053  => assert(109714272 > 48000000) = true so Frac 28 can be used */
4054  iqmRcRateOfs = Frac28a((u32)
4055  ((state->m_sysClockFreq *
4056  1000) / 3), bandwidth);
4057  /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4058  if ((iqmRcRateOfs & 0x7fL) >= 0x40)
4059  iqmRcRateOfs += 0x80L;
4060  iqmRcRateOfs = iqmRcRateOfs >> 7;
4061  /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
4062  iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
4063  }
4064 
4065  iqmRcRateOfs &=
4066  ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4067  IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4068  status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
4069  if (status < 0)
4070  goto error;
4071 
4072  /* Bandwidth setting done */
4073 
4074 #if 0
4075  status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
4076  if (status < 0)
4077  goto error;
4078 #endif
4079  status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
4080  if (status < 0)
4081  goto error;
4082 
4083  /*== Start SC, write channel settings to SC ===============================*/
4084 
4085  /* Activate SCU to enable SCU commands */
4086  status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4087  if (status < 0)
4088  goto error;
4089 
4090  /* Enable SC after setting all other parameters */
4091  status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4092  if (status < 0)
4093  goto error;
4094  status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4095  if (status < 0)
4096  goto error;
4097 
4098 
4099  status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4100  if (status < 0)
4101  goto error;
4102 
4103  /* Write SC parameter registers, set all AUTO flags in operation mode */
4104  param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4105  OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4106  OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4107  OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4108  OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4109  status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4110  0, transmissionParams, param1, 0, 0, 0);
4111  if (status < 0)
4112  goto error;
4113 
4114  if (!state->m_DRXK_A3_ROM_CODE)
4115  status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4116 error:
4117  if (status < 0)
4118  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4119 
4120  return status;
4121 }
4122 
4123 
4124 /*============================================================================*/
4125 
4133 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4134 {
4135  int status;
4136  const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4137  OFDM_SC_RA_RAM_LOCK_FEC__M);
4138  const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4139  const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4140 
4141  u16 ScRaRamLock = 0;
4142  u16 ScCommExec = 0;
4143 
4144  dprintk(1, "\n");
4145 
4146  *pLockStatus = NOT_LOCKED;
4147  /* driver 0.9.0 */
4148  /* Check if SC is running */
4149  status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
4150  if (status < 0)
4151  goto end;
4152  if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
4153  goto end;
4154 
4155  status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
4156  if (status < 0)
4157  goto end;
4158 
4159  if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4160  *pLockStatus = MPEG_LOCK;
4161  else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
4162  *pLockStatus = FEC_LOCK;
4163  else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
4164  *pLockStatus = DEMOD_LOCK;
4165  else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4166  *pLockStatus = NEVER_LOCK;
4167 end:
4168  if (status < 0)
4169  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4170 
4171  return status;
4172 }
4173 
4174 static int PowerUpQAM(struct drxk_state *state)
4175 {
4176  enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
4177  int status;
4178 
4179  dprintk(1, "\n");
4180  status = CtrlPowerMode(state, &powerMode);
4181  if (status < 0)
4182  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4183 
4184  return status;
4185 }
4186 
4187 
4189 static int PowerDownQAM(struct drxk_state *state)
4190 {
4191  u16 data = 0;
4192  u16 cmdResult;
4193  int status = 0;
4194 
4195  dprintk(1, "\n");
4196  status = read16(state, SCU_COMM_EXEC__A, &data);
4197  if (status < 0)
4198  goto error;
4199  if (data == SCU_COMM_EXEC_ACTIVE) {
4200  /*
4201  STOP demodulator
4202  QAM and HW blocks
4203  */
4204  /* stop all comstate->m_exec */
4205  status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4206  if (status < 0)
4207  goto error;
4208  status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
4209  if (status < 0)
4210  goto error;
4211  }
4212  /* powerdown AFE */
4213  status = SetIqmAf(state, false);
4214 
4215 error:
4216  if (status < 0)
4217  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4218 
4219  return status;
4220 }
4221 
4222 /*============================================================================*/
4223 
4235 static int SetQAMMeasurement(struct drxk_state *state,
4236  enum EDrxkConstellation modulation,
4237  u32 symbolRate)
4238 {
4239  u32 fecBitsDesired = 0; /* BER accounting period */
4240  u32 fecRsPeriodTotal = 0; /* Total period */
4241  u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
4242  u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
4243  int status = 0;
4244 
4245  dprintk(1, "\n");
4246 
4247  fecRsPrescale = 1;
4248  /* fecBitsDesired = symbolRate [kHz] *
4249  FrameLenght [ms] *
4250  (modulation + 1) *
4251  SyncLoss (== 1) *
4252  ViterbiLoss (==1)
4253  */
4254  switch (modulation) {
4255  case DRX_CONSTELLATION_QAM16:
4256  fecBitsDesired = 4 * symbolRate;
4257  break;
4258  case DRX_CONSTELLATION_QAM32:
4259  fecBitsDesired = 5 * symbolRate;
4260  break;
4261  case DRX_CONSTELLATION_QAM64:
4262  fecBitsDesired = 6 * symbolRate;
4263  break;
4264  case DRX_CONSTELLATION_QAM128:
4265  fecBitsDesired = 7 * symbolRate;
4266  break;
4267  case DRX_CONSTELLATION_QAM256:
4268  fecBitsDesired = 8 * symbolRate;
4269  break;
4270  default:
4271  status = -EINVAL;
4272  }
4273  if (status < 0)
4274  goto error;
4275 
4276  fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4277  fecBitsDesired *= 500; /* meas. period [ms] */
4278 
4279  /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4280  /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4281  fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
4282 
4283  /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
4284  fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4285  if (fecRsPrescale == 0) {
4286  /* Divide by zero (though impossible) */
4287  status = -EINVAL;
4288  if (status < 0)
4289  goto error;
4290  }
4291  fecRsPeriod =
4292  ((u16) fecRsPeriodTotal +
4293  (fecRsPrescale >> 1)) / fecRsPrescale;
4294 
4295  /* write corresponding registers */
4296  status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
4297  if (status < 0)
4298  goto error;
4299  status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4300  if (status < 0)
4301  goto error;
4302  status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4303 error:
4304  if (status < 0)
4305  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4306  return status;
4307 }
4308 
4309 static int SetQAM16(struct drxk_state *state)
4310 {
4311  int status = 0;
4312 
4313  dprintk(1, "\n");
4314  /* QAM Equalizer Setup */
4315  /* Equalizer */
4316  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4317  if (status < 0)
4318  goto error;
4319  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4320  if (status < 0)
4321  goto error;
4322  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4323  if (status < 0)
4324  goto error;
4325  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4326  if (status < 0)
4327  goto error;
4328  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4329  if (status < 0)
4330  goto error;
4331  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4332  if (status < 0)
4333  goto error;
4334  /* Decision Feedback Equalizer */
4335  status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4336  if (status < 0)
4337  goto error;
4338  status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4339  if (status < 0)
4340  goto error;
4341  status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4342  if (status < 0)
4343  goto error;
4344  status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4345  if (status < 0)
4346  goto error;
4347  status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4348  if (status < 0)
4349  goto error;
4350  status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4351  if (status < 0)
4352  goto error;
4353 
4354  status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4355  if (status < 0)
4356  goto error;
4357  status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4358  if (status < 0)
4359  goto error;
4360  status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4361  if (status < 0)
4362  goto error;
4363 
4364  /* QAM Slicer Settings */
4365  status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4366  if (status < 0)
4367  goto error;
4368 
4369  /* QAM Loop Controller Coeficients */
4370  status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4371  if (status < 0)
4372  goto error;
4373  status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4374  if (status < 0)
4375  goto error;
4376  status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4377  if (status < 0)
4378  goto error;
4379  status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4380  if (status < 0)
4381  goto error;
4382  status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4383  if (status < 0)
4384  goto error;
4385  status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4386  if (status < 0)
4387  goto error;
4388  status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4389  if (status < 0)
4390  goto error;
4391  status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4392  if (status < 0)
4393  goto error;
4394 
4395  status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4396  if (status < 0)
4397  goto error;
4398  status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4399  if (status < 0)
4400  goto error;
4401  status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4402  if (status < 0)
4403  goto error;
4404  status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4405  if (status < 0)
4406  goto error;
4407  status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4408  if (status < 0)
4409  goto error;
4410  status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4411  if (status < 0)
4412  goto error;
4413  status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4414  if (status < 0)
4415  goto error;
4416  status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4417  if (status < 0)
4418  goto error;
4419  status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4420  if (status < 0)
4421  goto error;
4422  status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4423  if (status < 0)
4424  goto error;
4425  status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4426  if (status < 0)
4427  goto error;
4428  status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4429  if (status < 0)
4430  goto error;
4431 
4432 
4433  /* QAM State Machine (FSM) Thresholds */
4434 
4435  status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4436  if (status < 0)
4437  goto error;
4438  status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4439  if (status < 0)
4440  goto error;
4441  status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4442  if (status < 0)
4443  goto error;
4444  status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4445  if (status < 0)
4446  goto error;
4447  status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4448  if (status < 0)
4449  goto error;
4450  status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4451  if (status < 0)
4452  goto error;
4453 
4454  status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4455  if (status < 0)
4456  goto error;
4457  status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4458  if (status < 0)
4459  goto error;
4460  status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4461  if (status < 0)
4462  goto error;
4463 
4464 
4465  /* QAM FSM Tracking Parameters */
4466 
4467  status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4468  if (status < 0)
4469  goto error;
4470  status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4471  if (status < 0)
4472  goto error;
4473  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4474  if (status < 0)
4475  goto error;
4476  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4477  if (status < 0)
4478  goto error;
4479  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4480  if (status < 0)
4481  goto error;
4482  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4483  if (status < 0)
4484  goto error;
4485  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4486  if (status < 0)
4487  goto error;
4488 
4489 error:
4490  if (status < 0)
4491  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4492  return status;
4493 }
4494 
4495 /*============================================================================*/
4496 
4502 static int SetQAM32(struct drxk_state *state)
4503 {
4504  int status = 0;
4505 
4506  dprintk(1, "\n");
4507 
4508  /* QAM Equalizer Setup */
4509  /* Equalizer */
4510  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4511  if (status < 0)
4512  goto error;
4513  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4514  if (status < 0)
4515  goto error;
4516  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4517  if (status < 0)
4518  goto error;
4519  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4520  if (status < 0)
4521  goto error;
4522  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4523  if (status < 0)
4524  goto error;
4525  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4526  if (status < 0)
4527  goto error;
4528 
4529  /* Decision Feedback Equalizer */
4530  status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4531  if (status < 0)
4532  goto error;
4533  status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4534  if (status < 0)
4535  goto error;
4536  status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4537  if (status < 0)
4538  goto error;
4539  status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4540  if (status < 0)
4541  goto error;
4542  status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4543  if (status < 0)
4544  goto error;
4545  status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4546  if (status < 0)
4547  goto error;
4548 
4549  status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4550  if (status < 0)
4551  goto error;
4552  status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4553  if (status < 0)
4554  goto error;
4555  status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4556  if (status < 0)
4557  goto error;
4558 
4559  /* QAM Slicer Settings */
4560 
4561  status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4562  if (status < 0)
4563  goto error;
4564 
4565 
4566  /* QAM Loop Controller Coeficients */
4567 
4568  status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4569  if (status < 0)
4570  goto error;
4571  status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4572  if (status < 0)
4573  goto error;
4574  status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4575  if (status < 0)
4576  goto error;
4577  status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4578  if (status < 0)
4579  goto error;
4580  status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4581  if (status < 0)
4582  goto error;
4583  status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4584  if (status < 0)
4585  goto error;
4586  status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4587  if (status < 0)
4588  goto error;
4589  status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4590  if (status < 0)
4591  goto error;
4592 
4593  status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4594  if (status < 0)
4595  goto error;
4596  status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4597  if (status < 0)
4598  goto error;
4599  status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4600  if (status < 0)
4601  goto error;
4602  status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4603  if (status < 0)
4604  goto error;
4605  status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4606  if (status < 0)
4607  goto error;
4608  status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4609  if (status < 0)
4610  goto error;
4611  status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4612  if (status < 0)
4613  goto error;
4614  status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4615  if (status < 0)
4616  goto error;
4617  status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4618  if (status < 0)
4619  goto error;
4620  status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4621  if (status < 0)
4622  goto error;
4623  status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4624  if (status < 0)
4625  goto error;
4626  status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4627  if (status < 0)
4628  goto error;
4629 
4630 
4631  /* QAM State Machine (FSM) Thresholds */
4632 
4633  status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4634  if (status < 0)
4635  goto error;
4636  status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4637  if (status < 0)
4638  goto error;
4639  status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4640  if (status < 0)
4641  goto error;
4642  status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4643  if (status < 0)
4644  goto error;
4645  status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4646  if (status < 0)
4647  goto error;
4648  status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4649  if (status < 0)
4650  goto error;
4651 
4652  status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4653  if (status < 0)
4654  goto error;
4655  status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4656  if (status < 0)
4657  goto error;
4658  status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4659  if (status < 0)
4660  goto error;
4661 
4662 
4663  /* QAM FSM Tracking Parameters */
4664 
4665  status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4666  if (status < 0)
4667  goto error;
4668  status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4669  if (status < 0)
4670  goto error;
4671  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4672  if (status < 0)
4673  goto error;
4674  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4675  if (status < 0)
4676  goto error;
4677  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4678  if (status < 0)
4679  goto error;
4680  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4681  if (status < 0)
4682  goto error;
4683  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4684 error:
4685  if (status < 0)
4686  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4687  return status;
4688 }
4689 
4690 /*============================================================================*/
4691 
4697 static int SetQAM64(struct drxk_state *state)
4698 {
4699  int status = 0;
4700 
4701  dprintk(1, "\n");
4702  /* QAM Equalizer Setup */
4703  /* Equalizer */
4704  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4705  if (status < 0)
4706  goto error;
4707  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4708  if (status < 0)
4709  goto error;
4710  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4711  if (status < 0)
4712  goto error;
4713  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4714  if (status < 0)
4715  goto error;
4716  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4717  if (status < 0)
4718  goto error;
4719  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4720  if (status < 0)
4721  goto error;
4722 
4723  /* Decision Feedback Equalizer */
4724  status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4725  if (status < 0)
4726  goto error;
4727  status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4728  if (status < 0)
4729  goto error;
4730  status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4731  if (status < 0)
4732  goto error;
4733  status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4734  if (status < 0)
4735  goto error;
4736  status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4737  if (status < 0)
4738  goto error;
4739  status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4740  if (status < 0)
4741  goto error;
4742 
4743  status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4744  if (status < 0)
4745  goto error;
4746  status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4747  if (status < 0)
4748  goto error;
4749  status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4750  if (status < 0)
4751  goto error;
4752 
4753  /* QAM Slicer Settings */
4754  status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4755  if (status < 0)
4756  goto error;
4757 
4758 
4759  /* QAM Loop Controller Coeficients */
4760 
4761  status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4762  if (status < 0)
4763  goto error;
4764  status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4765  if (status < 0)
4766  goto error;
4767  status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4768  if (status < 0)
4769  goto error;
4770  status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4771  if (status < 0)
4772  goto error;
4773  status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4774  if (status < 0)
4775  goto error;
4776  status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4777  if (status < 0)
4778  goto error;
4779  status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4780  if (status < 0)
4781  goto error;
4782  status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4783  if (status < 0)
4784  goto error;
4785 
4786  status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4787  if (status < 0)
4788  goto error;
4789  status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4790  if (status < 0)
4791  goto error;
4792  status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4793  if (status < 0)
4794  goto error;
4795  status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4796  if (status < 0)
4797  goto error;
4798  status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4799  if (status < 0)
4800  goto error;
4801  status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4802  if (status < 0)
4803  goto error;
4804  status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4805  if (status < 0)
4806  goto error;
4807  status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4808  if (status < 0)
4809  goto error;
4810  status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4811  if (status < 0)
4812  goto error;
4813  status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4814  if (status < 0)
4815  goto error;
4816  status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4817  if (status < 0)
4818  goto error;
4819  status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4820  if (status < 0)
4821  goto error;
4822 
4823 
4824  /* QAM State Machine (FSM) Thresholds */
4825 
4826  status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4827  if (status < 0)
4828  goto error;
4829  status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4830  if (status < 0)
4831  goto error;
4832  status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4833  if (status < 0)
4834  goto error;
4835  status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4836  if (status < 0)
4837  goto error;
4838  status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4839  if (status < 0)
4840  goto error;
4841  status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4842  if (status < 0)
4843  goto error;
4844 
4845  status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4846  if (status < 0)
4847  goto error;
4848  status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4849  if (status < 0)
4850  goto error;
4851  status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4852  if (status < 0)
4853  goto error;
4854 
4855 
4856  /* QAM FSM Tracking Parameters */
4857 
4858  status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4859  if (status < 0)
4860  goto error;
4861  status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4862  if (status < 0)
4863  goto error;
4864  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4865  if (status < 0)
4866  goto error;
4867  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4868  if (status < 0)
4869  goto error;
4870  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4871  if (status < 0)
4872  goto error;
4873  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4874  if (status < 0)
4875  goto error;
4876  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4877 error:
4878  if (status < 0)
4879  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4880 
4881  return status;
4882 }
4883 
4884 /*============================================================================*/
4885 
4891 static int SetQAM128(struct drxk_state *state)
4892 {
4893  int status = 0;
4894 
4895  dprintk(1, "\n");
4896  /* QAM Equalizer Setup */
4897  /* Equalizer */
4898  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4899  if (status < 0)
4900  goto error;
4901  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4902  if (status < 0)
4903  goto error;
4904  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4905  if (status < 0)
4906  goto error;
4907  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4908  if (status < 0)
4909  goto error;
4910  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4911  if (status < 0)
4912  goto error;
4913  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4914  if (status < 0)
4915  goto error;
4916 
4917  /* Decision Feedback Equalizer */
4918  status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4919  if (status < 0)
4920  goto error;
4921  status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4922  if (status < 0)
4923  goto error;
4924  status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4925  if (status < 0)
4926  goto error;
4927  status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4928  if (status < 0)
4929  goto error;
4930  status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4931  if (status < 0)
4932  goto error;
4933  status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4934  if (status < 0)
4935  goto error;
4936 
4937  status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4938  if (status < 0)
4939  goto error;
4940  status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4941  if (status < 0)
4942  goto error;
4943  status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4944  if (status < 0)
4945  goto error;
4946 
4947 
4948  /* QAM Slicer Settings */
4949 
4950  status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4951  if (status < 0)
4952  goto error;
4953 
4954 
4955  /* QAM Loop Controller Coeficients */
4956 
4957  status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4958  if (status < 0)
4959  goto error;
4960  status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4961  if (status < 0)
4962  goto error;
4963  status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4964  if (status < 0)
4965  goto error;
4966  status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4967  if (status < 0)
4968  goto error;
4969  status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4970  if (status < 0)
4971  goto error;
4972  status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4973  if (status < 0)
4974  goto error;
4975  status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4976  if (status < 0)
4977  goto error;
4978  status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4979  if (status < 0)
4980  goto error;
4981 
4982  status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4983  if (status < 0)
4984  goto error;
4985  status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4986  if (status < 0)
4987  goto error;
4988  status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4989  if (status < 0)
4990  goto error;
4991  status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4992  if (status < 0)
4993  goto error;
4994  status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4995  if (status < 0)
4996  goto error;
4997  status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4998  if (status < 0)
4999  goto error;
5000  status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5001  if (status < 0)
5002  goto error;
5003  status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5004  if (status < 0)
5005  goto error;
5006  status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
5007  if (status < 0)
5008  goto error;
5009  status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5010  if (status < 0)
5011  goto error;
5012  status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5013  if (status < 0)
5014  goto error;
5015  status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
5016  if (status < 0)
5017  goto error;
5018 
5019 
5020  /* QAM State Machine (FSM) Thresholds */
5021 
5022  status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5023  if (status < 0)
5024  goto error;
5025  status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5026  if (status < 0)
5027  goto error;
5028  status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5029  if (status < 0)
5030  goto error;
5031  status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5032  if (status < 0)
5033  goto error;
5034  status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
5035  if (status < 0)
5036  goto error;
5037  status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5038  if (status < 0)
5039  goto error;
5040 
5041  status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5042  if (status < 0)
5043  goto error;
5044  status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5045  if (status < 0)
5046  goto error;
5047 
5048  status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5049  if (status < 0)
5050  goto error;
5051 
5052  /* QAM FSM Tracking Parameters */
5053 
5054  status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5055  if (status < 0)
5056  goto error;
5057  status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5058  if (status < 0)
5059  goto error;
5060  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5061  if (status < 0)
5062  goto error;
5063  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5064  if (status < 0)
5065  goto error;
5066  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5067  if (status < 0)
5068  goto error;
5069  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5070  if (status < 0)
5071  goto error;
5072  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5073 error:
5074  if (status < 0)
5075  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5076 
5077  return status;
5078 }
5079 
5080 /*============================================================================*/
5081 
5087 static int SetQAM256(struct drxk_state *state)
5088 {
5089  int status = 0;
5090 
5091  dprintk(1, "\n");
5092  /* QAM Equalizer Setup */
5093  /* Equalizer */
5094  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5095  if (status < 0)
5096  goto error;
5097  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5098  if (status < 0)
5099  goto error;
5100  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5101  if (status < 0)
5102  goto error;
5103  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5104  if (status < 0)
5105  goto error;
5106  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5107  if (status < 0)
5108  goto error;
5109  status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5110  if (status < 0)
5111  goto error;
5112 
5113  /* Decision Feedback Equalizer */
5114  status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5115  if (status < 0)
5116  goto error;
5117  status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5118  if (status < 0)
5119  goto error;
5120  status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5121  if (status < 0)
5122  goto error;
5123  status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5124  if (status < 0)
5125  goto error;
5126  status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5127  if (status < 0)
5128  goto error;
5129  status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5130  if (status < 0)
5131  goto error;
5132 
5133  status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5134  if (status < 0)
5135  goto error;
5136  status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5137  if (status < 0)
5138  goto error;
5139  status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5140  if (status < 0)
5141  goto error;
5142 
5143  /* QAM Slicer Settings */
5144 
5145  status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5146  if (status < 0)
5147  goto error;
5148 
5149 
5150  /* QAM Loop Controller Coeficients */
5151 
5152  status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5153  if (status < 0)
5154  goto error;
5155  status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5156  if (status < 0)
5157  goto error;
5158  status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5159  if (status < 0)
5160  goto error;
5161  status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5162  if (status < 0)
5163  goto error;
5164  status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5165  if (status < 0)
5166  goto error;
5167  status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5168  if (status < 0)
5169  goto error;
5170  status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5171  if (status < 0)
5172  goto error;
5173  status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5174  if (status < 0)
5175  goto error;
5176 
5177  status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5178  if (status < 0)
5179  goto error;
5180  status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5181  if (status < 0)
5182  goto error;
5183  status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5184  if (status < 0)
5185  goto error;
5186  status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5187  if (status < 0)
5188  goto error;
5189  status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5190  if (status < 0)
5191  goto error;
5192  status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5193  if (status < 0)
5194  goto error;
5195  status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5196  if (status < 0)
5197  goto error;
5198  status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5199  if (status < 0)
5200  goto error;
5201  status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5202  if (status < 0)
5203  goto error;
5204  status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5205  if (status < 0)
5206  goto error;
5207  status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5208  if (status < 0)
5209  goto error;
5210  status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5211  if (status < 0)
5212  goto error;
5213 
5214 
5215  /* QAM State Machine (FSM) Thresholds */
5216 
5217  status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5218  if (status < 0)
5219  goto error;
5220  status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5221  if (status < 0)
5222  goto error;
5223  status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5224  if (status < 0)
5225  goto error;
5226  status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5227  if (status < 0)
5228  goto error;
5229  status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5230  if (status < 0)
5231  goto error;
5232  status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5233  if (status < 0)
5234  goto error;
5235 
5236  status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5237  if (status < 0)
5238  goto error;
5239  status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5240  if (status < 0)
5241  goto error;
5242  status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5243  if (status < 0)
5244  goto error;
5245 
5246 
5247  /* QAM FSM Tracking Parameters */
5248 
5249  status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5250  if (status < 0)
5251  goto error;
5252  status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5253  if (status < 0)
5254  goto error;
5255  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5256  if (status < 0)
5257  goto error;
5258  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5259  if (status < 0)
5260  goto error;
5261  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5262  if (status < 0)
5263  goto error;
5264  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5265  if (status < 0)
5266  goto error;
5267  status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5268 error:
5269  if (status < 0)
5270  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5271  return status;
5272 }
5273 
5274 
5275 /*============================================================================*/
5282 static int QAMResetQAM(struct drxk_state *state)
5283 {
5284  int status;
5285  u16 cmdResult;
5286 
5287  dprintk(1, "\n");
5288  /* Stop QAM comstate->m_exec */
5289  status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5290  if (status < 0)
5291  goto error;
5292 
5293  status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5294 error:
5295  if (status < 0)
5296  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5297  return status;
5298 }
5299 
5300 /*============================================================================*/
5301 
5308 static int QAMSetSymbolrate(struct drxk_state *state)
5309 {
5310  u32 adcFrequency = 0;
5311  u32 symbFreq = 0;
5312  u32 iqmRcRate = 0;
5313  u16 ratesel = 0;
5314  u32 lcSymbRate = 0;
5315  int status;
5316 
5317  dprintk(1, "\n");
5318  /* Select & calculate correct IQM rate */
5319  adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5320  ratesel = 0;
5321  /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */
5322  if (state->props.symbol_rate <= 1188750)
5323  ratesel = 3;
5324  else if (state->props.symbol_rate <= 2377500)
5325  ratesel = 2;
5326  else if (state->props.symbol_rate <= 4755000)
5327  ratesel = 1;
5328  status = write16(state, IQM_FD_RATESEL__A, ratesel);
5329  if (status < 0)
5330  goto error;
5331 
5332  /*
5333  IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5334  */
5335  symbFreq = state->props.symbol_rate * (1 << ratesel);
5336  if (symbFreq == 0) {
5337  /* Divide by zero */
5338  status = -EINVAL;
5339  goto error;
5340  }
5341  iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5342  (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5343  (1 << 23);
5344  status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5345  if (status < 0)
5346  goto error;
5347  state->m_iqmRcRate = iqmRcRate;
5348  /*
5349  LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5350  */
5351  symbFreq = state->props.symbol_rate;
5352  if (adcFrequency == 0) {
5353  /* Divide by zero */
5354  status = -EINVAL;
5355  goto error;
5356  }
5357  lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5358  (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5359  16);
5360  if (lcSymbRate > 511)
5361  lcSymbRate = 511;
5362  status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5363 
5364 error:
5365  if (status < 0)
5366  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5367  return status;
5368 }
5369 
5370 /*============================================================================*/
5371 
5379 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5380 {
5381  int status;
5382  u16 Result[2] = { 0, 0 };
5383 
5384  dprintk(1, "\n");
5385  *pLockStatus = NOT_LOCKED;
5386  status = scu_command(state,
5387  SCU_RAM_COMMAND_STANDARD_QAM |
5388  SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5389  Result);
5390  if (status < 0)
5391  printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5392 
5393  if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5394  /* 0x0000 NOT LOCKED */
5395  } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5396  /* 0x4000 DEMOD LOCKED */
5397  *pLockStatus = DEMOD_LOCK;
5398  } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5399  /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5400  *pLockStatus = MPEG_LOCK;
5401  } else {
5402  /* 0xC000 NEVER LOCKED */
5403  /* (system will never be able to lock to the signal) */
5404  /* TODO: check this, intermediate & standard specific lock states are not
5405  taken into account here */
5406  *pLockStatus = NEVER_LOCK;
5407  }
5408  return status;
5409 }
5410 
5411 #define QAM_MIRROR__M 0x03
5412 #define QAM_MIRROR_NORMAL 0x00
5413 #define QAM_MIRRORED 0x01
5414 #define QAM_MIRROR_AUTO_ON 0x02
5415 #define QAM_LOCKRANGE__M 0x10
5416 #define QAM_LOCKRANGE_NORMAL 0x10
5417 
5418 static int QAMDemodulatorCommand(struct drxk_state *state,
5419  int numberOfParameters)
5420 {
5421  int status;
5422  u16 cmdResult;
5423  u16 setParamParameters[4] = { 0, 0, 0, 0 };
5424 
5425  setParamParameters[0] = state->m_Constellation; /* modulation */
5426  setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5427 
5428  if (numberOfParameters == 2) {
5429  u16 setEnvParameters[1] = { 0 };
5430 
5431  if (state->m_OperationMode == OM_QAM_ITU_C)
5432  setEnvParameters[0] = QAM_TOP_ANNEX_C;
5433  else
5434  setEnvParameters[0] = QAM_TOP_ANNEX_A;
5435 
5436  status = scu_command(state,
5437  SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5438  1, setEnvParameters, 1, &cmdResult);
5439  if (status < 0)
5440  goto error;
5441 
5442  status = scu_command(state,
5443  SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5444  numberOfParameters, setParamParameters,
5445  1, &cmdResult);
5446  } else if (numberOfParameters == 4) {
5447  if (state->m_OperationMode == OM_QAM_ITU_C)
5448  setParamParameters[2] = QAM_TOP_ANNEX_C;
5449  else
5450  setParamParameters[2] = QAM_TOP_ANNEX_A;
5451 
5452  setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5453  /* Env parameters */
5454  /* check for LOCKRANGE Extented */
5455  /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
5456 
5457  status = scu_command(state,
5458  SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5459  numberOfParameters, setParamParameters,
5460  1, &cmdResult);
5461  } else {
5462  printk(KERN_WARNING "drxk: Unknown QAM demodulator parameter "
5463  "count %d\n", numberOfParameters);
5464  }
5465 
5466 error:
5467  if (status < 0)
5468  printk(KERN_WARNING "drxk: Warning %d on %s\n",
5469  status, __func__);
5470  return status;
5471 }
5472 
5473 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5474  s32 tunerFreqOffset)
5475 {
5476  int status;
5477  u16 cmdResult;
5478  int qamDemodParamCount = state->qam_demod_parameter_count;
5479 
5480  dprintk(1, "\n");
5481  /*
5482  * STEP 1: reset demodulator
5483  * resets FEC DI and FEC RS
5484  * resets QAM block
5485  * resets SCU variables
5486  */
5487  status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5488  if (status < 0)
5489  goto error;
5490  status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5491  if (status < 0)
5492  goto error;
5493  status = QAMResetQAM(state);
5494  if (status < 0)
5495  goto error;
5496 
5497  /*
5498  * STEP 2: configure demodulator
5499  * -set params; resets IQM,QAM,FEC HW; initializes some
5500  * SCU variables
5501  */
5502  status = QAMSetSymbolrate(state);
5503  if (status < 0)
5504  goto error;
5505 
5506  /* Set params */
5507  switch (state->props.modulation) {
5508  case QAM_256:
5509  state->m_Constellation = DRX_CONSTELLATION_QAM256;
5510  break;
5511  case QAM_AUTO:
5512  case QAM_64:
5513  state->m_Constellation = DRX_CONSTELLATION_QAM64;
5514  break;
5515  case QAM_16:
5516  state->m_Constellation = DRX_CONSTELLATION_QAM16;
5517  break;
5518  case QAM_32:
5519  state->m_Constellation = DRX_CONSTELLATION_QAM32;
5520  break;
5521  case QAM_128:
5522  state->m_Constellation = DRX_CONSTELLATION_QAM128;
5523  break;
5524  default:
5525  status = -EINVAL;
5526  break;
5527  }
5528  if (status < 0)
5529  goto error;
5530 
5531  /* Use the 4-parameter if it's requested or we're probing for
5532  * the correct command. */
5533  if (state->qam_demod_parameter_count == 4
5534  || !state->qam_demod_parameter_count) {
5535  qamDemodParamCount = 4;
5536  status = QAMDemodulatorCommand(state, qamDemodParamCount);
5537  }
5538 
5539  /* Use the 2-parameter command if it was requested or if we're
5540  * probing for the correct command and the 4-parameter command
5541  * failed. */
5542  if (state->qam_demod_parameter_count == 2
5543  || (!state->qam_demod_parameter_count && status < 0)) {
5544  qamDemodParamCount = 2;
5545  status = QAMDemodulatorCommand(state, qamDemodParamCount);
5546  }
5547 
5548  if (status < 0) {
5549  dprintk(1, "Could not set demodulator parameters. Make "
5550  "sure qam_demod_parameter_count (%d) is correct for "
5551  "your firmware (%s).\n",
5552  state->qam_demod_parameter_count,
5553  state->microcode_name);
5554  goto error;
5555  } else if (!state->qam_demod_parameter_count) {
5556  dprintk(1, "Auto-probing the correct QAM demodulator command "
5557  "parameters was successful - using %d parameters.\n",
5558  qamDemodParamCount);
5559 
5560  /*
5561  * One of our commands was successful. We don't need to
5562  * auto-probe anymore, now that we got the correct command.
5563  */
5564  state->qam_demod_parameter_count = qamDemodParamCount;
5565  }
5566 
5567  /*
5568  * STEP 3: enable the system in a mode where the ADC provides valid
5569  * signal setup modulation independent registers
5570  */
5571 #if 0
5572  status = SetFrequency(channel, tunerFreqOffset));
5573  if (status < 0)
5574  goto error;
5575 #endif
5576  status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5577  if (status < 0)
5578  goto error;
5579 
5580  /* Setup BER measurement */
5581  status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate);
5582  if (status < 0)
5583  goto error;
5584 
5585  /* Reset default values */
5586  status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5587  if (status < 0)
5588  goto error;
5589  status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5590  if (status < 0)
5591  goto error;
5592 
5593  /* Reset default LC values */
5594  status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5595  if (status < 0)
5596  goto error;
5597  status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5598  if (status < 0)
5599  goto error;
5600  status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5601  if (status < 0)
5602  goto error;
5603  status = write16(state, QAM_LC_MODE__A, 7);
5604  if (status < 0)
5605  goto error;
5606 
5607  status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5608  if (status < 0)
5609  goto error;
5610  status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5611  if (status < 0)
5612