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8139too.c File Reference
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/rtnetlink.h>
#include <linux/delay.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/completion.h>
#include <linux/crc32.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/gfp.h>
#include <asm/irq.h>

Go to the source code of this file.

Data Structures

struct  rtl_extra_stats
 
struct  rtl8139_stats
 
struct  rtl8139_private
 

Macros

#define pr_fmt(fmt)   KBUILD_MODNAME ": " fmt
 
#define DRV_NAME   "8139too"
 
#define DRV_VERSION   "0.9.28"
 
#define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION
 
#define RTL8139_DEF_MSG_ENABLE
 
#define RTL8139_DEBUG   0
 
#define assert(expr)
 
#define MAX_UNITS   8
 
#define RX_BUF_IDX   2 /* 32K ring */
 
#define RX_BUF_LEN   (8192 << RX_BUF_IDX)
 
#define RX_BUF_PAD   16
 
#define RX_BUF_WRAP_PAD   2048 /* spare padding to handle lack of packet wrap */
 
#define RX_BUF_TOT_LEN   (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
 
#define NUM_TX_DESC   4
 
#define MAX_ETH_FRAME_SIZE   1536
 
#define TX_BUF_SIZE   MAX_ETH_FRAME_SIZE
 
#define TX_BUF_TOT_LEN   (TX_BUF_SIZE * NUM_TX_DESC)
 
#define TX_FIFO_THRESH   256 /* In bytes, rounded down to 32 byte units. */
 
#define RX_FIFO_THRESH   7 /* Rx buffer level before first PCI xfer. */
 
#define RX_DMA_BURST   7 /* Maximum PCI burst, '6' is 1024 */
 
#define TX_DMA_BURST   6 /* Maximum PCI burst, '6' is 1024 */
 
#define TX_RETRY   8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
 
#define TX_TIMEOUT   (6*HZ)
 
#define RTL_NUM_STATS   4 /* number of ETHTOOL_GSTATS u64's */
 
#define RTL_REGS_VER   1 /* version of reg. data in ETHTOOL_GREGS */
 
#define RTL_MIN_IO_SIZE   0x80
 
#define RTL8139B_IO_SIZE   256
 
#define RTL8129_CAPS   HAS_MII_XCVR
 
#define RTL8139_CAPS   (HAS_CHIP_XCVR|HAS_LNK_CHNG)
 
#define HW_REVID(b30, b29, b28, b27, b26, b23, b22)   (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
 
#define HW_REVID_MASK   HW_REVID(1, 1, 1, 1, 1, 1, 1)
 
#define RTL_W8_F(reg, val8)   do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
 
#define RTL_W16_F(reg, val16)   do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
 
#define RTL_W32_F(reg, val32)   do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
 
#define RTL_W8(reg, val8)   iowrite8 ((val8), ioaddr + (reg))
 
#define RTL_W16(reg, val16)   iowrite16 ((val16), ioaddr + (reg))
 
#define RTL_W32(reg, val32)   iowrite32 ((val32), ioaddr + (reg))
 
#define RTL_R8(reg)   ioread8 (ioaddr + (reg))
 
#define RTL_R16(reg)   ioread16 (ioaddr + (reg))
 
#define RTL_R32(reg)   ioread32 (ioaddr + (reg))
 
#define EE_SHIFT_CLK   0x04 /* EEPROM shift clock. */
 
#define EE_CS   0x08 /* EEPROM chip select. */
 
#define EE_DATA_WRITE   0x02 /* EEPROM chip data in. */
 
#define EE_WRITE_0   0x00
 
#define EE_WRITE_1   0x02
 
#define EE_DATA_READ   0x01 /* EEPROM chip data out. */
 
#define EE_ENB   (0x80 | EE_CS)
 
#define eeprom_delay()   (void)RTL_R8(Cfg9346)
 
#define EE_WRITE_CMD   (5)
 
#define EE_READ_CMD   (6)
 
#define EE_ERASE_CMD   (7)
 
#define MDIO_DIR   0x80
 
#define MDIO_DATA_OUT   0x04
 
#define MDIO_DATA_IN   0x02
 
#define MDIO_CLK   0x01
 
#define MDIO_WRITE0   (MDIO_DIR)
 
#define MDIO_WRITE1   (MDIO_DIR | MDIO_DATA_OUT)
 
#define mdio_delay()   RTL_R8(Config4)
 

Enumerations

enum  { HAS_MII_XCVR = 0x010000, HAS_CHIP_XCVR = 0x020000, HAS_LNK_CHNG = 0x040000 }
 
enum  board_t {
  BCM5706 = 0, NC370T, NC370I, BCM5706S,
  NC370F, BCM5708, BCM5708S, BCM5709,
  BCM5709S, BCM5716, BCM5716S, RTL8139 = 0,
  RTL8129, PXG2BPFI, PXG2BPFIL, PXG2BPFILX,
  PXG2BPFILLX, PXGBPI, PXGBPIG, PXG2TBFI,
  PXG4BPI, PXG4BPFI, PEG4BPI, PEG2BPI,
  PEG4BPIN, PEG2BPFI, PEG2BPFILX, PMCXG2BPFI,
  PMCXG2BPFIN, PEG4BPII, PEG4BPFII, PXG4BPFILX,
  PMCXG2BPIN, PMCXG4BPIN, PXG2BISC1, PEG2TBFI,
  PXG2TBI, PXG4BPFID, PEG4BPFI, PEG4BPIPT,
  PXG6BPI, PEG4BPIL, PMCXG2BPIN2, PMCXG4BPIN2,
  PMCX2BPI, PEG2BPFID, PEG2BPFIDLX, PMCX4BPI,
  MEG2BPFILN, MEG2BPFINX, PEG4BPFILX, PE10G2BPISR,
  PE10G2BPILR, MHIO8AD, PE10G2BPICX4, PEG2BPI5,
  PEG6BPI, PEG4BPFI5, PEG4BPFI5LX, MEG2BPFILXLN,
  PEG2BPIX1, MEG2BPFILXNX, XE10G2BPIT, XE10G2BPICX4,
  XE10G2BPISR, XE10G2BPILR, PEG4BPIIO, XE10G2BPIXR,
  PE10GDBISR, PE10GDBILR, PEG2BISC6, PEG6BPIFC,
  PE10G2BPTCX4, PE10G2BPTSR, PE10G2BPTLR, PE10G2BPTT,
  PEG4BPI6, PEG4BPFI6, PEG4BPFI6LX, PEG4BPFI6ZX,
  PEG2BPI6, PEG2BPFI6, PEG2BPFI6LX, PEG2BPFI6ZX,
  PEG2BPFI6FLXM, PEG4BPI6FC, PEG4BPFI6FC, PEG4BPFI6FCLX,
  PEG4BPFI6FCZX, PEG6BPI6, PEG2BPI6SC6, MEG2BPI6,
  XEG2BPI6, MEG4BPI6, PEG2BPFI5, PEG2BPFI5LX,
  PXEG4BPFI, M1EG2BPI6, M1EG2BPFI6, M1EG2BPFI6LX,
  M1EG2BPFI6ZX, M1EG4BPI6, M1EG4BPFI6, M1EG4BPFI6LX,
  M1EG4BPFI6ZX, M1EG6BPI6, M1E2G4BPi80, M1E2G4BPFi80,
  M1E2G4BPFi80LX, M1E2G4BPFi80ZX, PE210G2SPI9, M1E10G2BPI9CX4,
  M1E10G2BPI9SR, M1E10G2BPI9LR, M1E10G2BPI9T, PE210G2BPI9CX4,
  PE210G2BPI9SR, PE210G2BPI9LR, PE210G2BPI9T, M2EG2BPFI6,
  M2EG2BPFI6LX, M2EG2BPFI6ZX, M2EG4BPI6, M2EG4BPFI6,
  M2EG4BPFI6LX, M2EG4BPFI6ZX, M2EG6BPI6, PEG2DBI6,
  PEG2DBFI6, PEG2DBFI6LX, PEG2DBFI6ZX, PE2G4BPi80,
  PE2G4BPFi80, PE2G4BPFi80LX, PE2G4BPFi80ZX, PE2G4BPi80L,
  M6E2G8BPi80A, PE2G2BPi35, PAC1200BPi35, PE2G2BPFi35,
  PE2G2BPFi35LX, PE2G2BPFi35ZX, PE2G4BPi35, PE2G4BPi35L,
  PE2G4BPFi35, PE2G4BPFi35LX, PE2G4BPFi35ZX, PE2G6BPi35,
  PE2G6BPi35CX, PE2G2BPi80, PE2G2BPFi80, PE2G2BPFi80LX,
  PE2G2BPFi80ZX, M2E10G2BPI9CX4, M2E10G2BPI9SR, M2E10G2BPI9LR,
  M2E10G2BPI9T, M6E2G8BPi80, PE210G2DBi9SR, PE210G2DBi9SRRB,
  PE210G2DBi9LR, PE210G2DBi9LRRB, PE310G4DBi940SR, PE310G4BPi9T,
  PE310G4BPi9SR, PE310G4BPi9LR, PE210G2BPi40
}
 
enum  RTL8139_registers {
  MAC0 = 0, MAR0 = 8, TxStatus0 = 0x10, TxAddr0 = 0x20,
  RxBuf = 0x30, ChipCmd = 0x37, RxBufPtr = 0x38, RxBufAddr = 0x3A,
  IntrMask = 0x3C, IntrStatus = 0x3E, TxConfig = 0x40, RxConfig = 0x44,
  Timer = 0x48, RxMissed = 0x4C, Cfg9346 = 0x50, Config0 = 0x51,
  Config1 = 0x52, TimerInt = 0x54, MediaStatus = 0x58, Config3 = 0x59,
  Config4 = 0x5A, HltClk = 0x5B, MultiIntr = 0x5C, TxSummary = 0x60,
  BasicModeCtrl = 0x62, BasicModeStatus = 0x64, NWayAdvert = 0x66, NWayLPAR = 0x68,
  NWayExpansion = 0x6A, FIFOTMS = 0x70, CSCR = 0x74, PARA78 = 0x78,
  FlashReg = 0xD4, PARA7c = 0x7c, Config5 = 0xD8
}
 
enum  ClearBitMasks { MultiIntrClear = 0xF000, ChipCmdClear = 0xE2, Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1) }
 
enum  ChipCmdBits { CmdReset = 0x10, CmdRxEnb = 0x08, CmdTxEnb = 0x04, RxBufEmpty = 0x01 }
 
enum  IntrStatusBits {
  PCIErr = 0x8000, PCSTimeout = 0x4000, RxFIFOOver = 0x40, RxUnderrun = 0x20,
  RxOverflow = 0x10, TxErr = 0x08, TxOK = 0x04, RxErr = 0x02,
  RxOK = 0x01, RxAckBits = RxFIFOOver | RxOverflow | RxOK, LinkFail = 0x80000000, LinkOK = 0x40000000,
  TimeOut = 0x20000000, RxOverflow = 0x0040, RxOK = 0x0020, TxOK = 0x0001,
  IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK
}
 
enum  TxStatusBits {
  TxHostOwns = 0x2000, TxUnderrun = 0x4000, TxStatOK = 0x8000, TxOutOfWindow = 0x20000000,
  TxAborted = 0x40000000, TxCarrierLost = 0x80000000, TxCarrierLost = 0x20000000, TxAborted = 0x10000000,
  TxOutOfWindow = 0x08000000, TxNccShift = 22, EarlyTxThresShift = 16, TxStatOK = 0x8000,
  TxUnderrun = 0x4000, TxOwn = 0x2000
}
 
enum  RxStatusBits {
  RxMulticast = 0x8000, RxPhysical = 0x4000, RxBroadcast = 0x2000, RxBadSymbol = 0x0020,
  RxRunt = 0x0010, RxTooLong = 0x0008, RxCRCErr = 0x0004, RxBadAlign = 0x0002,
  RxStatusOK = 0x0001, RxStatesOK = 0x80000, RxBadAlign = 0x40000, RxHugeFrame = 0x20000,
  RxSmallFrame = 0x10000, RxCRCOK = 0x8000, RxCrlFrame = 0x4000, Rx_Broadcast = 0x2000,
  Rx_Multicast = 0x1000, RxAddrMatch = 0x0800, MiiErr = 0x0400
}
 
enum  rx_mode_bits {
  AcceptBroadcast =0x04, AcceptAllMulticast =0x02, AcceptAll =0x01, AcceptMulticast =0x10,
  PerfectFilter =0x40, HashFilter =0x30, PerfectFilterVlan =0x80, MinVLANPrio =0xE000,
  VlanMode =0x0200, WakeupOnGFP =0x0800, AcceptErr =0x80, RxAcceptBroadcast =0x20,
  AcceptMulticast =0x10, RxAcceptAllPhys =0x08, AcceptMyPhys =0x02, AcceptAllIPMulti =0x20,
  AcceptMultiHash =0x10, AcceptAll =0x08, AcceptBroadcast =0x04, AcceptMulticast =0x02,
  AcceptMyPhys =0x01, CR_W_ENH = 0x02000000, CR_W_FD = 0x00100000, CR_W_PS10 = 0x00080000,
  CR_W_TXEN = 0x00040000, CR_W_PS1000 = 0x00010000, CR_W_RXMODEMASK = 0x000000e0, CR_W_PROM = 0x00000080,
  CR_W_AB = 0x00000040, CR_W_AM = 0x00000020, CR_W_ARP = 0x00000008, CR_W_ALP = 0x00000004,
  CR_W_SEP = 0x00000002, CR_W_RXEN = 0x00000001, CR_R_TXSTOP = 0x04000000, CR_R_FD = 0x00100000,
  CR_R_PS10 = 0x00080000, CR_R_RXSTOP = 0x00008000, AcceptErr = 0x20, AcceptRunt = 0x10,
  AcceptBroadcast = 0x08, AcceptMulticast = 0x04, AcceptMyPhys = 0x02, AcceptAllPhys = 0x01
}
 
enum  tx_config_bits {
  TxIFGShift = 24, TxIFG84 = (0 << TxIFGShift), TxIFG88 = (1 << TxIFGShift), TxIFG92 = (2 << TxIFGShift),
  TxIFG96 = (3 << TxIFGShift), TxLoopBack = (1 << 18) | (1 << 17), TxCRC = (1 << 16), TxClearAbt = (1 << 0),
  TxDMAShift = 8, TxRetryShift = 4, TxVersionMask = 0x7C800000
}
 
enum  Config1Bits {
  Cfg1_PM_Enable = 0x01, Cfg1_VPD_Enable = 0x02, Cfg1_PIO = 0x04, Cfg1_MMIO = 0x08,
  LWAKE = 0x10, Cfg1_Driver_Load = 0x20, Cfg1_LED0 = 0x40, Cfg1_LED1 = 0x80,
  SLEEP = (1 << 1), PWRDN = (1 << 0), Cfg1_EarlyRx = 1 << 31, Cfg1_EarlyTx = 1 << 30,
  Cfg1_Rcv8K = 0x0, Cfg1_Rcv16K = 0x1, Cfg1_Rcv32K = 0x3, Cfg1_Rcv64K = 0x7,
  Cfg1_Rcv128K = 0xf
}
 
enum  Config3Bits {
  Cfg3_FBtBEn = (1 << 0), Cfg3_FuncRegEn = (1 << 1), Cfg3_CLKRUN_En = (1 << 2), Cfg3_CardB_En = (1 << 3),
  Cfg3_LinkUp = (1 << 4), Cfg3_Magic = (1 << 5), Cfg3_PARM_En = (1 << 6), Cfg3_GNTSel = (1 << 7)
}
 
enum  Config4Bits { LWPTN = (1 << 2) }
 
enum  Config5Bits {
  Cfg5_PME_STS = (1 << 0), Cfg5_LANWake = (1 << 1), Cfg5_LDPS = (1 << 2), Cfg5_FIFOAddrPtr = (1 << 3),
  Cfg5_UWF = (1 << 4), Cfg5_MWF = (1 << 5), Cfg5_BWF = (1 << 6)
}
 
enum  RxConfigBits {
  RxCfgFIFOShift = 13, RxCfgFIFONone = (7 << RxCfgFIFOShift), RxCfgDMAShift = 8, RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
  RxCfgRcv8K = 0, RxCfgRcv16K = (1 << 11), RxCfgRcv32K = (1 << 12), RxCfgRcv64K = (1 << 11) | (1 << 12),
  RxNoWrap = (1 << 7), RxFullDx = 0x80000000, RxEnb = 0x40000000, RxSmall = 0x20000000,
  RxHuge = 0x10000000, RxErr = 0x08000000, RxAllphys = 0x04000000, RxMulticast = 0x02000000,
  RxBroadcast = 0x01000000, RxLoopBack = (1 << 23) | (1 << 22), LowThresholdShift = 12, HighThresholdShift = 2
}
 
enum  CSCRBits {
  CSCR_LinkOKBit = 0x0400, CSCR_LinkChangeBit = 0x0800, CSCR_LinkStatusBits = 0x0f000, CSCR_LinkDownOffCmd = 0x003c0,
  CSCR_LinkDownCmd = 0x0f3c0
}
 
enum  Cfg9346Bits { Cfg9346_Lock = 0x00, Cfg9346_Unlock = 0xC0 }
 
enum  chip_t {
  CH_8139 = 0, CH_8139_K, CH_8139A, CH_8139A_G,
  CH_8139B, CH_8130, CH_8139C, CH_8100,
  CH_8100B_8139D, CH_8101, SMSC_83C170_0, SMSC_83C170,
  SMSC_83C175
}
 
enum  chip_flags { HasHltClk = (1 << 0), HasLWake = (1 << 1) }
 

Functions

 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl)
 
 MODULE_AUTHOR ("Jeff Garzik <[email protected]>")
 
 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver")
 
 MODULE_LICENSE ("GPL")
 
 MODULE_VERSION (DRV_VERSION)
 
 module_param (use_io, bool, 0)
 
 MODULE_PARM_DESC (use_io,"Force use of I/O access mode. 0=MMIO 1=PIO")
 
 module_param (multicast_filter_limit, int, 0)
 
 module_param_array (media, int, NULL, 0)
 
 module_param_array (full_duplex, int, NULL, 0)
 
 module_param (debug, int, 0)
 
 MODULE_PARM_DESC (debug,"8139too bitmapped message enable number")
 
 MODULE_PARM_DESC (multicast_filter_limit,"8139too maximum number of filtered multicast addresses")
 
 MODULE_PARM_DESC (media,"8139too: Bits 4+9: force full duplex, bit 5: 100Mbps")
 
 MODULE_PARM_DESC (full_duplex,"8139too: Force full duplex for board(s) (1)")
 
 module_init (rtl8139_init_module)
 
 module_exit (rtl8139_cleanup_module)
 

Macro Definition Documentation

#define assert (   expr)
Value:
if (unlikely(!(expr))) { \
pr_err("Assertion failed! %s,%s,%s,line=%d\n", \
#expr, __FILE__, __func__, __LINE__); \
}

Definition at line 135 of file 8139too.c.

#define DRV_NAME   "8139too"

Definition at line 94 of file 8139too.c.

#define DRV_VERSION   "0.9.28"

Definition at line 95 of file 8139too.c.

#define EE_CS   0x08 /* EEPROM chip select. */

Definition at line 1126 of file 8139too.c.

#define EE_DATA_READ   0x01 /* EEPROM chip data out. */

Definition at line 1130 of file 8139too.c.

#define EE_DATA_WRITE   0x02 /* EEPROM chip data in. */

Definition at line 1127 of file 8139too.c.

#define EE_ENB   (0x80 | EE_CS)

Definition at line 1131 of file 8139too.c.

#define EE_ERASE_CMD   (7)

Definition at line 1142 of file 8139too.c.

#define EE_READ_CMD   (6)

Definition at line 1141 of file 8139too.c.

#define EE_SHIFT_CLK   0x04 /* EEPROM shift clock. */

Definition at line 1125 of file 8139too.c.

#define EE_WRITE_0   0x00

Definition at line 1128 of file 8139too.c.

#define EE_WRITE_1   0x02

Definition at line 1129 of file 8139too.c.

#define EE_WRITE_CMD   (5)

Definition at line 1140 of file 8139too.c.

#define eeprom_delay (   void)    (void)RTL_R8(Cfg9346)

Definition at line 1137 of file 8139too.c.

#define HW_REVID (   b30,
  b29,
  b28,
  b27,
  b26,
  b23,
  b22 
)    (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

Definition at line 499 of file 8139too.c.

#define HW_REVID_MASK   HW_REVID(1, 1, 1, 1, 1, 1, 1)

Definition at line 501 of file 8139too.c.

#define MAX_ETH_FRAME_SIZE   1536

Definition at line 186 of file 8139too.c.

#define MAX_UNITS   8

Definition at line 145 of file 8139too.c.

#define MDIO_CLK   0x01

Definition at line 1191 of file 8139too.c.

#define MDIO_DATA_IN   0x02

Definition at line 1190 of file 8139too.c.

#define MDIO_DATA_OUT   0x04

Definition at line 1189 of file 8139too.c.

#define mdio_delay ( )    RTL_R8(Config4)

Definition at line 1195 of file 8139too.c.

#define MDIO_DIR   0x80

Definition at line 1188 of file 8139too.c.

#define MDIO_WRITE0   (MDIO_DIR)

Definition at line 1192 of file 8139too.c.

#define MDIO_WRITE1   (MDIO_DIR | MDIO_DATA_OUT)

Definition at line 1193 of file 8139too.c.

#define NUM_TX_DESC   4

Definition at line 183 of file 8139too.c.

#define pr_fmt (   fmt)    KBUILD_MODNAME ": " fmt

Definition at line 92 of file 8139too.c.

#define RTL8129_CAPS   HAS_MII_XCVR

Definition at line 218 of file 8139too.c.

#define RTL8139_CAPS   (HAS_CHIP_XCVR|HAS_LNK_CHNG)

Definition at line 219 of file 8139too.c.

#define RTL8139_DEBUG   0

Definition at line 126 of file 8139too.c.

#define RTL8139_DEF_MSG_ENABLE
Value:
NETIF_MSG_PROBE | \
NETIF_MSG_LINK)

Definition at line 120 of file 8139too.c.

#define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION

Definition at line 117 of file 8139too.c.

#define RTL8139B_IO_SIZE   256

Definition at line 216 of file 8139too.c.

#define RTL_MIN_IO_SIZE   0x80

Definition at line 215 of file 8139too.c.

#define RTL_NUM_STATS   4 /* number of ETHTOOL_GSTATS u64's */

Definition at line 213 of file 8139too.c.

#define RTL_R16 (   reg)    ioread16 (ioaddr + (reg))

Definition at line 675 of file 8139too.c.

#define RTL_R32 (   reg)    ioread32 (ioaddr + (reg))

Definition at line 676 of file 8139too.c.

#define RTL_R8 (   reg)    ioread8 (ioaddr + (reg))

Definition at line 674 of file 8139too.c.

#define RTL_REGS_VER   1 /* version of reg. data in ETHTOOL_GREGS */

Definition at line 214 of file 8139too.c.

#define RTL_W16 (   reg,
  val16 
)    iowrite16 ((val16), ioaddr + (reg))

Definition at line 670 of file 8139too.c.

#define RTL_W16_F (   reg,
  val16 
)    do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)

Definition at line 665 of file 8139too.c.

#define RTL_W32 (   reg,
  val32 
)    iowrite32 ((val32), ioaddr + (reg))

Definition at line 671 of file 8139too.c.

#define RTL_W32_F (   reg,
  val32 
)    do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)

Definition at line 666 of file 8139too.c.

#define RTL_W8 (   reg,
  val8 
)    iowrite8 ((val8), ioaddr + (reg))

Definition at line 669 of file 8139too.c.

#define RTL_W8_F (   reg,
  val8 
)    do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)

Definition at line 664 of file 8139too.c.

#define RX_BUF_IDX   2 /* 32K ring */

Definition at line 170 of file 8139too.c.

#define RX_BUF_LEN   (8192 << RX_BUF_IDX)

Definition at line 172 of file 8139too.c.

#define RX_BUF_PAD   16

Definition at line 173 of file 8139too.c.

#define RX_BUF_TOT_LEN   (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

Definition at line 179 of file 8139too.c.

#define RX_BUF_WRAP_PAD   2048 /* spare padding to handle lack of packet wrap */

Definition at line 174 of file 8139too.c.

#define RX_DMA_BURST   7 /* Maximum PCI burst, '6' is 1024 */

Definition at line 198 of file 8139too.c.

#define RX_FIFO_THRESH   7 /* Rx buffer level before first PCI xfer. */

Definition at line 197 of file 8139too.c.

#define TX_BUF_SIZE   MAX_ETH_FRAME_SIZE

Definition at line 189 of file 8139too.c.

#define TX_BUF_TOT_LEN   (TX_BUF_SIZE * NUM_TX_DESC)

Definition at line 190 of file 8139too.c.

#define TX_DMA_BURST   6 /* Maximum PCI burst, '6' is 1024 */

Definition at line 199 of file 8139too.c.

#define TX_FIFO_THRESH   256 /* In bytes, rounded down to 32 byte units. */

Definition at line 194 of file 8139too.c.

#define TX_RETRY   8 /* 0-15. retries = 16 + (TX_RETRY * 16) */

Definition at line 200 of file 8139too.c.

#define TX_TIMEOUT   (6*HZ)

Definition at line 204 of file 8139too.c.

Enumeration Type Documentation

anonymous enum
Enumerator:
HAS_MII_XCVR 
HAS_CHIP_XCVR 
HAS_LNK_CHNG 

Definition at line 207 of file 8139too.c.

enum board_t
Enumerator:
BCM5706 
NC370T 
NC370I 
BCM5706S 
NC370F 
BCM5708 
BCM5708S 
BCM5709 
BCM5709S 
BCM5716 
BCM5716S 
RTL8139 
RTL8129 
PXG2BPFI 
PXG2BPFIL 
PXG2BPFILX 
PXG2BPFILLX 
PXGBPI 
PXGBPIG 
PXG2TBFI 
PXG4BPI 
PXG4BPFI 
PEG4BPI 
PEG2BPI 
PEG4BPIN 
PEG2BPFI 
PEG2BPFILX 
PMCXG2BPFI 
PMCXG2BPFIN 
PEG4BPII 
PEG4BPFII 
PXG4BPFILX 
PMCXG2BPIN 
PMCXG4BPIN 
PXG2BISC1 
PEG2TBFI 
PXG2TBI 
PXG4BPFID 
PEG4BPFI 
PEG4BPIPT 
PXG6BPI 
PEG4BPIL 
PMCXG2BPIN2 
PMCXG4BPIN2 
PMCX2BPI 
PEG2BPFID 
PEG2BPFIDLX 
PMCX4BPI 
MEG2BPFILN 
MEG2BPFINX 
PEG4BPFILX 
PE10G2BPISR 
PE10G2BPILR 
MHIO8AD 
PE10G2BPICX4 
PEG2BPI5 
PEG6BPI 
PEG4BPFI5 
PEG4BPFI5LX 
MEG2BPFILXLN 
PEG2BPIX1 
MEG2BPFILXNX 
XE10G2BPIT 
XE10G2BPICX4 
XE10G2BPISR 
XE10G2BPILR 
PEG4BPIIO 
XE10G2BPIXR 
PE10GDBISR 
PE10GDBILR 
PEG2BISC6 
PEG6BPIFC 
PE10G2BPTCX4 
PE10G2BPTSR 
PE10G2BPTLR 
PE10G2BPTT 
PEG4BPI6 
PEG4BPFI6 
PEG4BPFI6LX 
PEG4BPFI6ZX 
PEG2BPI6 
PEG2BPFI6 
PEG2BPFI6LX 
PEG2BPFI6ZX 
PEG2BPFI6FLXM 
PEG4BPI6FC 
PEG4BPFI6FC 
PEG4BPFI6FCLX 
PEG4BPFI6FCZX 
PEG6BPI6 
PEG2BPI6SC6 
MEG2BPI6 
XEG2BPI6 
MEG4BPI6 
PEG2BPFI5 
PEG2BPFI5LX 
PXEG4BPFI 
M1EG2BPI6 
M1EG2BPFI6 
M1EG2BPFI6LX 
M1EG2BPFI6ZX 
M1EG4BPI6 
M1EG4BPFI6 
M1EG4BPFI6LX 
M1EG4BPFI6ZX 
M1EG6BPI6 
M1E2G4BPi80 
M1E2G4BPFi80 
M1E2G4BPFi80LX 
M1E2G4BPFi80ZX 
PE210G2SPI9 
M1E10G2BPI9CX4 
M1E10G2BPI9SR 
M1E10G2BPI9LR 
M1E10G2BPI9T 
PE210G2BPI9CX4 
PE210G2BPI9SR 
PE210G2BPI9LR 
PE210G2BPI9T 
M2EG2BPFI6 
M2EG2BPFI6LX 
M2EG2BPFI6ZX 
M2EG4BPI6 
M2EG4BPFI6 
M2EG4BPFI6LX 
M2EG4BPFI6ZX 
M2EG6BPI6 
PEG2DBI6 
PEG2DBFI6 
PEG2DBFI6LX 
PEG2DBFI6ZX 
PE2G4BPi80 
PE2G4BPFi80 
PE2G4BPFi80LX 
PE2G4BPFi80ZX 
PE2G4BPi80L 
M6E2G8BPi80A 
PE2G2BPi35 
PAC1200BPi35 
PE2G2BPFi35 
PE2G2BPFi35LX 
PE2G2BPFi35ZX 
PE2G4BPi35 
PE2G4BPi35L 
PE2G4BPFi35 
PE2G4BPFi35LX 
PE2G4BPFi35ZX 
PE2G6BPi35 
PE2G6BPi35CX 
PE2G2BPi80 
PE2G2BPFi80 
PE2G2BPFi80LX 
PE2G2BPFi80ZX 
M2E10G2BPI9CX4 
M2E10G2BPI9SR 
M2E10G2BPI9LR 
M2E10G2BPI9T 
M6E2G8BPi80 
PE210G2DBi9SR 
PE210G2DBi9SRRB 
PE210G2DBi9LR 
PE210G2DBi9LRRB 
PE310G4DBi940SR 
PE310G4BPi9T 
PE310G4BPi9SR 
PE310G4BPi9LR 
PE210G2BPi40 

Definition at line 221 of file 8139too.c.

Enumerator:
Cfg9346_Lock 
Cfg9346_Unlock 

Definition at line 476 of file 8139too.c.

enum chip_flags
Enumerator:
HasHltClk 
HasLWake 

Definition at line 494 of file 8139too.c.

enum chip_t
Enumerator:
CH_8139 
CH_8139_K 
CH_8139A 
CH_8139A_G 
CH_8139B 
CH_8130 
CH_8139C 
CH_8100 
CH_8100B_8139D 
CH_8101 
SMSC_83C170_0 
SMSC_83C170 
SMSC_83C175 

Definition at line 481 of file 8139too.c.

Enumerator:
CmdReset 
CmdRxEnb 
CmdTxEnb 
RxBufEmpty 

Definition at line 335 of file 8139too.c.

Enumerator:
MultiIntrClear 
ChipCmdClear 
Config1Clear 

Definition at line 329 of file 8139too.c.

Enumerator:
Cfg1_PM_Enable 
Cfg1_VPD_Enable 
Cfg1_PIO 
Cfg1_MMIO 
LWAKE 
Cfg1_Driver_Load 
Cfg1_LED0 
Cfg1_LED1 
SLEEP 
PWRDN 
Cfg1_EarlyRx 
Cfg1_EarlyTx 
Cfg1_Rcv8K 
Cfg1_Rcv16K 
Cfg1_Rcv32K 
Cfg1_Rcv64K 
Cfg1_Rcv128K 

Definition at line 406 of file 8139too.c.

Enumerator:
Cfg3_FBtBEn 
Cfg3_FuncRegEn 
Cfg3_CLKRUN_En 
Cfg3_CardB_En 
Cfg3_LinkUp 
Cfg3_Magic 
Cfg3_PARM_En 
Cfg3_GNTSel 

Definition at line 420 of file 8139too.c.

Enumerator:
LWPTN 

Definition at line 432 of file 8139too.c.

Enumerator:
Cfg5_PME_STS 
Cfg5_LANWake 
Cfg5_LDPS 
Cfg5_FIFOAddrPtr 
Cfg5_UWF 
Cfg5_MWF 
Cfg5_BWF 

Definition at line 437 of file 8139too.c.

enum CSCRBits
Enumerator:
CSCR_LinkOKBit 
CSCR_LinkChangeBit 
CSCR_LinkStatusBits 
CSCR_LinkDownOffCmd 
CSCR_LinkDownCmd 

Definition at line 468 of file 8139too.c.

Enumerator:
PCIErr 
PCSTimeout 
RxFIFOOver 
RxUnderrun 
RxOverflow 
TxErr 
TxOK 
RxErr 
RxOK 
RxAckBits 
LinkFail 
LinkOK 
TimeOut 
RxOverflow 
RxOK 
TxOK 
IntrBits 

Definition at line 343 of file 8139too.c.

Enumerator:
MAC0 
MAR0 
TxStatus0 
TxAddr0 
RxBuf 
ChipCmd 
RxBufPtr 
RxBufAddr 
IntrMask 
IntrStatus 
TxConfig 
RxConfig 
Timer 
RxMissed 
Cfg9346 
Config0 
Config1 
TimerInt 
MediaStatus 
Config3 
Config4 
HltClk 
MultiIntr 
TxSummary 
BasicModeCtrl 
BasicModeStatus 
NWayAdvert 
NWayLPAR 
NWayExpansion 
FIFOTMS 
CSCR 
PARA78 
FlashReg 
PARA7c 
Config5 

Definition at line 290 of file 8139too.c.

Enumerator:
AcceptBroadcast 
AcceptAllMulticast 
AcceptAll 
AcceptMulticast 
PerfectFilter 
HashFilter 
PerfectFilterVlan 
MinVLANPrio 
VlanMode 
WakeupOnGFP 
AcceptErr 
RxAcceptBroadcast 
AcceptMulticast 
RxAcceptAllPhys 
AcceptMyPhys 
AcceptAllIPMulti 
AcceptMultiHash 
AcceptAll 
AcceptBroadcast 
AcceptMulticast 
AcceptMyPhys 
CR_W_ENH 
CR_W_FD 
CR_W_PS10 
CR_W_TXEN 
CR_W_PS1000 
CR_W_RXMODEMASK 
CR_W_PROM 
CR_W_AB 
CR_W_AM 
CR_W_ARP 
CR_W_ALP 
CR_W_SEP 
CR_W_RXEN 
CR_R_TXSTOP 
CR_R_FD 
CR_R_PS10 
CR_R_RXSTOP 
AcceptErr 
AcceptRunt 
AcceptBroadcast 
AcceptMulticast 
AcceptMyPhys 
AcceptAllPhys 

Definition at line 378 of file 8139too.c.

Enumerator:
RxCfgFIFOShift 
RxCfgFIFONone 
RxCfgDMAShift 
RxCfgDMAUnlimited 
RxCfgRcv8K 
RxCfgRcv16K 
RxCfgRcv32K 
RxCfgRcv64K 
RxNoWrap 
RxFullDx 
RxEnb 
RxSmall 
RxHuge 
RxErr 
RxAllphys 
RxMulticast 
RxBroadcast 
RxLoopBack 
LowThresholdShift 
HighThresholdShift 

Definition at line 447 of file 8139too.c.

Enumerator:
RxMulticast 
RxPhysical 
RxBroadcast 
RxBadSymbol 
RxRunt 
RxTooLong 
RxCRCErr 
RxBadAlign 
RxStatusOK 
RxStatesOK 
RxBadAlign 
RxHugeFrame 
RxSmallFrame 
RxCRCOK 
RxCrlFrame 
Rx_Broadcast 
Rx_Multicast 
RxAddrMatch 
MiiErr 

Definition at line 365 of file 8139too.c.

Enumerator:
TxIFGShift 
TxIFG84 
TxIFG88 
TxIFG92 
TxIFG96 
TxLoopBack 
TxCRC 
TxClearAbt 
TxDMAShift 
TxRetryShift 
TxVersionMask 

Definition at line 388 of file 8139too.c.

Enumerator:
TxHostOwns 
TxUnderrun 
TxStatOK 
TxOutOfWindow 
TxAborted 
TxCarrierLost 
TxCarrierLost 
TxAborted 
TxOutOfWindow 
TxNccShift 
EarlyTxThresShift 
TxStatOK 
TxUnderrun 
TxOwn 

Definition at line 357 of file 8139too.c.

Function Documentation

MODULE_AUTHOR ( "Jeff Garzik <[email protected]>"  )
MODULE_DESCRIPTION ( "RealTek RTL-8139 Fast Ethernet driver )
MODULE_DEVICE_TABLE ( pci  ,
rtl8139_pci_tbl   
)
module_exit ( rtl8139_cleanup_module  )
module_init ( rtl8139_init_module  )
MODULE_LICENSE ( "GPL"  )
module_param ( use_io  ,
bool  ,
 
)
module_param ( multicast_filter_limit  ,
int  ,
 
)
module_param ( debug  ,
int  ,
 
)
module_param_array ( media  ,
int  ,
NULL  ,
 
)
module_param_array ( full_duplex  ,
int  ,
NULL  ,
 
)
MODULE_PARM_DESC ( use_io  )
MODULE_PARM_DESC ( debug  ,
"8139too bitmapped message enable number"   
)
MODULE_PARM_DESC ( multicast_filter_limit  ,
"8139too maximum number of filtered multicast addresses"   
)
MODULE_PARM_DESC ( media  ,
"8139too: Bits 4+9: force full  duplex,
bit 5:100Mbps"   
)
MODULE_PARM_DESC ( full_duplex  ,
"8139too: Force full duplex for board(s) (1)"   
)
MODULE_VERSION ( DRV_VERSION  )

Variable Documentation

u32 flags

Definition at line 507 of file 8139too.c.

u32 hw_flags

Definition at line 230 of file 8139too.c.

const char* name

Definition at line 229 of file 8139too.c.

Definition at line 279 of file 8139too.c.

u32 version

Definition at line 506 of file 8139too.c.