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fealnx.c
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1 /*
2  Written 1998-2000 by Donald Becker.
3 
4  This software may be used and distributed according to the terms of
5  the GNU General Public License (GPL), incorporated herein by reference.
6  Drivers based on or derived from this code fall under the GPL and must
7  retain the authorship, copyright and license notice. This file is not
8  a complete program and may only be used when the entire operating
9  system is licensed under the GPL.
10 
11  The author may be reached as [email protected], or C/O
12  Scyld Computing Corporation
13  410 Severn Ave., Suite 210
14  Annapolis MD 21403
15 
16  Support information and updates available at
17  http://www.scyld.com/network/pci-skeleton.html
18 
19  Linux kernel updates:
20 
21  Version 2.51, Nov 17, 2001 (jgarzik):
22  - Add ethtool support
23  - Replace some MII-related magic numbers with constants
24 
25 */
26 
27 #define DRV_NAME "fealnx"
28 #define DRV_VERSION "2.52"
29 #define DRV_RELDATE "Sep-11-2006"
30 
31 static int debug; /* 1-> print debug message */
32 static int max_interrupt_work = 20;
33 
34 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
35 static int multicast_filter_limit = 32;
36 
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. */
38 /* Setting to > 1518 effectively disables this feature. */
39 static int rx_copybreak;
40 
41 /* Used to pass the media type, etc. */
42 /* Both 'options[]' and 'full_duplex[]' should exist for driver */
43 /* interoperability. */
44 /* The media type is usually passed in 'options[]'. */
45 #define MAX_UNITS 8 /* More are supported, limit only on options */
46 static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
47 static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
48 
49 /* Operational parameters that are set at compile time. */
50 /* Keep the ring sizes a power of two for compile efficiency. */
51 /* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */
52 /* Making the Tx ring too large decreases the effectiveness of channel */
53 /* bonding and packet priority. */
54 /* There are no ill effects from too-large receive rings. */
55 // 88-12-9 modify,
56 // #define TX_RING_SIZE 16
57 // #define RX_RING_SIZE 32
58 #define TX_RING_SIZE 6
59 #define RX_RING_SIZE 12
60 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc)
61 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc)
62 
63 /* Operational parameters that usually are not changed. */
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (2*HZ)
66 
67 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
68 
69 
70 /* Include files, designed to support most kernel versions 2.0.0 and later. */
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/string.h>
74 #include <linux/timer.h>
75 #include <linux/errno.h>
76 #include <linux/ioport.h>
77 #include <linux/interrupt.h>
78 #include <linux/pci.h>
79 #include <linux/netdevice.h>
80 #include <linux/etherdevice.h>
81 #include <linux/skbuff.h>
82 #include <linux/init.h>
83 #include <linux/mii.h>
84 #include <linux/ethtool.h>
85 #include <linux/crc32.h>
86 #include <linux/delay.h>
87 #include <linux/bitops.h>
88 
89 #include <asm/processor.h> /* Processor type for cache alignment. */
90 #include <asm/io.h>
91 #include <asm/uaccess.h>
92 #include <asm/byteorder.h>
93 
94 /* These identify the driver base version and may not be removed. */
95 static const char version[] __devinitconst =
96  KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
97 
98 
99 /* This driver was written to use PCI memory space, however some x86 systems
100  work only with I/O space accesses. */
101 #ifndef __alpha__
102 #define USE_IO_OPS
103 #endif
104 
105 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
106 /* This is only in the support-all-kernels source code. */
107 
108 #define RUN_AT(x) (jiffies + (x))
109 
110 MODULE_AUTHOR("Myson or whoever");
111 MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver");
112 MODULE_LICENSE("GPL");
113 module_param(max_interrupt_work, int, 0);
114 module_param(debug, int, 0);
115 module_param(rx_copybreak, int, 0);
116 module_param(multicast_filter_limit, int, 0);
117 module_param_array(options, int, NULL, 0);
118 module_param_array(full_duplex, int, NULL, 0);
119 MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt");
120 MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)");
121 MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames");
122 MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses");
123 MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
124 MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
125 
126 enum {
127  MIN_REGION_SIZE = 136,
128 };
129 
130 /* A chip capabilities table, matching the entries in pci_tbl[] above. */
131 enum chip_capability_flags {
132  HAS_MII_XCVR,
133  HAS_CHIP_XCVR,
134 };
135 
136 /* 89/6/13 add, */
137 /* for different PHY */
138 enum phy_type_flags {
139  MysonPHY = 1,
140  AhdocPHY = 2,
141  SeeqPHY = 3,
142  MarvellPHY = 4,
143  Myson981 = 5,
144  LevelOnePHY = 6,
145  OtherPHY = 10,
146 };
147 
148 struct chip_info {
149  char *chip_name;
150  int flags;
151 };
152 
153 static const struct chip_info skel_netdrv_tbl[] __devinitconst = {
154  { "100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
155  { "100/10M Ethernet PCI Adapter", HAS_CHIP_XCVR },
156  { "1000/100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
157 };
158 
159 /* Offsets to the Command and Status Registers. */
160 enum fealnx_offsets {
161  PAR0 = 0x0, /* physical address 0-3 */
162  PAR1 = 0x04, /* physical address 4-5 */
163  MAR0 = 0x08, /* multicast address 0-3 */
164  MAR1 = 0x0C, /* multicast address 4-7 */
165  FAR0 = 0x10, /* flow-control address 0-3 */
166  FAR1 = 0x14, /* flow-control address 4-5 */
167  TCRRCR = 0x18, /* receive & transmit configuration */
168  BCR = 0x1C, /* bus command */
169  TXPDR = 0x20, /* transmit polling demand */
170  RXPDR = 0x24, /* receive polling demand */
171  RXCWP = 0x28, /* receive current word pointer */
172  TXLBA = 0x2C, /* transmit list base address */
173  RXLBA = 0x30, /* receive list base address */
174  ISR = 0x34, /* interrupt status */
175  IMR = 0x38, /* interrupt mask */
176  FTH = 0x3C, /* flow control high/low threshold */
177  MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */
178  TALLY = 0x44, /* tally counters for crc and mpa */
179  TSR = 0x48, /* tally counter for transmit status */
180  BMCRSR = 0x4c, /* basic mode control and status */
181  PHYIDENTIFIER = 0x50, /* phy identifier */
182  ANARANLPAR = 0x54, /* auto-negotiation advertisement and link
183  partner ability */
184  ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */
185  BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */
186 };
187 
188 /* Bits in the interrupt status/enable registers. */
189 /* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
190 enum intr_status_bits {
191  RFCON = 0x00020000, /* receive flow control xon packet */
192  RFCOFF = 0x00010000, /* receive flow control xoff packet */
193  LSCStatus = 0x00008000, /* link status change */
194  ANCStatus = 0x00004000, /* autonegotiation completed */
195  FBE = 0x00002000, /* fatal bus error */
196  FBEMask = 0x00001800, /* mask bit12-11 */
197  ParityErr = 0x00000000, /* parity error */
198  TargetErr = 0x00001000, /* target abort */
199  MasterErr = 0x00000800, /* master error */
200  TUNF = 0x00000400, /* transmit underflow */
201  ROVF = 0x00000200, /* receive overflow */
202  ETI = 0x00000100, /* transmit early int */
203  ERI = 0x00000080, /* receive early int */
204  CNTOVF = 0x00000040, /* counter overflow */
205  RBU = 0x00000020, /* receive buffer unavailable */
206  TBU = 0x00000010, /* transmit buffer unavilable */
207  TI = 0x00000008, /* transmit interrupt */
208  RI = 0x00000004, /* receive interrupt */
209  RxErr = 0x00000002, /* receive error */
210 };
211 
212 /* Bits in the NetworkConfig register, W for writing, R for reading */
213 /* FIXME: some names are invented by me. Marked with (name?) */
214 /* If you have docs and know bit names, please fix 'em */
215 enum rx_mode_bits {
216  CR_W_ENH = 0x02000000, /* enhanced mode (name?) */
217  CR_W_FD = 0x00100000, /* full duplex */
218  CR_W_PS10 = 0x00080000, /* 10 mbit */
219  CR_W_TXEN = 0x00040000, /* tx enable (name?) */
220  CR_W_PS1000 = 0x00010000, /* 1000 mbit */
221  /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */
222  CR_W_RXMODEMASK = 0x000000e0,
223  CR_W_PROM = 0x00000080, /* promiscuous mode */
224  CR_W_AB = 0x00000040, /* accept broadcast */
225  CR_W_AM = 0x00000020, /* accept mutlicast */
226  CR_W_ARP = 0x00000008, /* receive runt pkt */
227  CR_W_ALP = 0x00000004, /* receive long pkt */
228  CR_W_SEP = 0x00000002, /* receive error pkt */
229  CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */
230 
231  CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */
232  CR_R_FD = 0x00100000, /* full duplex detected */
233  CR_R_PS10 = 0x00080000, /* 10 mbit detected */
234  CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */
235 };
236 
237 /* The Tulip Rx and Tx buffer descriptors. */
238 struct fealnx_desc {
239  s32 status;
240  s32 control;
241  u32 buffer;
242  u32 next_desc;
243  struct fealnx_desc *next_desc_logical;
244  struct sk_buff *skbuff;
245  u32 reserved1;
246  u32 reserved2;
247 };
248 
249 /* Bits in network_desc.status */
250 enum rx_desc_status_bits {
251  RXOWN = 0x80000000, /* own bit */
252  FLNGMASK = 0x0fff0000, /* frame length */
253  FLNGShift = 16,
254  MARSTATUS = 0x00004000, /* multicast address received */
255  BARSTATUS = 0x00002000, /* broadcast address received */
256  PHYSTATUS = 0x00001000, /* physical address received */
257  RXFSD = 0x00000800, /* first descriptor */
258  RXLSD = 0x00000400, /* last descriptor */
259  ErrorSummary = 0x80, /* error summary */
260  RUNT = 0x40, /* runt packet received */
261  LONG = 0x20, /* long packet received */
262  FAE = 0x10, /* frame align error */
263  CRC = 0x08, /* crc error */
264  RXER = 0x04, /* receive error */
265 };
266 
267 enum rx_desc_control_bits {
268  RXIC = 0x00800000, /* interrupt control */
269  RBSShift = 0,
270 };
271 
272 enum tx_desc_status_bits {
273  TXOWN = 0x80000000, /* own bit */
274  JABTO = 0x00004000, /* jabber timeout */
275  CSL = 0x00002000, /* carrier sense lost */
276  LC = 0x00001000, /* late collision */
277  EC = 0x00000800, /* excessive collision */
278  UDF = 0x00000400, /* fifo underflow */
279  DFR = 0x00000200, /* deferred */
280  HF = 0x00000100, /* heartbeat fail */
281  NCRMask = 0x000000ff, /* collision retry count */
282  NCRShift = 0,
283 };
284 
285 enum tx_desc_control_bits {
286  TXIC = 0x80000000, /* interrupt control */
287  ETIControl = 0x40000000, /* early transmit interrupt */
288  TXLD = 0x20000000, /* last descriptor */
289  TXFD = 0x10000000, /* first descriptor */
290  CRCEnable = 0x08000000, /* crc control */
291  PADEnable = 0x04000000, /* padding control */
292  RetryTxLC = 0x02000000, /* retry late collision */
293  PKTSMask = 0x3ff800, /* packet size bit21-11 */
294  PKTSShift = 11,
295  TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */
296  TBSShift = 0,
297 };
298 
299 /* BootROM/EEPROM/MII Management Register */
300 #define MASK_MIIR_MII_READ 0x00000000
301 #define MASK_MIIR_MII_WRITE 0x00000008
302 #define MASK_MIIR_MII_MDO 0x00000004
303 #define MASK_MIIR_MII_MDI 0x00000002
304 #define MASK_MIIR_MII_MDC 0x00000001
305 
306 /* ST+OP+PHYAD+REGAD+TA */
307 #define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
308 #define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
309 
310 /* ------------------------------------------------------------------------- */
311 /* Constants for Myson PHY */
312 /* ------------------------------------------------------------------------- */
313 #define MysonPHYID 0xd0000302
314 /* 89-7-27 add, (begin) */
315 #define MysonPHYID0 0x0302
316 #define StatusRegister 18
317 #define SPEED100 0x0400 // bit10
318 #define FULLMODE 0x0800 // bit11
319 /* 89-7-27 add, (end) */
320 
321 /* ------------------------------------------------------------------------- */
322 /* Constants for Seeq 80225 PHY */
323 /* ------------------------------------------------------------------------- */
324 #define SeeqPHYID0 0x0016
325 
326 #define MIIRegister18 18
327 #define SPD_DET_100 0x80
328 #define DPLX_DET_FULL 0x40
329 
330 /* ------------------------------------------------------------------------- */
331 /* Constants for Ahdoc 101 PHY */
332 /* ------------------------------------------------------------------------- */
333 #define AhdocPHYID0 0x0022
334 
335 #define DiagnosticReg 18
336 #define DPLX_FULL 0x0800
337 #define Speed_100 0x0400
338 
339 /* 89/6/13 add, */
340 /* -------------------------------------------------------------------------- */
341 /* Constants */
342 /* -------------------------------------------------------------------------- */
343 #define MarvellPHYID0 0x0141
344 #define LevelOnePHYID0 0x0013
345 
346 #define MII1000BaseTControlReg 9
347 #define MII1000BaseTStatusReg 10
348 #define SpecificReg 17
349 
350 /* for 1000BaseT Control Register */
351 #define PHYAbletoPerform1000FullDuplex 0x0200
352 #define PHYAbletoPerform1000HalfDuplex 0x0100
353 #define PHY1000AbilityMask 0x300
354 
355 // for phy specific status register, marvell phy.
356 #define SpeedMask 0x0c000
357 #define Speed_1000M 0x08000
358 #define Speed_100M 0x4000
359 #define Speed_10M 0
360 #define Full_Duplex 0x2000
361 
362 // 89/12/29 add, for phy specific status register, levelone phy, (begin)
363 #define LXT1000_100M 0x08000
364 #define LXT1000_1000M 0x0c000
365 #define LXT1000_Full 0x200
366 // 89/12/29 add, for phy specific status register, levelone phy, (end)
367 
368 /* for 3-in-1 case, BMCRSR register */
369 #define LinkIsUp2 0x00040000
370 
371 /* for PHY */
372 #define LinkIsUp 0x0004
373 
374 
375 struct netdev_private {
376  /* Descriptor rings first for alignment. */
377  struct fealnx_desc *rx_ring;
378  struct fealnx_desc *tx_ring;
379 
380  dma_addr_t rx_ring_dma;
381  dma_addr_t tx_ring_dma;
382 
383  spinlock_t lock;
384 
385  /* Media monitoring timer. */
386  struct timer_list timer;
387 
388  /* Reset timer */
389  struct timer_list reset_timer;
390  int reset_timer_armed;
391  unsigned long crvalue_sv;
392  unsigned long imrvalue_sv;
393 
394  /* Frequently used values: keep some adjacent for cache effect. */
395  int flags;
396  struct pci_dev *pci_dev;
397  unsigned long crvalue;
398  unsigned long bcrvalue;
399  unsigned long imrvalue;
400  struct fealnx_desc *cur_rx;
401  struct fealnx_desc *lack_rxbuf;
402  int really_rx_count;
403  struct fealnx_desc *cur_tx;
404  struct fealnx_desc *cur_tx_copy;
405  int really_tx_count;
406  int free_tx_count;
407  unsigned int rx_buf_sz; /* Based on MTU+slack. */
408 
409  /* These values are keep track of the transceiver/media in use. */
410  unsigned int linkok;
411  unsigned int line_speed;
412  unsigned int duplexmode;
413  unsigned int default_port:4; /* Last dev->if_port value. */
414  unsigned int PHYType;
415 
416  /* MII transceiver section. */
417  int mii_cnt; /* MII device addresses. */
418  unsigned char phys[2]; /* MII device addresses. */
419  struct mii_if_info mii;
420  void __iomem *mem;
421 };
422 
423 
424 static int mdio_read(struct net_device *dev, int phy_id, int location);
425 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
426 static int netdev_open(struct net_device *dev);
427 static void getlinktype(struct net_device *dev);
428 static void getlinkstatus(struct net_device *dev);
429 static void netdev_timer(unsigned long data);
430 static void reset_timer(unsigned long data);
431 static void fealnx_tx_timeout(struct net_device *dev);
432 static void init_ring(struct net_device *dev);
433 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
434 static irqreturn_t intr_handler(int irq, void *dev_instance);
435 static int netdev_rx(struct net_device *dev);
436 static void set_rx_mode(struct net_device *dev);
437 static void __set_rx_mode(struct net_device *dev);
438 static struct net_device_stats *get_stats(struct net_device *dev);
439 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
440 static const struct ethtool_ops netdev_ethtool_ops;
441 static int netdev_close(struct net_device *dev);
442 static void reset_rx_descriptors(struct net_device *dev);
443 static void reset_tx_descriptors(struct net_device *dev);
444 
445 static void stop_nic_rx(void __iomem *ioaddr, long crvalue)
446 {
447  int delay = 0x1000;
448  iowrite32(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
449  while (--delay) {
450  if ( (ioread32(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
451  break;
452  }
453 }
454 
455 
456 static void stop_nic_rxtx(void __iomem *ioaddr, long crvalue)
457 {
458  int delay = 0x1000;
459  iowrite32(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
460  while (--delay) {
461  if ( (ioread32(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
462  == (CR_R_RXSTOP+CR_R_TXSTOP) )
463  break;
464  }
465 }
466 
467 static const struct net_device_ops netdev_ops = {
468  .ndo_open = netdev_open,
469  .ndo_stop = netdev_close,
470  .ndo_start_xmit = start_tx,
471  .ndo_get_stats = get_stats,
472  .ndo_set_rx_mode = set_rx_mode,
473  .ndo_do_ioctl = mii_ioctl,
474  .ndo_tx_timeout = fealnx_tx_timeout,
475  .ndo_change_mtu = eth_change_mtu,
476  .ndo_set_mac_address = eth_mac_addr,
477  .ndo_validate_addr = eth_validate_addr,
478 };
479 
480 static int __devinit fealnx_init_one(struct pci_dev *pdev,
481  const struct pci_device_id *ent)
482 {
483  struct netdev_private *np;
484  int i, option, err, irq;
485  static int card_idx = -1;
486  char boardname[12];
487  void __iomem *ioaddr;
488  unsigned long len;
489  unsigned int chip_id = ent->driver_data;
490  struct net_device *dev;
491  void *ring_space;
492  dma_addr_t ring_dma;
493 #ifdef USE_IO_OPS
494  int bar = 0;
495 #else
496  int bar = 1;
497 #endif
498 
499 /* when built into the kernel, we only print version if device is found */
500 #ifndef MODULE
501  static int printed_version;
502  if (!printed_version++)
503  printk(version);
504 #endif
505 
506  card_idx++;
507  sprintf(boardname, "fealnx%d", card_idx);
508 
509  option = card_idx < MAX_UNITS ? options[card_idx] : 0;
510 
511  i = pci_enable_device(pdev);
512  if (i) return i;
513  pci_set_master(pdev);
514 
515  len = pci_resource_len(pdev, bar);
516  if (len < MIN_REGION_SIZE) {
517  dev_err(&pdev->dev,
518  "region size %ld too small, aborting\n", len);
519  return -ENODEV;
520  }
521 
522  i = pci_request_regions(pdev, boardname);
523  if (i)
524  return i;
525 
526  irq = pdev->irq;
527 
528  ioaddr = pci_iomap(pdev, bar, len);
529  if (!ioaddr) {
530  err = -ENOMEM;
531  goto err_out_res;
532  }
533 
534  dev = alloc_etherdev(sizeof(struct netdev_private));
535  if (!dev) {
536  err = -ENOMEM;
537  goto err_out_unmap;
538  }
539  SET_NETDEV_DEV(dev, &pdev->dev);
540 
541  /* read ethernet id */
542  for (i = 0; i < 6; ++i)
543  dev->dev_addr[i] = ioread8(ioaddr + PAR0 + i);
544 
545  /* Reset the chip to erase previous misconfiguration. */
546  iowrite32(0x00000001, ioaddr + BCR);
547 
548  /* Make certain the descriptor lists are aligned. */
549  np = netdev_priv(dev);
550  np->mem = ioaddr;
551  spin_lock_init(&np->lock);
552  np->pci_dev = pdev;
553  np->flags = skel_netdrv_tbl[chip_id].flags;
554  pci_set_drvdata(pdev, dev);
555  np->mii.dev = dev;
556  np->mii.mdio_read = mdio_read;
557  np->mii.mdio_write = mdio_write;
558  np->mii.phy_id_mask = 0x1f;
559  np->mii.reg_num_mask = 0x1f;
560 
561  ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
562  if (!ring_space) {
563  err = -ENOMEM;
564  goto err_out_free_dev;
565  }
566  np->rx_ring = ring_space;
567  np->rx_ring_dma = ring_dma;
568 
569  ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
570  if (!ring_space) {
571  err = -ENOMEM;
572  goto err_out_free_rx;
573  }
574  np->tx_ring = ring_space;
575  np->tx_ring_dma = ring_dma;
576 
577  /* find the connected MII xcvrs */
578  if (np->flags == HAS_MII_XCVR) {
579  int phy, phy_idx = 0;
580 
581  for (phy = 1; phy < 32 && phy_idx < ARRAY_SIZE(np->phys);
582  phy++) {
583  int mii_status = mdio_read(dev, phy, 1);
584 
585  if (mii_status != 0xffff && mii_status != 0x0000) {
586  np->phys[phy_idx++] = phy;
587  dev_info(&pdev->dev,
588  "MII PHY found at address %d, status "
589  "0x%4.4x.\n", phy, mii_status);
590  /* get phy type */
591  {
592  unsigned int data;
593 
594  data = mdio_read(dev, np->phys[0], 2);
595  if (data == SeeqPHYID0)
596  np->PHYType = SeeqPHY;
597  else if (data == AhdocPHYID0)
598  np->PHYType = AhdocPHY;
599  else if (data == MarvellPHYID0)
600  np->PHYType = MarvellPHY;
601  else if (data == MysonPHYID0)
602  np->PHYType = Myson981;
603  else if (data == LevelOnePHYID0)
604  np->PHYType = LevelOnePHY;
605  else
606  np->PHYType = OtherPHY;
607  }
608  }
609  }
610 
611  np->mii_cnt = phy_idx;
612  if (phy_idx == 0)
613  dev_warn(&pdev->dev,
614  "MII PHY not found -- this device may "
615  "not operate correctly.\n");
616  } else {
617  np->phys[0] = 32;
618 /* 89/6/23 add, (begin) */
619  /* get phy type */
620  if (ioread32(ioaddr + PHYIDENTIFIER) == MysonPHYID)
621  np->PHYType = MysonPHY;
622  else
623  np->PHYType = OtherPHY;
624  }
625  np->mii.phy_id = np->phys[0];
626 
627  if (dev->mem_start)
628  option = dev->mem_start;
629 
630  /* The lower four bits are the media type. */
631  if (option > 0) {
632  if (option & 0x200)
633  np->mii.full_duplex = 1;
634  np->default_port = option & 15;
635  }
636 
637  if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
638  np->mii.full_duplex = full_duplex[card_idx];
639 
640  if (np->mii.full_duplex) {
641  dev_info(&pdev->dev, "Media type forced to Full Duplex.\n");
642 /* 89/6/13 add, (begin) */
643 // if (np->PHYType==MarvellPHY)
644  if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
645  unsigned int data;
646 
647  data = mdio_read(dev, np->phys[0], 9);
648  data = (data & 0xfcff) | 0x0200;
649  mdio_write(dev, np->phys[0], 9, data);
650  }
651 /* 89/6/13 add, (end) */
652  if (np->flags == HAS_MII_XCVR)
653  mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
654  else
655  iowrite32(ADVERTISE_FULL, ioaddr + ANARANLPAR);
656  np->mii.force_media = 1;
657  }
658 
659  dev->netdev_ops = &netdev_ops;
660  dev->ethtool_ops = &netdev_ethtool_ops;
661  dev->watchdog_timeo = TX_TIMEOUT;
662 
663  err = register_netdev(dev);
664  if (err)
665  goto err_out_free_tx;
666 
667  printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
668  dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr,
669  dev->dev_addr, irq);
670 
671  return 0;
672 
673 err_out_free_tx:
674  pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
675 err_out_free_rx:
676  pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
677 err_out_free_dev:
678  free_netdev(dev);
679 err_out_unmap:
680  pci_iounmap(pdev, ioaddr);
681 err_out_res:
682  pci_release_regions(pdev);
683  return err;
684 }
685 
686 
687 static void __devexit fealnx_remove_one(struct pci_dev *pdev)
688 {
689  struct net_device *dev = pci_get_drvdata(pdev);
690 
691  if (dev) {
692  struct netdev_private *np = netdev_priv(dev);
693 
694  pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
695  np->tx_ring_dma);
696  pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
697  np->rx_ring_dma);
698  unregister_netdev(dev);
699  pci_iounmap(pdev, np->mem);
700  free_netdev(dev);
701  pci_release_regions(pdev);
702  pci_set_drvdata(pdev, NULL);
703  } else
704  printk(KERN_ERR "fealnx: remove for unknown device\n");
705 }
706 
707 
708 static ulong m80x_send_cmd_to_phy(void __iomem *miiport, int opcode, int phyad, int regad)
709 {
710  ulong miir;
711  int i;
712  unsigned int mask, data;
713 
714  /* enable MII output */
715  miir = (ulong) ioread32(miiport);
716  miir &= 0xfffffff0;
717 
718  miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
719 
720  /* send 32 1's preamble */
721  for (i = 0; i < 32; i++) {
722  /* low MDC; MDO is already high (miir) */
723  miir &= ~MASK_MIIR_MII_MDC;
724  iowrite32(miir, miiport);
725 
726  /* high MDC */
727  miir |= MASK_MIIR_MII_MDC;
728  iowrite32(miir, miiport);
729  }
730 
731  /* calculate ST+OP+PHYAD+REGAD+TA */
732  data = opcode | (phyad << 7) | (regad << 2);
733 
734  /* sent out */
735  mask = 0x8000;
736  while (mask) {
737  /* low MDC, prepare MDO */
738  miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
739  if (mask & data)
740  miir |= MASK_MIIR_MII_MDO;
741 
742  iowrite32(miir, miiport);
743  /* high MDC */
744  miir |= MASK_MIIR_MII_MDC;
745  iowrite32(miir, miiport);
746  udelay(30);
747 
748  /* next */
749  mask >>= 1;
750  if (mask == 0x2 && opcode == OP_READ)
751  miir &= ~MASK_MIIR_MII_WRITE;
752  }
753  return miir;
754 }
755 
756 
757 static int mdio_read(struct net_device *dev, int phyad, int regad)
758 {
759  struct netdev_private *np = netdev_priv(dev);
760  void __iomem *miiport = np->mem + MANAGEMENT;
761  ulong miir;
762  unsigned int mask, data;
763 
764  miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad);
765 
766  /* read data */
767  mask = 0x8000;
768  data = 0;
769  while (mask) {
770  /* low MDC */
771  miir &= ~MASK_MIIR_MII_MDC;
772  iowrite32(miir, miiport);
773 
774  /* read MDI */
775  miir = ioread32(miiport);
776  if (miir & MASK_MIIR_MII_MDI)
777  data |= mask;
778 
779  /* high MDC, and wait */
780  miir |= MASK_MIIR_MII_MDC;
781  iowrite32(miir, miiport);
782  udelay(30);
783 
784  /* next */
785  mask >>= 1;
786  }
787 
788  /* low MDC */
789  miir &= ~MASK_MIIR_MII_MDC;
790  iowrite32(miir, miiport);
791 
792  return data & 0xffff;
793 }
794 
795 
796 static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
797 {
798  struct netdev_private *np = netdev_priv(dev);
799  void __iomem *miiport = np->mem + MANAGEMENT;
800  ulong miir;
801  unsigned int mask;
802 
803  miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad);
804 
805  /* write data */
806  mask = 0x8000;
807  while (mask) {
808  /* low MDC, prepare MDO */
809  miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
810  if (mask & data)
811  miir |= MASK_MIIR_MII_MDO;
812  iowrite32(miir, miiport);
813 
814  /* high MDC */
815  miir |= MASK_MIIR_MII_MDC;
816  iowrite32(miir, miiport);
817 
818  /* next */
819  mask >>= 1;
820  }
821 
822  /* low MDC */
823  miir &= ~MASK_MIIR_MII_MDC;
824  iowrite32(miir, miiport);
825 }
826 
827 
828 static int netdev_open(struct net_device *dev)
829 {
830  struct netdev_private *np = netdev_priv(dev);
831  void __iomem *ioaddr = np->mem;
832  const int irq = np->pci_dev->irq;
833  int rc, i;
834 
835  iowrite32(0x00000001, ioaddr + BCR); /* Reset */
836 
837  rc = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
838  if (rc)
839  return -EAGAIN;
840 
841  for (i = 0; i < 3; i++)
842  iowrite16(((unsigned short*)dev->dev_addr)[i],
843  ioaddr + PAR0 + i*2);
844 
845  init_ring(dev);
846 
847  iowrite32(np->rx_ring_dma, ioaddr + RXLBA);
848  iowrite32(np->tx_ring_dma, ioaddr + TXLBA);
849 
850  /* Initialize other registers. */
851  /* Configure the PCI bus bursts and FIFO thresholds.
852  486: Set 8 longword burst.
853  586: no burst limit.
854  Burst length 5:3
855  0 0 0 1
856  0 0 1 4
857  0 1 0 8
858  0 1 1 16
859  1 0 0 32
860  1 0 1 64
861  1 1 0 128
862  1 1 1 256
863  Wait the specified 50 PCI cycles after a reset by initializing
864  Tx and Rx queues and the address filter list.
865  FIXME (Ueimor): optimistic for alpha + posted writes ? */
866 
867  np->bcrvalue = 0x10; /* little-endian, 8 burst length */
868 #ifdef __BIG_ENDIAN
869  np->bcrvalue |= 0x04; /* big-endian */
870 #endif
871 
872 #if defined(__i386__) && !defined(MODULE)
873  if (boot_cpu_data.x86 <= 4)
874  np->crvalue = 0xa00;
875  else
876 #endif
877  np->crvalue = 0xe00; /* rx 128 burst length */
878 
879 
880 // 89/12/29 add,
881 // 90/1/16 modify,
882 // np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
883  np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
884  if (np->pci_dev->device == 0x891) {
885  np->bcrvalue |= 0x200; /* set PROG bit */
886  np->crvalue |= CR_W_ENH; /* set enhanced bit */
887  np->imrvalue |= ETI;
888  }
889  iowrite32(np->bcrvalue, ioaddr + BCR);
890 
891  if (dev->if_port == 0)
892  dev->if_port = np->default_port;
893 
894  iowrite32(0, ioaddr + RXPDR);
895 // 89/9/1 modify,
896 // np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
897  np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
898  np->mii.full_duplex = np->mii.force_media;
899  getlinkstatus(dev);
900  if (np->linkok)
901  getlinktype(dev);
902  __set_rx_mode(dev);
903 
904  netif_start_queue(dev);
905 
906  /* Clear and Enable interrupts by setting the interrupt mask. */
907  iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
908  iowrite32(np->imrvalue, ioaddr + IMR);
909 
910  if (debug)
911  printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
912 
913  /* Set the timer to check for link beat. */
914  init_timer(&np->timer);
915  np->timer.expires = RUN_AT(3 * HZ);
916  np->timer.data = (unsigned long) dev;
917  np->timer.function = netdev_timer;
918 
919  /* timer handler */
920  add_timer(&np->timer);
921 
922  init_timer(&np->reset_timer);
923  np->reset_timer.data = (unsigned long) dev;
924  np->reset_timer.function = reset_timer;
925  np->reset_timer_armed = 0;
926  return rc;
927 }
928 
929 
930 static void getlinkstatus(struct net_device *dev)
931 /* function: Routine will read MII Status Register to get link status. */
932 /* input : dev... pointer to the adapter block. */
933 /* output : none. */
934 {
935  struct netdev_private *np = netdev_priv(dev);
936  unsigned int i, DelayTime = 0x1000;
937 
938  np->linkok = 0;
939 
940  if (np->PHYType == MysonPHY) {
941  for (i = 0; i < DelayTime; ++i) {
942  if (ioread32(np->mem + BMCRSR) & LinkIsUp2) {
943  np->linkok = 1;
944  return;
945  }
946  udelay(100);
947  }
948  } else {
949  for (i = 0; i < DelayTime; ++i) {
950  if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
951  np->linkok = 1;
952  return;
953  }
954  udelay(100);
955  }
956  }
957 }
958 
959 
960 static void getlinktype(struct net_device *dev)
961 {
962  struct netdev_private *np = netdev_priv(dev);
963 
964  if (np->PHYType == MysonPHY) { /* 3-in-1 case */
965  if (ioread32(np->mem + TCRRCR) & CR_R_FD)
966  np->duplexmode = 2; /* full duplex */
967  else
968  np->duplexmode = 1; /* half duplex */
969  if (ioread32(np->mem + TCRRCR) & CR_R_PS10)
970  np->line_speed = 1; /* 10M */
971  else
972  np->line_speed = 2; /* 100M */
973  } else {
974  if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */
975  unsigned int data;
976 
977  data = mdio_read(dev, np->phys[0], MIIRegister18);
978  if (data & SPD_DET_100)
979  np->line_speed = 2; /* 100M */
980  else
981  np->line_speed = 1; /* 10M */
982  if (data & DPLX_DET_FULL)
983  np->duplexmode = 2; /* full duplex mode */
984  else
985  np->duplexmode = 1; /* half duplex mode */
986  } else if (np->PHYType == AhdocPHY) {
987  unsigned int data;
988 
989  data = mdio_read(dev, np->phys[0], DiagnosticReg);
990  if (data & Speed_100)
991  np->line_speed = 2; /* 100M */
992  else
993  np->line_speed = 1; /* 10M */
994  if (data & DPLX_FULL)
995  np->duplexmode = 2; /* full duplex mode */
996  else
997  np->duplexmode = 1; /* half duplex mode */
998  }
999 /* 89/6/13 add, (begin) */
1000  else if (np->PHYType == MarvellPHY) {
1001  unsigned int data;
1002 
1003  data = mdio_read(dev, np->phys[0], SpecificReg);
1004  if (data & Full_Duplex)
1005  np->duplexmode = 2; /* full duplex mode */
1006  else
1007  np->duplexmode = 1; /* half duplex mode */
1008  data &= SpeedMask;
1009  if (data == Speed_1000M)
1010  np->line_speed = 3; /* 1000M */
1011  else if (data == Speed_100M)
1012  np->line_speed = 2; /* 100M */
1013  else
1014  np->line_speed = 1; /* 10M */
1015  }
1016 /* 89/6/13 add, (end) */
1017 /* 89/7/27 add, (begin) */
1018  else if (np->PHYType == Myson981) {
1019  unsigned int data;
1020 
1021  data = mdio_read(dev, np->phys[0], StatusRegister);
1022 
1023  if (data & SPEED100)
1024  np->line_speed = 2;
1025  else
1026  np->line_speed = 1;
1027 
1028  if (data & FULLMODE)
1029  np->duplexmode = 2;
1030  else
1031  np->duplexmode = 1;
1032  }
1033 /* 89/7/27 add, (end) */
1034 /* 89/12/29 add */
1035  else if (np->PHYType == LevelOnePHY) {
1036  unsigned int data;
1037 
1038  data = mdio_read(dev, np->phys[0], SpecificReg);
1039  if (data & LXT1000_Full)
1040  np->duplexmode = 2; /* full duplex mode */
1041  else
1042  np->duplexmode = 1; /* half duplex mode */
1043  data &= SpeedMask;
1044  if (data == LXT1000_1000M)
1045  np->line_speed = 3; /* 1000M */
1046  else if (data == LXT1000_100M)
1047  np->line_speed = 2; /* 100M */
1048  else
1049  np->line_speed = 1; /* 10M */
1050  }
1051  np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000);
1052  if (np->line_speed == 1)
1053  np->crvalue |= CR_W_PS10;
1054  else if (np->line_speed == 3)
1055  np->crvalue |= CR_W_PS1000;
1056  if (np->duplexmode == 2)
1057  np->crvalue |= CR_W_FD;
1058  }
1059 }
1060 
1061 
1062 /* Take lock before calling this */
1063 static void allocate_rx_buffers(struct net_device *dev)
1064 {
1065  struct netdev_private *np = netdev_priv(dev);
1066 
1067  /* allocate skb for rx buffers */
1068  while (np->really_rx_count != RX_RING_SIZE) {
1069  struct sk_buff *skb;
1070 
1071  skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1072  if (skb == NULL)
1073  break; /* Better luck next round. */
1074 
1075  while (np->lack_rxbuf->skbuff)
1076  np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1077 
1078  np->lack_rxbuf->skbuff = skb;
1079  np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->data,
1080  np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1081  np->lack_rxbuf->status = RXOWN;
1082  ++np->really_rx_count;
1083  }
1084 }
1085 
1086 
1087 static void netdev_timer(unsigned long data)
1088 {
1089  struct net_device *dev = (struct net_device *) data;
1090  struct netdev_private *np = netdev_priv(dev);
1091  void __iomem *ioaddr = np->mem;
1092  int old_crvalue = np->crvalue;
1093  unsigned int old_linkok = np->linkok;
1094  unsigned long flags;
1095 
1096  if (debug)
1097  printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
1098  "config %8.8x.\n", dev->name, ioread32(ioaddr + ISR),
1099  ioread32(ioaddr + TCRRCR));
1100 
1101  spin_lock_irqsave(&np->lock, flags);
1102 
1103  if (np->flags == HAS_MII_XCVR) {
1104  getlinkstatus(dev);
1105  if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */
1106  getlinktype(dev);
1107  if (np->crvalue != old_crvalue) {
1108  stop_nic_rxtx(ioaddr, np->crvalue);
1109  iowrite32(np->crvalue, ioaddr + TCRRCR);
1110  }
1111  }
1112  }
1113 
1114  allocate_rx_buffers(dev);
1115 
1116  spin_unlock_irqrestore(&np->lock, flags);
1117 
1118  np->timer.expires = RUN_AT(10 * HZ);
1119  add_timer(&np->timer);
1120 }
1121 
1122 
1123 /* Take lock before calling */
1124 /* Reset chip and disable rx, tx and interrupts */
1125 static void reset_and_disable_rxtx(struct net_device *dev)
1126 {
1127  struct netdev_private *np = netdev_priv(dev);
1128  void __iomem *ioaddr = np->mem;
1129  int delay=51;
1130 
1131  /* Reset the chip's Tx and Rx processes. */
1132  stop_nic_rxtx(ioaddr, 0);
1133 
1134  /* Disable interrupts by clearing the interrupt mask. */
1135  iowrite32(0, ioaddr + IMR);
1136 
1137  /* Reset the chip to erase previous misconfiguration. */
1138  iowrite32(0x00000001, ioaddr + BCR);
1139 
1140  /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
1141  We surely wait too long (address+data phase). Who cares? */
1142  while (--delay) {
1143  ioread32(ioaddr + BCR);
1144  rmb();
1145  }
1146 }
1147 
1148 
1149 /* Take lock before calling */
1150 /* Restore chip after reset */
1151 static void enable_rxtx(struct net_device *dev)
1152 {
1153  struct netdev_private *np = netdev_priv(dev);
1154  void __iomem *ioaddr = np->mem;
1155 
1156  reset_rx_descriptors(dev);
1157 
1158  iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
1159  ioaddr + TXLBA);
1160  iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1161  ioaddr + RXLBA);
1162 
1163  iowrite32(np->bcrvalue, ioaddr + BCR);
1164 
1165  iowrite32(0, ioaddr + RXPDR);
1166  __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
1167 
1168  /* Clear and Enable interrupts by setting the interrupt mask. */
1169  iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
1170  iowrite32(np->imrvalue, ioaddr + IMR);
1171 
1172  iowrite32(0, ioaddr + TXPDR);
1173 }
1174 
1175 
1176 static void reset_timer(unsigned long data)
1177 {
1178  struct net_device *dev = (struct net_device *) data;
1179  struct netdev_private *np = netdev_priv(dev);
1180  unsigned long flags;
1181 
1182  printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name);
1183 
1184  spin_lock_irqsave(&np->lock, flags);
1185  np->crvalue = np->crvalue_sv;
1186  np->imrvalue = np->imrvalue_sv;
1187 
1188  reset_and_disable_rxtx(dev);
1189  /* works for me without this:
1190  reset_tx_descriptors(dev); */
1191  enable_rxtx(dev);
1192  netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */
1193 
1194  np->reset_timer_armed = 0;
1195 
1196  spin_unlock_irqrestore(&np->lock, flags);
1197 }
1198 
1199 
1200 static void fealnx_tx_timeout(struct net_device *dev)
1201 {
1202  struct netdev_private *np = netdev_priv(dev);
1203  void __iomem *ioaddr = np->mem;
1204  unsigned long flags;
1205  int i;
1206 
1207  printk(KERN_WARNING
1208  "%s: Transmit timed out, status %8.8x, resetting...\n",
1209  dev->name, ioread32(ioaddr + ISR));
1210 
1211  {
1212  printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
1213  for (i = 0; i < RX_RING_SIZE; i++)
1214  printk(KERN_CONT " %8.8x",
1215  (unsigned int) np->rx_ring[i].status);
1216  printk(KERN_CONT "\n");
1217  printk(KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1218  for (i = 0; i < TX_RING_SIZE; i++)
1219  printk(KERN_CONT " %4.4x", np->tx_ring[i].status);
1220  printk(KERN_CONT "\n");
1221  }
1222 
1223  spin_lock_irqsave(&np->lock, flags);
1224 
1225  reset_and_disable_rxtx(dev);
1226  reset_tx_descriptors(dev);
1227  enable_rxtx(dev);
1228 
1229  spin_unlock_irqrestore(&np->lock, flags);
1230 
1231  dev->trans_start = jiffies; /* prevent tx timeout */
1232  dev->stats.tx_errors++;
1233  netif_wake_queue(dev); /* or .._start_.. ?? */
1234 }
1235 
1236 
1237 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1238 static void init_ring(struct net_device *dev)
1239 {
1240  struct netdev_private *np = netdev_priv(dev);
1241  int i;
1242 
1243  /* initialize rx variables */
1244  np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1245  np->cur_rx = &np->rx_ring[0];
1246  np->lack_rxbuf = np->rx_ring;
1247  np->really_rx_count = 0;
1248 
1249  /* initial rx descriptors. */
1250  for (i = 0; i < RX_RING_SIZE; i++) {
1251  np->rx_ring[i].status = 0;
1252  np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1253  np->rx_ring[i].next_desc = np->rx_ring_dma +
1254  (i + 1)*sizeof(struct fealnx_desc);
1255  np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1256  np->rx_ring[i].skbuff = NULL;
1257  }
1258 
1259  /* for the last rx descriptor */
1260  np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1261  np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1262 
1263  /* allocate skb for rx buffers */
1264  for (i = 0; i < RX_RING_SIZE; i++) {
1265  struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1266 
1267  if (skb == NULL) {
1268  np->lack_rxbuf = &np->rx_ring[i];
1269  break;
1270  }
1271 
1272  ++np->really_rx_count;
1273  np->rx_ring[i].skbuff = skb;
1274  np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->data,
1275  np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1276  np->rx_ring[i].status = RXOWN;
1277  np->rx_ring[i].control |= RXIC;
1278  }
1279 
1280  /* initialize tx variables */
1281  np->cur_tx = &np->tx_ring[0];
1282  np->cur_tx_copy = &np->tx_ring[0];
1283  np->really_tx_count = 0;
1284  np->free_tx_count = TX_RING_SIZE;
1285 
1286  for (i = 0; i < TX_RING_SIZE; i++) {
1287  np->tx_ring[i].status = 0;
1288  /* do we need np->tx_ring[i].control = XXX; ?? */
1289  np->tx_ring[i].next_desc = np->tx_ring_dma +
1290  (i + 1)*sizeof(struct fealnx_desc);
1291  np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1292  np->tx_ring[i].skbuff = NULL;
1293  }
1294 
1295  /* for the last tx descriptor */
1296  np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1297  np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1298 }
1299 
1300 
1301 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1302 {
1303  struct netdev_private *np = netdev_priv(dev);
1304  unsigned long flags;
1305 
1306  spin_lock_irqsave(&np->lock, flags);
1307 
1308  np->cur_tx_copy->skbuff = skb;
1309 
1310 #define one_buffer
1311 #define BPT 1022
1312 #if defined(one_buffer)
1313  np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1314  skb->len, PCI_DMA_TODEVICE);
1315  np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1316  np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1317  np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1318 // 89/12/29 add,
1319  if (np->pci_dev->device == 0x891)
1320  np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1321  np->cur_tx_copy->status = TXOWN;
1322  np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1323  --np->free_tx_count;
1324 #elif defined(two_buffer)
1325  if (skb->len > BPT) {
1326  struct fealnx_desc *next;
1327 
1328  /* for the first descriptor */
1329  np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1330  BPT, PCI_DMA_TODEVICE);
1331  np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1332  np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1333  np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */
1334 
1335  /* for the last descriptor */
1336  next = np->cur_tx_copy->next_desc_logical;
1337  next->skbuff = skb;
1338  next->control = TXIC | TXLD | CRCEnable | PADEnable;
1339  next->control |= (skb->len << PKTSShift); /* pkt size */
1340  next->control |= ((skb->len - BPT) << TBSShift); /* buf size */
1341 // 89/12/29 add,
1342  if (np->pci_dev->device == 0x891)
1343  np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1344  next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT,
1345  skb->len - BPT, PCI_DMA_TODEVICE);
1346 
1347  next->status = TXOWN;
1348  np->cur_tx_copy->status = TXOWN;
1349 
1350  np->cur_tx_copy = next->next_desc_logical;
1351  np->free_tx_count -= 2;
1352  } else {
1353  np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1354  skb->len, PCI_DMA_TODEVICE);
1355  np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1356  np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1357  np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1358 // 89/12/29 add,
1359  if (np->pci_dev->device == 0x891)
1360  np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1361  np->cur_tx_copy->status = TXOWN;
1362  np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1363  --np->free_tx_count;
1364  }
1365 #endif
1366 
1367  if (np->free_tx_count < 2)
1368  netif_stop_queue(dev);
1369  ++np->really_tx_count;
1370  iowrite32(0, np->mem + TXPDR);
1371 
1372  spin_unlock_irqrestore(&np->lock, flags);
1373  return NETDEV_TX_OK;
1374 }
1375 
1376 
1377 /* Take lock before calling */
1378 /* Chip probably hosed tx ring. Clean up. */
1379 static void reset_tx_descriptors(struct net_device *dev)
1380 {
1381  struct netdev_private *np = netdev_priv(dev);
1382  struct fealnx_desc *cur;
1383  int i;
1384 
1385  /* initialize tx variables */
1386  np->cur_tx = &np->tx_ring[0];
1387  np->cur_tx_copy = &np->tx_ring[0];
1388  np->really_tx_count = 0;
1389  np->free_tx_count = TX_RING_SIZE;
1390 
1391  for (i = 0; i < TX_RING_SIZE; i++) {
1392  cur = &np->tx_ring[i];
1393  if (cur->skbuff) {
1394  pci_unmap_single(np->pci_dev, cur->buffer,
1395  cur->skbuff->len, PCI_DMA_TODEVICE);
1396  dev_kfree_skb_any(cur->skbuff);
1397  cur->skbuff = NULL;
1398  }
1399  cur->status = 0;
1400  cur->control = 0; /* needed? */
1401  /* probably not needed. We do it for purely paranoid reasons */
1402  cur->next_desc = np->tx_ring_dma +
1403  (i + 1)*sizeof(struct fealnx_desc);
1404  cur->next_desc_logical = &np->tx_ring[i + 1];
1405  }
1406  /* for the last tx descriptor */
1407  np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma;
1408  np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0];
1409 }
1410 
1411 
1412 /* Take lock and stop rx before calling this */
1413 static void reset_rx_descriptors(struct net_device *dev)
1414 {
1415  struct netdev_private *np = netdev_priv(dev);
1416  struct fealnx_desc *cur = np->cur_rx;
1417  int i;
1418 
1419  allocate_rx_buffers(dev);
1420 
1421  for (i = 0; i < RX_RING_SIZE; i++) {
1422  if (cur->skbuff)
1423  cur->status = RXOWN;
1424  cur = cur->next_desc_logical;
1425  }
1426 
1427  iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1428  np->mem + RXLBA);
1429 }
1430 
1431 
1432 /* The interrupt handler does all of the Rx thread work and cleans up
1433  after the Tx thread. */
1434 static irqreturn_t intr_handler(int irq, void *dev_instance)
1435 {
1436  struct net_device *dev = (struct net_device *) dev_instance;
1437  struct netdev_private *np = netdev_priv(dev);
1438  void __iomem *ioaddr = np->mem;
1439  long boguscnt = max_interrupt_work;
1440  unsigned int num_tx = 0;
1441  int handled = 0;
1442 
1443  spin_lock(&np->lock);
1444 
1445  iowrite32(0, ioaddr + IMR);
1446 
1447  do {
1448  u32 intr_status = ioread32(ioaddr + ISR);
1449 
1450  /* Acknowledge all of the current interrupt sources ASAP. */
1451  iowrite32(intr_status, ioaddr + ISR);
1452 
1453  if (debug)
1454  printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
1455  intr_status);
1456 
1457  if (!(intr_status & np->imrvalue))
1458  break;
1459 
1460  handled = 1;
1461 
1462 // 90/1/16 delete,
1463 //
1464 // if (intr_status & FBE)
1465 // { /* fatal error */
1466 // stop_nic_tx(ioaddr, 0);
1467 // stop_nic_rx(ioaddr, 0);
1468 // break;
1469 // };
1470 
1471  if (intr_status & TUNF)
1472  iowrite32(0, ioaddr + TXPDR);
1473 
1474  if (intr_status & CNTOVF) {
1475  /* missed pkts */
1476  dev->stats.rx_missed_errors +=
1477  ioread32(ioaddr + TALLY) & 0x7fff;
1478 
1479  /* crc error */
1480  dev->stats.rx_crc_errors +=
1481  (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1482  }
1483 
1484  if (intr_status & (RI | RBU)) {
1485  if (intr_status & RI)
1486  netdev_rx(dev);
1487  else {
1488  stop_nic_rx(ioaddr, np->crvalue);
1489  reset_rx_descriptors(dev);
1490  iowrite32(np->crvalue, ioaddr + TCRRCR);
1491  }
1492  }
1493 
1494  while (np->really_tx_count) {
1495  long tx_status = np->cur_tx->status;
1496  long tx_control = np->cur_tx->control;
1497 
1498  if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */
1499  struct fealnx_desc *next;
1500 
1501  next = np->cur_tx->next_desc_logical;
1502  tx_status = next->status;
1503  tx_control = next->control;
1504  }
1505 
1506  if (tx_status & TXOWN)
1507  break;
1508 
1509  if (!(np->crvalue & CR_W_ENH)) {
1510  if (tx_status & (CSL | LC | EC | UDF | HF)) {
1511  dev->stats.tx_errors++;
1512  if (tx_status & EC)
1513  dev->stats.tx_aborted_errors++;
1514  if (tx_status & CSL)
1515  dev->stats.tx_carrier_errors++;
1516  if (tx_status & LC)
1517  dev->stats.tx_window_errors++;
1518  if (tx_status & UDF)
1519  dev->stats.tx_fifo_errors++;
1520  if ((tx_status & HF) && np->mii.full_duplex == 0)
1521  dev->stats.tx_heartbeat_errors++;
1522 
1523  } else {
1524  dev->stats.tx_bytes +=
1525  ((tx_control & PKTSMask) >> PKTSShift);
1526 
1527  dev->stats.collisions +=
1528  ((tx_status & NCRMask) >> NCRShift);
1529  dev->stats.tx_packets++;
1530  }
1531  } else {
1532  dev->stats.tx_bytes +=
1533  ((tx_control & PKTSMask) >> PKTSShift);
1534  dev->stats.tx_packets++;
1535  }
1536 
1537  /* Free the original skb. */
1538  pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1539  np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1540  dev_kfree_skb_irq(np->cur_tx->skbuff);
1541  np->cur_tx->skbuff = NULL;
1542  --np->really_tx_count;
1543  if (np->cur_tx->control & TXLD) {
1544  np->cur_tx = np->cur_tx->next_desc_logical;
1545  ++np->free_tx_count;
1546  } else {
1547  np->cur_tx = np->cur_tx->next_desc_logical;
1548  np->cur_tx = np->cur_tx->next_desc_logical;
1549  np->free_tx_count += 2;
1550  }
1551  num_tx++;
1552  } /* end of for loop */
1553 
1554  if (num_tx && np->free_tx_count >= 2)
1555  netif_wake_queue(dev);
1556 
1557  /* read transmit status for enhanced mode only */
1558  if (np->crvalue & CR_W_ENH) {
1559  long data;
1560 
1561  data = ioread32(ioaddr + TSR);
1562  dev->stats.tx_errors += (data & 0xff000000) >> 24;
1563  dev->stats.tx_aborted_errors +=
1564  (data & 0xff000000) >> 24;
1565  dev->stats.tx_window_errors +=
1566  (data & 0x00ff0000) >> 16;
1567  dev->stats.collisions += (data & 0x0000ffff);
1568  }
1569 
1570  if (--boguscnt < 0) {
1571  printk(KERN_WARNING "%s: Too much work at interrupt, "
1572  "status=0x%4.4x.\n", dev->name, intr_status);
1573  if (!np->reset_timer_armed) {
1574  np->reset_timer_armed = 1;
1575  np->reset_timer.expires = RUN_AT(HZ/2);
1576  add_timer(&np->reset_timer);
1577  stop_nic_rxtx(ioaddr, 0);
1578  netif_stop_queue(dev);
1579  /* or netif_tx_disable(dev); ?? */
1580  /* Prevent other paths from enabling tx,rx,intrs */
1581  np->crvalue_sv = np->crvalue;
1582  np->imrvalue_sv = np->imrvalue;
1583  np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */
1584  np->imrvalue = 0;
1585  }
1586 
1587  break;
1588  }
1589  } while (1);
1590 
1591  /* read the tally counters */
1592  /* missed pkts */
1593  dev->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1594 
1595  /* crc error */
1596  dev->stats.rx_crc_errors +=
1597  (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1598 
1599  if (debug)
1600  printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1601  dev->name, ioread32(ioaddr + ISR));
1602 
1603  iowrite32(np->imrvalue, ioaddr + IMR);
1604 
1605  spin_unlock(&np->lock);
1606 
1607  return IRQ_RETVAL(handled);
1608 }
1609 
1610 
1611 /* This routine is logically part of the interrupt handler, but separated
1612  for clarity and better register allocation. */
1613 static int netdev_rx(struct net_device *dev)
1614 {
1615  struct netdev_private *np = netdev_priv(dev);
1616  void __iomem *ioaddr = np->mem;
1617 
1618  /* If EOP is set on the next entry, it's a new packet. Send it up. */
1619  while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
1620  s32 rx_status = np->cur_rx->status;
1621 
1622  if (np->really_rx_count == 0)
1623  break;
1624 
1625  if (debug)
1626  printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status);
1627 
1628  if ((!((rx_status & RXFSD) && (rx_status & RXLSD))) ||
1629  (rx_status & ErrorSummary)) {
1630  if (rx_status & ErrorSummary) { /* there was a fatal error */
1631  if (debug)
1632  printk(KERN_DEBUG
1633  "%s: Receive error, Rx status %8.8x.\n",
1634  dev->name, rx_status);
1635 
1636  dev->stats.rx_errors++; /* end of a packet. */
1637  if (rx_status & (LONG | RUNT))
1638  dev->stats.rx_length_errors++;
1639  if (rx_status & RXER)
1640  dev->stats.rx_frame_errors++;
1641  if (rx_status & CRC)
1642  dev->stats.rx_crc_errors++;
1643  } else {
1644  int need_to_reset = 0;
1645  int desno = 0;
1646 
1647  if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */
1648  struct fealnx_desc *cur;
1649 
1650  /* check this packet is received completely? */
1651  cur = np->cur_rx;
1652  while (desno <= np->really_rx_count) {
1653  ++desno;
1654  if ((!(cur->status & RXOWN)) &&
1655  (cur->status & RXLSD))
1656  break;
1657  /* goto next rx descriptor */
1658  cur = cur->next_desc_logical;
1659  }
1660  if (desno > np->really_rx_count)
1661  need_to_reset = 1;
1662  } else /* RXLSD did not find, something error */
1663  need_to_reset = 1;
1664 
1665  if (need_to_reset == 0) {
1666  int i;
1667 
1668  dev->stats.rx_length_errors++;
1669 
1670  /* free all rx descriptors related this long pkt */
1671  for (i = 0; i < desno; ++i) {
1672  if (!np->cur_rx->skbuff) {
1673  printk(KERN_DEBUG
1674  "%s: I'm scared\n", dev->name);
1675  break;
1676  }
1677  np->cur_rx->status = RXOWN;
1678  np->cur_rx = np->cur_rx->next_desc_logical;
1679  }
1680  continue;
1681  } else { /* rx error, need to reset this chip */
1682  stop_nic_rx(ioaddr, np->crvalue);
1683  reset_rx_descriptors(dev);
1684  iowrite32(np->crvalue, ioaddr + TCRRCR);
1685  }
1686  break; /* exit the while loop */
1687  }
1688  } else { /* this received pkt is ok */
1689 
1690  struct sk_buff *skb;
1691  /* Omit the four octet CRC from the length. */
1692  short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4;
1693 
1694 #ifndef final_version
1695  if (debug)
1696  printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1697  " status %x.\n", pkt_len, rx_status);
1698 #endif
1699 
1700  /* Check if the packet is long enough to accept without copying
1701  to a minimally-sized skbuff. */
1702  if (pkt_len < rx_copybreak &&
1703  (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
1704  skb_reserve(skb, 2); /* 16 byte align the IP header */
1705  pci_dma_sync_single_for_cpu(np->pci_dev,
1706  np->cur_rx->buffer,
1707  np->rx_buf_sz,
1708  PCI_DMA_FROMDEVICE);
1709  /* Call copy + cksum if available. */
1710 
1711 #if ! defined(__alpha__)
1712  skb_copy_to_linear_data(skb,
1713  np->cur_rx->skbuff->data, pkt_len);
1714  skb_put(skb, pkt_len);
1715 #else
1716  memcpy(skb_put(skb, pkt_len),
1717  np->cur_rx->skbuff->data, pkt_len);
1718 #endif
1719  pci_dma_sync_single_for_device(np->pci_dev,
1720  np->cur_rx->buffer,
1721  np->rx_buf_sz,
1722  PCI_DMA_FROMDEVICE);
1723  } else {
1724  pci_unmap_single(np->pci_dev,
1725  np->cur_rx->buffer,
1726  np->rx_buf_sz,
1727  PCI_DMA_FROMDEVICE);
1728  skb_put(skb = np->cur_rx->skbuff, pkt_len);
1729  np->cur_rx->skbuff = NULL;
1730  --np->really_rx_count;
1731  }
1732  skb->protocol = eth_type_trans(skb, dev);
1733  netif_rx(skb);
1734  dev->stats.rx_packets++;
1735  dev->stats.rx_bytes += pkt_len;
1736  }
1737 
1738  np->cur_rx = np->cur_rx->next_desc_logical;
1739  } /* end of while loop */
1740 
1741  /* allocate skb for rx buffers */
1742  allocate_rx_buffers(dev);
1743 
1744  return 0;
1745 }
1746 
1747 
1748 static struct net_device_stats *get_stats(struct net_device *dev)
1749 {
1750  struct netdev_private *np = netdev_priv(dev);
1751  void __iomem *ioaddr = np->mem;
1752 
1753  /* The chip only need report frame silently dropped. */
1754  if (netif_running(dev)) {
1755  dev->stats.rx_missed_errors +=
1756  ioread32(ioaddr + TALLY) & 0x7fff;
1757  dev->stats.rx_crc_errors +=
1758  (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1759  }
1760 
1761  return &dev->stats;
1762 }
1763 
1764 
1765 /* for dev->set_multicast_list */
1766 static void set_rx_mode(struct net_device *dev)
1767 {
1768  spinlock_t *lp = &((struct netdev_private *)netdev_priv(dev))->lock;
1769  unsigned long flags;
1770  spin_lock_irqsave(lp, flags);
1771  __set_rx_mode(dev);
1772  spin_unlock_irqrestore(lp, flags);
1773 }
1774 
1775 
1776 /* Take lock before calling */
1777 static void __set_rx_mode(struct net_device *dev)
1778 {
1779  struct netdev_private *np = netdev_priv(dev);
1780  void __iomem *ioaddr = np->mem;
1781  u32 mc_filter[2]; /* Multicast hash filter */
1782  u32 rx_mode;
1783 
1784  if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1785  memset(mc_filter, 0xff, sizeof(mc_filter));
1786  rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM;
1787  } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1788  (dev->flags & IFF_ALLMULTI)) {
1789  /* Too many to match, or accept all multicasts. */
1790  memset(mc_filter, 0xff, sizeof(mc_filter));
1791  rx_mode = CR_W_AB | CR_W_AM;
1792  } else {
1793  struct netdev_hw_addr *ha;
1794 
1795  memset(mc_filter, 0, sizeof(mc_filter));
1796  netdev_for_each_mc_addr(ha, dev) {
1797  unsigned int bit;
1798  bit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F;
1799  mc_filter[bit >> 5] |= (1 << bit);
1800  }
1801  rx_mode = CR_W_AB | CR_W_AM;
1802  }
1803 
1804  stop_nic_rxtx(ioaddr, np->crvalue);
1805 
1806  iowrite32(mc_filter[0], ioaddr + MAR0);
1807  iowrite32(mc_filter[1], ioaddr + MAR1);
1808  np->crvalue &= ~CR_W_RXMODEMASK;
1809  np->crvalue |= rx_mode;
1810  iowrite32(np->crvalue, ioaddr + TCRRCR);
1811 }
1812 
1813 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1814 {
1815  struct netdev_private *np = netdev_priv(dev);
1816 
1817  strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1818  strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1819  strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
1820 }
1821 
1822 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1823 {
1824  struct netdev_private *np = netdev_priv(dev);
1825  int rc;
1826 
1827  spin_lock_irq(&np->lock);
1828  rc = mii_ethtool_gset(&np->mii, cmd);
1829  spin_unlock_irq(&np->lock);
1830 
1831  return rc;
1832 }
1833 
1834 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1835 {
1836  struct netdev_private *np = netdev_priv(dev);
1837  int rc;
1838 
1839  spin_lock_irq(&np->lock);
1840  rc = mii_ethtool_sset(&np->mii, cmd);
1841  spin_unlock_irq(&np->lock);
1842 
1843  return rc;
1844 }
1845 
1846 static int netdev_nway_reset(struct net_device *dev)
1847 {
1848  struct netdev_private *np = netdev_priv(dev);
1849  return mii_nway_restart(&np->mii);
1850 }
1851 
1852 static u32 netdev_get_link(struct net_device *dev)
1853 {
1854  struct netdev_private *np = netdev_priv(dev);
1855  return mii_link_ok(&np->mii);
1856 }
1857 
1858 static u32 netdev_get_msglevel(struct net_device *dev)
1859 {
1860  return debug;
1861 }
1862 
1863 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1864 {
1865  debug = value;
1866 }
1867 
1868 static const struct ethtool_ops netdev_ethtool_ops = {
1869  .get_drvinfo = netdev_get_drvinfo,
1870  .get_settings = netdev_get_settings,
1871  .set_settings = netdev_set_settings,
1872  .nway_reset = netdev_nway_reset,
1873  .get_link = netdev_get_link,
1874  .get_msglevel = netdev_get_msglevel,
1875  .set_msglevel = netdev_set_msglevel,
1876 };
1877 
1878 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1879 {
1880  struct netdev_private *np = netdev_priv(dev);
1881  int rc;
1882 
1883  if (!netif_running(dev))
1884  return -EINVAL;
1885 
1886  spin_lock_irq(&np->lock);
1887  rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
1888  spin_unlock_irq(&np->lock);
1889 
1890  return rc;
1891 }
1892 
1893 
1894 static int netdev_close(struct net_device *dev)
1895 {
1896  struct netdev_private *np = netdev_priv(dev);
1897  void __iomem *ioaddr = np->mem;
1898  int i;
1899 
1900  netif_stop_queue(dev);
1901 
1902  /* Disable interrupts by clearing the interrupt mask. */
1903  iowrite32(0x0000, ioaddr + IMR);
1904 
1905  /* Stop the chip's Tx and Rx processes. */
1906  stop_nic_rxtx(ioaddr, 0);
1907 
1908  del_timer_sync(&np->timer);
1909  del_timer_sync(&np->reset_timer);
1910 
1911  free_irq(np->pci_dev->irq, dev);
1912 
1913  /* Free all the skbuffs in the Rx queue. */
1914  for (i = 0; i < RX_RING_SIZE; i++) {
1915  struct sk_buff *skb = np->rx_ring[i].skbuff;
1916 
1917  np->rx_ring[i].status = 0;
1918  if (skb) {
1919  pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1920  np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1921  dev_kfree_skb(skb);
1922  np->rx_ring[i].skbuff = NULL;
1923  }
1924  }
1925 
1926  for (i = 0; i < TX_RING_SIZE; i++) {
1927  struct sk_buff *skb = np->tx_ring[i].skbuff;
1928 
1929  if (skb) {
1930  pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1931  skb->len, PCI_DMA_TODEVICE);
1932  dev_kfree_skb(skb);
1933  np->tx_ring[i].skbuff = NULL;
1934  }
1935  }
1936 
1937  return 0;
1938 }
1939 
1940 static DEFINE_PCI_DEVICE_TABLE(fealnx_pci_tbl) = {
1941  {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1942  {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1943  {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1944  {} /* terminate list */
1945 };
1946 MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl);
1947 
1948 
1949 static struct pci_driver fealnx_driver = {
1950  .name = "fealnx",
1951  .id_table = fealnx_pci_tbl,
1952  .probe = fealnx_init_one,
1953  .remove = __devexit_p(fealnx_remove_one),
1954 };
1955 
1956 static int __init fealnx_init(void)
1957 {
1958 /* when a module, this is printed whether or not devices are found in probe */
1959 #ifdef MODULE
1960  printk(version);
1961 #endif
1962 
1963  return pci_register_driver(&fealnx_driver);
1964 }
1965 
1966 static void __exit fealnx_exit(void)
1967 {
1968  pci_unregister_driver(&fealnx_driver);
1969 }
1970 
1971 module_init(fealnx_init);
1972 module_exit(fealnx_exit);
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