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fsmc_nand.c
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1 /*
2  * drivers/mtd/nand/fsmc_nand.c
3  *
4  * ST Microelectronics
5  * Flexible Static Memory Controller (FSMC)
6  * Driver for NAND portions
7  *
8  * Copyright © 2010 ST Microelectronics
9  * Vipin Kumar <[email protected]>
10  * Ashish Priyadarshi
11  *
12  * Based on drivers/mtd/nand/nomadik_nand.c
13  *
14  * This file is licensed under the terms of the GNU General Public
15  * License version 2. This program is licensed "as is" without any
16  * warranty of any kind, whether express or implied.
17  */
18 
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/dmaengine.h>
22 #include <linux/dma-direction.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/resource.h>
28 #include <linux/sched.h>
29 #include <linux/types.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/nand_ecc.h>
33 #include <linux/platform_device.h>
34 #include <linux/of.h>
35 #include <linux/mtd/partitions.h>
36 #include <linux/io.h>
37 #include <linux/slab.h>
38 #include <linux/mtd/fsmc.h>
39 #include <linux/amba/bus.h>
40 #include <mtd/mtd-abi.h>
41 
42 static struct nand_ecclayout fsmc_ecc1_128_layout = {
43  .eccbytes = 24,
44  .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
45  66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
46  .oobfree = {
47  {.offset = 8, .length = 8},
48  {.offset = 24, .length = 8},
49  {.offset = 40, .length = 8},
50  {.offset = 56, .length = 8},
51  {.offset = 72, .length = 8},
52  {.offset = 88, .length = 8},
53  {.offset = 104, .length = 8},
54  {.offset = 120, .length = 8}
55  }
56 };
57 
58 static struct nand_ecclayout fsmc_ecc1_64_layout = {
59  .eccbytes = 12,
60  .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52},
61  .oobfree = {
62  {.offset = 8, .length = 8},
63  {.offset = 24, .length = 8},
64  {.offset = 40, .length = 8},
65  {.offset = 56, .length = 8},
66  }
67 };
68 
69 static struct nand_ecclayout fsmc_ecc1_16_layout = {
70  .eccbytes = 3,
71  .eccpos = {2, 3, 4},
72  .oobfree = {
73  {.offset = 8, .length = 8},
74  }
75 };
76 
77 /*
78  * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes
79  * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46
80  * bytes are free for use.
81  */
82 static struct nand_ecclayout fsmc_ecc4_256_layout = {
83  .eccbytes = 208,
84  .eccpos = { 2, 3, 4, 5, 6, 7, 8,
85  9, 10, 11, 12, 13, 14,
86  18, 19, 20, 21, 22, 23, 24,
87  25, 26, 27, 28, 29, 30,
88  34, 35, 36, 37, 38, 39, 40,
89  41, 42, 43, 44, 45, 46,
90  50, 51, 52, 53, 54, 55, 56,
91  57, 58, 59, 60, 61, 62,
92  66, 67, 68, 69, 70, 71, 72,
93  73, 74, 75, 76, 77, 78,
94  82, 83, 84, 85, 86, 87, 88,
95  89, 90, 91, 92, 93, 94,
96  98, 99, 100, 101, 102, 103, 104,
97  105, 106, 107, 108, 109, 110,
98  114, 115, 116, 117, 118, 119, 120,
99  121, 122, 123, 124, 125, 126,
100  130, 131, 132, 133, 134, 135, 136,
101  137, 138, 139, 140, 141, 142,
102  146, 147, 148, 149, 150, 151, 152,
103  153, 154, 155, 156, 157, 158,
104  162, 163, 164, 165, 166, 167, 168,
105  169, 170, 171, 172, 173, 174,
106  178, 179, 180, 181, 182, 183, 184,
107  185, 186, 187, 188, 189, 190,
108  194, 195, 196, 197, 198, 199, 200,
109  201, 202, 203, 204, 205, 206,
110  210, 211, 212, 213, 214, 215, 216,
111  217, 218, 219, 220, 221, 222,
112  226, 227, 228, 229, 230, 231, 232,
113  233, 234, 235, 236, 237, 238,
114  242, 243, 244, 245, 246, 247, 248,
115  249, 250, 251, 252, 253, 254
116  },
117  .oobfree = {
118  {.offset = 15, .length = 3},
119  {.offset = 31, .length = 3},
120  {.offset = 47, .length = 3},
121  {.offset = 63, .length = 3},
122  {.offset = 79, .length = 3},
123  {.offset = 95, .length = 3},
124  {.offset = 111, .length = 3},
125  {.offset = 127, .length = 3},
126  {.offset = 143, .length = 3},
127  {.offset = 159, .length = 3},
128  {.offset = 175, .length = 3},
129  {.offset = 191, .length = 3},
130  {.offset = 207, .length = 3},
131  {.offset = 223, .length = 3},
132  {.offset = 239, .length = 3},
133  {.offset = 255, .length = 1}
134  }
135 };
136 
137 /*
138  * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
139  * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
140  * bytes are free for use.
141  */
142 static struct nand_ecclayout fsmc_ecc4_224_layout = {
143  .eccbytes = 104,
144  .eccpos = { 2, 3, 4, 5, 6, 7, 8,
145  9, 10, 11, 12, 13, 14,
146  18, 19, 20, 21, 22, 23, 24,
147  25, 26, 27, 28, 29, 30,
148  34, 35, 36, 37, 38, 39, 40,
149  41, 42, 43, 44, 45, 46,
150  50, 51, 52, 53, 54, 55, 56,
151  57, 58, 59, 60, 61, 62,
152  66, 67, 68, 69, 70, 71, 72,
153  73, 74, 75, 76, 77, 78,
154  82, 83, 84, 85, 86, 87, 88,
155  89, 90, 91, 92, 93, 94,
156  98, 99, 100, 101, 102, 103, 104,
157  105, 106, 107, 108, 109, 110,
158  114, 115, 116, 117, 118, 119, 120,
159  121, 122, 123, 124, 125, 126
160  },
161  .oobfree = {
162  {.offset = 15, .length = 3},
163  {.offset = 31, .length = 3},
164  {.offset = 47, .length = 3},
165  {.offset = 63, .length = 3},
166  {.offset = 79, .length = 3},
167  {.offset = 95, .length = 3},
168  {.offset = 111, .length = 3},
169  {.offset = 127, .length = 97}
170  }
171 };
172 
173 /*
174  * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes
175  * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22
176  * bytes are free for use.
177  */
178 static struct nand_ecclayout fsmc_ecc4_128_layout = {
179  .eccbytes = 104,
180  .eccpos = { 2, 3, 4, 5, 6, 7, 8,
181  9, 10, 11, 12, 13, 14,
182  18, 19, 20, 21, 22, 23, 24,
183  25, 26, 27, 28, 29, 30,
184  34, 35, 36, 37, 38, 39, 40,
185  41, 42, 43, 44, 45, 46,
186  50, 51, 52, 53, 54, 55, 56,
187  57, 58, 59, 60, 61, 62,
188  66, 67, 68, 69, 70, 71, 72,
189  73, 74, 75, 76, 77, 78,
190  82, 83, 84, 85, 86, 87, 88,
191  89, 90, 91, 92, 93, 94,
192  98, 99, 100, 101, 102, 103, 104,
193  105, 106, 107, 108, 109, 110,
194  114, 115, 116, 117, 118, 119, 120,
195  121, 122, 123, 124, 125, 126
196  },
197  .oobfree = {
198  {.offset = 15, .length = 3},
199  {.offset = 31, .length = 3},
200  {.offset = 47, .length = 3},
201  {.offset = 63, .length = 3},
202  {.offset = 79, .length = 3},
203  {.offset = 95, .length = 3},
204  {.offset = 111, .length = 3},
205  {.offset = 127, .length = 1}
206  }
207 };
208 
209 /*
210  * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of
211  * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10
212  * bytes are free for use.
213  */
214 static struct nand_ecclayout fsmc_ecc4_64_layout = {
215  .eccbytes = 52,
216  .eccpos = { 2, 3, 4, 5, 6, 7, 8,
217  9, 10, 11, 12, 13, 14,
218  18, 19, 20, 21, 22, 23, 24,
219  25, 26, 27, 28, 29, 30,
220  34, 35, 36, 37, 38, 39, 40,
221  41, 42, 43, 44, 45, 46,
222  50, 51, 52, 53, 54, 55, 56,
223  57, 58, 59, 60, 61, 62,
224  },
225  .oobfree = {
226  {.offset = 15, .length = 3},
227  {.offset = 31, .length = 3},
228  {.offset = 47, .length = 3},
229  {.offset = 63, .length = 1},
230  }
231 };
232 
233 /*
234  * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of
235  * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One
236  * byte is free for use.
237  */
238 static struct nand_ecclayout fsmc_ecc4_16_layout = {
239  .eccbytes = 13,
240  .eccpos = { 0, 1, 2, 3, 6, 7, 8,
241  9, 10, 11, 12, 13, 14
242  },
243  .oobfree = {
244  {.offset = 15, .length = 1},
245  }
246 };
247 
248 /*
249  * ECC placement definitions in oobfree type format.
250  * There are 13 bytes of ecc for every 512 byte block and it has to be read
251  * consecutively and immediately after the 512 byte data block for hardware to
252  * generate the error bit offsets in 512 byte data.
253  * Managing the ecc bytes in the following way makes it easier for software to
254  * read ecc bytes consecutive to data bytes. This way is similar to
255  * oobfree structure maintained already in generic nand driver
256  */
257 static struct fsmc_eccplace fsmc_ecc4_lp_place = {
258  .eccplace = {
259  {.offset = 2, .length = 13},
260  {.offset = 18, .length = 13},
261  {.offset = 34, .length = 13},
262  {.offset = 50, .length = 13},
263  {.offset = 66, .length = 13},
264  {.offset = 82, .length = 13},
265  {.offset = 98, .length = 13},
266  {.offset = 114, .length = 13}
267  }
268 };
269 
270 static struct fsmc_eccplace fsmc_ecc4_sp_place = {
271  .eccplace = {
272  {.offset = 0, .length = 4},
273  {.offset = 6, .length = 9}
274  }
275 };
276 
300 struct fsmc_nand_data {
301  u32 pid;
302  struct mtd_info mtd;
303  struct nand_chip nand;
304  struct mtd_partition *partitions;
305  unsigned int nr_partitions;
306 
307  struct fsmc_eccplace *ecc_place;
308  unsigned int bank;
309  struct device *dev;
310  enum access_mode mode;
311  struct clk *clk;
312 
313  /* DMA related objects */
314  struct dma_chan *read_dma_chan;
315  struct dma_chan *write_dma_chan;
316  struct completion dma_access_complete;
317 
318  struct fsmc_nand_timings *dev_timings;
319 
320  dma_addr_t data_pa;
321  void __iomem *data_va;
322  void __iomem *cmd_va;
323  void __iomem *addr_va;
324  void __iomem *regs_va;
325 
326  void (*select_chip)(uint32_t bank, uint32_t busw);
327 };
328 
329 /* Assert CS signal based on chipnr */
330 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
331 {
332  struct nand_chip *chip = mtd->priv;
333  struct fsmc_nand_data *host;
334 
335  host = container_of(mtd, struct fsmc_nand_data, mtd);
336 
337  switch (chipnr) {
338  case -1:
339  chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
340  break;
341  case 0:
342  case 1:
343  case 2:
344  case 3:
345  if (host->select_chip)
346  host->select_chip(chipnr,
347  chip->options & NAND_BUSWIDTH_16);
348  break;
349 
350  default:
351  BUG();
352  }
353 }
354 
355 /*
356  * fsmc_cmd_ctrl - For facilitaing Hardware access
357  * This routine allows hardware specific access to control-lines(ALE,CLE)
358  */
359 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
360 {
361  struct nand_chip *this = mtd->priv;
362  struct fsmc_nand_data *host = container_of(mtd,
363  struct fsmc_nand_data, mtd);
364  void *__iomem *regs = host->regs_va;
365  unsigned int bank = host->bank;
366 
367  if (ctrl & NAND_CTRL_CHANGE) {
368  u32 pc;
369 
370  if (ctrl & NAND_CLE) {
371  this->IO_ADDR_R = host->cmd_va;
372  this->IO_ADDR_W = host->cmd_va;
373  } else if (ctrl & NAND_ALE) {
374  this->IO_ADDR_R = host->addr_va;
375  this->IO_ADDR_W = host->addr_va;
376  } else {
377  this->IO_ADDR_R = host->data_va;
378  this->IO_ADDR_W = host->data_va;
379  }
380 
381  pc = readl(FSMC_NAND_REG(regs, bank, PC));
382  if (ctrl & NAND_NCE)
383  pc |= FSMC_ENABLE;
384  else
385  pc &= ~FSMC_ENABLE;
386  writel(pc, FSMC_NAND_REG(regs, bank, PC));
387  }
388 
389  mb();
390 
391  if (cmd != NAND_CMD_NONE)
392  writeb(cmd, this->IO_ADDR_W);
393 }
394 
395 /*
396  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
397  *
398  * This routine initializes timing parameters related to NAND memory access in
399  * FSMC registers
400  */
401 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
402  uint32_t busw, struct fsmc_nand_timings *timings)
403 {
404  uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
405  uint32_t tclr, tar, thiz, thold, twait, tset;
406  struct fsmc_nand_timings *tims;
407  struct fsmc_nand_timings default_timings = {
408  .tclr = FSMC_TCLR_1,
409  .tar = FSMC_TAR_1,
410  .thiz = FSMC_THIZ_1,
411  .thold = FSMC_THOLD_4,
412  .twait = FSMC_TWAIT_6,
413  .tset = FSMC_TSET_0,
414  };
415 
416  if (timings)
417  tims = timings;
418  else
419  tims = &default_timings;
420 
421  tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
422  tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
423  thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
424  thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
425  twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
426  tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
427 
428  if (busw)
429  writel(value | FSMC_DEVWID_16, FSMC_NAND_REG(regs, bank, PC));
430  else
431  writel(value | FSMC_DEVWID_8, FSMC_NAND_REG(regs, bank, PC));
432 
433  writel(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
434  FSMC_NAND_REG(regs, bank, PC));
435  writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, COMM));
436  writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, ATTRIB));
437 }
438 
439 /*
440  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
441  */
442 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
443 {
444  struct fsmc_nand_data *host = container_of(mtd,
445  struct fsmc_nand_data, mtd);
446  void __iomem *regs = host->regs_va;
447  uint32_t bank = host->bank;
448 
449  writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
450  FSMC_NAND_REG(regs, bank, PC));
451  writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
452  FSMC_NAND_REG(regs, bank, PC));
453  writel(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
454  FSMC_NAND_REG(regs, bank, PC));
455 }
456 
457 /*
458  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
459  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
460  * max of 8-bits)
461  */
462 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
463  uint8_t *ecc)
464 {
465  struct fsmc_nand_data *host = container_of(mtd,
466  struct fsmc_nand_data, mtd);
467  void __iomem *regs = host->regs_va;
468  uint32_t bank = host->bank;
469  uint32_t ecc_tmp;
470  unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
471 
472  do {
473  if (readl(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
474  break;
475  else
476  cond_resched();
477  } while (!time_after_eq(jiffies, deadline));
478 
479  if (time_after_eq(jiffies, deadline)) {
480  dev_err(host->dev, "calculate ecc timed out\n");
481  return -ETIMEDOUT;
482  }
483 
484  ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));
485  ecc[0] = (uint8_t) (ecc_tmp >> 0);
486  ecc[1] = (uint8_t) (ecc_tmp >> 8);
487  ecc[2] = (uint8_t) (ecc_tmp >> 16);
488  ecc[3] = (uint8_t) (ecc_tmp >> 24);
489 
490  ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC2));
491  ecc[4] = (uint8_t) (ecc_tmp >> 0);
492  ecc[5] = (uint8_t) (ecc_tmp >> 8);
493  ecc[6] = (uint8_t) (ecc_tmp >> 16);
494  ecc[7] = (uint8_t) (ecc_tmp >> 24);
495 
496  ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC3));
497  ecc[8] = (uint8_t) (ecc_tmp >> 0);
498  ecc[9] = (uint8_t) (ecc_tmp >> 8);
499  ecc[10] = (uint8_t) (ecc_tmp >> 16);
500  ecc[11] = (uint8_t) (ecc_tmp >> 24);
501 
502  ecc_tmp = readl(FSMC_NAND_REG(regs, bank, STS));
503  ecc[12] = (uint8_t) (ecc_tmp >> 16);
504 
505  return 0;
506 }
507 
508 /*
509  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
510  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
511  * max of 1-bit)
512  */
513 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
514  uint8_t *ecc)
515 {
516  struct fsmc_nand_data *host = container_of(mtd,
517  struct fsmc_nand_data, mtd);
518  void __iomem *regs = host->regs_va;
519  uint32_t bank = host->bank;
520  uint32_t ecc_tmp;
521 
522  ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));
523  ecc[0] = (uint8_t) (ecc_tmp >> 0);
524  ecc[1] = (uint8_t) (ecc_tmp >> 8);
525  ecc[2] = (uint8_t) (ecc_tmp >> 16);
526 
527  return 0;
528 }
529 
530 /* Count the number of 0's in buff upto a max of max_bits */
531 static int count_written_bits(uint8_t *buff, int size, int max_bits)
532 {
533  int k, written_bits = 0;
534 
535  for (k = 0; k < size; k++) {
536  written_bits += hweight8(~buff[k]);
537  if (written_bits > max_bits)
538  break;
539  }
540 
541  return written_bits;
542 }
543 
544 static void dma_complete(void *param)
545 {
546  struct fsmc_nand_data *host = param;
547 
548  complete(&host->dma_access_complete);
549 }
550 
551 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
552  enum dma_data_direction direction)
553 {
554  struct dma_chan *chan;
555  struct dma_device *dma_dev;
556  struct dma_async_tx_descriptor *tx;
557  dma_addr_t dma_dst, dma_src, dma_addr;
558  dma_cookie_t cookie;
559  unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
560  int ret;
561 
562  if (direction == DMA_TO_DEVICE)
563  chan = host->write_dma_chan;
564  else if (direction == DMA_FROM_DEVICE)
565  chan = host->read_dma_chan;
566  else
567  return -EINVAL;
568 
569  dma_dev = chan->device;
570  dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
571 
572  if (direction == DMA_TO_DEVICE) {
573  dma_src = dma_addr;
574  dma_dst = host->data_pa;
575  flags |= DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_SKIP_DEST_UNMAP;
576  } else {
577  dma_src = host->data_pa;
578  dma_dst = dma_addr;
579  flags |= DMA_COMPL_DEST_UNMAP_SINGLE | DMA_COMPL_SKIP_SRC_UNMAP;
580  }
581 
582  tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
583  len, flags);
584 
585  if (!tx) {
586  dev_err(host->dev, "device_prep_dma_memcpy error\n");
587  dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
588  return -EIO;
589  }
590 
591  tx->callback = dma_complete;
592  tx->callback_param = host;
593  cookie = tx->tx_submit(tx);
594 
595  ret = dma_submit_error(cookie);
596  if (ret) {
597  dev_err(host->dev, "dma_submit_error %d\n", cookie);
598  return ret;
599  }
600 
601  dma_async_issue_pending(chan);
602 
603  ret =
604  wait_for_completion_interruptible_timeout(&host->dma_access_complete,
605  msecs_to_jiffies(3000));
606  if (ret <= 0) {
607  chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
608  dev_err(host->dev, "wait_for_completion_timeout\n");
609  return ret ? ret : -ETIMEDOUT;
610  }
611 
612  return 0;
613 }
614 
615 /*
616  * fsmc_write_buf - write buffer to chip
617  * @mtd: MTD device structure
618  * @buf: data buffer
619  * @len: number of bytes to write
620  */
621 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
622 {
623  int i;
624  struct nand_chip *chip = mtd->priv;
625 
626  if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
627  IS_ALIGNED(len, sizeof(uint32_t))) {
628  uint32_t *p = (uint32_t *)buf;
629  len = len >> 2;
630  for (i = 0; i < len; i++)
631  writel(p[i], chip->IO_ADDR_W);
632  } else {
633  for (i = 0; i < len; i++)
634  writeb(buf[i], chip->IO_ADDR_W);
635  }
636 }
637 
638 /*
639  * fsmc_read_buf - read chip data into buffer
640  * @mtd: MTD device structure
641  * @buf: buffer to store date
642  * @len: number of bytes to read
643  */
644 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
645 {
646  int i;
647  struct nand_chip *chip = mtd->priv;
648 
649  if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
650  IS_ALIGNED(len, sizeof(uint32_t))) {
651  uint32_t *p = (uint32_t *)buf;
652  len = len >> 2;
653  for (i = 0; i < len; i++)
654  p[i] = readl(chip->IO_ADDR_R);
655  } else {
656  for (i = 0; i < len; i++)
657  buf[i] = readb(chip->IO_ADDR_R);
658  }
659 }
660 
661 /*
662  * fsmc_read_buf_dma - read chip data into buffer
663  * @mtd: MTD device structure
664  * @buf: buffer to store date
665  * @len: number of bytes to read
666  */
667 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
668 {
669  struct fsmc_nand_data *host;
670 
671  host = container_of(mtd, struct fsmc_nand_data, mtd);
672  dma_xfer(host, buf, len, DMA_FROM_DEVICE);
673 }
674 
675 /*
676  * fsmc_write_buf_dma - write buffer to chip
677  * @mtd: MTD device structure
678  * @buf: data buffer
679  * @len: number of bytes to write
680  */
681 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
682  int len)
683 {
684  struct fsmc_nand_data *host;
685 
686  host = container_of(mtd, struct fsmc_nand_data, mtd);
687  dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
688 }
689 
690 /*
691  * fsmc_read_page_hwecc
692  * @mtd: mtd info structure
693  * @chip: nand chip info structure
694  * @buf: buffer to store read data
695  * @oob_required: caller expects OOB data read to chip->oob_poi
696  * @page: page number to read
697  *
698  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
699  * performed in a strict sequence as follows:
700  * data(512 byte) -> ecc(13 byte)
701  * After this read, fsmc hardware generates and reports error data bits(up to a
702  * max of 8 bits)
703  */
704 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
705  uint8_t *buf, int oob_required, int page)
706 {
707  struct fsmc_nand_data *host = container_of(mtd,
708  struct fsmc_nand_data, mtd);
709  struct fsmc_eccplace *ecc_place = host->ecc_place;
710  int i, j, s, stat, eccsize = chip->ecc.size;
711  int eccbytes = chip->ecc.bytes;
712  int eccsteps = chip->ecc.steps;
713  uint8_t *p = buf;
714  uint8_t *ecc_calc = chip->buffers->ecccalc;
715  uint8_t *ecc_code = chip->buffers->ecccode;
716  int off, len, group = 0;
717  /*
718  * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
719  * end up reading 14 bytes (7 words) from oob. The local array is
720  * to maintain word alignment
721  */
722  uint16_t ecc_oob[7];
723  uint8_t *oob = (uint8_t *)&ecc_oob[0];
724  unsigned int max_bitflips = 0;
725 
726  for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
727  chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
728  chip->ecc.hwctl(mtd, NAND_ECC_READ);
729  chip->read_buf(mtd, p, eccsize);
730 
731  for (j = 0; j < eccbytes;) {
732  off = ecc_place->eccplace[group].offset;
733  len = ecc_place->eccplace[group].length;
734  group++;
735 
736  /*
737  * length is intentionally kept a higher multiple of 2
738  * to read at least 13 bytes even in case of 16 bit NAND
739  * devices
740  */
741  if (chip->options & NAND_BUSWIDTH_16)
742  len = roundup(len, 2);
743 
744  chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
745  chip->read_buf(mtd, oob + j, len);
746  j += len;
747  }
748 
749  memcpy(&ecc_code[i], oob, chip->ecc.bytes);
750  chip->ecc.calculate(mtd, p, &ecc_calc[i]);
751 
752  stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
753  if (stat < 0) {
754  mtd->ecc_stats.failed++;
755  } else {
756  mtd->ecc_stats.corrected += stat;
757  max_bitflips = max_t(unsigned int, max_bitflips, stat);
758  }
759  }
760 
761  return max_bitflips;
762 }
763 
764 /*
765  * fsmc_bch8_correct_data
766  * @mtd: mtd info structure
767  * @dat: buffer of read data
768  * @read_ecc: ecc read from device spare area
769  * @calc_ecc: ecc calculated from read data
770  *
771  * calc_ecc is a 104 bit information containing maximum of 8 error
772  * offset informations of 13 bits each in 512 bytes of read data.
773  */
774 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
775  uint8_t *read_ecc, uint8_t *calc_ecc)
776 {
777  struct fsmc_nand_data *host = container_of(mtd,
778  struct fsmc_nand_data, mtd);
779  struct nand_chip *chip = mtd->priv;
780  void __iomem *regs = host->regs_va;
781  unsigned int bank = host->bank;
782  uint32_t err_idx[8];
783  uint32_t num_err, i;
784  uint32_t ecc1, ecc2, ecc3, ecc4;
785 
786  num_err = (readl(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
787 
788  /* no bit flipping */
789  if (likely(num_err == 0))
790  return 0;
791 
792  /* too many errors */
793  if (unlikely(num_err > 8)) {
794  /*
795  * This is a temporary erase check. A newly erased page read
796  * would result in an ecc error because the oob data is also
797  * erased to FF and the calculated ecc for an FF data is not
798  * FF..FF.
799  * This is a workaround to skip performing correction in case
800  * data is FF..FF
801  *
802  * Logic:
803  * For every page, each bit written as 0 is counted until these
804  * number of bits are greater than 8 (the maximum correction
805  * capability of FSMC for each 512 + 13 bytes)
806  */
807 
808  int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
809  int bits_data = count_written_bits(dat, chip->ecc.size, 8);
810 
811  if ((bits_ecc + bits_data) <= 8) {
812  if (bits_data)
813  memset(dat, 0xff, chip->ecc.size);
814  return bits_data;
815  }
816 
817  return -EBADMSG;
818  }
819 
820  /*
821  * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
822  * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
823  *
824  * calc_ecc is a 104 bit information containing maximum of 8 error
825  * offset informations of 13 bits each. calc_ecc is copied into a
826  * uint64_t array and error offset indexes are populated in err_idx
827  * array
828  */
829  ecc1 = readl(FSMC_NAND_REG(regs, bank, ECC1));
830  ecc2 = readl(FSMC_NAND_REG(regs, bank, ECC2));
831  ecc3 = readl(FSMC_NAND_REG(regs, bank, ECC3));
832  ecc4 = readl(FSMC_NAND_REG(regs, bank, STS));
833 
834  err_idx[0] = (ecc1 >> 0) & 0x1FFF;
835  err_idx[1] = (ecc1 >> 13) & 0x1FFF;
836  err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
837  err_idx[3] = (ecc2 >> 7) & 0x1FFF;
838  err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
839  err_idx[5] = (ecc3 >> 1) & 0x1FFF;
840  err_idx[6] = (ecc3 >> 14) & 0x1FFF;
841  err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
842 
843  i = 0;
844  while (num_err--) {
845  change_bit(0, (unsigned long *)&err_idx[i]);
846  change_bit(1, (unsigned long *)&err_idx[i]);
847 
848  if (err_idx[i] < chip->ecc.size * 8) {
849  change_bit(err_idx[i], (unsigned long *)dat);
850  i++;
851  }
852  }
853  return i;
854 }
855 
856 static bool filter(struct dma_chan *chan, void *slave)
857 {
858  chan->private = slave;
859  return true;
860 }
861 
862 #ifdef CONFIG_OF
863 static int __devinit fsmc_nand_probe_config_dt(struct platform_device *pdev,
864  struct device_node *np)
865 {
866  struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
867  u32 val;
868 
869  /* Set default NAND width to 8 bits */
870  pdata->width = 8;
871  if (!of_property_read_u32(np, "bank-width", &val)) {
872  if (val == 2) {
873  pdata->width = 16;
874  } else if (val != 1) {
875  dev_err(&pdev->dev, "invalid bank-width %u\n", val);
876  return -EINVAL;
877  }
878  }
879  of_property_read_u32(np, "st,ale-off", &pdata->ale_off);
880  of_property_read_u32(np, "st,cle-off", &pdata->cle_off);
881  if (of_get_property(np, "nand-skip-bbtscan", NULL))
882  pdata->options = NAND_SKIP_BBTSCAN;
883 
884  return 0;
885 }
886 #else
887 static int __devinit fsmc_nand_probe_config_dt(struct platform_device *pdev,
888  struct device_node *np)
889 {
890  return -ENOSYS;
891 }
892 #endif
893 
894 /*
895  * fsmc_nand_probe - Probe function
896  * @pdev: platform device structure
897  */
898 static int __init fsmc_nand_probe(struct platform_device *pdev)
899 {
900  struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
901  struct device_node __maybe_unused *np = pdev->dev.of_node;
902  struct mtd_part_parser_data ppdata = {};
903  struct fsmc_nand_data *host;
904  struct mtd_info *mtd;
905  struct nand_chip *nand;
906  struct resource *res;
907  dma_cap_mask_t mask;
908  int ret = 0;
909  u32 pid;
910  int i;
911 
912  if (np) {
913  pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
914  pdev->dev.platform_data = pdata;
915  ret = fsmc_nand_probe_config_dt(pdev, np);
916  if (ret) {
917  dev_err(&pdev->dev, "no platform data\n");
918  return -ENODEV;
919  }
920  }
921 
922  if (!pdata) {
923  dev_err(&pdev->dev, "platform data is NULL\n");
924  return -EINVAL;
925  }
926 
927  /* Allocate memory for the device structure (and zero it) */
928  host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
929  if (!host) {
930  dev_err(&pdev->dev, "failed to allocate device structure\n");
931  return -ENOMEM;
932  }
933 
934  res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
935  if (!res)
936  return -EINVAL;
937 
938  if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
939  pdev->name)) {
940  dev_err(&pdev->dev, "Failed to get memory data resourse\n");
941  return -ENOENT;
942  }
943 
944  host->data_pa = (dma_addr_t)res->start;
945  host->data_va = devm_ioremap(&pdev->dev, res->start,
946  resource_size(res));
947  if (!host->data_va) {
948  dev_err(&pdev->dev, "data ioremap failed\n");
949  return -ENOMEM;
950  }
951 
952  if (!devm_request_mem_region(&pdev->dev, res->start + pdata->ale_off,
953  resource_size(res), pdev->name)) {
954  dev_err(&pdev->dev, "Failed to get memory ale resourse\n");
955  return -ENOENT;
956  }
957 
958  host->addr_va = devm_ioremap(&pdev->dev, res->start + pdata->ale_off,
959  resource_size(res));
960  if (!host->addr_va) {
961  dev_err(&pdev->dev, "ale ioremap failed\n");
962  return -ENOMEM;
963  }
964 
965  if (!devm_request_mem_region(&pdev->dev, res->start + pdata->cle_off,
966  resource_size(res), pdev->name)) {
967  dev_err(&pdev->dev, "Failed to get memory cle resourse\n");
968  return -ENOENT;
969  }
970 
971  host->cmd_va = devm_ioremap(&pdev->dev, res->start + pdata->cle_off,
972  resource_size(res));
973  if (!host->cmd_va) {
974  dev_err(&pdev->dev, "ale ioremap failed\n");
975  return -ENOMEM;
976  }
977 
978  res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
979  if (!res)
980  return -EINVAL;
981 
982  if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
983  pdev->name)) {
984  dev_err(&pdev->dev, "Failed to get memory regs resourse\n");
985  return -ENOENT;
986  }
987 
988  host->regs_va = devm_ioremap(&pdev->dev, res->start,
989  resource_size(res));
990  if (!host->regs_va) {
991  dev_err(&pdev->dev, "regs ioremap failed\n");
992  return -ENOMEM;
993  }
994 
995  host->clk = clk_get(&pdev->dev, NULL);
996  if (IS_ERR(host->clk)) {
997  dev_err(&pdev->dev, "failed to fetch block clock\n");
998  return PTR_ERR(host->clk);
999  }
1000 
1001  ret = clk_prepare_enable(host->clk);
1002  if (ret)
1003  goto err_clk_prepare_enable;
1004 
1005  /*
1006  * This device ID is actually a common AMBA ID as used on the
1007  * AMBA PrimeCell bus. However it is not a PrimeCell.
1008  */
1009  for (pid = 0, i = 0; i < 4; i++)
1010  pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
1011  host->pid = pid;
1012  dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
1013  "revision %02x, config %02x\n",
1014  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
1015  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
1016 
1017  host->bank = pdata->bank;
1018  host->select_chip = pdata->select_bank;
1019  host->partitions = pdata->partitions;
1020  host->nr_partitions = pdata->nr_partitions;
1021  host->dev = &pdev->dev;
1022  host->dev_timings = pdata->nand_timings;
1023  host->mode = pdata->mode;
1024 
1025  if (host->mode == USE_DMA_ACCESS)
1026  init_completion(&host->dma_access_complete);
1027 
1028  /* Link all private pointers */
1029  mtd = &host->mtd;
1030  nand = &host->nand;
1031  mtd->priv = nand;
1032  nand->priv = host;
1033 
1034  host->mtd.owner = THIS_MODULE;
1035  nand->IO_ADDR_R = host->data_va;
1036  nand->IO_ADDR_W = host->data_va;
1037  nand->cmd_ctrl = fsmc_cmd_ctrl;
1038  nand->chip_delay = 30;
1039 
1040  nand->ecc.mode = NAND_ECC_HW;
1041  nand->ecc.hwctl = fsmc_enable_hwecc;
1042  nand->ecc.size = 512;
1043  nand->options = pdata->options;
1044  nand->select_chip = fsmc_select_chip;
1045  nand->badblockbits = 7;
1046 
1047  if (pdata->width == FSMC_NAND_BW16)
1048  nand->options |= NAND_BUSWIDTH_16;
1049 
1050  switch (host->mode) {
1051  case USE_DMA_ACCESS:
1052  dma_cap_zero(mask);
1053  dma_cap_set(DMA_MEMCPY, mask);
1054  host->read_dma_chan = dma_request_channel(mask, filter,
1055  pdata->read_dma_priv);
1056  if (!host->read_dma_chan) {
1057  dev_err(&pdev->dev, "Unable to get read dma channel\n");
1058  goto err_req_read_chnl;
1059  }
1060  host->write_dma_chan = dma_request_channel(mask, filter,
1061  pdata->write_dma_priv);
1062  if (!host->write_dma_chan) {
1063  dev_err(&pdev->dev, "Unable to get write dma channel\n");
1064  goto err_req_write_chnl;
1065  }
1066  nand->read_buf = fsmc_read_buf_dma;
1067  nand->write_buf = fsmc_write_buf_dma;
1068  break;
1069 
1070  default:
1071  case USE_WORD_ACCESS:
1072  nand->read_buf = fsmc_read_buf;
1073  nand->write_buf = fsmc_write_buf;
1074  break;
1075  }
1076 
1077  fsmc_nand_setup(host->regs_va, host->bank,
1078  nand->options & NAND_BUSWIDTH_16,
1079  host->dev_timings);
1080 
1081  if (AMBA_REV_BITS(host->pid) >= 8) {
1082  nand->ecc.read_page = fsmc_read_page_hwecc;
1083  nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1084  nand->ecc.correct = fsmc_bch8_correct_data;
1085  nand->ecc.bytes = 13;
1086  nand->ecc.strength = 8;
1087  } else {
1088  nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1089  nand->ecc.correct = nand_correct_data;
1090  nand->ecc.bytes = 3;
1091  nand->ecc.strength = 1;
1092  }
1093 
1094  /*
1095  * Scan to find existence of the device
1096  */
1097  if (nand_scan_ident(&host->mtd, 1, NULL)) {
1098  ret = -ENXIO;
1099  dev_err(&pdev->dev, "No NAND Device found!\n");
1100  goto err_scan_ident;
1101  }
1102 
1103  if (AMBA_REV_BITS(host->pid) >= 8) {
1104  switch (host->mtd.oobsize) {
1105  case 16:
1106  nand->ecc.layout = &fsmc_ecc4_16_layout;
1107  host->ecc_place = &fsmc_ecc4_sp_place;
1108  break;
1109  case 64:
1110  nand->ecc.layout = &fsmc_ecc4_64_layout;
1111  host->ecc_place = &fsmc_ecc4_lp_place;
1112  break;
1113  case 128:
1114  nand->ecc.layout = &fsmc_ecc4_128_layout;
1115  host->ecc_place = &fsmc_ecc4_lp_place;
1116  break;
1117  case 224:
1118  nand->ecc.layout = &fsmc_ecc4_224_layout;
1119  host->ecc_place = &fsmc_ecc4_lp_place;
1120  break;
1121  case 256:
1122  nand->ecc.layout = &fsmc_ecc4_256_layout;
1123  host->ecc_place = &fsmc_ecc4_lp_place;
1124  break;
1125  default:
1126  printk(KERN_WARNING "No oob scheme defined for "
1127  "oobsize %d\n", mtd->oobsize);
1128  BUG();
1129  }
1130  } else {
1131  switch (host->mtd.oobsize) {
1132  case 16:
1133  nand->ecc.layout = &fsmc_ecc1_16_layout;
1134  break;
1135  case 64:
1136  nand->ecc.layout = &fsmc_ecc1_64_layout;
1137  break;
1138  case 128:
1139  nand->ecc.layout = &fsmc_ecc1_128_layout;
1140  break;
1141  default:
1142  printk(KERN_WARNING "No oob scheme defined for "
1143  "oobsize %d\n", mtd->oobsize);
1144  BUG();
1145  }
1146  }
1147 
1148  /* Second stage of scan to fill MTD data-structures */
1149  if (nand_scan_tail(&host->mtd)) {
1150  ret = -ENXIO;
1151  goto err_probe;
1152  }
1153 
1154  /*
1155  * The partition information can is accessed by (in the same precedence)
1156  *
1157  * command line through Bootloader,
1158  * platform data,
1159  * default partition information present in driver.
1160  */
1161  /*
1162  * Check for partition info passed
1163  */
1164  host->mtd.name = "nand";
1165  ppdata.of_node = np;
1166  ret = mtd_device_parse_register(&host->mtd, NULL, &ppdata,
1167  host->partitions, host->nr_partitions);
1168  if (ret)
1169  goto err_probe;
1170 
1171  platform_set_drvdata(pdev, host);
1172  dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1173  return 0;
1174 
1175 err_probe:
1176 err_scan_ident:
1177  if (host->mode == USE_DMA_ACCESS)
1178  dma_release_channel(host->write_dma_chan);
1179 err_req_write_chnl:
1180  if (host->mode == USE_DMA_ACCESS)
1181  dma_release_channel(host->read_dma_chan);
1182 err_req_read_chnl:
1183  clk_disable_unprepare(host->clk);
1184 err_clk_prepare_enable:
1185  clk_put(host->clk);
1186  return ret;
1187 }
1188 
1189 /*
1190  * Clean up routine
1191  */
1192 static int fsmc_nand_remove(struct platform_device *pdev)
1193 {
1194  struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1195 
1196  platform_set_drvdata(pdev, NULL);
1197 
1198  if (host) {
1199  nand_release(&host->mtd);
1200 
1201  if (host->mode == USE_DMA_ACCESS) {
1202  dma_release_channel(host->write_dma_chan);
1203  dma_release_channel(host->read_dma_chan);
1204  }
1205  clk_disable_unprepare(host->clk);
1206  clk_put(host->clk);
1207  }
1208 
1209  return 0;
1210 }
1211 
1212 #ifdef CONFIG_PM
1213 static int fsmc_nand_suspend(struct device *dev)
1214 {
1215  struct fsmc_nand_data *host = dev_get_drvdata(dev);
1216  if (host)
1217  clk_disable_unprepare(host->clk);
1218  return 0;
1219 }
1220 
1221 static int fsmc_nand_resume(struct device *dev)
1222 {
1223  struct fsmc_nand_data *host = dev_get_drvdata(dev);
1224  if (host) {
1225  clk_prepare_enable(host->clk);
1226  fsmc_nand_setup(host->regs_va, host->bank,
1227  host->nand.options & NAND_BUSWIDTH_16,
1228  host->dev_timings);
1229  }
1230  return 0;
1231 }
1232 
1233 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1234 #endif
1235 
1236 #ifdef CONFIG_OF
1237 static const struct of_device_id fsmc_nand_id_table[] = {
1238  { .compatible = "st,spear600-fsmc-nand" },
1239  {}
1240 };
1241 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1242 #endif
1243 
1244 static struct platform_driver fsmc_nand_driver = {
1245  .remove = fsmc_nand_remove,
1246  .driver = {
1247  .owner = THIS_MODULE,
1248  .name = "fsmc-nand",
1249  .of_match_table = of_match_ptr(fsmc_nand_id_table),
1250 #ifdef CONFIG_PM
1251  .pm = &fsmc_nand_pm_ops,
1252 #endif
1253  },
1254 };
1255 
1256 static int __init fsmc_nand_init(void)
1257 {
1258  return platform_driver_probe(&fsmc_nand_driver,
1259  fsmc_nand_probe);
1260 }
1261 module_init(fsmc_nand_init);
1262 
1263 static void __exit fsmc_nand_exit(void)
1264 {
1265  platform_driver_unregister(&fsmc_nand_driver);
1266 }
1267 module_exit(fsmc_nand_exit);
1268 
1269 MODULE_LICENSE("GPL");
1270 MODULE_AUTHOR("Vipin Kumar <[email protected]>, Ashish Priyadarshi");
1271 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
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