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| #define | ICH_FLASH_GFPREG 0x0000 |
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| #define | ICH_FLASH_HSFSTS 0x0004 |
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| #define | ICH_FLASH_HSFCTL 0x0006 |
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| #define | ICH_FLASH_FADDR 0x0008 |
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| #define | ICH_FLASH_FDATA0 0x0010 |
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| #define | ICH_FLASH_PR0 0x0074 |
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| #define | ICH_FLASH_READ_COMMAND_TIMEOUT 500 |
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| #define | ICH_FLASH_WRITE_COMMAND_TIMEOUT 500 |
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| #define | ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000 |
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| #define | ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF |
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| #define | ICH_FLASH_CYCLE_REPEAT_COUNT 10 |
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| #define | ICH_CYCLE_READ 0 |
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| #define | ICH_CYCLE_WRITE 2 |
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| #define | ICH_CYCLE_ERASE 3 |
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| #define | FLASH_GFPREG_BASE_MASK 0x1FFF |
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| #define | FLASH_SECTOR_ADDR_SHIFT 12 |
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| #define | ICH_FLASH_SEG_SIZE_256 256 |
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| #define | ICH_FLASH_SEG_SIZE_4K 4096 |
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| #define | ICH_FLASH_SEG_SIZE_8K 8192 |
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| #define | ICH_FLASH_SEG_SIZE_64K 65536 |
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| #define | E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ |
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| #define | E1000_ICH_FWSM_FW_VALID 0x00008000 |
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| #define | E1000_ICH_MNG_IAMT_MODE 0x2 |
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| #define | ID_LED_DEFAULT_ICH8LAN |
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| #define | E1000_ICH_NVM_SIG_WORD 0x13 |
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| #define | E1000_ICH_NVM_SIG_MASK 0xC000 |
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| #define | E1000_ICH_NVM_VALID_SIG_MASK 0xC0 |
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| #define | E1000_ICH_NVM_SIG_VALUE 0x80 |
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| #define | E1000_ICH8_LAN_INIT_TIMEOUT 1500 |
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| #define | E1000_FEXTNVM_SW_CONFIG 1 |
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| #define | E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */ |
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| #define | E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 |
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| #define | E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 |
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| #define | E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 |
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| #define | E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 |
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| #define | E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 |
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| #define | PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL |
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| #define | E1000_ICH_RAR_ENTRIES 7 |
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| #define | E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ |
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| #define | E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ |
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| #define | PHY_PAGE_SHIFT 5 |
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| #define | PHY_REG(page, reg) |
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| #define | IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ |
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| #define | IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ |
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| #define | IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 |
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| #define | IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 |
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| #define | IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 |
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| #define | HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ |
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| #define | SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */ |
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| #define | CV_SMB_CTRL PHY_REG(769, 23) |
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| #define | CV_SMB_CTRL_FORCE_SMBUS 0x0001 |
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| #define | HV_SMB_ADDR PHY_REG(768, 26) |
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| #define | HV_SMB_ADDR_MASK 0x007F |
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| #define | HV_SMB_ADDR_PEC_EN 0x0200 |
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| #define | HV_SMB_ADDR_VALID 0x0080 |
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| #define | HV_SMB_ADDR_FREQ_MASK 0x1100 |
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| #define | HV_SMB_ADDR_FREQ_LOW_SHIFT 8 |
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| #define | HV_SMB_ADDR_FREQ_HIGH_SHIFT 12 |
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| #define | HV_PM_CTRL PHY_REG(770, 17) |
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| #define | HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100 |
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| #define | I82579_LPI_CTRL PHY_REG(772, 20) |
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| #define | I82579_LPI_CTRL_ENABLE_MASK 0x6000 |
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| #define | I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80 |
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| #define | I82579_EMI_ADDR 0x10 |
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| #define | I82579_EMI_DATA 0x11 |
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| #define | I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ |
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| #define | I82579_MSE_THRESHOLD 0x084F /* Mean Square Error Threshold */ |
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| #define | I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ |
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| #define | I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ |
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| #define | I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */ |
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| #define | I217_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE supported */ |
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| #define | I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70) |
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| #define | I217_PROXY_CTRL_AUTO_DISABLE 0x0080 |
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| #define | I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28) |
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| #define | I217_SxCTRL_ENABLE_LPI_RESET 0x1000 |
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| #define | I217_CGFREG PHY_REG(772, 29) |
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| #define | I217_CGFREG_ENABLE_MTA_RESET 0x0002 |
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| #define | I217_MEMPWR PHY_REG(772, 26) |
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| #define | I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010 |
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| #define | E1000_STRAP 0x0000C |
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| #define | E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 |
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| #define | E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 |
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| #define | E1000_STRAP_SMT_FREQ_MASK 0x00003000 |
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| #define | E1000_STRAP_SMT_FREQ_SHIFT 12 |
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| #define | HV_OEM_BITS PHY_REG(768, 25) |
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| #define | HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ |
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| #define | HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ |
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| #define | HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ |
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| #define | E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ |
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| #define | E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ |
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| #define | HV_KMRN_MODE_CTRL PHY_REG(769, 16) |
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| #define | HV_KMRN_MDIO_SLOW 0x0400 |
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| #define | HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16) |
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| #define | HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 |
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| #define | HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 |
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| #define | er16flash(reg) __er16flash(hw, (reg)) |
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| #define | er32flash(reg) __er32flash(hw, (reg)) |
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| #define | ew16flash(reg, val) __ew16flash(hw, (reg), (val)) |
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| #define | ew32flash(reg, val) __ew32flash(hw, (reg), (val)) |
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e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx : pointer to the HW structure
During S0 to Sx transition, it is possible the link remains at gig instead of negotiating to a lower speed. Before going to Sx, set 'Gig Disable' to force link speed negotiation to a lower speed based on the LPLU setting in the NVM or custom setting. For PCH and newer parts, the OEM bits PHY register (LED, GbE disable and LPLU configurations) also needs to be written. Parts that support (and are linked to a partner which support) EEE in 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power than 10Mbps w/o EEE.
Definition at line 4057 of file ich8lan.c.
e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working : pointer to the HW structure
Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), LPLU, Gig disable, MDIC PHY reset): 1) Set Kumeran Near-end loopback 2) Clear Kumeran Near-end loopback Should only be called for ICH8[m] devices with any 1G Phy.
Definition at line 4021 of file ich8lan.c.
1.8.2