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integrator_cp.c
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1 /*
2  * linux/arch/arm/mach-integrator/integrator_cp.c
3  *
4  * Copyright (C) 2003 Deep Blue Solutions Ltd
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License.
9  */
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/string.h>
17 #include <linux/device.h>
18 #include <linux/amba/bus.h>
19 #include <linux/amba/kmi.h>
20 #include <linux/amba/clcd.h>
21 #include <linux/amba/mmci.h>
22 #include <linux/io.h>
23 #include <linux/gfp.h>
24 #include <linux/mtd/physmap.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 
30 #include <mach/hardware.h>
31 #include <mach/platform.h>
32 #include <asm/setup.h>
33 #include <asm/mach-types.h>
34 #include <asm/hardware/arm_timer.h>
35 #include <asm/hardware/icst.h>
36 
37 #include <mach/cm.h>
38 #include <mach/lm.h>
39 #include <mach/irqs.h>
40 
41 #include <asm/mach/arch.h>
42 #include <asm/mach/irq.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/time.h>
45 
46 #include <asm/hardware/timer-sp.h>
47 
48 #include <plat/clcd.h>
49 #include <plat/fpga-irq.h>
50 #include <plat/sched_clock.h>
51 
52 #include "common.h"
53 
54 #define INTCP_PA_FLASH_BASE 0x24000000
55 
56 #define INTCP_PA_CLCD_BASE 0xc0000000
57 
58 #define INTCP_VA_CTRL_BASE __io_address(INTEGRATOR_CP_CTL_BASE)
59 #define INTCP_FLASHPROG 0x04
60 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
61 #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
62 
63 /*
64  * Logical Physical
65  * f1000000 10000000 Core module registers
66  * f1100000 11000000 System controller registers
67  * f1200000 12000000 EBI registers
68  * f1300000 13000000 Counter/Timer
69  * f1400000 14000000 Interrupt controller
70  * f1600000 16000000 UART 0
71  * f1700000 17000000 UART 1
72  * f1a00000 1a000000 Debug LEDs
73  * fc900000 c9000000 GPIO
74  * fca00000 ca000000 SIC
75  * fcb00000 cb000000 CP system control
76  */
77 
78 static struct map_desc intcp_io_desc[] __initdata = {
79  {
80  .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
82  .length = SZ_4K,
83  .type = MT_DEVICE
84  }, {
85  .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
87  .length = SZ_4K,
88  .type = MT_DEVICE
89  }, {
90  .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
92  .length = SZ_4K,
93  .type = MT_DEVICE
94  }, {
95  .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
97  .length = SZ_4K,
98  .type = MT_DEVICE
99  }, {
100  .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
102  .length = SZ_4K,
103  .type = MT_DEVICE
104  }, {
105  .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
107  .length = SZ_4K,
108  .type = MT_DEVICE
109  }, {
110  .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
112  .length = SZ_4K,
113  .type = MT_DEVICE
114  }, {
115  .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
117  .length = SZ_4K,
118  .type = MT_DEVICE
119  }, {
122  .length = SZ_4K,
123  .type = MT_DEVICE
124  }, {
127  .length = SZ_4K,
128  .type = MT_DEVICE
129  }, {
132  .length = SZ_4K,
133  .type = MT_DEVICE
134  }
135 };
136 
137 static void __init intcp_map_io(void)
138 {
139  iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
140 }
141 
142 /*
143  * Flash handling.
144  */
145 static int intcp_flash_init(struct platform_device *dev)
146 {
147  u32 val;
148 
152 
153  return 0;
154 }
155 
156 static void intcp_flash_exit(struct platform_device *dev)
157 {
158  u32 val;
159 
163 }
164 
165 static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
166 {
167  u32 val;
168 
170  if (on)
172  else
175 }
176 
177 static struct physmap_flash_data intcp_flash_data = {
178  .width = 4,
179  .init = intcp_flash_init,
180  .exit = intcp_flash_exit,
181  .set_vpp = intcp_flash_set_vpp,
182 };
183 
184 /*
185  * It seems that the card insertion interrupt remains active after
186  * we've acknowledged it. We therefore ignore the interrupt, and
187  * rely on reading it from the SIC. This also means that we must
188  * clear the latched interrupt.
189  */
190 static unsigned int mmc_status(struct device *dev)
191 {
192  unsigned int status = readl(__io_address(0xca000000 + 4));
194 
195  return status & 8;
196 }
197 
198 static struct mmci_platform_data mmc_data = {
199  .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
200  .status = mmc_status,
201  .gpio_wp = -1,
202  .gpio_cd = -1,
203 };
204 
205 /*
206  * CLCD support
207  */
208 /*
209  * Ensure VGA is selected.
210  */
211 static void cp_clcd_enable(struct clcd_fb *fb)
212 {
213  struct fb_var_screeninfo *var = &fb->fb.var;
215 
216  if (var->bits_per_pixel <= 8 ||
217  (var->bits_per_pixel == 16 && var->green.length == 5))
218  /* Pseudocolor, RGB555, BGR555 */
220  else if (fb->fb.var.bits_per_pixel <= 16)
221  /* truecolor RGB565 */
223  else
224  val = 0; /* no idea for this, don't trust the docs */
225 
232  CM_CTRL_n24BITEN, val);
233 }
234 
235 static int cp_clcd_setup(struct clcd_fb *fb)
236 {
237  fb->panel = versatile_clcd_get_panel("VGA");
238  if (!fb->panel)
239  return -EINVAL;
240 
241  return versatile_clcd_setup_dma(fb, SZ_1M);
242 }
243 
244 static struct clcd_board clcd_data = {
245  .name = "Integrator/CP",
247  .check = clcdfb_check,
248  .decode = clcdfb_decode,
249  .enable = cp_clcd_enable,
250  .setup = cp_clcd_setup,
251  .mmap = versatile_clcd_mmap_dma,
252  .remove = versatile_clcd_remove_dma,
253 };
254 
255 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
256 
257 static void __init intcp_init_early(void)
258 {
259 #ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
261 #endif
262 }
263 
264 #ifdef CONFIG_OF
265 
266 static void __init intcp_timer_init_of(void)
267 {
268  struct device_node *node;
269  const char *path;
270  void __iomem *base;
271  int err;
272  int irq;
273 
275  "arm,timer-primary", &path);
276  if (WARN_ON(err))
277  return;
278  node = of_find_node_by_path(path);
279  base = of_iomap(node, 0);
280  if (WARN_ON(!base))
281  return;
282  writel(0, base + TIMER_CTRL);
283  sp804_clocksource_init(base, node->name);
284 
286  "arm,timer-secondary", &path);
287  if (WARN_ON(err))
288  return;
289  node = of_find_node_by_path(path);
290  base = of_iomap(node, 0);
291  if (WARN_ON(!base))
292  return;
293  irq = irq_of_parse_and_map(node, 0);
294  writel(0, base + TIMER_CTRL);
295  sp804_clockevents_init(base, irq, node->name);
296 }
297 
298 static struct sys_timer cp_of_timer = {
299  .init = intcp_timer_init_of,
300 };
301 
302 static const struct of_device_id fpga_irq_of_match[] __initconst = {
303  { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
304  { /* Sentinel */ }
305 };
306 
307 static void __init intcp_init_irq_of(void)
308 {
309  of_irq_init(fpga_irq_of_match);
310  integrator_clk_init(true);
311 }
312 
313 /*
314  * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
315  * and enforce the bus names since these are used for clock lookups.
316  */
317 static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
318  OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
319  "rtc", NULL),
320  OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
321  "uart0", &integrator_uart_data),
322  OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
323  "uart1", &integrator_uart_data),
324  OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
325  "kmi0", NULL),
326  OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
327  "kmi1", NULL),
328  OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
329  "mmci", &mmc_data),
330  OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
331  "aaci", &mmc_data),
332  OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
333  "clcd", &clcd_data),
334  OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
335  "physmap-flash", &intcp_flash_data),
336  { /* sentinel */ },
337 };
338 
339 static void __init intcp_init_of(void)
340 {
341  of_platform_populate(NULL, of_default_bus_match_table,
342  intcp_auxdata_lookup, NULL);
343 }
344 
345 static const char * intcp_dt_board_compat[] = {
346  "arm,integrator-cp",
347  NULL,
348 };
349 
350 DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
351  .reserve = integrator_reserve,
352  .map_io = intcp_map_io,
353  .nr_irqs = NR_IRQS_INTEGRATOR_CP,
354  .init_early = intcp_init_early,
355  .init_irq = intcp_init_irq_of,
356  .handle_irq = fpga_handle_irq,
357  .timer = &cp_of_timer,
358  .init_machine = intcp_init_of,
359  .restart = integrator_restart,
360  .dt_compat = intcp_dt_board_compat,
362 
363 #endif
364 
365 #ifdef CONFIG_ATAGS
366 
367 /*
368  * This is where non-devicetree initialization code is collected and stashed
369  * for eventual deletion.
370  */
371 
372 #define INTCP_FLASH_SIZE SZ_32M
373 
374 static struct resource intcp_flash_resource = {
376  .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
377  .flags = IORESOURCE_MEM,
378 };
379 
380 static struct platform_device intcp_flash_device = {
381  .name = "physmap-flash",
382  .id = 0,
383  .dev = {
384  .platform_data = &intcp_flash_data,
385  },
386  .num_resources = 1,
387  .resource = &intcp_flash_resource,
388 };
389 
390 #define INTCP_ETH_SIZE 0x10
391 
392 static struct resource smc91x_resources[] = {
393  [0] = {
395  .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
396  .flags = IORESOURCE_MEM,
397  },
398  [1] = {
399  .start = IRQ_CP_ETHINT,
400  .end = IRQ_CP_ETHINT,
401  .flags = IORESOURCE_IRQ,
402  },
403 };
404 
405 static struct platform_device smc91x_device = {
406  .name = "smc91x",
407  .id = 0,
408  .num_resources = ARRAY_SIZE(smc91x_resources),
409  .resource = smc91x_resources,
410 };
411 
412 static struct platform_device *intcp_devs[] __initdata = {
413  &intcp_flash_device,
414  &smc91x_device,
415 };
416 
417 #define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40)
418 #define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE)
419 #define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE)
420 
421 static void __init intcp_init_irq(void)
422 {
423  u32 pic_mask, cic_mask, sic_mask;
424 
425  /* These masks are for the HW IRQ registers */
426  pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
427  pic_mask |= (~((~0u) << (29 - 22))) << 22;
428  cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
429  sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
430 
431  /*
432  * Disable all interrupt sources
433  */
434  writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
435  writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
436  writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
437  writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
438  writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
439  writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
440 
441  fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
442  -1, pic_mask, NULL);
443 
444  fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
445  -1, cic_mask, NULL);
446 
447  fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
448  IRQ_CP_CPPLDINT, sic_mask, NULL);
449 
450  integrator_clk_init(true);
451 }
452 
453 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
454 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
455 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
456 
457 static void __init intcp_timer_init(void)
458 {
462 
463  sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
465 }
466 
467 static struct sys_timer cp_timer = {
468  .init = intcp_timer_init,
469 };
470 
471 #define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
472 #define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
473 
474 static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
475  INTEGRATOR_CP_MMC_IRQS, &mmc_data);
476 
477 static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
478  INTEGRATOR_CP_AACI_IRQS, NULL);
479 
480 static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
481  { IRQ_CP_CLCDCINT }, &clcd_data);
482 
483 static struct amba_device *amba_devs[] __initdata = {
484  &mmc_device,
485  &aaci_device,
486  &clcd_device,
487 };
488 
489 static void __init intcp_init(void)
490 {
491  int i;
492 
493  platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
494 
495  for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
496  struct amba_device *d = amba_devs[i];
498  }
499  integrator_init(true);
500 }
501 
502 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
503  /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
504  .atag_offset = 0x100,
505  .reserve = integrator_reserve,
506  .map_io = intcp_map_io,
507  .nr_irqs = NR_IRQS_INTEGRATOR_CP,
508  .init_early = intcp_init_early,
509  .init_irq = intcp_init_irq,
510  .handle_irq = fpga_handle_irq,
511  .timer = &cp_timer,
512  .init_machine = intcp_init,
513  .restart = integrator_restart,
515 
516 #endif