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38 #include <linux/types.h>
40 #include <linux/kernel.h>
53 #define QIB_MAX_RDMA_ATOMIC 16
54 #define QIB_GUIDS_PER_PORT 5
56 #define QPN_MAX (1 << 24)
57 #define QPNMAP_ENTRIES (QPN_MAX / PAGE_SIZE / BITS_PER_BYTE)
63 #define QIB_UVERBS_ABI_VERSION 2
69 #define IB_CQ_NONE (IB_CQ_NEXT_COMP + 1)
71 #define IB_SEQ_NAK (3 << 29)
74 #define IB_RNR_NAK 0x20
75 #define IB_NAK_PSN_ERROR 0x60
76 #define IB_NAK_INVALID_REQUEST 0x61
77 #define IB_NAK_REMOTE_ACCESS_ERROR 0x62
78 #define IB_NAK_REMOTE_OPERATIONAL_ERROR 0x63
79 #define IB_NAK_INVALID_RD_REQUEST 0x64
82 #define QIB_POST_SEND_OK 0x01
83 #define QIB_POST_RECV_OK 0x02
84 #define QIB_PROCESS_RECV_OK 0x04
85 #define QIB_PROCESS_SEND_OK 0x08
86 #define QIB_PROCESS_NEXT_SEND_OK 0x10
87 #define QIB_FLUSH_SEND 0x20
88 #define QIB_FLUSH_RECV 0x40
89 #define QIB_PROCESS_OR_FLUSH_SEND \
90 (QIB_PROCESS_SEND_OK | QIB_FLUSH_SEND)
93 #define IB_PMA_SAMPLE_STATUS_DONE 0x00
94 #define IB_PMA_SAMPLE_STATUS_STARTED 0x01
95 #define IB_PMA_SAMPLE_STATUS_RUNNING 0x02
98 #define IB_PMA_PORT_XMIT_DATA cpu_to_be16(0x0001)
99 #define IB_PMA_PORT_RCV_DATA cpu_to_be16(0x0002)
100 #define IB_PMA_PORT_XMIT_PKTS cpu_to_be16(0x0003)
101 #define IB_PMA_PORT_RCV_PKTS cpu_to_be16(0x0004)
102 #define IB_PMA_PORT_XMIT_WAIT cpu_to_be16(0x0005)
104 #define QIB_VENDOR_IPG cpu_to_be16(0xFFA0)
106 #define IB_BTH_REQ_ACK (1 << 31)
107 #define IB_BTH_SOLICITED (1 << 23)
108 #define IB_BTH_MIG_REQ (1 << 22)
111 #define IB_PORT_OTHER_LOCAL_CHANGES_SUP (1 << 26)
113 #define IB_GRH_VERSION 6
114 #define IB_GRH_VERSION_MASK 0xF
115 #define IB_GRH_VERSION_SHIFT 28
116 #define IB_GRH_TCLASS_MASK 0xFF
117 #define IB_GRH_TCLASS_SHIFT 20
118 #define IB_GRH_FLOW_MASK 0xFFFFF
119 #define IB_GRH_FLOW_SHIFT 0
120 #define IB_GRH_NEXT_HDR 0x1B
122 #define IB_DEFAULT_GID_PREFIX cpu_to_be64(0xfe80000000000000ULL)
126 #define IB_VL_VL0_1 2
127 #define IB_VL_VL0_3 3
128 #define IB_VL_VL0_7 4
129 #define IB_VL_VL0_14 5
131 static inline int qib_num_vls(
int vls)
289 #define QIB_SEGSZ (PAGE_SIZE / sizeof(struct qib_seg))
532 #define QIB_R_WRID_VALID 0
533 #define QIB_R_REWIND_SGE 1
538 #define QIB_R_REUSE_SGE 0x01
539 #define QIB_R_RDMAR_SEQ 0x02
540 #define QIB_R_RSP_NAK 0x04
541 #define QIB_R_RSP_SEND 0x08
542 #define QIB_R_COMM_EST 0x10
567 #define QIB_S_SIGNAL_REQ_WR 0x0001
568 #define QIB_S_BUSY 0x0002
569 #define QIB_S_TIMER 0x0004
570 #define QIB_S_RESP_PENDING 0x0008
571 #define QIB_S_ACK_PENDING 0x0010
572 #define QIB_S_WAIT_FENCE 0x0020
573 #define QIB_S_WAIT_RDMAR 0x0040
574 #define QIB_S_WAIT_RNR 0x0080
575 #define QIB_S_WAIT_SSN_CREDIT 0x0100
576 #define QIB_S_WAIT_DMA 0x0200
577 #define QIB_S_WAIT_PIO 0x0400
578 #define QIB_S_WAIT_TX 0x0800
579 #define QIB_S_WAIT_DMA_DESC 0x1000
580 #define QIB_S_WAIT_KMEM 0x2000
581 #define QIB_S_WAIT_PSN 0x4000
582 #define QIB_S_WAIT_ACK 0x8000
583 #define QIB_S_SEND_ONE 0x10000
584 #define QIB_S_UNLIMITED_CREDIT 0x20000
589 #define QIB_S_ANY_WAIT_IO (QIB_S_WAIT_PIO | QIB_S_WAIT_TX | \
590 QIB_S_WAIT_DMA_DESC | QIB_S_WAIT_KMEM)
595 #define QIB_S_ANY_WAIT_SEND (QIB_S_WAIT_FENCE | QIB_S_WAIT_RDMAR | \
596 QIB_S_WAIT_RNR | QIB_S_WAIT_SSN_CREDIT | QIB_S_WAIT_DMA | \
597 QIB_S_WAIT_PSN | QIB_S_WAIT_ACK)
599 #define QIB_S_ANY_WAIT (QIB_S_ANY_WAIT_IO | QIB_S_ANY_WAIT_SEND)
601 #define QIB_PSN_CREDIT 16
623 ((
char *) rq->
wq->wq +
828 static inline int qib_send_ok(
struct qib_qp *qp)
842 static inline int qib_pkey_ok(
u16 pkey1,
u16 pkey2)
844 u16 p1 = pkey1 & 0x7FFF;
845 u16 p2 = pkey2 & 0x7FFF;
851 return p1 && p1 == p2 && ((
__s16)pkey1 < 0 || (
__s16)pkey2 < 0);
871 return (((
int) a) - ((
int) b)) << 8;
902 int attr_mask,
struct ib_udata *udata);
993 int num_phys_buf,
int acc,
u64 *iova_start);
996 u64 virt_addr,
int mr_access_flags,
1004 struct ib_device *ibdev,
int page_list_len);
1020 static inline void qib_get_mr(
struct qib_mregion *mr)
1027 static inline void qib_put_mr(
struct qib_mregion *mr)
1036 qib_put_mr(ss->
sge.mr);
1059 int has_grh,
struct qib_qp *qp,
u32 bth0);
1098 #define IB_PHYSPORTSTATE_SLEEP 1
1099 #define IB_PHYSPORTSTATE_POLL 2
1100 #define IB_PHYSPORTSTATE_DISABLED 3
1101 #define IB_PHYSPORTSTATE_CFG_TRAIN 4
1102 #define IB_PHYSPORTSTATE_LINKUP 5
1103 #define IB_PHYSPORTSTATE_LINK_ERR_RECOVER 6
1104 #define IB_PHYSPORTSTATE_CFG_DEBOUNCE 8
1105 #define IB_PHYSPORTSTATE_CFG_IDLE 0xB
1106 #define IB_PHYSPORTSTATE_RECOVERY_RETRAIN 0xC
1107 #define IB_PHYSPORTSTATE_RECOVERY_WAITRMT 0xE
1108 #define IB_PHYSPORTSTATE_RECOVERY_IDLE 0xF
1109 #define IB_PHYSPORTSTATE_CFG_ENH 0x10
1110 #define IB_PHYSPORTSTATE_CFG_WAIT_ENH 0x13