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s5p_mfc_enc.c
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1 /*
2  * linux/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
3  *
4  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5  * http://www.samsung.com/
6  *
7  * Jeongtae Park <[email protected]>
8  * Kamil Debski <[email protected]>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  */
15 
16 #include <linux/clk.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/sched.h>
22 #include <linux/version.h>
23 #include <linux/videodev2.h>
24 #include <media/v4l2-event.h>
25 #include <linux/workqueue.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/videobuf2-core.h>
28 #include "s5p_mfc_common.h"
29 #include "s5p_mfc_debug.h"
30 #include "s5p_mfc_enc.h"
31 #include "s5p_mfc_intr.h"
32 #include "s5p_mfc_opr.h"
33 
34 #define DEF_SRC_FMT_ENC V4L2_PIX_FMT_NV12MT
35 #define DEF_DST_FMT_ENC V4L2_PIX_FMT_H264
36 
37 static struct s5p_mfc_fmt formats[] = {
38  {
39  .name = "4:2:0 2 Planes 16x16 Tiles",
40  .fourcc = V4L2_PIX_FMT_NV12MT_16X16,
41  .codec_mode = S5P_MFC_CODEC_NONE,
42  .type = MFC_FMT_RAW,
43  .num_planes = 2,
44  },
45  {
46  .name = "4:2:0 2 Planes 64x32 Tiles",
47  .fourcc = V4L2_PIX_FMT_NV12MT,
48  .codec_mode = S5P_MFC_CODEC_NONE,
49  .type = MFC_FMT_RAW,
50  .num_planes = 2,
51  },
52  {
53  .name = "4:2:0 2 Planes Y/CbCr",
54  .fourcc = V4L2_PIX_FMT_NV12M,
55  .codec_mode = S5P_MFC_CODEC_NONE,
56  .type = MFC_FMT_RAW,
57  .num_planes = 2,
58  },
59  {
60  .name = "4:2:0 2 Planes Y/CrCb",
61  .fourcc = V4L2_PIX_FMT_NV21M,
62  .codec_mode = S5P_MFC_CODEC_NONE,
63  .type = MFC_FMT_RAW,
64  .num_planes = 2,
65  },
66  {
67  .name = "H264 Encoded Stream",
68  .fourcc = V4L2_PIX_FMT_H264,
69  .codec_mode = S5P_MFC_CODEC_H264_ENC,
70  .type = MFC_FMT_ENC,
71  .num_planes = 1,
72  },
73  {
74  .name = "MPEG4 Encoded Stream",
75  .fourcc = V4L2_PIX_FMT_MPEG4,
76  .codec_mode = S5P_MFC_CODEC_MPEG4_ENC,
77  .type = MFC_FMT_ENC,
78  .num_planes = 1,
79  },
80  {
81  .name = "H263 Encoded Stream",
82  .fourcc = V4L2_PIX_FMT_H263,
83  .codec_mode = S5P_MFC_CODEC_H263_ENC,
84  .type = MFC_FMT_ENC,
85  .num_planes = 1,
86  },
87 };
88 
89 #define NUM_FORMATS ARRAY_SIZE(formats)
90 static struct s5p_mfc_fmt *find_format(struct v4l2_format *f, unsigned int t)
91 {
92  unsigned int i;
93 
94  for (i = 0; i < NUM_FORMATS; i++) {
95  if (formats[i].fourcc == f->fmt.pix_mp.pixelformat &&
96  formats[i].type == t)
97  return &formats[i];
98  }
99  return NULL;
100 }
101 
102 static struct mfc_control controls[] = {
103  {
105  .type = V4L2_CTRL_TYPE_INTEGER,
106  .minimum = 0,
107  .maximum = (1 << 16) - 1,
108  .step = 1,
109  .default_value = 0,
110  },
111  {
113  .type = V4L2_CTRL_TYPE_MENU,
117  .menu_skip_mask = 0,
118  },
119  {
121  .type = V4L2_CTRL_TYPE_INTEGER,
122  .minimum = 1,
123  .maximum = (1 << 16) - 1,
124  .step = 1,
125  .default_value = 1,
126  },
127  {
129  .type = V4L2_CTRL_TYPE_INTEGER,
130  .minimum = 1900,
131  .maximum = (1 << 30) - 1,
132  .step = 1,
133  .default_value = 1900,
134  },
135  {
137  .type = V4L2_CTRL_TYPE_INTEGER,
138  .minimum = 0,
139  .maximum = (1 << 16) - 1,
140  .step = 1,
141  .default_value = 0,
142  },
143  {
145  .type = V4L2_CTRL_TYPE_BOOLEAN,
146  .name = "Padding Control Enable",
147  .minimum = 0,
148  .maximum = 1,
149  .step = 1,
150  .default_value = 0,
151  },
152  {
154  .type = V4L2_CTRL_TYPE_INTEGER,
155  .name = "Padding Color YUV Value",
156  .minimum = 0,
157  .maximum = (1 << 25) - 1,
158  .step = 1,
159  .default_value = 0,
160  },
161  {
163  .type = V4L2_CTRL_TYPE_BOOLEAN,
164  .minimum = 0,
165  .maximum = 1,
166  .step = 1,
167  .default_value = 0,
168  },
169  {
171  .type = V4L2_CTRL_TYPE_INTEGER,
172  .minimum = 1,
173  .maximum = (1 << 30) - 1,
174  .step = 1,
175  .default_value = 1,
176  },
177  {
179  .type = V4L2_CTRL_TYPE_INTEGER,
180  .name = "Rate Control Reaction Coeff.",
181  .minimum = 1,
182  .maximum = (1 << 16) - 1,
183  .step = 1,
184  .default_value = 1,
185  },
186  {
188  .type = V4L2_CTRL_TYPE_MENU,
189  .name = "Force frame type",
193  .menu_skip_mask = 0,
194  },
195  {
197  .type = V4L2_CTRL_TYPE_INTEGER,
198  .minimum = 0,
199  .maximum = (1 << 16) - 1,
200  .step = 1,
201  .default_value = 0,
202  },
203  {
205  .type = V4L2_CTRL_TYPE_INTEGER,
206  .minimum = 0,
207  .maximum = (1 << 16) - 1,
208  .step = 1,
209  .default_value = 0,
210  },
211  {
213  .type = V4L2_CTRL_TYPE_MENU,
216  .default_value = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
217  .menu_skip_mask = 0,
218  },
219  {
221  .type = V4L2_CTRL_TYPE_MENU,
222  .name = "Frame Skip Enable",
225  .menu_skip_mask = 0,
227  },
228  {
230  .type = V4L2_CTRL_TYPE_BOOLEAN,
231  .name = "Fixed Target Bit Enable",
232  .minimum = 0,
233  .maximum = 1,
234  .default_value = 0,
235  .menu_skip_mask = 0,
236  },
237  {
239  .type = V4L2_CTRL_TYPE_INTEGER,
240  .minimum = 0,
241  .maximum = 2,
242  .step = 1,
243  .default_value = 0,
244  },
245  {
247  .type = V4L2_CTRL_TYPE_MENU,
250  .default_value = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
251  .menu_skip_mask = ~(
255  ),
256  },
257  {
259  .type = V4L2_CTRL_TYPE_MENU,
262  .default_value = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
263  },
264  {
266  .type = V4L2_CTRL_TYPE_MENU,
269  .default_value = V4L2_MPEG_VIDEO_MPEG4_LEVEL_0,
270  .menu_skip_mask = 0,
271  },
272  {
274  .type = V4L2_CTRL_TYPE_MENU,
278  .menu_skip_mask = 0,
279  },
280  {
282  .type = V4L2_CTRL_TYPE_INTEGER,
283  .minimum = -6,
284  .maximum = 6,
285  .step = 1,
286  .default_value = 0,
287  },
288  {
290  .type = V4L2_CTRL_TYPE_INTEGER,
291  .minimum = -6,
292  .maximum = 6,
293  .step = 1,
294  .default_value = 0,
295  },
296  {
298  .type = V4L2_CTRL_TYPE_MENU,
302  .menu_skip_mask = 0,
303  },
304  {
306  .type = V4L2_CTRL_TYPE_INTEGER,
307  .name = "The Number of Ref. Pic for P",
308  .minimum = 1,
309  .maximum = 2,
310  .step = 1,
311  .default_value = 1,
312  },
313  {
315  .type = V4L2_CTRL_TYPE_BOOLEAN,
316  .minimum = 0,
317  .maximum = 1,
318  .step = 1,
319  .default_value = 0,
320  },
321  {
323  .type = V4L2_CTRL_TYPE_BOOLEAN,
324  .minimum = 0,
325  .maximum = 1,
326  .step = 1,
327  .default_value = 0,
328  },
329  {
331  .type = V4L2_CTRL_TYPE_INTEGER,
332  .minimum = 0,
333  .maximum = 51,
334  .step = 1,
335  .default_value = 1,
336  },
337  {
339  .type = V4L2_CTRL_TYPE_INTEGER,
340  .minimum = 0,
341  .maximum = 51,
342  .step = 1,
343  .default_value = 1,
344  },
345  {
347  .type = V4L2_CTRL_TYPE_INTEGER,
348  .minimum = 0,
349  .maximum = 51,
350  .step = 1,
351  .default_value = 1,
352  },
353  {
355  .type = V4L2_CTRL_TYPE_INTEGER,
356  .minimum = 0,
357  .maximum = 51,
358  .step = 1,
359  .default_value = 1,
360  },
361  {
363  .type = V4L2_CTRL_TYPE_INTEGER,
364  .minimum = 0,
365  .maximum = 51,
366  .step = 1,
367  .default_value = 1,
368  },
369  {
371  .type = V4L2_CTRL_TYPE_INTEGER,
372  .name = "H263 I-Frame QP value",
373  .minimum = 1,
374  .maximum = 31,
375  .step = 1,
376  .default_value = 1,
377  },
378  {
380  .type = V4L2_CTRL_TYPE_INTEGER,
381  .name = "H263 Minimum QP value",
382  .minimum = 1,
383  .maximum = 31,
384  .step = 1,
385  .default_value = 1,
386  },
387  {
389  .type = V4L2_CTRL_TYPE_INTEGER,
390  .name = "H263 Maximum QP value",
391  .minimum = 1,
392  .maximum = 31,
393  .step = 1,
394  .default_value = 1,
395  },
396  {
398  .type = V4L2_CTRL_TYPE_INTEGER,
399  .name = "H263 P frame QP value",
400  .minimum = 1,
401  .maximum = 31,
402  .step = 1,
403  .default_value = 1,
404  },
405  {
407  .type = V4L2_CTRL_TYPE_INTEGER,
408  .name = "H263 B frame QP value",
409  .minimum = 1,
410  .maximum = 31,
411  .step = 1,
412  .default_value = 1,
413  },
414  {
416  .type = V4L2_CTRL_TYPE_INTEGER,
417  .name = "MPEG4 I-Frame QP value",
418  .minimum = 1,
419  .maximum = 31,
420  .step = 1,
421  .default_value = 1,
422  },
423  {
425  .type = V4L2_CTRL_TYPE_INTEGER,
426  .name = "MPEG4 Minimum QP value",
427  .minimum = 1,
428  .maximum = 31,
429  .step = 1,
430  .default_value = 1,
431  },
432  {
434  .type = V4L2_CTRL_TYPE_INTEGER,
435  .name = "MPEG4 Maximum QP value",
436  .minimum = 0,
437  .maximum = 51,
438  .step = 1,
439  .default_value = 1,
440  },
441  {
443  .type = V4L2_CTRL_TYPE_INTEGER,
444  .name = "MPEG4 P frame QP value",
445  .minimum = 1,
446  .maximum = 31,
447  .step = 1,
448  .default_value = 1,
449  },
450  {
452  .type = V4L2_CTRL_TYPE_INTEGER,
453  .name = "MPEG4 B frame QP value",
454  .minimum = 1,
455  .maximum = 31,
456  .step = 1,
457  .default_value = 1,
458  },
459  {
461  .type = V4L2_CTRL_TYPE_BOOLEAN,
462  .name = "H264 Dark Reg Adaptive RC",
463  .minimum = 0,
464  .maximum = 1,
465  .step = 1,
466  .default_value = 0,
467  },
468  {
470  .type = V4L2_CTRL_TYPE_BOOLEAN,
471  .name = "H264 Smooth Reg Adaptive RC",
472  .minimum = 0,
473  .maximum = 1,
474  .step = 1,
475  .default_value = 0,
476  },
477  {
479  .type = V4L2_CTRL_TYPE_BOOLEAN,
480  .name = "H264 Static Reg Adaptive RC",
481  .minimum = 0,
482  .maximum = 1,
483  .step = 1,
484  .default_value = 0,
485  },
486  {
488  .type = V4L2_CTRL_TYPE_BOOLEAN,
489  .name = "H264 Activity Reg Adaptive RC",
490  .minimum = 0,
491  .maximum = 1,
492  .step = 1,
493  .default_value = 0,
494  },
495  {
497  .type = V4L2_CTRL_TYPE_BOOLEAN,
498  .minimum = 0,
499  .maximum = 1,
500  .step = 1,
501  .default_value = 0,
502  },
503  {
505  .type = V4L2_CTRL_TYPE_MENU,
509  .menu_skip_mask = 0,
510  },
511  {
513  .type = V4L2_CTRL_TYPE_INTEGER,
514  .minimum = 0,
515  .maximum = (1 << 16) - 1,
516  .step = 1,
517  .default_value = 0,
518  },
519  {
521  .type = V4L2_CTRL_TYPE_INTEGER,
522  .minimum = 0,
523  .maximum = (1 << 16) - 1,
524  .step = 1,
525  .default_value = 0,
526  },
527  {
529  .type = V4L2_CTRL_TYPE_BOOLEAN,
530  .minimum = 0,
531  .maximum = 1,
532  .step = 1,
533  .default_value = 1,
534  },
535  {
537  .type = V4L2_CTRL_TYPE_INTEGER,
538  .minimum = 0,
539  .maximum = (1 << 16) - 1,
540  .step = 1,
541  .default_value = 0,
542  },
543  {
545  .type = V4L2_CTRL_TYPE_MENU,
548  .default_value = V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE,
549  .menu_skip_mask = 0,
550  },
551  {
553  .type = V4L2_CTRL_TYPE_BOOLEAN,
554  .minimum = 0,
555  .maximum = 1,
556  .step = 1,
557  .default_value = 0,
558  },
559 };
560 
561 #define NUM_CTRLS ARRAY_SIZE(controls)
562 static const char * const *mfc51_get_menu(u32 id)
563 {
564  static const char * const mfc51_video_frame_skip[] = {
565  "Disabled",
566  "Level Limit",
567  "VBV/CPB Limit",
568  NULL,
569  };
570  static const char * const mfc51_video_force_frame[] = {
571  "Disabled",
572  "I Frame",
573  "Not Coded",
574  NULL,
575  };
576  switch (id) {
578  return mfc51_video_frame_skip;
580  return mfc51_video_force_frame;
581  }
582  return NULL;
583 }
584 
585 static int s5p_mfc_ctx_ready(struct s5p_mfc_ctx *ctx)
586 {
587  mfc_debug(2, "src=%d, dst=%d, state=%d\n",
588  ctx->src_queue_cnt, ctx->dst_queue_cnt, ctx->state);
589  /* context is ready to make header */
590  if (ctx->state == MFCINST_GOT_INST && ctx->dst_queue_cnt >= 1)
591  return 1;
592  /* context is ready to encode a frame */
593  if ((ctx->state == MFCINST_RUNNING ||
594  ctx->state == MFCINST_HEAD_PARSED) &&
595  ctx->src_queue_cnt >= 1 && ctx->dst_queue_cnt >= 1)
596  return 1;
597  /* context is ready to encode remaining frames */
598  if (ctx->state == MFCINST_FINISHING &&
599  ctx->dst_queue_cnt >= 1)
600  return 1;
601  mfc_debug(2, "ctx is not ready\n");
602  return 0;
603 }
604 
605 static void cleanup_ref_queue(struct s5p_mfc_ctx *ctx)
606 {
607  struct s5p_mfc_buf *mb_entry;
608  unsigned long mb_y_addr, mb_c_addr;
609 
610  /* move buffers in ref queue to src queue */
611  while (!list_empty(&ctx->ref_queue)) {
612  mb_entry = list_entry((&ctx->ref_queue)->next,
613  struct s5p_mfc_buf, list);
614  mb_y_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 0);
615  mb_c_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 1);
616  list_del(&mb_entry->list);
617  ctx->ref_queue_cnt--;
618  list_add_tail(&mb_entry->list, &ctx->src_queue);
619  ctx->src_queue_cnt++;
620  }
621  mfc_debug(2, "enc src count: %d, enc ref count: %d\n",
622  ctx->src_queue_cnt, ctx->ref_queue_cnt);
623  INIT_LIST_HEAD(&ctx->ref_queue);
624  ctx->ref_queue_cnt = 0;
625 }
626 
627 static int enc_pre_seq_start(struct s5p_mfc_ctx *ctx)
628 {
629  struct s5p_mfc_dev *dev = ctx->dev;
630  struct s5p_mfc_buf *dst_mb;
631  unsigned long dst_addr;
632  unsigned int dst_size;
633  unsigned long flags;
634 
635  spin_lock_irqsave(&dev->irqlock, flags);
636  dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
637  dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
638  dst_size = vb2_plane_size(dst_mb->b, 0);
639  s5p_mfc_hw_call(dev->mfc_ops, set_enc_stream_buffer, ctx, dst_addr,
640  dst_size);
641  spin_unlock_irqrestore(&dev->irqlock, flags);
642  return 0;
643 }
644 
645 static int enc_post_seq_start(struct s5p_mfc_ctx *ctx)
646 {
647  struct s5p_mfc_dev *dev = ctx->dev;
648  struct s5p_mfc_enc_params *p = &ctx->enc_params;
649  struct s5p_mfc_buf *dst_mb;
650  unsigned long flags;
651 
653  spin_lock_irqsave(&dev->irqlock, flags);
654  dst_mb = list_entry(ctx->dst_queue.next,
655  struct s5p_mfc_buf, list);
656  list_del(&dst_mb->list);
657  ctx->dst_queue_cnt--;
658  vb2_set_plane_payload(dst_mb->b, 0,
659  s5p_mfc_hw_call(dev->mfc_ops, get_enc_strm_size, dev));
661  spin_unlock_irqrestore(&dev->irqlock, flags);
662  }
663  if (IS_MFCV6(dev)) {
664  ctx->state = MFCINST_HEAD_PARSED; /* for INIT_BUFFER cmd */
665  } else {
666  ctx->state = MFCINST_RUNNING;
667  if (s5p_mfc_ctx_ready(ctx))
669  s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
670  }
671 
672  if (IS_MFCV6(dev))
673  ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops,
674  get_enc_dpb_count, dev);
675 
676  return 0;
677 }
678 
679 static int enc_pre_frame_start(struct s5p_mfc_ctx *ctx)
680 {
681  struct s5p_mfc_dev *dev = ctx->dev;
682  struct s5p_mfc_buf *dst_mb;
683  struct s5p_mfc_buf *src_mb;
684  unsigned long flags;
685  unsigned long src_y_addr, src_c_addr, dst_addr;
686  unsigned int dst_size;
687 
688  spin_lock_irqsave(&dev->irqlock, flags);
689  src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
690  src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0);
691  src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1);
692  s5p_mfc_hw_call(dev->mfc_ops, set_enc_frame_buffer, ctx, src_y_addr,
693  src_c_addr);
694  spin_unlock_irqrestore(&dev->irqlock, flags);
695 
696  spin_lock_irqsave(&dev->irqlock, flags);
697  dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
698  dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
699  dst_size = vb2_plane_size(dst_mb->b, 0);
700  s5p_mfc_hw_call(dev->mfc_ops, set_enc_stream_buffer, ctx, dst_addr,
701  dst_size);
702  spin_unlock_irqrestore(&dev->irqlock, flags);
703 
704  return 0;
705 }
706 
707 static int enc_post_frame_start(struct s5p_mfc_ctx *ctx)
708 {
709  struct s5p_mfc_dev *dev = ctx->dev;
710  struct s5p_mfc_buf *mb_entry;
711  unsigned long enc_y_addr, enc_c_addr;
712  unsigned long mb_y_addr, mb_c_addr;
713  int slice_type;
714  unsigned int strm_size;
715  unsigned long flags;
716 
717  slice_type = s5p_mfc_hw_call(dev->mfc_ops, get_enc_slice_type, dev);
718  strm_size = s5p_mfc_hw_call(dev->mfc_ops, get_enc_strm_size, dev);
719  mfc_debug(2, "Encoded slice type: %d", slice_type);
720  mfc_debug(2, "Encoded stream size: %d", strm_size);
721  mfc_debug(2, "Display order: %d",
723  spin_lock_irqsave(&dev->irqlock, flags);
724  if (slice_type >= 0) {
725  s5p_mfc_hw_call(dev->mfc_ops, get_enc_frame_buffer, ctx,
726  &enc_y_addr, &enc_c_addr);
727  list_for_each_entry(mb_entry, &ctx->src_queue, list) {
728  mb_y_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 0);
729  mb_c_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 1);
730  if ((enc_y_addr == mb_y_addr) &&
731  (enc_c_addr == mb_c_addr)) {
732  list_del(&mb_entry->list);
733  ctx->src_queue_cnt--;
734  vb2_buffer_done(mb_entry->b,
736  break;
737  }
738  }
739  list_for_each_entry(mb_entry, &ctx->ref_queue, list) {
740  mb_y_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 0);
741  mb_c_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 1);
742  if ((enc_y_addr == mb_y_addr) &&
743  (enc_c_addr == mb_c_addr)) {
744  list_del(&mb_entry->list);
745  ctx->ref_queue_cnt--;
746  vb2_buffer_done(mb_entry->b,
748  break;
749  }
750  }
751  }
752  if ((ctx->src_queue_cnt > 0) && (ctx->state == MFCINST_RUNNING)) {
753  mb_entry = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
754  list);
755  if (mb_entry->flags & MFC_BUF_FLAG_USED) {
756  list_del(&mb_entry->list);
757  ctx->src_queue_cnt--;
758  list_add_tail(&mb_entry->list, &ctx->ref_queue);
759  ctx->ref_queue_cnt++;
760  }
761  mfc_debug(2, "enc src count: %d, enc ref count: %d\n",
762  ctx->src_queue_cnt, ctx->ref_queue_cnt);
763  }
764  if (strm_size > 0) {
765  /* at least one more dest. buffers exist always */
766  mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
767  list);
768  list_del(&mb_entry->list);
769  ctx->dst_queue_cnt--;
770  switch (slice_type) {
772  mb_entry->b->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
773  break;
775  mb_entry->b->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
776  break;
778  mb_entry->b->v4l2_buf.flags |= V4L2_BUF_FLAG_BFRAME;
779  break;
780  }
781  vb2_set_plane_payload(mb_entry->b, 0, strm_size);
783  }
784  spin_unlock_irqrestore(&dev->irqlock, flags);
785  if ((ctx->src_queue_cnt == 0) || (ctx->dst_queue_cnt == 0))
786  clear_work_bit(ctx);
787  return 0;
788 }
789 
790 static struct s5p_mfc_codec_ops encoder_codec_ops = {
791  .pre_seq_start = enc_pre_seq_start,
792  .post_seq_start = enc_post_seq_start,
793  .pre_frame_start = enc_pre_frame_start,
794  .post_frame_start = enc_post_frame_start,
795 };
796 
797 /* Query capabilities of the device */
798 static int vidioc_querycap(struct file *file, void *priv,
799  struct v4l2_capability *cap)
800 {
801  struct s5p_mfc_dev *dev = video_drvdata(file);
802 
803  strncpy(cap->driver, dev->plat_dev->name, sizeof(cap->driver) - 1);
804  strncpy(cap->card, dev->plat_dev->name, sizeof(cap->card) - 1);
805  cap->bus_info[0] = 0;
806  cap->version = KERNEL_VERSION(1, 0, 0);
807  /*
808  * This is only a mem-to-mem video device. The capture and output
809  * device capability flags are left only for backward compatibility
810  * and are scheduled for removal.
811  */
815  return 0;
816 }
817 
818 static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, bool mplane, bool out)
819 {
820  struct s5p_mfc_fmt *fmt;
821  int i, j = 0;
822 
823  for (i = 0; i < ARRAY_SIZE(formats); ++i) {
824  if (mplane && formats[i].num_planes == 1)
825  continue;
826  else if (!mplane && formats[i].num_planes > 1)
827  continue;
828  if (out && formats[i].type != MFC_FMT_RAW)
829  continue;
830  else if (!out && formats[i].type != MFC_FMT_ENC)
831  continue;
832  if (j == f->index) {
833  fmt = &formats[i];
834  strlcpy(f->description, fmt->name,
835  sizeof(f->description));
836  f->pixelformat = fmt->fourcc;
837  return 0;
838  }
839  ++j;
840  }
841  return -EINVAL;
842 }
843 
844 static int vidioc_enum_fmt_vid_cap(struct file *file, void *pirv,
845  struct v4l2_fmtdesc *f)
846 {
847  return vidioc_enum_fmt(f, false, false);
848 }
849 
850 static int vidioc_enum_fmt_vid_cap_mplane(struct file *file, void *pirv,
851  struct v4l2_fmtdesc *f)
852 {
853  return vidioc_enum_fmt(f, true, false);
854 }
855 
856 static int vidioc_enum_fmt_vid_out(struct file *file, void *prov,
857  struct v4l2_fmtdesc *f)
858 {
859  return vidioc_enum_fmt(f, false, true);
860 }
861 
862 static int vidioc_enum_fmt_vid_out_mplane(struct file *file, void *prov,
863  struct v4l2_fmtdesc *f)
864 {
865  return vidioc_enum_fmt(f, true, true);
866 }
867 
868 static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
869 {
870  struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
871  struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
872 
873  mfc_debug(2, "f->type = %d ctx->state = %d\n", f->type, ctx->state);
875  /* This is run on output (encoder dest) */
876  pix_fmt_mp->width = 0;
877  pix_fmt_mp->height = 0;
878  pix_fmt_mp->field = V4L2_FIELD_NONE;
879  pix_fmt_mp->pixelformat = ctx->dst_fmt->fourcc;
880  pix_fmt_mp->num_planes = ctx->dst_fmt->num_planes;
881 
882  pix_fmt_mp->plane_fmt[0].bytesperline = ctx->enc_dst_buf_size;
883  pix_fmt_mp->plane_fmt[0].sizeimage = ctx->enc_dst_buf_size;
884  } else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
885  /* This is run on capture (encoder src) */
886  pix_fmt_mp->width = ctx->img_width;
887  pix_fmt_mp->height = ctx->img_height;
888 
889  pix_fmt_mp->field = V4L2_FIELD_NONE;
890  pix_fmt_mp->pixelformat = ctx->src_fmt->fourcc;
891  pix_fmt_mp->num_planes = ctx->src_fmt->num_planes;
892 
893  pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width;
894  pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size;
895  pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width;
896  pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
897  } else {
898  mfc_err("invalid buf type\n");
899  return -EINVAL;
900  }
901  return 0;
902 }
903 
904 static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
905 {
906  struct s5p_mfc_fmt *fmt;
907  struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
908 
910  fmt = find_format(f, MFC_FMT_ENC);
911  if (!fmt) {
912  mfc_err("failed to try output format\n");
913  return -EINVAL;
914  }
915 
916  if (pix_fmt_mp->plane_fmt[0].sizeimage == 0) {
917  mfc_err("must be set encoding output size\n");
918  return -EINVAL;
919  }
920 
921  pix_fmt_mp->plane_fmt[0].bytesperline =
922  pix_fmt_mp->plane_fmt[0].sizeimage;
923  } else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
924  fmt = find_format(f, MFC_FMT_RAW);
925  if (!fmt) {
926  mfc_err("failed to try output format\n");
927  return -EINVAL;
928  }
929 
930  if (fmt->num_planes != pix_fmt_mp->num_planes) {
931  mfc_err("failed to try output format\n");
932  return -EINVAL;
933  }
934  v4l_bound_align_image(&pix_fmt_mp->width, 8, 1920, 1,
935  &pix_fmt_mp->height, 4, 1080, 1, 0);
936  } else {
937  mfc_err("invalid buf type\n");
938  return -EINVAL;
939  }
940  return 0;
941 }
942 
943 static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
944 {
945  struct s5p_mfc_dev *dev = video_drvdata(file);
946  struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
947  struct s5p_mfc_fmt *fmt;
948  struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
949  int ret = 0;
950 
951  ret = vidioc_try_fmt(file, priv, f);
952  if (ret)
953  return ret;
954  if (ctx->vq_src.streaming || ctx->vq_dst.streaming) {
955  v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
956  ret = -EBUSY;
957  goto out;
958  }
960  fmt = find_format(f, MFC_FMT_ENC);
961  if (!fmt) {
962  mfc_err("failed to set capture format\n");
963  return -EINVAL;
964  }
965  ctx->state = MFCINST_INIT;
966  ctx->dst_fmt = fmt;
967  ctx->codec_mode = ctx->dst_fmt->codec_mode;
968  ctx->enc_dst_buf_size = pix_fmt_mp->plane_fmt[0].sizeimage;
969  pix_fmt_mp->plane_fmt[0].bytesperline = 0;
970  ctx->dst_bufs_cnt = 0;
971  ctx->capture_state = QUEUE_FREE;
972  s5p_mfc_hw_call(dev->mfc_ops, alloc_instance_buffer, ctx);
975  s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
976  if (s5p_mfc_wait_for_done_ctx(ctx, \
978  /* Error or timeout */
979  mfc_err("Error getting instance from hardware\n");
980  s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer,
981  ctx);
982  ret = -EIO;
983  goto out;
984  }
985  mfc_debug(2, "Got instance number: %d\n", ctx->inst_no);
986  } else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
987  fmt = find_format(f, MFC_FMT_RAW);
988  if (!fmt) {
989  mfc_err("failed to set output format\n");
990  return -EINVAL;
991  }
992 
993  if (!IS_MFCV6(dev) &&
994  (fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)) {
995  mfc_err("Not supported format.\n");
996  return -EINVAL;
997  } else if (IS_MFCV6(dev) &&
998  (fmt->fourcc == V4L2_PIX_FMT_NV12MT)) {
999  mfc_err("Not supported format.\n");
1000  return -EINVAL;
1001  }
1002 
1003  if (fmt->num_planes != pix_fmt_mp->num_planes) {
1004  mfc_err("failed to set output format\n");
1005  ret = -EINVAL;
1006  goto out;
1007  }
1008  ctx->src_fmt = fmt;
1009  ctx->img_width = pix_fmt_mp->width;
1010  ctx->img_height = pix_fmt_mp->height;
1011  mfc_debug(2, "codec number: %d\n", ctx->src_fmt->codec_mode);
1012  mfc_debug(2, "fmt - w: %d, h: %d, ctx - w: %d, h: %d\n",
1013  pix_fmt_mp->width, pix_fmt_mp->height,
1014  ctx->img_width, ctx->img_height);
1015 
1016  s5p_mfc_hw_call(dev->mfc_ops, enc_calc_src_size, ctx);
1017  pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size;
1018  pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width;
1019  pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
1020  pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width;
1021 
1022  ctx->src_bufs_cnt = 0;
1023  ctx->output_state = QUEUE_FREE;
1024  } else {
1025  mfc_err("invalid buf type\n");
1026  return -EINVAL;
1027  }
1028 out:
1029  mfc_debug_leave();
1030  return ret;
1031 }
1032 
1033 static int vidioc_reqbufs(struct file *file, void *priv,
1034  struct v4l2_requestbuffers *reqbufs)
1035 {
1036  struct s5p_mfc_dev *dev = video_drvdata(file);
1037  struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1038  int ret = 0;
1039 
1040  /* if memory is not mmp or userptr return error */
1041  if ((reqbufs->memory != V4L2_MEMORY_MMAP) &&
1042  (reqbufs->memory != V4L2_MEMORY_USERPTR))
1043  return -EINVAL;
1044  if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1045  if (ctx->capture_state != QUEUE_FREE) {
1046  mfc_err("invalid capture state: %d\n",
1047  ctx->capture_state);
1048  return -EINVAL;
1049  }
1050  ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
1051  if (ret != 0) {
1052  mfc_err("error in vb2_reqbufs() for E(D)\n");
1053  return ret;
1054  }
1056 
1057  if (!IS_MFCV6(dev)) {
1058  ret = s5p_mfc_hw_call(ctx->dev->mfc_ops,
1059  alloc_codec_buffers, ctx);
1060  if (ret) {
1061  mfc_err("Failed to allocate encoding buffers\n");
1062  reqbufs->count = 0;
1063  ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
1064  return -ENOMEM;
1065  }
1066  }
1067  } else if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1068  if (ctx->output_state != QUEUE_FREE) {
1069  mfc_err("invalid output state: %d\n",
1070  ctx->output_state);
1071  return -EINVAL;
1072  }
1073  ret = vb2_reqbufs(&ctx->vq_src, reqbufs);
1074  if (ret != 0) {
1075  mfc_err("error in vb2_reqbufs() for E(S)\n");
1076  return ret;
1077  }
1079  } else {
1080  mfc_err("invalid buf type\n");
1081  return -EINVAL;
1082  }
1083  return ret;
1084 }
1085 
1086 static int vidioc_querybuf(struct file *file, void *priv,
1087  struct v4l2_buffer *buf)
1088 {
1089  struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1090  int ret = 0;
1091 
1092  /* if memory is not mmp or userptr return error */
1093  if ((buf->memory != V4L2_MEMORY_MMAP) &&
1094  (buf->memory != V4L2_MEMORY_USERPTR))
1095  return -EINVAL;
1097  if (ctx->state != MFCINST_GOT_INST) {
1098  mfc_err("invalid context state: %d\n", ctx->state);
1099  return -EINVAL;
1100  }
1101  ret = vb2_querybuf(&ctx->vq_dst, buf);
1102  if (ret != 0) {
1103  mfc_err("error in vb2_querybuf() for E(D)\n");
1104  return ret;
1105  }
1106  buf->m.planes[0].m.mem_offset += DST_QUEUE_OFF_BASE;
1107  } else if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1108  ret = vb2_querybuf(&ctx->vq_src, buf);
1109  if (ret != 0) {
1110  mfc_err("error in vb2_querybuf() for E(S)\n");
1111  return ret;
1112  }
1113  } else {
1114  mfc_err("invalid buf type\n");
1115  return -EINVAL;
1116  }
1117  return ret;
1118 }
1119 
1120 /* Queue a buffer */
1121 static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1122 {
1123  struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1124 
1125  if (ctx->state == MFCINST_ERROR) {
1126  mfc_err("Call on QBUF after unrecoverable error\n");
1127  return -EIO;
1128  }
1130  if (ctx->state == MFCINST_FINISHING) {
1131  mfc_err("Call on QBUF after EOS command\n");
1132  return -EIO;
1133  }
1134  return vb2_qbuf(&ctx->vq_src, buf);
1135  } else if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1136  return vb2_qbuf(&ctx->vq_dst, buf);
1137  }
1138  return -EINVAL;
1139 }
1140 
1141 /* Dequeue a buffer */
1142 static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1143 {
1144  const struct v4l2_event ev = {
1145  .type = V4L2_EVENT_EOS
1146  };
1147  struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1148  int ret;
1149 
1150  if (ctx->state == MFCINST_ERROR) {
1151  mfc_err("Call on DQBUF after unrecoverable error\n");
1152  return -EIO;
1153  }
1155  ret = vb2_dqbuf(&ctx->vq_src, buf, file->f_flags & O_NONBLOCK);
1156  } else if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1157  ret = vb2_dqbuf(&ctx->vq_dst, buf, file->f_flags & O_NONBLOCK);
1158  if (ret == 0 && ctx->state == MFCINST_FINISHED
1159  && list_empty(&ctx->vq_dst.done_list))
1160  v4l2_event_queue_fh(&ctx->fh, &ev);
1161  } else {
1162  ret = -EINVAL;
1163  }
1164 
1165  return ret;
1166 }
1167 
1168 /* Stream on */
1169 static int vidioc_streamon(struct file *file, void *priv,
1170  enum v4l2_buf_type type)
1171 {
1172  struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1173 
1175  return vb2_streamon(&ctx->vq_src, type);
1176  else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1177  return vb2_streamon(&ctx->vq_dst, type);
1178  return -EINVAL;
1179 }
1180 
1181 /* Stream off, which equals to a pause */
1182 static int vidioc_streamoff(struct file *file, void *priv,
1183  enum v4l2_buf_type type)
1184 {
1185  struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1186 
1188  return vb2_streamoff(&ctx->vq_src, type);
1189  else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1190  return vb2_streamoff(&ctx->vq_dst, type);
1191  return -EINVAL;
1192 }
1193 
1194 static inline int h264_level(enum v4l2_mpeg_video_h264_level lvl)
1195 {
1196  static unsigned int t[V4L2_MPEG_VIDEO_H264_LEVEL_4_0 + 1] = {
1197  /* V4L2_MPEG_VIDEO_H264_LEVEL_1_0 */ 10,
1198  /* V4L2_MPEG_VIDEO_H264_LEVEL_1B */ 9,
1199  /* V4L2_MPEG_VIDEO_H264_LEVEL_1_1 */ 11,
1200  /* V4L2_MPEG_VIDEO_H264_LEVEL_1_2 */ 12,
1201  /* V4L2_MPEG_VIDEO_H264_LEVEL_1_3 */ 13,
1202  /* V4L2_MPEG_VIDEO_H264_LEVEL_2_0 */ 20,
1203  /* V4L2_MPEG_VIDEO_H264_LEVEL_2_1 */ 21,
1204  /* V4L2_MPEG_VIDEO_H264_LEVEL_2_2 */ 22,
1205  /* V4L2_MPEG_VIDEO_H264_LEVEL_3_0 */ 30,
1206  /* V4L2_MPEG_VIDEO_H264_LEVEL_3_1 */ 31,
1207  /* V4L2_MPEG_VIDEO_H264_LEVEL_3_2 */ 32,
1208  /* V4L2_MPEG_VIDEO_H264_LEVEL_4_0 */ 40,
1209  };
1210  return t[lvl];
1211 }
1212 
1213 static inline int mpeg4_level(enum v4l2_mpeg_video_mpeg4_level lvl)
1214 {
1215  static unsigned int t[V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 + 1] = {
1216  /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 */ 0,
1217  /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B */ 9,
1218  /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 */ 1,
1219  /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 */ 2,
1220  /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 */ 3,
1221  /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B */ 7,
1222  /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 */ 4,
1223  /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 */ 5,
1224  };
1225  return t[lvl];
1226 }
1227 
1228 static inline int vui_sar_idc(enum v4l2_mpeg_video_h264_vui_sar_idc sar)
1229 {
1230  static unsigned int t[V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED + 1] = {
1231  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED */ 0,
1232  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 */ 1,
1233  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 */ 2,
1234  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 */ 3,
1235  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 */ 4,
1236  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 */ 5,
1237  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 */ 6,
1238  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 */ 7,
1239  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 */ 8,
1240  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 */ 9,
1241  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 */ 10,
1242  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 */ 11,
1243  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 */ 12,
1244  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 */ 13,
1245  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 */ 14,
1246  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 */ 15,
1247  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 */ 16,
1248  /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED */ 255,
1249  };
1250  return t[sar];
1251 }
1252 
1253 static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl)
1254 {
1255  struct s5p_mfc_ctx *ctx = ctrl_to_ctx(ctrl);
1256  struct s5p_mfc_dev *dev = ctx->dev;
1257  struct s5p_mfc_enc_params *p = &ctx->enc_params;
1258  int ret = 0;
1259 
1260  switch (ctrl->id) {
1262  p->gop_size = ctrl->val;
1263  break;
1265  p->slice_mode = ctrl->val;
1266  break;
1268  p->slice_mb = ctrl->val;
1269  break;
1271  p->slice_bit = ctrl->val * 8;
1272  break;
1274  p->intra_refresh_mb = ctrl->val;
1275  break;
1277  p->pad = ctrl->val;
1278  break;
1280  p->pad_luma = (ctrl->val >> 16) & 0xff;
1281  p->pad_cb = (ctrl->val >> 8) & 0xff;
1282  p->pad_cr = (ctrl->val >> 0) & 0xff;
1283  break;
1285  p->rc_frame = ctrl->val;
1286  break;
1288  p->rc_bitrate = ctrl->val;
1289  break;
1291  p->rc_reaction_coeff = ctrl->val;
1292  break;
1294  ctx->force_frame_type = ctrl->val;
1295  break;
1297  p->vbv_size = ctrl->val;
1298  break;
1300  p->codec.h264.cpb_size = ctrl->val;
1301  break;
1303  p->seq_hdr_mode = ctrl->val;
1304  break;
1306  p->frame_skip_mode = ctrl->val;
1307  break;
1309  p->fixed_target_bit = ctrl->val;
1310  break;
1312  p->num_b_frame = ctrl->val;
1313  break;
1315  switch (ctrl->val) {
1317  p->codec.h264.profile =
1319  break;
1321  p->codec.h264.profile =
1323  break;
1325  p->codec.h264.profile =
1327  break;
1329  if (IS_MFCV6(dev))
1330  p->codec.h264.profile =
1332  else
1333  ret = -EINVAL;
1334  break;
1335  default:
1336  ret = -EINVAL;
1337  }
1338  break;
1340  p->codec.h264.level_v4l2 = ctrl->val;
1341  p->codec.h264.level = h264_level(ctrl->val);
1342  if (p->codec.h264.level < 0) {
1343  mfc_err("Level number is wrong\n");
1344  ret = p->codec.h264.level;
1345  }
1346  break;
1348  p->codec.mpeg4.level_v4l2 = ctrl->val;
1349  p->codec.mpeg4.level = mpeg4_level(ctrl->val);
1350  if (p->codec.mpeg4.level < 0) {
1351  mfc_err("Level number is wrong\n");
1352  ret = p->codec.mpeg4.level;
1353  }
1354  break;
1356  p->codec.h264.loop_filter_mode = ctrl->val;
1357  break;
1359  p->codec.h264.loop_filter_alpha = ctrl->val;
1360  break;
1362  p->codec.h264.loop_filter_beta = ctrl->val;
1363  break;
1365  p->codec.h264.entropy_mode = ctrl->val;
1366  break;
1368  p->codec.h264.num_ref_pic_4p = ctrl->val;
1369  break;
1371  p->codec.h264._8x8_transform = ctrl->val;
1372  break;
1374  p->rc_mb = ctrl->val;
1375  break;
1377  p->codec.h264.rc_frame_qp = ctrl->val;
1378  break;
1380  p->codec.h264.rc_min_qp = ctrl->val;
1381  break;
1383  p->codec.h264.rc_max_qp = ctrl->val;
1384  break;
1386  p->codec.h264.rc_p_frame_qp = ctrl->val;
1387  break;
1389  p->codec.h264.rc_b_frame_qp = ctrl->val;
1390  break;
1393  p->codec.mpeg4.rc_frame_qp = ctrl->val;
1394  break;
1397  p->codec.mpeg4.rc_min_qp = ctrl->val;
1398  break;
1401  p->codec.mpeg4.rc_max_qp = ctrl->val;
1402  break;
1405  p->codec.mpeg4.rc_p_frame_qp = ctrl->val;
1406  break;
1409  p->codec.mpeg4.rc_b_frame_qp = ctrl->val;
1410  break;
1412  p->codec.h264.rc_mb_dark = ctrl->val;
1413  break;
1415  p->codec.h264.rc_mb_smooth = ctrl->val;
1416  break;
1418  p->codec.h264.rc_mb_static = ctrl->val;
1419  break;
1421  p->codec.h264.rc_mb_activity = ctrl->val;
1422  break;
1424  p->codec.h264.vui_sar = ctrl->val;
1425  break;
1427  p->codec.h264.vui_sar_idc = vui_sar_idc(ctrl->val);
1428  break;
1430  p->codec.h264.vui_ext_sar_width = ctrl->val;
1431  break;
1433  p->codec.h264.vui_ext_sar_height = ctrl->val;
1434  break;
1436  p->codec.h264.open_gop = !ctrl->val;
1437  break;
1439  p->codec.h264.open_gop_size = ctrl->val;
1440  break;
1442  switch (ctrl->val) {
1444  p->codec.mpeg4.profile =
1446  break;
1448  p->codec.mpeg4.profile =
1450  break;
1451  default:
1452  ret = -EINVAL;
1453  }
1454  break;
1456  p->codec.mpeg4.quarter_pixel = ctrl->val;
1457  break;
1458  default:
1459  v4l2_err(&dev->v4l2_dev, "Invalid control, id=%d, val=%d\n",
1460  ctrl->id, ctrl->val);
1461  ret = -EINVAL;
1462  }
1463  return ret;
1464 }
1465 
1466 static const struct v4l2_ctrl_ops s5p_mfc_enc_ctrl_ops = {
1467  .s_ctrl = s5p_mfc_enc_s_ctrl,
1468 };
1469 
1470 static int vidioc_s_parm(struct file *file, void *priv,
1471  struct v4l2_streamparm *a)
1472 {
1473  struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1474 
1476  ctx->enc_params.rc_framerate_num =
1477  a->parm.output.timeperframe.denominator;
1478  ctx->enc_params.rc_framerate_denom =
1479  a->parm.output.timeperframe.numerator;
1480  } else {
1481  mfc_err("Setting FPS is only possible for the output queue\n");
1482  return -EINVAL;
1483  }
1484  return 0;
1485 }
1486 
1487 static int vidioc_g_parm(struct file *file, void *priv,
1488  struct v4l2_streamparm *a)
1489 {
1490  struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1491 
1492  if (a->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
1493  a->parm.output.timeperframe.denominator =
1494  ctx->enc_params.rc_framerate_num;
1495  a->parm.output.timeperframe.numerator =
1496  ctx->enc_params.rc_framerate_denom;
1497  } else {
1498  mfc_err("Setting FPS is only possible for the output queue\n");
1499  return -EINVAL;
1500  }
1501  return 0;
1502 }
1503 
1504 int vidioc_encoder_cmd(struct file *file, void *priv,
1505  struct v4l2_encoder_cmd *cmd)
1506 {
1507  struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1508  struct s5p_mfc_dev *dev = ctx->dev;
1509  struct s5p_mfc_buf *buf;
1510  unsigned long flags;
1511 
1512  switch (cmd->cmd) {
1513  case V4L2_ENC_CMD_STOP:
1514  if (cmd->flags != 0)
1515  return -EINVAL;
1516 
1517  if (!ctx->vq_src.streaming)
1518  return -EINVAL;
1519 
1520  spin_lock_irqsave(&dev->irqlock, flags);
1521  if (list_empty(&ctx->src_queue)) {
1522  mfc_debug(2, "EOS: empty src queue, entering finishing state");
1523  ctx->state = MFCINST_FINISHING;
1524  spin_unlock_irqrestore(&dev->irqlock, flags);
1525  s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
1526  } else {
1527  mfc_debug(2, "EOS: marking last buffer of stream");
1528  buf = list_entry(ctx->src_queue.prev,
1529  struct s5p_mfc_buf, list);
1530  if (buf->flags & MFC_BUF_FLAG_USED)
1531  ctx->state = MFCINST_FINISHING;
1532  else
1533  buf->flags |= MFC_BUF_FLAG_EOS;
1534  spin_unlock_irqrestore(&dev->irqlock, flags);
1535  }
1536  break;
1537  default:
1538  return -EINVAL;
1539 
1540  }
1541  return 0;
1542 }
1543 
1544 static int vidioc_subscribe_event(struct v4l2_fh *fh,
1545  struct v4l2_event_subscription *sub)
1546 {
1547  switch (sub->type) {
1548  case V4L2_EVENT_EOS:
1549  return v4l2_event_subscribe(fh, sub, 2, NULL);
1550  default:
1551  return -EINVAL;
1552  }
1553 }
1554 
1555 static const struct v4l2_ioctl_ops s5p_mfc_enc_ioctl_ops = {
1556  .vidioc_querycap = vidioc_querycap,
1557  .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1558  .vidioc_enum_fmt_vid_cap_mplane = vidioc_enum_fmt_vid_cap_mplane,
1559  .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
1560  .vidioc_enum_fmt_vid_out_mplane = vidioc_enum_fmt_vid_out_mplane,
1561  .vidioc_g_fmt_vid_cap_mplane = vidioc_g_fmt,
1562  .vidioc_g_fmt_vid_out_mplane = vidioc_g_fmt,
1563  .vidioc_try_fmt_vid_cap_mplane = vidioc_try_fmt,
1564  .vidioc_try_fmt_vid_out_mplane = vidioc_try_fmt,
1565  .vidioc_s_fmt_vid_cap_mplane = vidioc_s_fmt,
1566  .vidioc_s_fmt_vid_out_mplane = vidioc_s_fmt,
1567  .vidioc_reqbufs = vidioc_reqbufs,
1568  .vidioc_querybuf = vidioc_querybuf,
1569  .vidioc_qbuf = vidioc_qbuf,
1570  .vidioc_dqbuf = vidioc_dqbuf,
1571  .vidioc_streamon = vidioc_streamon,
1572  .vidioc_streamoff = vidioc_streamoff,
1573  .vidioc_s_parm = vidioc_s_parm,
1574  .vidioc_g_parm = vidioc_g_parm,
1575  .vidioc_encoder_cmd = vidioc_encoder_cmd,
1576  .vidioc_subscribe_event = vidioc_subscribe_event,
1577  .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1578 };
1579 
1580 static int check_vb_with_fmt(struct s5p_mfc_fmt *fmt, struct vb2_buffer *vb)
1581 {
1582  int i;
1583 
1584  if (!fmt)
1585  return -EINVAL;
1586  if (fmt->num_planes != vb->num_planes) {
1587  mfc_err("invalid plane number for the format\n");
1588  return -EINVAL;
1589  }
1590  for (i = 0; i < fmt->num_planes; i++) {
1591  if (!vb2_dma_contig_plane_dma_addr(vb, i)) {
1592  mfc_err("failed to get plane cookie\n");
1593  return -EINVAL;
1594  }
1595  mfc_debug(2, "index: %d, plane[%d] cookie: 0x%08zx",
1596  vb->v4l2_buf.index, i,
1597  vb2_dma_contig_plane_dma_addr(vb, i));
1598  }
1599  return 0;
1600 }
1601 
1602 static int s5p_mfc_queue_setup(struct vb2_queue *vq,
1603  const struct v4l2_format *fmt,
1604  unsigned int *buf_count, unsigned int *plane_count,
1605  unsigned int psize[], void *allocators[])
1606 {
1607  struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
1608  struct s5p_mfc_dev *dev = ctx->dev;
1609 
1610  if (ctx->state != MFCINST_GOT_INST) {
1611  mfc_err("inavlid state: %d\n", ctx->state);
1612  return -EINVAL;
1613  }
1615  if (ctx->dst_fmt)
1616  *plane_count = ctx->dst_fmt->num_planes;
1617  else
1618  *plane_count = MFC_ENC_CAP_PLANE_COUNT;
1619  if (*buf_count < 1)
1620  *buf_count = 1;
1621  if (*buf_count > MFC_MAX_BUFFERS)
1622  *buf_count = MFC_MAX_BUFFERS;
1623  psize[0] = ctx->enc_dst_buf_size;
1624  allocators[0] = ctx->dev->alloc_ctx[MFC_BANK1_ALLOC_CTX];
1625  } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1626  if (ctx->src_fmt)
1627  *plane_count = ctx->src_fmt->num_planes;
1628  else
1629  *plane_count = MFC_ENC_OUT_PLANE_COUNT;
1630 
1631  if (*buf_count < 1)
1632  *buf_count = 1;
1633  if (*buf_count > MFC_MAX_BUFFERS)
1634  *buf_count = MFC_MAX_BUFFERS;
1635  psize[0] = ctx->luma_size;
1636  psize[1] = ctx->chroma_size;
1637  if (IS_MFCV6(dev)) {
1638  allocators[0] =
1639  ctx->dev->alloc_ctx[MFC_BANK1_ALLOC_CTX];
1640  allocators[1] =
1641  ctx->dev->alloc_ctx[MFC_BANK1_ALLOC_CTX];
1642  } else {
1643  allocators[0] =
1644  ctx->dev->alloc_ctx[MFC_BANK2_ALLOC_CTX];
1645  allocators[1] =
1646  ctx->dev->alloc_ctx[MFC_BANK2_ALLOC_CTX];
1647  }
1648  } else {
1649  mfc_err("inavlid queue type: %d\n", vq->type);
1650  return -EINVAL;
1651  }
1652  return 0;
1653 }
1654 
1655 static void s5p_mfc_unlock(struct vb2_queue *q)
1656 {
1657  struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
1658  struct s5p_mfc_dev *dev = ctx->dev;
1659 
1660  mutex_unlock(&dev->mfc_mutex);
1661 }
1662 
1663 static void s5p_mfc_lock(struct vb2_queue *q)
1664 {
1665  struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
1666  struct s5p_mfc_dev *dev = ctx->dev;
1667 
1668  mutex_lock(&dev->mfc_mutex);
1669 }
1670 
1671 static int s5p_mfc_buf_init(struct vb2_buffer *vb)
1672 {
1673  struct vb2_queue *vq = vb->vb2_queue;
1674  struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
1675  unsigned int i;
1676  int ret;
1677 
1679  ret = check_vb_with_fmt(ctx->dst_fmt, vb);
1680  if (ret < 0)
1681  return ret;
1682  i = vb->v4l2_buf.index;
1683  ctx->dst_bufs[i].b = vb;
1684  ctx->dst_bufs[i].cookie.stream =
1685  vb2_dma_contig_plane_dma_addr(vb, 0);
1686  ctx->dst_bufs_cnt++;
1687  } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1688  ret = check_vb_with_fmt(ctx->src_fmt, vb);
1689  if (ret < 0)
1690  return ret;
1691  i = vb->v4l2_buf.index;
1692  ctx->src_bufs[i].b = vb;
1693  ctx->src_bufs[i].cookie.raw.luma =
1694  vb2_dma_contig_plane_dma_addr(vb, 0);
1695  ctx->src_bufs[i].cookie.raw.chroma =
1696  vb2_dma_contig_plane_dma_addr(vb, 1);
1697  ctx->src_bufs_cnt++;
1698  } else {
1699  mfc_err("inavlid queue type: %d\n", vq->type);
1700  return -EINVAL;
1701  }
1702  return 0;
1703 }
1704 
1705 static int s5p_mfc_buf_prepare(struct vb2_buffer *vb)
1706 {
1707  struct vb2_queue *vq = vb->vb2_queue;
1708  struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
1709  int ret;
1710 
1712  ret = check_vb_with_fmt(ctx->dst_fmt, vb);
1713  if (ret < 0)
1714  return ret;
1715  mfc_debug(2, "plane size: %ld, dst size: %d\n",
1716  vb2_plane_size(vb, 0), ctx->enc_dst_buf_size);
1717  if (vb2_plane_size(vb, 0) < ctx->enc_dst_buf_size) {
1718  mfc_err("plane size is too small for capture\n");
1719  return -EINVAL;
1720  }
1721  } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1722  ret = check_vb_with_fmt(ctx->src_fmt, vb);
1723  if (ret < 0)
1724  return ret;
1725  mfc_debug(2, "plane size: %ld, luma size: %d\n",
1726  vb2_plane_size(vb, 0), ctx->luma_size);
1727  mfc_debug(2, "plane size: %ld, chroma size: %d\n",
1728  vb2_plane_size(vb, 1), ctx->chroma_size);
1729  if (vb2_plane_size(vb, 0) < ctx->luma_size ||
1730  vb2_plane_size(vb, 1) < ctx->chroma_size) {
1731  mfc_err("plane size is too small for output\n");
1732  return -EINVAL;
1733  }
1734  } else {
1735  mfc_err("inavlid queue type: %d\n", vq->type);
1736  return -EINVAL;
1737  }
1738  return 0;
1739 }
1740 
1741 static int s5p_mfc_start_streaming(struct vb2_queue *q, unsigned int count)
1742 {
1743  struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
1744  struct s5p_mfc_dev *dev = ctx->dev;
1745 
1747  /* If context is ready then dev = work->data;schedule it to run */
1748  if (s5p_mfc_ctx_ready(ctx))
1749  set_work_bit_irqsave(ctx);
1750  s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
1751  return 0;
1752 }
1753 
1754 static int s5p_mfc_stop_streaming(struct vb2_queue *q)
1755 {
1756  unsigned long flags;
1757  struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
1758  struct s5p_mfc_dev *dev = ctx->dev;
1759 
1760  if ((ctx->state == MFCINST_FINISHING ||
1761  ctx->state == MFCINST_RUNNING) &&
1762  dev->curr_ctx == ctx->num && dev->hw_lock) {
1763  ctx->state = MFCINST_ABORT;
1765  0);
1766  }
1767  ctx->state = MFCINST_FINISHED;
1768  spin_lock_irqsave(&dev->irqlock, flags);
1770  s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
1771  &ctx->vq_dst);
1772  INIT_LIST_HEAD(&ctx->dst_queue);
1773  ctx->dst_queue_cnt = 0;
1774  }
1776  cleanup_ref_queue(ctx);
1777  s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
1778  &ctx->vq_src);
1779  INIT_LIST_HEAD(&ctx->src_queue);
1780  ctx->src_queue_cnt = 0;
1781  }
1782  spin_unlock_irqrestore(&dev->irqlock, flags);
1783  return 0;
1784 }
1785 
1786 static void s5p_mfc_buf_queue(struct vb2_buffer *vb)
1787 {
1788  struct vb2_queue *vq = vb->vb2_queue;
1789  struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
1790  struct s5p_mfc_dev *dev = ctx->dev;
1791  unsigned long flags;
1792  struct s5p_mfc_buf *mfc_buf;
1793 
1794  if (ctx->state == MFCINST_ERROR) {
1796  cleanup_ref_queue(ctx);
1797  return;
1798  }
1800  mfc_buf = &ctx->dst_bufs[vb->v4l2_buf.index];
1801  mfc_buf->flags &= ~MFC_BUF_FLAG_USED;
1802  /* Mark destination as available for use by MFC */
1803  spin_lock_irqsave(&dev->irqlock, flags);
1804  list_add_tail(&mfc_buf->list, &ctx->dst_queue);
1805  ctx->dst_queue_cnt++;
1806  spin_unlock_irqrestore(&dev->irqlock, flags);
1807  } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1808  mfc_buf = &ctx->src_bufs[vb->v4l2_buf.index];
1809  mfc_buf->flags &= ~MFC_BUF_FLAG_USED;
1810  spin_lock_irqsave(&dev->irqlock, flags);
1811  list_add_tail(&mfc_buf->list, &ctx->src_queue);
1812  ctx->src_queue_cnt++;
1813  spin_unlock_irqrestore(&dev->irqlock, flags);
1814  } else {
1815  mfc_err("unsupported buffer type (%d)\n", vq->type);
1816  }
1817  if (s5p_mfc_ctx_ready(ctx))
1818  set_work_bit_irqsave(ctx);
1819  s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
1820 }
1821 
1822 static struct vb2_ops s5p_mfc_enc_qops = {
1823  .queue_setup = s5p_mfc_queue_setup,
1824  .wait_prepare = s5p_mfc_unlock,
1825  .wait_finish = s5p_mfc_lock,
1826  .buf_init = s5p_mfc_buf_init,
1827  .buf_prepare = s5p_mfc_buf_prepare,
1828  .start_streaming = s5p_mfc_start_streaming,
1829  .stop_streaming = s5p_mfc_stop_streaming,
1830  .buf_queue = s5p_mfc_buf_queue,
1831 };
1832 
1834 {
1835  return &encoder_codec_ops;
1836 }
1837 
1839 {
1840  return &s5p_mfc_enc_qops;
1841 }
1842 
1844 {
1845  return &s5p_mfc_enc_ioctl_ops;
1846 }
1847 
1848 #define IS_MFC51_PRIV(x) ((V4L2_CTRL_ID2CLASS(x) == V4L2_CTRL_CLASS_MPEG) \
1849  && V4L2_CTRL_DRIVER_PRIV(x))
1850 
1852 {
1853  struct v4l2_ctrl_config cfg;
1854  int i;
1855 
1857  if (ctx->ctrl_handler.error) {
1858  mfc_err("v4l2_ctrl_handler_init failed\n");
1859  return ctx->ctrl_handler.error;
1860  }
1861  for (i = 0; i < NUM_CTRLS; i++) {
1862  if (IS_MFC51_PRIV(controls[i].id)) {
1863  memset(&cfg, 0, sizeof(struct v4l2_ctrl_config));
1864  cfg.ops = &s5p_mfc_enc_ctrl_ops;
1865  cfg.id = controls[i].id;
1866  cfg.min = controls[i].minimum;
1867  cfg.max = controls[i].maximum;
1868  cfg.def = controls[i].default_value;
1869  cfg.name = controls[i].name;
1870  cfg.type = controls[i].type;
1871  cfg.flags = 0;
1872 
1873  if (cfg.type == V4L2_CTRL_TYPE_MENU) {
1874  cfg.step = 0;
1875  cfg.menu_skip_mask = cfg.menu_skip_mask;
1876  cfg.qmenu = mfc51_get_menu(cfg.id);
1877  } else {
1878  cfg.step = controls[i].step;
1879  cfg.menu_skip_mask = 0;
1880  }
1881  ctx->ctrls[i] = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
1882  &cfg, NULL);
1883  } else {
1884  if (controls[i].type == V4L2_CTRL_TYPE_MENU) {
1885  ctx->ctrls[i] = v4l2_ctrl_new_std_menu(
1886  &ctx->ctrl_handler,
1887  &s5p_mfc_enc_ctrl_ops, controls[i].id,
1888  controls[i].maximum, 0,
1889  controls[i].default_value);
1890  } else {
1891  ctx->ctrls[i] = v4l2_ctrl_new_std(
1892  &ctx->ctrl_handler,
1893  &s5p_mfc_enc_ctrl_ops, controls[i].id,
1894  controls[i].minimum,
1895  controls[i].maximum, controls[i].step,
1896  controls[i].default_value);
1897  }
1898  }
1899  if (ctx->ctrl_handler.error) {
1900  mfc_err("Adding control (%d) failed\n", i);
1901  return ctx->ctrl_handler.error;
1902  }
1903  if (controls[i].is_volatile && ctx->ctrls[i])
1904  ctx->ctrls[i]->flags |= V4L2_CTRL_FLAG_VOLATILE;
1905  }
1906  return 0;
1907 }
1908 
1910 {
1911  int i;
1912 
1914  for (i = 0; i < NUM_CTRLS; i++)
1915  ctx->ctrls[i] = NULL;
1916 }
1917 
1919 {
1920  struct v4l2_format f;
1921  f.fmt.pix_mp.pixelformat = DEF_SRC_FMT_ENC;
1922  ctx->src_fmt = find_format(&f, MFC_FMT_RAW);
1923  f.fmt.pix_mp.pixelformat = DEF_DST_FMT_ENC;
1924  ctx->dst_fmt = find_format(&f, MFC_FMT_ENC);
1925 }
1926