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spi-omap2-mcspi.c
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1 /*
2  * OMAP2 McSPI controller driver
3  *
4  * Copyright (C) 2005, 2006 Nokia Corporation
5  * Author: Samuel Ortiz <[email protected]> and
6  * Juha Yrj�l� <[email protected]>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21  *
22  */
23 
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/omap-dma.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
36 #include <linux/io.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/of.h>
40 #include <linux/of_device.h>
41 #include <linux/pinctrl/consumer.h>
42 #include <linux/err.h>
43 
44 #include <linux/spi/spi.h>
45 
46 #include <linux/platform_data/spi-omap2-mcspi.h>
47 
48 #define OMAP2_MCSPI_MAX_FREQ 48000000
49 #define SPI_AUTOSUSPEND_TIMEOUT 2000
50 
51 #define OMAP2_MCSPI_REVISION 0x00
52 #define OMAP2_MCSPI_SYSSTATUS 0x14
53 #define OMAP2_MCSPI_IRQSTATUS 0x18
54 #define OMAP2_MCSPI_IRQENABLE 0x1c
55 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
56 #define OMAP2_MCSPI_SYST 0x24
57 #define OMAP2_MCSPI_MODULCTRL 0x28
58 
59 /* per-channel banks, 0x14 bytes each, first is: */
60 #define OMAP2_MCSPI_CHCONF0 0x2c
61 #define OMAP2_MCSPI_CHSTAT0 0x30
62 #define OMAP2_MCSPI_CHCTRL0 0x34
63 #define OMAP2_MCSPI_TX0 0x38
64 #define OMAP2_MCSPI_RX0 0x3c
65 
66 /* per-register bitmasks: */
67 
68 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
69 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
70 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
71 
72 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
73 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
74 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
75 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
76 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
77 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
78 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
79 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
80 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
81 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
82 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
83 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
84 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
85 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
86 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
87 
88 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
89 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
90 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
91 
92 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
93 
94 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
95 
96 /* We have 2 DMA channels per CS, one for RX and one for TX */
97 struct omap2_mcspi_dma {
98  struct dma_chan *dma_tx;
99  struct dma_chan *dma_rx;
100 
101  int dma_tx_sync_dev;
102  int dma_rx_sync_dev;
103 
104  struct completion dma_tx_completion;
105  struct completion dma_rx_completion;
106 };
107 
108 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
109  * cache operations; better heuristics consider wordsize and bitrate.
110  */
111 #define DMA_MIN_BYTES 160
112 
113 
114 /*
115  * Used for context save and restore, structure members to be updated whenever
116  * corresponding registers are modified.
117  */
118 struct omap2_mcspi_regs {
119  u32 modulctrl;
120  u32 wakeupenable;
121  struct list_head cs;
122 };
123 
124 struct omap2_mcspi {
125  struct spi_master *master;
126  /* Virtual base address of the controller */
127  void __iomem *base;
128  unsigned long phys;
129  /* SPI1 has 4 channels, while SPI2 has 2 */
130  struct omap2_mcspi_dma *dma_channels;
131  struct device *dev;
132  struct omap2_mcspi_regs ctx;
133 };
134 
135 struct omap2_mcspi_cs {
136  void __iomem *base;
137  unsigned long phys;
138  int word_len;
139  struct list_head node;
140  /* Context save and restore shadow register */
141  u32 chconf0;
142 };
143 
144 static inline void mcspi_write_reg(struct spi_master *master,
145  int idx, u32 val)
146 {
147  struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
148 
149  __raw_writel(val, mcspi->base + idx);
150 }
151 
152 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
153 {
154  struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
155 
156  return __raw_readl(mcspi->base + idx);
157 }
158 
159 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
160  int idx, u32 val)
161 {
162  struct omap2_mcspi_cs *cs = spi->controller_state;
163 
164  __raw_writel(val, cs->base + idx);
165 }
166 
167 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
168 {
169  struct omap2_mcspi_cs *cs = spi->controller_state;
170 
171  return __raw_readl(cs->base + idx);
172 }
173 
174 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
175 {
176  struct omap2_mcspi_cs *cs = spi->controller_state;
177 
178  return cs->chconf0;
179 }
180 
181 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
182 {
183  struct omap2_mcspi_cs *cs = spi->controller_state;
184 
185  cs->chconf0 = val;
186  mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
187  mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
188 }
189 
190 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
191  int is_read, int enable)
192 {
193  u32 l, rw;
194 
195  l = mcspi_cached_chconf0(spi);
196 
197  if (is_read) /* 1 is read, 0 write */
198  rw = OMAP2_MCSPI_CHCONF_DMAR;
199  else
200  rw = OMAP2_MCSPI_CHCONF_DMAW;
201 
202  if (enable)
203  l |= rw;
204  else
205  l &= ~rw;
206 
207  mcspi_write_chconf0(spi, l);
208 }
209 
210 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
211 {
212  u32 l;
213 
214  l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
215  mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
216  /* Flash post-writes */
217  mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
218 }
219 
220 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
221 {
222  u32 l;
223 
224  l = mcspi_cached_chconf0(spi);
225  if (cs_active)
226  l |= OMAP2_MCSPI_CHCONF_FORCE;
227  else
228  l &= ~OMAP2_MCSPI_CHCONF_FORCE;
229 
230  mcspi_write_chconf0(spi, l);
231 }
232 
233 static void omap2_mcspi_set_master_mode(struct spi_master *master)
234 {
235  struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
236  struct omap2_mcspi_regs *ctx = &mcspi->ctx;
237  u32 l;
238 
239  /*
240  * Setup when switching from (reset default) slave mode
241  * to single-channel master mode
242  */
243  l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
244  l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
245  l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
246  mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
247 
248  ctx->modulctrl = l;
249 }
250 
251 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
252 {
253  struct spi_master *spi_cntrl = mcspi->master;
254  struct omap2_mcspi_regs *ctx = &mcspi->ctx;
255  struct omap2_mcspi_cs *cs;
256 
257  /* McSPI: context restore */
258  mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
259  mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
260 
261  list_for_each_entry(cs, &ctx->cs, node)
262  __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
263 }
264 
265 static int omap2_prepare_transfer(struct spi_master *master)
266 {
267  struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
268 
269  pm_runtime_get_sync(mcspi->dev);
270  return 0;
271 }
272 
273 static int omap2_unprepare_transfer(struct spi_master *master)
274 {
275  struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
276 
277  pm_runtime_mark_last_busy(mcspi->dev);
278  pm_runtime_put_autosuspend(mcspi->dev);
279  return 0;
280 }
281 
282 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
283 {
284  unsigned long timeout;
285 
286  timeout = jiffies + msecs_to_jiffies(1000);
287  while (!(__raw_readl(reg) & bit)) {
288  if (time_after(jiffies, timeout))
289  return -1;
290  cpu_relax();
291  }
292  return 0;
293 }
294 
295 static void omap2_mcspi_rx_callback(void *data)
296 {
297  struct spi_device *spi = data;
298  struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
299  struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
300 
301  complete(&mcspi_dma->dma_rx_completion);
302 
303  /* We must disable the DMA RX request */
304  omap2_mcspi_set_dma_req(spi, 1, 0);
305 }
306 
307 static void omap2_mcspi_tx_callback(void *data)
308 {
309  struct spi_device *spi = data;
310  struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
311  struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
312 
313  complete(&mcspi_dma->dma_tx_completion);
314 
315  /* We must disable the DMA TX request */
316  omap2_mcspi_set_dma_req(spi, 0, 0);
317 }
318 
319 static void omap2_mcspi_tx_dma(struct spi_device *spi,
320  struct spi_transfer *xfer,
321  struct dma_slave_config cfg)
322 {
323  struct omap2_mcspi *mcspi;
324  struct omap2_mcspi_dma *mcspi_dma;
325  unsigned int count;
326  u8 * rx;
327  const u8 * tx;
328  void __iomem *chstat_reg;
329  struct omap2_mcspi_cs *cs = spi->controller_state;
330 
331  mcspi = spi_master_get_devdata(spi->master);
332  mcspi_dma = &mcspi->dma_channels[spi->chip_select];
333  count = xfer->len;
334 
335  rx = xfer->rx_buf;
336  tx = xfer->tx_buf;
337  chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
338 
339  if (mcspi_dma->dma_tx) {
340  struct dma_async_tx_descriptor *tx;
341  struct scatterlist sg;
342 
343  dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
344 
345  sg_init_table(&sg, 1);
346  sg_dma_address(&sg) = xfer->tx_dma;
347  sg_dma_len(&sg) = xfer->len;
348 
349  tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
350  DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
351  if (tx) {
352  tx->callback = omap2_mcspi_tx_callback;
353  tx->callback_param = spi;
354  dmaengine_submit(tx);
355  } else {
356  /* FIXME: fall back to PIO? */
357  }
358  }
359  dma_async_issue_pending(mcspi_dma->dma_tx);
360  omap2_mcspi_set_dma_req(spi, 0, 1);
361 
362  wait_for_completion(&mcspi_dma->dma_tx_completion);
363  dma_unmap_single(mcspi->dev, xfer->tx_dma, count,
364  DMA_TO_DEVICE);
365 
366  /* for TX_ONLY mode, be sure all words have shifted out */
367  if (rx == NULL) {
368  if (mcspi_wait_for_reg_bit(chstat_reg,
369  OMAP2_MCSPI_CHSTAT_TXS) < 0)
370  dev_err(&spi->dev, "TXS timed out\n");
371  else if (mcspi_wait_for_reg_bit(chstat_reg,
372  OMAP2_MCSPI_CHSTAT_EOT) < 0)
373  dev_err(&spi->dev, "EOT timed out\n");
374  }
375 }
376 
377 static unsigned
378 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
379  struct dma_slave_config cfg,
380  unsigned es)
381 {
382  struct omap2_mcspi *mcspi;
383  struct omap2_mcspi_dma *mcspi_dma;
384  unsigned int count;
385  u32 l;
386  int elements = 0;
387  int word_len, element_count;
388  struct omap2_mcspi_cs *cs = spi->controller_state;
389  mcspi = spi_master_get_devdata(spi->master);
390  mcspi_dma = &mcspi->dma_channels[spi->chip_select];
391  count = xfer->len;
392  word_len = cs->word_len;
393  l = mcspi_cached_chconf0(spi);
394 
395  if (word_len <= 8)
396  element_count = count;
397  else if (word_len <= 16)
398  element_count = count >> 1;
399  else /* word_len <= 32 */
400  element_count = count >> 2;
401 
402  if (mcspi_dma->dma_rx) {
403  struct dma_async_tx_descriptor *tx;
404  struct scatterlist sg;
405  size_t len = xfer->len - es;
406 
407  dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
408 
409  if (l & OMAP2_MCSPI_CHCONF_TURBO)
410  len -= es;
411 
412  sg_init_table(&sg, 1);
413  sg_dma_address(&sg) = xfer->rx_dma;
414  sg_dma_len(&sg) = len;
415 
416  tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
417  DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
418  DMA_CTRL_ACK);
419  if (tx) {
420  tx->callback = omap2_mcspi_rx_callback;
421  tx->callback_param = spi;
422  dmaengine_submit(tx);
423  } else {
424  /* FIXME: fall back to PIO? */
425  }
426  }
427 
428  dma_async_issue_pending(mcspi_dma->dma_rx);
429  omap2_mcspi_set_dma_req(spi, 1, 1);
430 
431  wait_for_completion(&mcspi_dma->dma_rx_completion);
432  dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
433  DMA_FROM_DEVICE);
434  omap2_mcspi_set_enable(spi, 0);
435 
436  elements = element_count - 1;
437 
438  if (l & OMAP2_MCSPI_CHCONF_TURBO) {
439  elements--;
440 
441  if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
442  & OMAP2_MCSPI_CHSTAT_RXS)) {
443  u32 w;
444 
445  w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
446  if (word_len <= 8)
447  ((u8 *)xfer->rx_buf)[elements++] = w;
448  else if (word_len <= 16)
449  ((u16 *)xfer->rx_buf)[elements++] = w;
450  else /* word_len <= 32 */
451  ((u32 *)xfer->rx_buf)[elements++] = w;
452  } else {
453  dev_err(&spi->dev, "DMA RX penultimate word empty");
454  count -= (word_len <= 8) ? 2 :
455  (word_len <= 16) ? 4 :
456  /* word_len <= 32 */ 8;
457  omap2_mcspi_set_enable(spi, 1);
458  return count;
459  }
460  }
461  if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
462  & OMAP2_MCSPI_CHSTAT_RXS)) {
463  u32 w;
464 
465  w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
466  if (word_len <= 8)
467  ((u8 *)xfer->rx_buf)[elements] = w;
468  else if (word_len <= 16)
469  ((u16 *)xfer->rx_buf)[elements] = w;
470  else /* word_len <= 32 */
471  ((u32 *)xfer->rx_buf)[elements] = w;
472  } else {
473  dev_err(&spi->dev, "DMA RX last word empty");
474  count -= (word_len <= 8) ? 1 :
475  (word_len <= 16) ? 2 :
476  /* word_len <= 32 */ 4;
477  }
478  omap2_mcspi_set_enable(spi, 1);
479  return count;
480 }
481 
482 static unsigned
483 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
484 {
485  struct omap2_mcspi *mcspi;
486  struct omap2_mcspi_cs *cs = spi->controller_state;
487  struct omap2_mcspi_dma *mcspi_dma;
488  unsigned int count;
489  u32 l;
490  u8 *rx;
491  const u8 *tx;
492  struct dma_slave_config cfg;
493  enum dma_slave_buswidth width;
494  unsigned es;
495 
496  mcspi = spi_master_get_devdata(spi->master);
497  mcspi_dma = &mcspi->dma_channels[spi->chip_select];
498  l = mcspi_cached_chconf0(spi);
499 
500 
501  if (cs->word_len <= 8) {
502  width = DMA_SLAVE_BUSWIDTH_1_BYTE;
503  es = 1;
504  } else if (cs->word_len <= 16) {
505  width = DMA_SLAVE_BUSWIDTH_2_BYTES;
506  es = 2;
507  } else {
508  width = DMA_SLAVE_BUSWIDTH_4_BYTES;
509  es = 4;
510  }
511 
512  memset(&cfg, 0, sizeof(cfg));
513  cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
514  cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
515  cfg.src_addr_width = width;
516  cfg.dst_addr_width = width;
517  cfg.src_maxburst = 1;
518  cfg.dst_maxburst = 1;
519 
520  rx = xfer->rx_buf;
521  tx = xfer->tx_buf;
522 
523  count = xfer->len;
524 
525  if (tx != NULL)
526  omap2_mcspi_tx_dma(spi, xfer, cfg);
527 
528  if (rx != NULL)
529  return omap2_mcspi_rx_dma(spi, xfer, cfg, es);
530 
531  return count;
532 }
533 
534 static unsigned
535 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
536 {
537  struct omap2_mcspi *mcspi;
538  struct omap2_mcspi_cs *cs = spi->controller_state;
539  unsigned int count, c;
540  u32 l;
541  void __iomem *base = cs->base;
542  void __iomem *tx_reg;
543  void __iomem *rx_reg;
544  void __iomem *chstat_reg;
545  int word_len;
546 
547  mcspi = spi_master_get_devdata(spi->master);
548  count = xfer->len;
549  c = count;
550  word_len = cs->word_len;
551 
552  l = mcspi_cached_chconf0(spi);
553 
554  /* We store the pre-calculated register addresses on stack to speed
555  * up the transfer loop. */
556  tx_reg = base + OMAP2_MCSPI_TX0;
557  rx_reg = base + OMAP2_MCSPI_RX0;
558  chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
559 
560  if (c < (word_len>>3))
561  return 0;
562 
563  if (word_len <= 8) {
564  u8 *rx;
565  const u8 *tx;
566 
567  rx = xfer->rx_buf;
568  tx = xfer->tx_buf;
569 
570  do {
571  c -= 1;
572  if (tx != NULL) {
573  if (mcspi_wait_for_reg_bit(chstat_reg,
574  OMAP2_MCSPI_CHSTAT_TXS) < 0) {
575  dev_err(&spi->dev, "TXS timed out\n");
576  goto out;
577  }
578  dev_vdbg(&spi->dev, "write-%d %02x\n",
579  word_len, *tx);
580  __raw_writel(*tx++, tx_reg);
581  }
582  if (rx != NULL) {
583  if (mcspi_wait_for_reg_bit(chstat_reg,
584  OMAP2_MCSPI_CHSTAT_RXS) < 0) {
585  dev_err(&spi->dev, "RXS timed out\n");
586  goto out;
587  }
588 
589  if (c == 1 && tx == NULL &&
590  (l & OMAP2_MCSPI_CHCONF_TURBO)) {
591  omap2_mcspi_set_enable(spi, 0);
592  *rx++ = __raw_readl(rx_reg);
593  dev_vdbg(&spi->dev, "read-%d %02x\n",
594  word_len, *(rx - 1));
595  if (mcspi_wait_for_reg_bit(chstat_reg,
596  OMAP2_MCSPI_CHSTAT_RXS) < 0) {
597  dev_err(&spi->dev,
598  "RXS timed out\n");
599  goto out;
600  }
601  c = 0;
602  } else if (c == 0 && tx == NULL) {
603  omap2_mcspi_set_enable(spi, 0);
604  }
605 
606  *rx++ = __raw_readl(rx_reg);
607  dev_vdbg(&spi->dev, "read-%d %02x\n",
608  word_len, *(rx - 1));
609  }
610  } while (c);
611  } else if (word_len <= 16) {
612  u16 *rx;
613  const u16 *tx;
614 
615  rx = xfer->rx_buf;
616  tx = xfer->tx_buf;
617  do {
618  c -= 2;
619  if (tx != NULL) {
620  if (mcspi_wait_for_reg_bit(chstat_reg,
621  OMAP2_MCSPI_CHSTAT_TXS) < 0) {
622  dev_err(&spi->dev, "TXS timed out\n");
623  goto out;
624  }
625  dev_vdbg(&spi->dev, "write-%d %04x\n",
626  word_len, *tx);
627  __raw_writel(*tx++, tx_reg);
628  }
629  if (rx != NULL) {
630  if (mcspi_wait_for_reg_bit(chstat_reg,
631  OMAP2_MCSPI_CHSTAT_RXS) < 0) {
632  dev_err(&spi->dev, "RXS timed out\n");
633  goto out;
634  }
635 
636  if (c == 2 && tx == NULL &&
637  (l & OMAP2_MCSPI_CHCONF_TURBO)) {
638  omap2_mcspi_set_enable(spi, 0);
639  *rx++ = __raw_readl(rx_reg);
640  dev_vdbg(&spi->dev, "read-%d %04x\n",
641  word_len, *(rx - 1));
642  if (mcspi_wait_for_reg_bit(chstat_reg,
643  OMAP2_MCSPI_CHSTAT_RXS) < 0) {
644  dev_err(&spi->dev,
645  "RXS timed out\n");
646  goto out;
647  }
648  c = 0;
649  } else if (c == 0 && tx == NULL) {
650  omap2_mcspi_set_enable(spi, 0);
651  }
652 
653  *rx++ = __raw_readl(rx_reg);
654  dev_vdbg(&spi->dev, "read-%d %04x\n",
655  word_len, *(rx - 1));
656  }
657  } while (c >= 2);
658  } else if (word_len <= 32) {
659  u32 *rx;
660  const u32 *tx;
661 
662  rx = xfer->rx_buf;
663  tx = xfer->tx_buf;
664  do {
665  c -= 4;
666  if (tx != NULL) {
667  if (mcspi_wait_for_reg_bit(chstat_reg,
668  OMAP2_MCSPI_CHSTAT_TXS) < 0) {
669  dev_err(&spi->dev, "TXS timed out\n");
670  goto out;
671  }
672  dev_vdbg(&spi->dev, "write-%d %08x\n",
673  word_len, *tx);
674  __raw_writel(*tx++, tx_reg);
675  }
676  if (rx != NULL) {
677  if (mcspi_wait_for_reg_bit(chstat_reg,
678  OMAP2_MCSPI_CHSTAT_RXS) < 0) {
679  dev_err(&spi->dev, "RXS timed out\n");
680  goto out;
681  }
682 
683  if (c == 4 && tx == NULL &&
684  (l & OMAP2_MCSPI_CHCONF_TURBO)) {
685  omap2_mcspi_set_enable(spi, 0);
686  *rx++ = __raw_readl(rx_reg);
687  dev_vdbg(&spi->dev, "read-%d %08x\n",
688  word_len, *(rx - 1));
689  if (mcspi_wait_for_reg_bit(chstat_reg,
690  OMAP2_MCSPI_CHSTAT_RXS) < 0) {
691  dev_err(&spi->dev,
692  "RXS timed out\n");
693  goto out;
694  }
695  c = 0;
696  } else if (c == 0 && tx == NULL) {
697  omap2_mcspi_set_enable(spi, 0);
698  }
699 
700  *rx++ = __raw_readl(rx_reg);
701  dev_vdbg(&spi->dev, "read-%d %08x\n",
702  word_len, *(rx - 1));
703  }
704  } while (c >= 4);
705  }
706 
707  /* for TX_ONLY mode, be sure all words have shifted out */
708  if (xfer->rx_buf == NULL) {
709  if (mcspi_wait_for_reg_bit(chstat_reg,
710  OMAP2_MCSPI_CHSTAT_TXS) < 0) {
711  dev_err(&spi->dev, "TXS timed out\n");
712  } else if (mcspi_wait_for_reg_bit(chstat_reg,
713  OMAP2_MCSPI_CHSTAT_EOT) < 0)
714  dev_err(&spi->dev, "EOT timed out\n");
715 
716  /* disable chan to purge rx datas received in TX_ONLY transfer,
717  * otherwise these rx datas will affect the direct following
718  * RX_ONLY transfer.
719  */
720  omap2_mcspi_set_enable(spi, 0);
721  }
722 out:
723  omap2_mcspi_set_enable(spi, 1);
724  return count - c;
725 }
726 
727 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
728 {
729  u32 div;
730 
731  for (div = 0; div < 15; div++)
732  if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
733  return div;
734 
735  return 15;
736 }
737 
738 /* called only when no transfer is active to this device */
739 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
740  struct spi_transfer *t)
741 {
742  struct omap2_mcspi_cs *cs = spi->controller_state;
743  struct omap2_mcspi *mcspi;
744  struct spi_master *spi_cntrl;
745  u32 l = 0, div = 0;
746  u8 word_len = spi->bits_per_word;
747  u32 speed_hz = spi->max_speed_hz;
748 
749  mcspi = spi_master_get_devdata(spi->master);
750  spi_cntrl = mcspi->master;
751 
752  if (t != NULL && t->bits_per_word)
753  word_len = t->bits_per_word;
754 
755  cs->word_len = word_len;
756 
757  if (t && t->speed_hz)
758  speed_hz = t->speed_hz;
759 
760  speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
761  div = omap2_mcspi_calc_divisor(speed_hz);
762 
763  l = mcspi_cached_chconf0(spi);
764 
765  /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
766  * REVISIT: this controller could support SPI_3WIRE mode.
767  */
768  l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
769  l |= OMAP2_MCSPI_CHCONF_DPE0;
770 
771  /* wordlength */
772  l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
773  l |= (word_len - 1) << 7;
774 
775  /* set chipselect polarity; manage with FORCE */
776  if (!(spi->mode & SPI_CS_HIGH))
777  l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
778  else
779  l &= ~OMAP2_MCSPI_CHCONF_EPOL;
780 
781  /* set clock divisor */
782  l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
783  l |= div << 2;
784 
785  /* set SPI mode 0..3 */
786  if (spi->mode & SPI_CPOL)
787  l |= OMAP2_MCSPI_CHCONF_POL;
788  else
789  l &= ~OMAP2_MCSPI_CHCONF_POL;
790  if (spi->mode & SPI_CPHA)
791  l |= OMAP2_MCSPI_CHCONF_PHA;
792  else
793  l &= ~OMAP2_MCSPI_CHCONF_PHA;
794 
795  mcspi_write_chconf0(spi, l);
796 
797  dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
798  OMAP2_MCSPI_MAX_FREQ >> div,
799  (spi->mode & SPI_CPHA) ? "trailing" : "leading",
800  (spi->mode & SPI_CPOL) ? "inverted" : "normal");
801 
802  return 0;
803 }
804 
805 static int omap2_mcspi_request_dma(struct spi_device *spi)
806 {
807  struct spi_master *master = spi->master;
808  struct omap2_mcspi *mcspi;
809  struct omap2_mcspi_dma *mcspi_dma;
810  dma_cap_mask_t mask;
811  unsigned sig;
812 
813  mcspi = spi_master_get_devdata(master);
814  mcspi_dma = mcspi->dma_channels + spi->chip_select;
815 
816  init_completion(&mcspi_dma->dma_rx_completion);
817  init_completion(&mcspi_dma->dma_tx_completion);
818 
819  dma_cap_zero(mask);
820  dma_cap_set(DMA_SLAVE, mask);
821  sig = mcspi_dma->dma_rx_sync_dev;
822  mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
823  if (!mcspi_dma->dma_rx) {
824  dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
825  return -EAGAIN;
826  }
827 
828  sig = mcspi_dma->dma_tx_sync_dev;
829  mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
830  if (!mcspi_dma->dma_tx) {
831  dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n");
832  dma_release_channel(mcspi_dma->dma_rx);
833  mcspi_dma->dma_rx = NULL;
834  return -EAGAIN;
835  }
836 
837  return 0;
838 }
839 
840 static int omap2_mcspi_setup(struct spi_device *spi)
841 {
842  int ret;
843  struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
844  struct omap2_mcspi_regs *ctx = &mcspi->ctx;
845  struct omap2_mcspi_dma *mcspi_dma;
846  struct omap2_mcspi_cs *cs = spi->controller_state;
847 
848  if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
849  dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
850  spi->bits_per_word);
851  return -EINVAL;
852  }
853 
854  mcspi_dma = &mcspi->dma_channels[spi->chip_select];
855 
856  if (!cs) {
857  cs = kzalloc(sizeof *cs, GFP_KERNEL);
858  if (!cs)
859  return -ENOMEM;
860  cs->base = mcspi->base + spi->chip_select * 0x14;
861  cs->phys = mcspi->phys + spi->chip_select * 0x14;
862  cs->chconf0 = 0;
863  spi->controller_state = cs;
864  /* Link this to context save list */
865  list_add_tail(&cs->node, &ctx->cs);
866  }
867 
868  if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
869  ret = omap2_mcspi_request_dma(spi);
870  if (ret < 0)
871  return ret;
872  }
873 
874  ret = pm_runtime_get_sync(mcspi->dev);
875  if (ret < 0)
876  return ret;
877 
878  ret = omap2_mcspi_setup_transfer(spi, NULL);
879  pm_runtime_mark_last_busy(mcspi->dev);
880  pm_runtime_put_autosuspend(mcspi->dev);
881 
882  return ret;
883 }
884 
885 static void omap2_mcspi_cleanup(struct spi_device *spi)
886 {
887  struct omap2_mcspi *mcspi;
888  struct omap2_mcspi_dma *mcspi_dma;
889  struct omap2_mcspi_cs *cs;
890 
891  mcspi = spi_master_get_devdata(spi->master);
892 
893  if (spi->controller_state) {
894  /* Unlink controller state from context save list */
895  cs = spi->controller_state;
896  list_del(&cs->node);
897 
898  kfree(cs);
899  }
900 
901  if (spi->chip_select < spi->master->num_chipselect) {
902  mcspi_dma = &mcspi->dma_channels[spi->chip_select];
903 
904  if (mcspi_dma->dma_rx) {
905  dma_release_channel(mcspi_dma->dma_rx);
906  mcspi_dma->dma_rx = NULL;
907  }
908  if (mcspi_dma->dma_tx) {
909  dma_release_channel(mcspi_dma->dma_tx);
910  mcspi_dma->dma_tx = NULL;
911  }
912  }
913 }
914 
915 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
916 {
917 
918  /* We only enable one channel at a time -- the one whose message is
919  * -- although this controller would gladly
920  * arbitrate among multiple channels. This corresponds to "single
921  * channel" master mode. As a side effect, we need to manage the
922  * chipselect with the FORCE bit ... CS != channel enable.
923  */
924 
925  struct spi_device *spi;
926  struct spi_transfer *t = NULL;
927  int cs_active = 0;
928  struct omap2_mcspi_cs *cs;
929  struct omap2_mcspi_device_config *cd;
930  int par_override = 0;
931  int status = 0;
932  u32 chconf;
933 
934  spi = m->spi;
935  cs = spi->controller_state;
936  cd = spi->controller_data;
937 
938  omap2_mcspi_set_enable(spi, 1);
939  list_for_each_entry(t, &m->transfers, transfer_list) {
940  if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
941  status = -EINVAL;
942  break;
943  }
944  if (par_override || t->speed_hz || t->bits_per_word) {
945  par_override = 1;
946  status = omap2_mcspi_setup_transfer(spi, t);
947  if (status < 0)
948  break;
949  if (!t->speed_hz && !t->bits_per_word)
950  par_override = 0;
951  }
952 
953  if (!cs_active) {
954  omap2_mcspi_force_cs(spi, 1);
955  cs_active = 1;
956  }
957 
958  chconf = mcspi_cached_chconf0(spi);
959  chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
960  chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
961 
962  if (t->tx_buf == NULL)
963  chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
964  else if (t->rx_buf == NULL)
965  chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
966 
967  if (cd && cd->turbo_mode && t->tx_buf == NULL) {
968  /* Turbo mode is for more than one word */
969  if (t->len > ((cs->word_len + 7) >> 3))
970  chconf |= OMAP2_MCSPI_CHCONF_TURBO;
971  }
972 
973  mcspi_write_chconf0(spi, chconf);
974 
975  if (t->len) {
976  unsigned count;
977 
978  /* RX_ONLY mode needs dummy data in TX reg */
979  if (t->tx_buf == NULL)
980  __raw_writel(0, cs->base
981  + OMAP2_MCSPI_TX0);
982 
983  if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
984  count = omap2_mcspi_txrx_dma(spi, t);
985  else
986  count = omap2_mcspi_txrx_pio(spi, t);
987  m->actual_length += count;
988 
989  if (count != t->len) {
990  status = -EIO;
991  break;
992  }
993  }
994 
995  if (t->delay_usecs)
996  udelay(t->delay_usecs);
997 
998  /* ignore the "leave it on after last xfer" hint */
999  if (t->cs_change) {
1000  omap2_mcspi_force_cs(spi, 0);
1001  cs_active = 0;
1002  }
1003  }
1004  /* Restore defaults if they were overriden */
1005  if (par_override) {
1006  par_override = 0;
1007  status = omap2_mcspi_setup_transfer(spi, NULL);
1008  }
1009 
1010  if (cs_active)
1011  omap2_mcspi_force_cs(spi, 0);
1012 
1013  omap2_mcspi_set_enable(spi, 0);
1014 
1015  m->status = status;
1016 
1017 }
1018 
1019 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1020  struct spi_message *m)
1021 {
1022  struct omap2_mcspi *mcspi;
1023  struct spi_transfer *t;
1024 
1025  mcspi = spi_master_get_devdata(master);
1026  m->actual_length = 0;
1027  m->status = 0;
1028 
1029  /* reject invalid messages and transfers */
1030  if (list_empty(&m->transfers))
1031  return -EINVAL;
1032  list_for_each_entry(t, &m->transfers, transfer_list) {
1033  const void *tx_buf = t->tx_buf;
1034  void *rx_buf = t->rx_buf;
1035  unsigned len = t->len;
1036 
1037  if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1038  || (len && !(rx_buf || tx_buf))
1039  || (t->bits_per_word &&
1040  ( t->bits_per_word < 4
1041  || t->bits_per_word > 32))) {
1042  dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1043  t->speed_hz,
1044  len,
1045  tx_buf ? "tx" : "",
1046  rx_buf ? "rx" : "",
1047  t->bits_per_word);
1048  return -EINVAL;
1049  }
1050  if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1051  dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1052  t->speed_hz,
1053  OMAP2_MCSPI_MAX_FREQ >> 15);
1054  return -EINVAL;
1055  }
1056 
1057  if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1058  continue;
1059 
1060  if (tx_buf != NULL) {
1061  t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1062  len, DMA_TO_DEVICE);
1063  if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1064  dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1065  'T', len);
1066  return -EINVAL;
1067  }
1068  }
1069  if (rx_buf != NULL) {
1070  t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1071  DMA_FROM_DEVICE);
1072  if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1073  dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1074  'R', len);
1075  if (tx_buf != NULL)
1076  dma_unmap_single(mcspi->dev, t->tx_dma,
1077  len, DMA_TO_DEVICE);
1078  return -EINVAL;
1079  }
1080  }
1081  }
1082 
1083  omap2_mcspi_work(mcspi, m);
1084  spi_finalize_current_message(master);
1085  return 0;
1086 }
1087 
1088 static int __devinit omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1089 {
1090  struct spi_master *master = mcspi->master;
1091  struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1092  int ret = 0;
1093 
1094  ret = pm_runtime_get_sync(mcspi->dev);
1095  if (ret < 0)
1096  return ret;
1097 
1098  mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1099  OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1100  ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1101 
1102  omap2_mcspi_set_master_mode(master);
1103  pm_runtime_mark_last_busy(mcspi->dev);
1104  pm_runtime_put_autosuspend(mcspi->dev);
1105  return 0;
1106 }
1107 
1108 static int omap_mcspi_runtime_resume(struct device *dev)
1109 {
1110  struct omap2_mcspi *mcspi;
1111  struct spi_master *master;
1112 
1113  master = dev_get_drvdata(dev);
1114  mcspi = spi_master_get_devdata(master);
1115  omap2_mcspi_restore_ctx(mcspi);
1116 
1117  return 0;
1118 }
1119 
1120 static struct omap2_mcspi_platform_config omap2_pdata = {
1121  .regs_offset = 0,
1122 };
1123 
1124 static struct omap2_mcspi_platform_config omap4_pdata = {
1125  .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1126 };
1127 
1128 static const struct of_device_id omap_mcspi_of_match[] = {
1129  {
1130  .compatible = "ti,omap2-mcspi",
1131  .data = &omap2_pdata,
1132  },
1133  {
1134  .compatible = "ti,omap4-mcspi",
1135  .data = &omap4_pdata,
1136  },
1137  { },
1138 };
1139 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1140 
1141 static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
1142 {
1143  struct spi_master *master;
1144  const struct omap2_mcspi_platform_config *pdata;
1145  struct omap2_mcspi *mcspi;
1146  struct resource *r;
1147  int status = 0, i;
1148  u32 regs_offset = 0;
1149  static int bus_num = 1;
1150  struct device_node *node = pdev->dev.of_node;
1151  const struct of_device_id *match;
1152  struct pinctrl *pinctrl;
1153 
1154  master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1155  if (master == NULL) {
1156  dev_dbg(&pdev->dev, "master allocation failed\n");
1157  return -ENOMEM;
1158  }
1159 
1160  /* the spi->mode bits understood by this driver: */
1161  master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1162 
1163  master->setup = omap2_mcspi_setup;
1164  master->prepare_transfer_hardware = omap2_prepare_transfer;
1165  master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1166  master->transfer_one_message = omap2_mcspi_transfer_one_message;
1167  master->cleanup = omap2_mcspi_cleanup;
1168  master->dev.of_node = node;
1169 
1170  match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1171  if (match) {
1172  u32 num_cs = 1; /* default number of chipselect */
1173  pdata = match->data;
1174 
1175  of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1176  master->num_chipselect = num_cs;
1177  master->bus_num = bus_num++;
1178  } else {
1179  pdata = pdev->dev.platform_data;
1180  master->num_chipselect = pdata->num_cs;
1181  if (pdev->id != -1)
1182  master->bus_num = pdev->id;
1183  }
1184  regs_offset = pdata->regs_offset;
1185 
1186  dev_set_drvdata(&pdev->dev, master);
1187 
1188  mcspi = spi_master_get_devdata(master);
1189  mcspi->master = master;
1190 
1191  r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1192  if (r == NULL) {
1193  status = -ENODEV;
1194  goto free_master;
1195  }
1196 
1197  r->start += regs_offset;
1198  r->end += regs_offset;
1199  mcspi->phys = r->start;
1200 
1201  mcspi->base = devm_request_and_ioremap(&pdev->dev, r);
1202  if (!mcspi->base) {
1203  dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1204  status = -ENOMEM;
1205  goto free_master;
1206  }
1207 
1208  mcspi->dev = &pdev->dev;
1209 
1210  INIT_LIST_HEAD(&mcspi->ctx.cs);
1211 
1212  mcspi->dma_channels = kcalloc(master->num_chipselect,
1213  sizeof(struct omap2_mcspi_dma),
1214  GFP_KERNEL);
1215 
1216  if (mcspi->dma_channels == NULL)
1217  goto free_master;
1218 
1219  for (i = 0; i < master->num_chipselect; i++) {
1220  char dma_ch_name[14];
1221  struct resource *dma_res;
1222 
1223  sprintf(dma_ch_name, "rx%d", i);
1224  dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1225  dma_ch_name);
1226  if (!dma_res) {
1227  dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1228  status = -ENODEV;
1229  break;
1230  }
1231 
1232  mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1233  sprintf(dma_ch_name, "tx%d", i);
1234  dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1235  dma_ch_name);
1236  if (!dma_res) {
1237  dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1238  status = -ENODEV;
1239  break;
1240  }
1241 
1242  mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
1243  }
1244 
1245  if (status < 0)
1246  goto dma_chnl_free;
1247 
1248  pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1249  if (IS_ERR(pinctrl))
1250  dev_warn(&pdev->dev,
1251  "pins are not configured from the driver\n");
1252 
1253  pm_runtime_use_autosuspend(&pdev->dev);
1254  pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1255  pm_runtime_enable(&pdev->dev);
1256 
1257  if (status || omap2_mcspi_master_setup(mcspi) < 0)
1258  goto disable_pm;
1259 
1260  status = spi_register_master(master);
1261  if (status < 0)
1262  goto disable_pm;
1263 
1264  return status;
1265 
1266 disable_pm:
1267  pm_runtime_disable(&pdev->dev);
1268 dma_chnl_free:
1269  kfree(mcspi->dma_channels);
1270 free_master:
1271  spi_master_put(master);
1272  return status;
1273 }
1274 
1275 static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
1276 {
1277  struct spi_master *master;
1278  struct omap2_mcspi *mcspi;
1279  struct omap2_mcspi_dma *dma_channels;
1280 
1281  master = dev_get_drvdata(&pdev->dev);
1282  mcspi = spi_master_get_devdata(master);
1283  dma_channels = mcspi->dma_channels;
1284 
1285  pm_runtime_put_sync(mcspi->dev);
1286  pm_runtime_disable(&pdev->dev);
1287 
1288  spi_unregister_master(master);
1289  kfree(dma_channels);
1290 
1291  return 0;
1292 }
1293 
1294 /* work with hotplug and coldplug */
1295 MODULE_ALIAS("platform:omap2_mcspi");
1296 
1297 #ifdef CONFIG_SUSPEND
1298 /*
1299  * When SPI wake up from off-mode, CS is in activate state. If it was in
1300  * unactive state when driver was suspend, then force it to unactive state at
1301  * wake up.
1302  */
1303 static int omap2_mcspi_resume(struct device *dev)
1304 {
1305  struct spi_master *master = dev_get_drvdata(dev);
1306  struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1307  struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1308  struct omap2_mcspi_cs *cs;
1309 
1310  pm_runtime_get_sync(mcspi->dev);
1311  list_for_each_entry(cs, &ctx->cs, node) {
1312  if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1313  /*
1314  * We need to toggle CS state for OMAP take this
1315  * change in account.
1316  */
1317  cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1318  __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1319  cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1320  __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1321  }
1322  }
1323  pm_runtime_mark_last_busy(mcspi->dev);
1324  pm_runtime_put_autosuspend(mcspi->dev);
1325  return 0;
1326 }
1327 #else
1328 #define omap2_mcspi_resume NULL
1329 #endif
1330 
1331 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1332  .resume = omap2_mcspi_resume,
1333  .runtime_resume = omap_mcspi_runtime_resume,
1334 };
1335 
1336 static struct platform_driver omap2_mcspi_driver = {
1337  .driver = {
1338  .name = "omap2_mcspi",
1339  .owner = THIS_MODULE,
1340  .pm = &omap2_mcspi_pm_ops,
1341  .of_match_table = omap_mcspi_of_match,
1342  },
1343  .probe = omap2_mcspi_probe,
1344  .remove = __devexit_p(omap2_mcspi_remove),
1345 };
1346 
1347 module_platform_driver(omap2_mcspi_driver);
1348 MODULE_LICENSE("GPL");
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