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Data Structures | Macros
vme_tsi148.h File Reference

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Data Structures

struct  tsi148_driver
 
struct  tsi148_dma_descriptor
 
struct  tsi148_dma_entry
 

Macros

#define PCI_VENDOR_ID_TUNDRA   0x10e3
 
#define PCI_DEVICE_ID_TUNDRA_TSI148   0x148
 
#define TSI148_MAX_MASTER   8 /* Max Master Windows */
 
#define TSI148_MAX_SLAVE   8 /* Max Slave Windows */
 
#define TSI148_MAX_DMA   2 /* Max DMA Controllers */
 
#define TSI148_MAX_MAILBOX   4 /* Max Mail Box registers */
 
#define TSI148_MAX_SEMAPHORE   8 /* Max Semaphores */
 
#define TSI148_PCFS_ID   0x0
 
#define TSI148_PCFS_CSR   0x4
 
#define TSI148_PCFS_CLASS   0x8
 
#define TSI148_PCFS_MISC0   0xC
 
#define TSI148_PCFS_MBARL   0x10
 
#define TSI148_PCFS_MBARU   0x14
 
#define TSI148_PCFS_SUBID   0x28
 
#define TSI148_PCFS_CAPP   0x34
 
#define TSI148_PCFS_MISC1   0x3C
 
#define TSI148_PCFS_XCAPP   0x40
 
#define TSI148_PCFS_XSTAT   0x44
 
#define TSI148_LCSR_OT0_OTSAU   0x100
 
#define TSI148_LCSR_OT0_OTSAL   0x104
 
#define TSI148_LCSR_OT0_OTEAU   0x108
 
#define TSI148_LCSR_OT0_OTEAL   0x10C
 
#define TSI148_LCSR_OT0_OTOFU   0x110
 
#define TSI148_LCSR_OT0_OTOFL   0x114
 
#define TSI148_LCSR_OT0_OTBS   0x118
 
#define TSI148_LCSR_OT0_OTAT   0x11C
 
#define TSI148_LCSR_OT1_OTSAU   0x120
 
#define TSI148_LCSR_OT1_OTSAL   0x124
 
#define TSI148_LCSR_OT1_OTEAU   0x128
 
#define TSI148_LCSR_OT1_OTEAL   0x12C
 
#define TSI148_LCSR_OT1_OTOFU   0x130
 
#define TSI148_LCSR_OT1_OTOFL   0x134
 
#define TSI148_LCSR_OT1_OTBS   0x138
 
#define TSI148_LCSR_OT1_OTAT   0x13C
 
#define TSI148_LCSR_OT2_OTSAU   0x140
 
#define TSI148_LCSR_OT2_OTSAL   0x144
 
#define TSI148_LCSR_OT2_OTEAU   0x148
 
#define TSI148_LCSR_OT2_OTEAL   0x14C
 
#define TSI148_LCSR_OT2_OTOFU   0x150
 
#define TSI148_LCSR_OT2_OTOFL   0x154
 
#define TSI148_LCSR_OT2_OTBS   0x158
 
#define TSI148_LCSR_OT2_OTAT   0x15C
 
#define TSI148_LCSR_OT3_OTSAU   0x160
 
#define TSI148_LCSR_OT3_OTSAL   0x164
 
#define TSI148_LCSR_OT3_OTEAU   0x168
 
#define TSI148_LCSR_OT3_OTEAL   0x16C
 
#define TSI148_LCSR_OT3_OTOFU   0x170
 
#define TSI148_LCSR_OT3_OTOFL   0x174
 
#define TSI148_LCSR_OT3_OTBS   0x178
 
#define TSI148_LCSR_OT3_OTAT   0x17C
 
#define TSI148_LCSR_OT4_OTSAU   0x180
 
#define TSI148_LCSR_OT4_OTSAL   0x184
 
#define TSI148_LCSR_OT4_OTEAU   0x188
 
#define TSI148_LCSR_OT4_OTEAL   0x18C
 
#define TSI148_LCSR_OT4_OTOFU   0x190
 
#define TSI148_LCSR_OT4_OTOFL   0x194
 
#define TSI148_LCSR_OT4_OTBS   0x198
 
#define TSI148_LCSR_OT4_OTAT   0x19C
 
#define TSI148_LCSR_OT5_OTSAU   0x1A0
 
#define TSI148_LCSR_OT5_OTSAL   0x1A4
 
#define TSI148_LCSR_OT5_OTEAU   0x1A8
 
#define TSI148_LCSR_OT5_OTEAL   0x1AC
 
#define TSI148_LCSR_OT5_OTOFU   0x1B0
 
#define TSI148_LCSR_OT5_OTOFL   0x1B4
 
#define TSI148_LCSR_OT5_OTBS   0x1B8
 
#define TSI148_LCSR_OT5_OTAT   0x1BC
 
#define TSI148_LCSR_OT6_OTSAU   0x1C0
 
#define TSI148_LCSR_OT6_OTSAL   0x1C4
 
#define TSI148_LCSR_OT6_OTEAU   0x1C8
 
#define TSI148_LCSR_OT6_OTEAL   0x1CC
 
#define TSI148_LCSR_OT6_OTOFU   0x1D0
 
#define TSI148_LCSR_OT6_OTOFL   0x1D4
 
#define TSI148_LCSR_OT6_OTBS   0x1D8
 
#define TSI148_LCSR_OT6_OTAT   0x1DC
 
#define TSI148_LCSR_OT7_OTSAU   0x1E0
 
#define TSI148_LCSR_OT7_OTSAL   0x1E4
 
#define TSI148_LCSR_OT7_OTEAU   0x1E8
 
#define TSI148_LCSR_OT7_OTEAL   0x1EC
 
#define TSI148_LCSR_OT7_OTOFU   0x1F0
 
#define TSI148_LCSR_OT7_OTOFL   0x1F4
 
#define TSI148_LCSR_OT7_OTBS   0x1F8
 
#define TSI148_LCSR_OT7_OTAT   0x1FC
 
#define TSI148_LCSR_OT0   0x100
 
#define TSI148_LCSR_OT1   0x120
 
#define TSI148_LCSR_OT2   0x140
 
#define TSI148_LCSR_OT3   0x160
 
#define TSI148_LCSR_OT4   0x180
 
#define TSI148_LCSR_OT5   0x1A0
 
#define TSI148_LCSR_OT6   0x1C0
 
#define TSI148_LCSR_OT7   0x1E0
 
#define TSI148_LCSR_OFFSET_OTSAU   0x0
 
#define TSI148_LCSR_OFFSET_OTSAL   0x4
 
#define TSI148_LCSR_OFFSET_OTEAU   0x8
 
#define TSI148_LCSR_OFFSET_OTEAL   0xC
 
#define TSI148_LCSR_OFFSET_OTOFU   0x10
 
#define TSI148_LCSR_OFFSET_OTOFL   0x14
 
#define TSI148_LCSR_OFFSET_OTBS   0x18
 
#define TSI148_LCSR_OFFSET_OTAT   0x1C
 
#define TSI148_LCSR_VIACK1   0x204
 
#define TSI148_LCSR_VIACK2   0x208
 
#define TSI148_LCSR_VIACK3   0x20C
 
#define TSI148_LCSR_VIACK4   0x210
 
#define TSI148_LCSR_VIACK5   0x214
 
#define TSI148_LCSR_VIACK6   0x218
 
#define TSI148_LCSR_VIACK7   0x21C
 
#define TSI148_LCSR_RMWAU   0x220
 
#define TSI148_LCSR_RMWAL   0x224
 
#define TSI148_LCSR_RMWEN   0x228
 
#define TSI148_LCSR_RMWC   0x22C
 
#define TSI148_LCSR_RMWS   0x230
 
#define TSI148_LCSR_VMCTRL   0x234
 
#define TSI148_LCSR_VCTRL   0x238
 
#define TSI148_LCSR_VSTAT   0x23C
 
#define TSI148_LCSR_PSTAT   0x240
 
#define TSI148_LCSR_VMEFL   0x250
 
#define TSI148_LCSR_VEAU   0x260
 
#define TSI148_LCSR_VEAL   0x264
 
#define TSI148_LCSR_VEAT   0x268
 
#define TSI148_LCSR_EDPAU   0x270
 
#define TSI148_LCSR_EDPAL   0x274
 
#define TSI148_LCSR_EDPXA   0x278
 
#define TSI148_LCSR_EDPXS   0x27C
 
#define TSI148_LCSR_EDPAT   0x280
 
#define TSI148_LCSR_IT0_ITSAU   0x300
 
#define TSI148_LCSR_IT0_ITSAL   0x304
 
#define TSI148_LCSR_IT0_ITEAU   0x308
 
#define TSI148_LCSR_IT0_ITEAL   0x30C
 
#define TSI148_LCSR_IT0_ITOFU   0x310
 
#define TSI148_LCSR_IT0_ITOFL   0x314
 
#define TSI148_LCSR_IT0_ITAT   0x318
 
#define TSI148_LCSR_IT1_ITSAU   0x320
 
#define TSI148_LCSR_IT1_ITSAL   0x324
 
#define TSI148_LCSR_IT1_ITEAU   0x328
 
#define TSI148_LCSR_IT1_ITEAL   0x32C
 
#define TSI148_LCSR_IT1_ITOFU   0x330
 
#define TSI148_LCSR_IT1_ITOFL   0x334
 
#define TSI148_LCSR_IT1_ITAT   0x338
 
#define TSI148_LCSR_IT2_ITSAU   0x340
 
#define TSI148_LCSR_IT2_ITSAL   0x344
 
#define TSI148_LCSR_IT2_ITEAU   0x348
 
#define TSI148_LCSR_IT2_ITEAL   0x34C
 
#define TSI148_LCSR_IT2_ITOFU   0x350
 
#define TSI148_LCSR_IT2_ITOFL   0x354
 
#define TSI148_LCSR_IT2_ITAT   0x358
 
#define TSI148_LCSR_IT3_ITSAU   0x360
 
#define TSI148_LCSR_IT3_ITSAL   0x364
 
#define TSI148_LCSR_IT3_ITEAU   0x368
 
#define TSI148_LCSR_IT3_ITEAL   0x36C
 
#define TSI148_LCSR_IT3_ITOFU   0x370
 
#define TSI148_LCSR_IT3_ITOFL   0x374
 
#define TSI148_LCSR_IT3_ITAT   0x378
 
#define TSI148_LCSR_IT4_ITSAU   0x380
 
#define TSI148_LCSR_IT4_ITSAL   0x384
 
#define TSI148_LCSR_IT4_ITEAU   0x388
 
#define TSI148_LCSR_IT4_ITEAL   0x38C
 
#define TSI148_LCSR_IT4_ITOFU   0x390
 
#define TSI148_LCSR_IT4_ITOFL   0x394
 
#define TSI148_LCSR_IT4_ITAT   0x398
 
#define TSI148_LCSR_IT5_ITSAU   0x3A0
 
#define TSI148_LCSR_IT5_ITSAL   0x3A4
 
#define TSI148_LCSR_IT5_ITEAU   0x3A8
 
#define TSI148_LCSR_IT5_ITEAL   0x3AC
 
#define TSI148_LCSR_IT5_ITOFU   0x3B0
 
#define TSI148_LCSR_IT5_ITOFL   0x3B4
 
#define TSI148_LCSR_IT5_ITAT   0x3B8
 
#define TSI148_LCSR_IT6_ITSAU   0x3C0
 
#define TSI148_LCSR_IT6_ITSAL   0x3C4
 
#define TSI148_LCSR_IT6_ITEAU   0x3C8
 
#define TSI148_LCSR_IT6_ITEAL   0x3CC
 
#define TSI148_LCSR_IT6_ITOFU   0x3D0
 
#define TSI148_LCSR_IT6_ITOFL   0x3D4
 
#define TSI148_LCSR_IT6_ITAT   0x3D8
 
#define TSI148_LCSR_IT7_ITSAU   0x3E0
 
#define TSI148_LCSR_IT7_ITSAL   0x3E4
 
#define TSI148_LCSR_IT7_ITEAU   0x3E8
 
#define TSI148_LCSR_IT7_ITEAL   0x3EC
 
#define TSI148_LCSR_IT7_ITOFU   0x3F0
 
#define TSI148_LCSR_IT7_ITOFL   0x3F4
 
#define TSI148_LCSR_IT7_ITAT   0x3F8
 
#define TSI148_LCSR_IT0   0x300
 
#define TSI148_LCSR_IT1   0x320
 
#define TSI148_LCSR_IT2   0x340
 
#define TSI148_LCSR_IT3   0x360
 
#define TSI148_LCSR_IT4   0x380
 
#define TSI148_LCSR_IT5   0x3A0
 
#define TSI148_LCSR_IT6   0x3C0
 
#define TSI148_LCSR_IT7   0x3E0
 
#define TSI148_LCSR_OFFSET_ITSAU   0x0
 
#define TSI148_LCSR_OFFSET_ITSAL   0x4
 
#define TSI148_LCSR_OFFSET_ITEAU   0x8
 
#define TSI148_LCSR_OFFSET_ITEAL   0xC
 
#define TSI148_LCSR_OFFSET_ITOFU   0x10
 
#define TSI148_LCSR_OFFSET_ITOFL   0x14
 
#define TSI148_LCSR_OFFSET_ITAT   0x18
 
#define TSI148_LCSR_GBAU   0x400
 
#define TSI148_LCSR_GBAL   0x404
 
#define TSI148_LCSR_GCSRAT   0x408
 
#define TSI148_LCSR_CBAU   0x40C
 
#define TSI148_LCSR_CBAL   0x410
 
#define TSI148_LCSR_CSRAT   0x414
 
#define TSI148_LCSR_CROU   0x418
 
#define TSI148_LCSR_CROL   0x41C
 
#define TSI148_LCSR_CRAT   0x420
 
#define TSI148_LCSR_LMBAU   0x424
 
#define TSI148_LCSR_LMBAL   0x428
 
#define TSI148_LCSR_LMAT   0x42C
 
#define TSI148_LCSR_BCU   0x430
 
#define TSI148_LCSR_BCL   0x434
 
#define TSI148_LCSR_BPGTR   0x438
 
#define TSI148_LCSR_BPCTR   0x43C
 
#define TSI148_LCSR_VICR   0x440
 
#define TSI148_LCSR_INTEN   0x448
 
#define TSI148_LCSR_INTEO   0x44C
 
#define TSI148_LCSR_INTS   0x450
 
#define TSI148_LCSR_INTC   0x454
 
#define TSI148_LCSR_INTM1   0x458
 
#define TSI148_LCSR_INTM2   0x45C
 
#define TSI148_LCSR_DCTL0   0x500
 
#define TSI148_LCSR_DSTA0   0x504
 
#define TSI148_LCSR_DCSAU0   0x508
 
#define TSI148_LCSR_DCSAL0   0x50C
 
#define TSI148_LCSR_DCDAU0   0x510
 
#define TSI148_LCSR_DCDAL0   0x514
 
#define TSI148_LCSR_DCLAU0   0x518
 
#define TSI148_LCSR_DCLAL0   0x51C
 
#define TSI148_LCSR_DSAU0   0x520
 
#define TSI148_LCSR_DSAL0   0x524
 
#define TSI148_LCSR_DDAU0   0x528
 
#define TSI148_LCSR_DDAL0   0x52C
 
#define TSI148_LCSR_DSAT0   0x530
 
#define TSI148_LCSR_DDAT0   0x534
 
#define TSI148_LCSR_DNLAU0   0x538
 
#define TSI148_LCSR_DNLAL0   0x53C
 
#define TSI148_LCSR_DCNT0   0x540
 
#define TSI148_LCSR_DDBS0   0x544
 
#define TSI148_LCSR_DCTL1   0x580
 
#define TSI148_LCSR_DSTA1   0x584
 
#define TSI148_LCSR_DCSAU1   0x588
 
#define TSI148_LCSR_DCSAL1   0x58C
 
#define TSI148_LCSR_DCDAU1   0x590
 
#define TSI148_LCSR_DCDAL1   0x594
 
#define TSI148_LCSR_DCLAU1   0x598
 
#define TSI148_LCSR_DCLAL1   0x59C
 
#define TSI148_LCSR_DSAU1   0x5A0
 
#define TSI148_LCSR_DSAL1   0x5A4
 
#define TSI148_LCSR_DDAU1   0x5A8
 
#define TSI148_LCSR_DDAL1   0x5AC
 
#define TSI148_LCSR_DSAT1   0x5B0
 
#define TSI148_LCSR_DDAT1   0x5B4
 
#define TSI148_LCSR_DNLAU1   0x5B8
 
#define TSI148_LCSR_DNLAL1   0x5BC
 
#define TSI148_LCSR_DCNT1   0x5C0
 
#define TSI148_LCSR_DDBS1   0x5C4
 
#define TSI148_LCSR_DMA0   0x500
 
#define TSI148_LCSR_DMA1   0x580
 
#define TSI148_LCSR_OFFSET_DCTL   0x0
 
#define TSI148_LCSR_OFFSET_DSTA   0x4
 
#define TSI148_LCSR_OFFSET_DCSAU   0x8
 
#define TSI148_LCSR_OFFSET_DCSAL   0xC
 
#define TSI148_LCSR_OFFSET_DCDAU   0x10
 
#define TSI148_LCSR_OFFSET_DCDAL   0x14
 
#define TSI148_LCSR_OFFSET_DCLAU   0x18
 
#define TSI148_LCSR_OFFSET_DCLAL   0x1C
 
#define TSI148_LCSR_OFFSET_DSAU   0x20
 
#define TSI148_LCSR_OFFSET_DSAL   0x24
 
#define TSI148_LCSR_OFFSET_DDAU   0x28
 
#define TSI148_LCSR_OFFSET_DDAL   0x2C
 
#define TSI148_LCSR_OFFSET_DSAT   0x30
 
#define TSI148_LCSR_OFFSET_DDAT   0x34
 
#define TSI148_LCSR_OFFSET_DNLAU   0x38
 
#define TSI148_LCSR_OFFSET_DNLAL   0x3C
 
#define TSI148_LCSR_OFFSET_DCNT   0x40
 
#define TSI148_LCSR_OFFSET_DDBS   0x44
 
#define TSI148_GCSR_ID   0x600
 
#define TSI148_GCSR_CSR   0x604
 
#define TSI148_GCSR_SEMA0   0x608
 
#define TSI148_GCSR_SEMA1   0x60C
 
#define TSI148_GCSR_MBOX0   0x610
 
#define TSI148_GCSR_MBOX1   0x614
 
#define TSI148_GCSR_MBOX2   0x618
 
#define TSI148_GCSR_MBOX3   0x61C
 
#define TSI148_CSRBCR   0xFF4
 
#define TSI148_CSRBSR   0xFF8
 
#define TSI148_CBAR   0xFFC
 
#define TSI148_PCFS_CMMD_SERR   (1<<8) /* SERR_L out pin ssys err */
 
#define TSI148_PCFS_CMMD_PERR   (1<<6) /* PERR_L out pin parity */
 
#define TSI148_PCFS_CMMD_MSTR   (1<<2) /* PCI bus master */
 
#define TSI148_PCFS_CMMD_MEMSP   (1<<1) /* PCI mem space access */
 
#define TSI148_PCFS_CMMD_IOSP   (1<<0) /* PCI I/O space enable */
 
#define TSI148_PCFS_STAT_RCPVE   (1<<15) /* Detected Parity Error */
 
#define TSI148_PCFS_STAT_SIGSE   (1<<14) /* Signalled System Error */
 
#define TSI148_PCFS_STAT_RCVMA   (1<<13) /* Received Master Abort */
 
#define TSI148_PCFS_STAT_RCVTA   (1<<12) /* Received Target Abort */
 
#define TSI148_PCFS_STAT_SIGTA   (1<<11) /* Signalled Target Abort */
 
#define TSI148_PCFS_STAT_SELTIM   (3<<9) /* DELSEL Timing */
 
#define TSI148_PCFS_STAT_DPAR   (1<<8) /* Data Parity Err Reported */
 
#define TSI148_PCFS_STAT_FAST   (1<<7) /* Fast back-to-back Cap */
 
#define TSI148_PCFS_STAT_P66M   (1<<5) /* 66 MHz Capable */
 
#define TSI148_PCFS_STAT_CAPL   (1<<4) /* Capab List - address $34 */
 
#define TSI148_PCFS_CLAS_M   (0xFF<<24) /* Class ID */
 
#define TSI148_PCFS_SUBCLAS_M   (0xFF<<16) /* Sub-Class ID */
 
#define TSI148_PCFS_PROGIF_M   (0xFF<<8) /* Sub-Class ID */
 
#define TSI148_PCFS_REVID_M   (0xFF<<0) /* Rev ID */
 
#define TSI148_PCFS_HEAD_M   (0xFF<<16) /* Master Lat Timer */
 
#define TSI148_PCFS_MLAT_M   (0xFF<<8) /* Master Lat Timer */
 
#define TSI148_PCFS_CLSZ_M   (0xFF<<0) /* Cache Line Size */
 
#define TSI148_PCFS_MBARL_BASEL_M   (0xFFFFF<<12) /* Base Addr Lower Mask */
 
#define TSI148_PCFS_MBARL_PRE   (1<<3) /* Prefetch */
 
#define TSI148_PCFS_MBARL_MTYPE_M   (3<<1) /* Memory Type Mask */
 
#define TSI148_PCFS_MBARL_IOMEM   (1<<0) /* I/O Space Indicator */
 
#define TSI148_PCFS_MSICAP_64BAC   (1<<7) /* 64-bit Address Capable */
 
#define TSI148_PCFS_MSICAP_MME_M   (7<<4) /* Multiple Msg Enable Mask */
 
#define TSI148_PCFS_MSICAP_MMC_M   (7<<1) /* Multiple Msg Capable Mask */
 
#define TSI148_PCFS_MSICAP_MSIEN   (1<<0) /* Msg signaled INT Enable */
 
#define TSI148_PCFS_MSIAL_M   (0x3FFFFFFF<<2) /* Mask */
 
#define TSI148_PCFS_MSIMD_M   (0xFFFF<<0) /* Mask */
 
#define TSI148_PCFS_PCIXCAP_MOST_M   (7<<4) /* Max outstanding Split Tran */
 
#define TSI148_PCFS_PCIXCAP_MMRBC_M   (3<<2) /* Max Mem Read byte cnt */
 
#define TSI148_PCFS_PCIXCAP_ERO   (1<<1) /* Enable Relaxed Ordering */
 
#define TSI148_PCFS_PCIXCAP_DPERE   (1<<0) /* Data Parity Recover Enable */
 
#define TSI148_PCFS_PCIXSTAT_RSCEM   (1<<29) /* Received Split Comp Error */
 
#define TSI148_PCFS_PCIXSTAT_DMCRS_M   (7<<26) /* max Cumulative Read Size */
 
#define TSI148_PCFS_PCIXSTAT_DMOST_M
 
#define TSI148_PCFS_PCIXSTAT_DMMRC_M   (3<<21) /* max mem read byte count */
 
#define TSI148_PCFS_PCIXSTAT_DC   (1<<20) /* Device Complexity */
 
#define TSI148_PCFS_PCIXSTAT_USC   (1<<19) /* Unexpected Split comp */
 
#define TSI148_PCFS_PCIXSTAT_SCD   (1<<18) /* Split completion discard */
 
#define TSI148_PCFS_PCIXSTAT_133C   (1<<17) /* 133MHz capable */
 
#define TSI148_PCFS_PCIXSTAT_64D   (1<<16) /* 64 bit device */
 
#define TSI148_PCFS_PCIXSTAT_BN_M   (0xFF<<8) /* Bus number */
 
#define TSI148_PCFS_PCIXSTAT_DN_M   (0x1F<<3) /* Device number */
 
#define TSI148_PCFS_PCIXSTAT_FN_M   (7<<0) /* Function Number */
 
#define TSI148_LCSR_OTSAL_M   (0xFFFF<<16) /* Mask */
 
#define TSI148_LCSR_OTEAL_M   (0xFFFF<<16) /* Mask */
 
#define TSI148_LCSR_OTOFFL_M   (0xFFFF<<16) /* Mask */
 
#define TSI148_LCSR_OTBS_M   (0xFFFFF<<0) /* Mask */
 
#define TSI148_LCSR_OTAT_EN   (1<<31) /* Window Enable */
 
#define TSI148_LCSR_OTAT_MRPFD   (1<<18) /* Prefetch Disable */
 
#define TSI148_LCSR_OTAT_PFS_M   (3<<16) /* Prefetch Size Mask */
 
#define TSI148_LCSR_OTAT_PFS_2   (0<<16) /* 2 Cache Lines P Size */
 
#define TSI148_LCSR_OTAT_PFS_4   (1<<16) /* 4 Cache Lines P Size */
 
#define TSI148_LCSR_OTAT_PFS_8   (2<<16) /* 8 Cache Lines P Size */
 
#define TSI148_LCSR_OTAT_PFS_16   (3<<16) /* 16 Cache Lines P Size */
 
#define TSI148_LCSR_OTAT_2eSSTM_M   (7<<11) /* 2eSST Xfer Rate Mask */
 
#define TSI148_LCSR_OTAT_2eSSTM_160   (0<<11) /* 160MB/s 2eSST Xfer Rate */
 
#define TSI148_LCSR_OTAT_2eSSTM_267   (1<<11) /* 267MB/s 2eSST Xfer Rate */
 
#define TSI148_LCSR_OTAT_2eSSTM_320   (2<<11) /* 320MB/s 2eSST Xfer Rate */
 
#define TSI148_LCSR_OTAT_TM_M   (7<<8) /* Xfer Protocol Mask */
 
#define TSI148_LCSR_OTAT_TM_SCT   (0<<8) /* SCT Xfer Protocol */
 
#define TSI148_LCSR_OTAT_TM_BLT   (1<<8) /* BLT Xfer Protocol */
 
#define TSI148_LCSR_OTAT_TM_MBLT   (2<<8) /* MBLT Xfer Protocol */
 
#define TSI148_LCSR_OTAT_TM_2eVME   (3<<8) /* 2eVME Xfer Protocol */
 
#define TSI148_LCSR_OTAT_TM_2eSST   (4<<8) /* 2eSST Xfer Protocol */
 
#define TSI148_LCSR_OTAT_TM_2eSSTB   (5<<8) /* 2eSST Bcast Xfer Protocol */
 
#define TSI148_LCSR_OTAT_DBW_M   (3<<6) /* Max Data Width */
 
#define TSI148_LCSR_OTAT_DBW_16   (0<<6) /* 16-bit Data Width */
 
#define TSI148_LCSR_OTAT_DBW_32   (1<<6) /* 32-bit Data Width */
 
#define TSI148_LCSR_OTAT_SUP   (1<<5) /* Supervisory Access */
 
#define TSI148_LCSR_OTAT_PGM   (1<<4) /* Program Access */
 
#define TSI148_LCSR_OTAT_AMODE_M   (0xf<<0) /* Address Mode Mask */
 
#define TSI148_LCSR_OTAT_AMODE_A16   (0<<0) /* A16 Address Space */
 
#define TSI148_LCSR_OTAT_AMODE_A24   (1<<0) /* A24 Address Space */
 
#define TSI148_LCSR_OTAT_AMODE_A32   (2<<0) /* A32 Address Space */
 
#define TSI148_LCSR_OTAT_AMODE_A64   (4<<0) /* A32 Address Space */
 
#define TSI148_LCSR_OTAT_AMODE_CRCSR   (5<<0) /* CR/CSR Address Space */
 
#define TSI148_LCSR_OTAT_AMODE_USER1   (8<<0) /* User1 Address Space */
 
#define TSI148_LCSR_OTAT_AMODE_USER2   (9<<0) /* User2 Address Space */
 
#define TSI148_LCSR_OTAT_AMODE_USER3   (10<<0) /* User3 Address Space */
 
#define TSI148_LCSR_OTAT_AMODE_USER4   (11<<0) /* User4 Address Space */
 
#define TSI148_LCSR_VMCTRL_VSA   (1<<27) /* VMEbus Stop Ack */
 
#define TSI148_LCSR_VMCTRL_VS   (1<<26) /* VMEbus Stop */
 
#define TSI148_LCSR_VMCTRL_DHB   (1<<25) /* Device Has Bus */
 
#define TSI148_LCSR_VMCTRL_DWB   (1<<24) /* Device Wants Bus */
 
#define TSI148_LCSR_VMCTRL_RMWEN   (1<<20) /* RMW Enable */
 
#define TSI148_LCSR_VMCTRL_ATO_M
 
#define TSI148_LCSR_VMCTRL_ATO_32   (0<<16) /* 32 us */
 
#define TSI148_LCSR_VMCTRL_ATO_128   (1<<16) /* 128 us */
 
#define TSI148_LCSR_VMCTRL_ATO_512   (2<<16) /* 512 us */
 
#define TSI148_LCSR_VMCTRL_ATO_2M   (3<<16) /* 2 ms */
 
#define TSI148_LCSR_VMCTRL_ATO_8M   (4<<16) /* 8 ms */
 
#define TSI148_LCSR_VMCTRL_ATO_32M   (5<<16) /* 32 ms */
 
#define TSI148_LCSR_VMCTRL_ATO_128M   (6<<16) /* 128 ms */
 
#define TSI148_LCSR_VMCTRL_ATO_DIS   (7<<16) /* Disabled */
 
#define TSI148_LCSR_VMCTRL_VTOFF_M   (7<<12) /* VMEbus Master Time off */
 
#define TSI148_LCSR_VMCTRL_VTOFF_0   (0<<12) /* 0us */
 
#define TSI148_LCSR_VMCTRL_VTOFF_1   (1<<12) /* 1us */
 
#define TSI148_LCSR_VMCTRL_VTOFF_2   (2<<12) /* 2us */
 
#define TSI148_LCSR_VMCTRL_VTOFF_4   (3<<12) /* 4us */
 
#define TSI148_LCSR_VMCTRL_VTOFF_8   (4<<12) /* 8us */
 
#define TSI148_LCSR_VMCTRL_VTOFF_16   (5<<12) /* 16us */
 
#define TSI148_LCSR_VMCTRL_VTOFF_32   (6<<12) /* 32us */
 
#define TSI148_LCSR_VMCTRL_VTOFF_64   (7<<12) /* 64us */
 
#define TSI148_LCSR_VMCTRL_VTON_M   (7<<8) /* VMEbus Master Time On */
 
#define TSI148_LCSR_VMCTRL_VTON_4   (0<<8) /* 8us */
 
#define TSI148_LCSR_VMCTRL_VTON_8   (1<<8) /* 8us */
 
#define TSI148_LCSR_VMCTRL_VTON_16   (2<<8) /* 16us */
 
#define TSI148_LCSR_VMCTRL_VTON_32   (3<<8) /* 32us */
 
#define TSI148_LCSR_VMCTRL_VTON_64   (4<<8) /* 64us */
 
#define TSI148_LCSR_VMCTRL_VTON_128   (5<<8) /* 128us */
 
#define TSI148_LCSR_VMCTRL_VTON_256   (6<<8) /* 256us */
 
#define TSI148_LCSR_VMCTRL_VTON_512   (7<<8) /* 512us */
 
#define TSI148_LCSR_VMCTRL_VREL_M
 
#define TSI148_LCSR_VMCTRL_VREL_T_D   (0<<3) /* Time on or Done */
 
#define TSI148_LCSR_VMCTRL_VREL_T_R_D   (1<<3) /* Time on and REQ or Done */
 
#define TSI148_LCSR_VMCTRL_VREL_T_B_D   (2<<3) /* Time on and BCLR or Done */
 
#define TSI148_LCSR_VMCTRL_VREL_T_D_R   (3<<3) /* Time on or Done and REQ */
 
#define TSI148_LCSR_VMCTRL_VFAIR   (1<<2) /* VMEbus Master Fair Mode */
 
#define TSI148_LCSR_VMCTRL_VREQL_M
 
#define TSI148_LCSR_VCTRL_LRE   (1<<31) /* Late Retry Enable */
 
#define TSI148_LCSR_VCTRL_DLT_M   (0xF<<24) /* Deadlock Timer */
 
#define TSI148_LCSR_VCTRL_DLT_OFF   (0<<24) /* Deadlock Timer Off */
 
#define TSI148_LCSR_VCTRL_DLT_16   (1<<24) /* 16 VCLKS */
 
#define TSI148_LCSR_VCTRL_DLT_32   (2<<24) /* 32 VCLKS */
 
#define TSI148_LCSR_VCTRL_DLT_64   (3<<24) /* 64 VCLKS */
 
#define TSI148_LCSR_VCTRL_DLT_128   (4<<24) /* 128 VCLKS */
 
#define TSI148_LCSR_VCTRL_DLT_256   (5<<24) /* 256 VCLKS */
 
#define TSI148_LCSR_VCTRL_DLT_512   (6<<24) /* 512 VCLKS */
 
#define TSI148_LCSR_VCTRL_DLT_1024   (7<<24) /* 1024 VCLKS */
 
#define TSI148_LCSR_VCTRL_DLT_2048   (8<<24) /* 2048 VCLKS */
 
#define TSI148_LCSR_VCTRL_DLT_4096   (9<<24) /* 4096 VCLKS */
 
#define TSI148_LCSR_VCTRL_DLT_8192   (0xA<<24) /* 8192 VCLKS */
 
#define TSI148_LCSR_VCTRL_DLT_16384   (0xB<<24) /* 16384 VCLKS */
 
#define TSI148_LCSR_VCTRL_DLT_32768   (0xC<<24) /* 32768 VCLKS */
 
#define TSI148_LCSR_VCTRL_NERBB
 
#define TSI148_LCSR_VCTRL_SRESET   (1<<17) /* System Reset */
 
#define TSI148_LCSR_VCTRL_LRESET   (1<<16) /* Local Reset */
 
#define TSI148_LCSR_VCTRL_SFAILAI   (1<<15) /* SYSFAIL Auto Slot ID */
 
#define TSI148_LCSR_VCTRL_BID_M   (0x1F<<8) /* Broadcast ID Mask */
 
#define TSI148_LCSR_VCTRL_ATOEN   (1<<7) /* Arbiter Time-out Enable */
 
#define TSI148_LCSR_VCTRL_ROBIN   (1<<6) /* VMEbus Round Robin */
 
#define TSI148_LCSR_VCTRL_GTO_M
 
#define TSI148_LCSR_VCTRL_GTO_8   (0<<0) /* 8 us */
 
#define TSI148_LCSR_VCTRL_GTO_16   (1<<0) /* 16 us */
 
#define TSI148_LCSR_VCTRL_GTO_32   (2<<0) /* 32 us */
 
#define TSI148_LCSR_VCTRL_GTO_64   (3<<0) /* 64 us */
 
#define TSI148_LCSR_VCTRL_GTO_128   (4<<0) /* 128 us */
 
#define TSI148_LCSR_VCTRL_GTO_256   (5<<0) /* 256 us */
 
#define TSI148_LCSR_VCTRL_GTO_512   (6<<0) /* 512 us */
 
#define TSI148_LCSR_VCTRL_GTO_DIS   (7<<0) /* Disabled */
 
#define TSI148_LCSR_VSTAT_CPURST   (1<<15) /* Clear power up reset */
 
#define TSI148_LCSR_VSTAT_BRDFL   (1<<14) /* Board fail */
 
#define TSI148_LCSR_VSTAT_PURSTS   (1<<12) /* Power up reset status */
 
#define TSI148_LCSR_VSTAT_BDFAILS   (1<<11) /* Board Fail Status */
 
#define TSI148_LCSR_VSTAT_SYSFAILS   (1<<10) /* System Fail Status */
 
#define TSI148_LCSR_VSTAT_ACFAILS   (1<<9) /* AC fail status */
 
#define TSI148_LCSR_VSTAT_SCONS   (1<<8) /* System Cont Status */
 
#define TSI148_LCSR_VSTAT_GAP   (1<<5) /* Geographic Addr Parity */
 
#define TSI148_LCSR_VSTAT_GA_M   (0x1F<<0) /* Geographic Addr Mask */
 
#define TSI148_LCSR_PSTAT_REQ64S   (1<<6) /* Request 64 status set */
 
#define TSI148_LCSR_PSTAT_M66ENS   (1<<5) /* M66ENS 66Mhz enable */
 
#define TSI148_LCSR_PSTAT_FRAMES   (1<<4) /* Frame Status */
 
#define TSI148_LCSR_PSTAT_IRDYS   (1<<3) /* IRDY status */
 
#define TSI148_LCSR_PSTAT_DEVSELS   (1<<2) /* DEVL status */
 
#define TSI148_LCSR_PSTAT_STOPS   (1<<1) /* STOP status */
 
#define TSI148_LCSR_PSTAT_TRDYS   (1<<0) /* TRDY status */
 
#define TSI148_LCSR_VEAT_VES   (1<<31) /* Status */
 
#define TSI148_LCSR_VEAT_VEOF   (1<<30) /* Overflow */
 
#define TSI148_LCSR_VEAT_VESCL   (1<<29) /* Status Clear */
 
#define TSI148_LCSR_VEAT_2EOT   (1<<21) /* 2e Odd Termination */
 
#define TSI148_LCSR_VEAT_2EST   (1<<20) /* 2e Slave terminated */
 
#define TSI148_LCSR_VEAT_BERR   (1<<19) /* Bus Error */
 
#define TSI148_LCSR_VEAT_LWORD   (1<<18) /* LWORD_ signal state */
 
#define TSI148_LCSR_VEAT_WRITE   (1<<17) /* WRITE_ signal state */
 
#define TSI148_LCSR_VEAT_IACK   (1<<16) /* IACK_ signal state */
 
#define TSI148_LCSR_VEAT_DS1   (1<<15) /* DS1_ signal state */
 
#define TSI148_LCSR_VEAT_DS0   (1<<14) /* DS0_ signal state */
 
#define TSI148_LCSR_VEAT_AM_M   (0x3F<<8) /* Address Mode Mask */
 
#define TSI148_LCSR_VEAT_XAM_M   (0xFF<<0) /* Master AMode Mask */
 
#define TSI148_LCSR_EDPAT_EDPCL   (1<<29)
 
#define TSI148_LCSR_ITSAL6432_M   (0xFFFF<<16) /* Mask */
 
#define TSI148_LCSR_ITSAL24_M   (0x00FFF<<12) /* Mask */
 
#define TSI148_LCSR_ITSAL16_M   (0x0000FFF<<4) /* Mask */
 
#define TSI148_LCSR_ITEAL6432_M   (0xFFFF<<16) /* Mask */
 
#define TSI148_LCSR_ITEAL24_M   (0x00FFF<<12) /* Mask */
 
#define TSI148_LCSR_ITEAL16_M   (0x0000FFF<<4) /* Mask */
 
#define TSI148_LCSR_ITOFFL6432_M   (0xFFFF<<16) /* Mask */
 
#define TSI148_LCSR_ITOFFL24_M   (0xFFFFF<<12) /* Mask */
 
#define TSI148_LCSR_ITOFFL16_M   (0xFFFFFFF<<4) /* Mask */
 
#define TSI148_LCSR_ITAT_EN   (1<<31) /* Window Enable */
 
#define TSI148_LCSR_ITAT_TH   (1<<18) /* Prefetch Threshold */
 
#define TSI148_LCSR_ITAT_VFS_M   (3<<16) /* Virtual FIFO Size Mask */
 
#define TSI148_LCSR_ITAT_VFS_64   (0<<16) /* 64 bytes Virtual FIFO Size */
 
#define TSI148_LCSR_ITAT_VFS_128   (1<<16) /* 128 bytes Virtual FIFO Sz */
 
#define TSI148_LCSR_ITAT_VFS_256   (2<<16) /* 256 bytes Virtual FIFO Sz */
 
#define TSI148_LCSR_ITAT_VFS_512   (3<<16) /* 512 bytes Virtual FIFO Sz */
 
#define TSI148_LCSR_ITAT_2eSSTM_M   (7<<12) /* 2eSST Xfer Rate Mask */
 
#define TSI148_LCSR_ITAT_2eSSTM_160   (0<<12) /* 160MB/s 2eSST Xfer Rate */
 
#define TSI148_LCSR_ITAT_2eSSTM_267   (1<<12) /* 267MB/s 2eSST Xfer Rate */
 
#define TSI148_LCSR_ITAT_2eSSTM_320   (2<<12) /* 320MB/s 2eSST Xfer Rate */
 
#define TSI148_LCSR_ITAT_2eSSTB   (1<<11) /* 2eSST Bcast Xfer Protocol */
 
#define TSI148_LCSR_ITAT_2eSST   (1<<10) /* 2eSST Xfer Protocol */
 
#define TSI148_LCSR_ITAT_2eVME   (1<<9) /* 2eVME Xfer Protocol */
 
#define TSI148_LCSR_ITAT_MBLT   (1<<8) /* MBLT Xfer Protocol */
 
#define TSI148_LCSR_ITAT_BLT   (1<<7) /* BLT Xfer Protocol */
 
#define TSI148_LCSR_ITAT_AS_M   (7<<4) /* Address Space Mask */
 
#define TSI148_LCSR_ITAT_AS_A16   (0<<4) /* A16 Address Space */
 
#define TSI148_LCSR_ITAT_AS_A24   (1<<4) /* A24 Address Space */
 
#define TSI148_LCSR_ITAT_AS_A32   (2<<4) /* A32 Address Space */
 
#define TSI148_LCSR_ITAT_AS_A64   (4<<4) /* A64 Address Space */
 
#define TSI148_LCSR_ITAT_SUPR   (1<<3) /* Supervisor Access */
 
#define TSI148_LCSR_ITAT_NPRIV   (1<<2) /* Non-Priv (User) Access */
 
#define TSI148_LCSR_ITAT_PGM   (1<<1) /* Program Access */
 
#define TSI148_LCSR_ITAT_DATA   (1<<0) /* Data Access */
 
#define TSI148_LCSR_GBAL_M   (0x7FFFFFF<<5) /* Mask */
 
#define TSI148_LCSR_GCSRAT_EN   (1<<7) /* Enable access to GCSR */
 
#define TSI148_LCSR_GCSRAT_AS_M   (7<<4) /* Address Space Mask */
 
#define TSI148_LCSR_GCSRAT_AS_A16   (0<<4) /* Address Space 16 */
 
#define TSI148_LCSR_GCSRAT_AS_A24   (1<<4) /* Address Space 24 */
 
#define TSI148_LCSR_GCSRAT_AS_A32   (2<<4) /* Address Space 32 */
 
#define TSI148_LCSR_GCSRAT_AS_A64   (4<<4) /* Address Space 64 */
 
#define TSI148_LCSR_GCSRAT_SUPR   (1<<3) /* Sup set -GCSR decoder */
 
#define TSI148_LCSR_GCSRAT_NPRIV   (1<<2) /* Non-Privliged set - CGSR */
 
#define TSI148_LCSR_GCSRAT_PGM   (1<<1) /* Program set - GCSR decoder */
 
#define TSI148_LCSR_GCSRAT_DATA   (1<<0) /* DATA set GCSR decoder */
 
#define TSI148_LCSR_CBAL_M   (0xFFFFF<<12)
 
#define TSI148_LCSR_CRGAT_EN   (1<<7) /* Enable PRG Access */
 
#define TSI148_LCSR_CRGAT_AS_M   (7<<4) /* Address Space */
 
#define TSI148_LCSR_CRGAT_AS_A16   (0<<4) /* Address Space 16 */
 
#define TSI148_LCSR_CRGAT_AS_A24   (1<<4) /* Address Space 24 */
 
#define TSI148_LCSR_CRGAT_AS_A32   (2<<4) /* Address Space 32 */
 
#define TSI148_LCSR_CRGAT_AS_A64   (4<<4) /* Address Space 64 */
 
#define TSI148_LCSR_CRGAT_SUPR   (1<<3) /* Supervisor Access */
 
#define TSI148_LCSR_CRGAT_NPRIV   (1<<2) /* Non-Privliged(User) Access */
 
#define TSI148_LCSR_CRGAT_PGM   (1<<1) /* Program Access */
 
#define TSI148_LCSR_CRGAT_DATA   (1<<0) /* Data Access */
 
#define TSI148_LCSR_CROL_M   (0x1FFF<<19) /* Mask */
 
#define TSI148_LCSR_CRAT_EN   (1<<7) /* Enable access to CR/CSR */
 
#define TSI148_LCSR_LMBAL_M   (0x7FFFFFF<<5) /* Mask */
 
#define TSI148_LCSR_LMAT_EN   (1<<7) /* Enable Location Monitor */
 
#define TSI148_LCSR_LMAT_AS_M   (7<<4) /* Address Space MASK */
 
#define TSI148_LCSR_LMAT_AS_A16   (0<<4) /* A16 */
 
#define TSI148_LCSR_LMAT_AS_A24   (1<<4) /* A24 */
 
#define TSI148_LCSR_LMAT_AS_A32   (2<<4) /* A32 */
 
#define TSI148_LCSR_LMAT_AS_A64   (4<<4) /* A64 */
 
#define TSI148_LCSR_LMAT_SUPR   (1<<3) /* Supervisor Access */
 
#define TSI148_LCSR_LMAT_NPRIV   (1<<2) /* Non-Priv (User) Access */
 
#define TSI148_LCSR_LMAT_PGM   (1<<1) /* Program Access */
 
#define TSI148_LCSR_LMAT_DATA   (1<<0) /* Data Access */
 
#define TSI148_LCSR_BPGTR_BPGT_M   (0xFFFF<<0) /* Mask */
 
#define TSI148_LCSR_BPCTR_BPCT_M   (0xFFFFFF<<0) /* Mask */
 
#define TSI148_LCSR_VICR_CNTS_M   (3<<22) /* Cntr Source MASK */
 
#define TSI148_LCSR_VICR_CNTS_DIS   (1<<22) /* Cntr Disable */
 
#define TSI148_LCSR_VICR_CNTS_IRQ1   (2<<22) /* IRQ1 to Cntr */
 
#define TSI148_LCSR_VICR_CNTS_IRQ2   (3<<22) /* IRQ2 to Cntr */
 
#define TSI148_LCSR_VICR_EDGIS_M   (3<<20) /* Edge interrupt MASK */
 
#define TSI148_LCSR_VICR_EDGIS_DIS   (1<<20) /* Edge interrupt Disable */
 
#define TSI148_LCSR_VICR_EDGIS_IRQ1   (2<<20) /* IRQ1 to Edge */
 
#define TSI148_LCSR_VICR_EDGIS_IRQ2   (3<<20) /* IRQ2 to Edge */
 
#define TSI148_LCSR_VICR_IRQIF_M   (3<<18) /* IRQ1* Function MASK */
 
#define TSI148_LCSR_VICR_IRQIF_NORM   (1<<18) /* Normal */
 
#define TSI148_LCSR_VICR_IRQIF_PULSE   (2<<18) /* Pulse Generator */
 
#define TSI148_LCSR_VICR_IRQIF_PROG   (3<<18) /* Programmable Clock */
 
#define TSI148_LCSR_VICR_IRQIF_1U   (4<<18) /* 1us Clock */
 
#define TSI148_LCSR_VICR_IRQ2F_M   (3<<16) /* IRQ2* Function MASK */
 
#define TSI148_LCSR_VICR_IRQ2F_NORM   (1<<16) /* Normal */
 
#define TSI148_LCSR_VICR_IRQ2F_PULSE   (2<<16) /* Pulse Generator */
 
#define TSI148_LCSR_VICR_IRQ2F_PROG   (3<<16) /* Programmable Clock */
 
#define TSI148_LCSR_VICR_IRQ2F_1U   (4<<16) /* 1us Clock */
 
#define TSI148_LCSR_VICR_BIP   (1<<15) /* Broadcast Interrupt Pulse */
 
#define TSI148_LCSR_VICR_IRQC   (1<<12) /* VMEbus IRQ Clear */
 
#define TSI148_LCSR_VICR_IRQS   (1<<11) /* VMEbus IRQ Status */
 
#define TSI148_LCSR_VICR_IRQL_M   (7<<8) /* VMEbus SW IRQ Level Mask */
 
#define TSI148_LCSR_VICR_IRQL_1   (1<<8) /* VMEbus SW IRQ Level 1 */
 
#define TSI148_LCSR_VICR_IRQL_2   (2<<8) /* VMEbus SW IRQ Level 2 */
 
#define TSI148_LCSR_VICR_IRQL_3   (3<<8) /* VMEbus SW IRQ Level 3 */
 
#define TSI148_LCSR_VICR_IRQL_4   (4<<8) /* VMEbus SW IRQ Level 4 */
 
#define TSI148_LCSR_VICR_IRQL_5   (5<<8) /* VMEbus SW IRQ Level 5 */
 
#define TSI148_LCSR_VICR_IRQL_6   (6<<8) /* VMEbus SW IRQ Level 6 */
 
#define TSI148_LCSR_VICR_IRQL_7   (7<<8) /* VMEbus SW IRQ Level 7 */
 
#define TSI148_LCSR_VICR_STID_M   (0xFF<<0) /* Status/ID Mask */
 
#define TSI148_LCSR_INTEN_DMA1EN   (1<<25) /* DMAC 1 */
 
#define TSI148_LCSR_INTEN_DMA0EN   (1<<24) /* DMAC 0 */
 
#define TSI148_LCSR_INTEN_LM3EN   (1<<23) /* Location Monitor 3 */
 
#define TSI148_LCSR_INTEN_LM2EN   (1<<22) /* Location Monitor 2 */
 
#define TSI148_LCSR_INTEN_LM1EN   (1<<21) /* Location Monitor 1 */
 
#define TSI148_LCSR_INTEN_LM0EN   (1<<20) /* Location Monitor 0 */
 
#define TSI148_LCSR_INTEN_MB3EN   (1<<19) /* Mail Box 3 */
 
#define TSI148_LCSR_INTEN_MB2EN   (1<<18) /* Mail Box 2 */
 
#define TSI148_LCSR_INTEN_MB1EN   (1<<17) /* Mail Box 1 */
 
#define TSI148_LCSR_INTEN_MB0EN   (1<<16) /* Mail Box 0 */
 
#define TSI148_LCSR_INTEN_PERREN   (1<<13) /* PCI/X Error */
 
#define TSI148_LCSR_INTEN_VERREN   (1<<12) /* VMEbus Error */
 
#define TSI148_LCSR_INTEN_VIEEN   (1<<11) /* VMEbus IRQ Edge */
 
#define TSI148_LCSR_INTEN_IACKEN   (1<<10) /* IACK */
 
#define TSI148_LCSR_INTEN_SYSFLEN   (1<<9) /* System Fail */
 
#define TSI148_LCSR_INTEN_ACFLEN   (1<<8) /* AC Fail */
 
#define TSI148_LCSR_INTEN_IRQ7EN   (1<<7) /* IRQ7 */
 
#define TSI148_LCSR_INTEN_IRQ6EN   (1<<6) /* IRQ6 */
 
#define TSI148_LCSR_INTEN_IRQ5EN   (1<<5) /* IRQ5 */
 
#define TSI148_LCSR_INTEN_IRQ4EN   (1<<4) /* IRQ4 */
 
#define TSI148_LCSR_INTEN_IRQ3EN   (1<<3) /* IRQ3 */
 
#define TSI148_LCSR_INTEN_IRQ2EN   (1<<2) /* IRQ2 */
 
#define TSI148_LCSR_INTEN_IRQ1EN   (1<<1) /* IRQ1 */
 
#define TSI148_LCSR_INTEO_DMA1EO   (1<<25) /* DMAC 1 */
 
#define TSI148_LCSR_INTEO_DMA0EO   (1<<24) /* DMAC 0 */
 
#define TSI148_LCSR_INTEO_LM3EO   (1<<23) /* Loc Monitor 3 */
 
#define TSI148_LCSR_INTEO_LM2EO   (1<<22) /* Loc Monitor 2 */
 
#define TSI148_LCSR_INTEO_LM1EO   (1<<21) /* Loc Monitor 1 */
 
#define TSI148_LCSR_INTEO_LM0EO   (1<<20) /* Location Monitor 0 */
 
#define TSI148_LCSR_INTEO_MB3EO   (1<<19) /* Mail Box 3 */
 
#define TSI148_LCSR_INTEO_MB2EO   (1<<18) /* Mail Box 2 */
 
#define TSI148_LCSR_INTEO_MB1EO   (1<<17) /* Mail Box 1 */
 
#define TSI148_LCSR_INTEO_MB0EO   (1<<16) /* Mail Box 0 */
 
#define TSI148_LCSR_INTEO_PERREO   (1<<13) /* PCI/X Error */
 
#define TSI148_LCSR_INTEO_VERREO   (1<<12) /* VMEbus Error */
 
#define TSI148_LCSR_INTEO_VIEEO   (1<<11) /* VMEbus IRQ Edge */
 
#define TSI148_LCSR_INTEO_IACKEO   (1<<10) /* IACK */
 
#define TSI148_LCSR_INTEO_SYSFLEO   (1<<9) /* System Fail */
 
#define TSI148_LCSR_INTEO_ACFLEO   (1<<8) /* AC Fail */
 
#define TSI148_LCSR_INTEO_IRQ7EO   (1<<7) /* IRQ7 */
 
#define TSI148_LCSR_INTEO_IRQ6EO   (1<<6) /* IRQ6 */
 
#define TSI148_LCSR_INTEO_IRQ5EO   (1<<5) /* IRQ5 */
 
#define TSI148_LCSR_INTEO_IRQ4EO   (1<<4) /* IRQ4 */
 
#define TSI148_LCSR_INTEO_IRQ3EO   (1<<3) /* IRQ3 */
 
#define TSI148_LCSR_INTEO_IRQ2EO   (1<<2) /* IRQ2 */
 
#define TSI148_LCSR_INTEO_IRQ1EO   (1<<1) /* IRQ1 */
 
#define TSI148_LCSR_INTS_DMA1S   (1<<25) /* DMA 1 */
 
#define TSI148_LCSR_INTS_DMA0S   (1<<24) /* DMA 0 */
 
#define TSI148_LCSR_INTS_LM3S   (1<<23) /* Location Monitor 3 */
 
#define TSI148_LCSR_INTS_LM2S   (1<<22) /* Location Monitor 2 */
 
#define TSI148_LCSR_INTS_LM1S   (1<<21) /* Location Monitor 1 */
 
#define TSI148_LCSR_INTS_LM0S   (1<<20) /* Location Monitor 0 */
 
#define TSI148_LCSR_INTS_MB3S   (1<<19) /* Mail Box 3 */
 
#define TSI148_LCSR_INTS_MB2S   (1<<18) /* Mail Box 2 */
 
#define TSI148_LCSR_INTS_MB1S   (1<<17) /* Mail Box 1 */
 
#define TSI148_LCSR_INTS_MB0S   (1<<16) /* Mail Box 0 */
 
#define TSI148_LCSR_INTS_PERRS   (1<<13) /* PCI/X Error */
 
#define TSI148_LCSR_INTS_VERRS   (1<<12) /* VMEbus Error */
 
#define TSI148_LCSR_INTS_VIES   (1<<11) /* VMEbus IRQ Edge */
 
#define TSI148_LCSR_INTS_IACKS   (1<<10) /* IACK */
 
#define TSI148_LCSR_INTS_SYSFLS   (1<<9) /* System Fail */
 
#define TSI148_LCSR_INTS_ACFLS   (1<<8) /* AC Fail */
 
#define TSI148_LCSR_INTS_IRQ7S   (1<<7) /* IRQ7 */
 
#define TSI148_LCSR_INTS_IRQ6S   (1<<6) /* IRQ6 */
 
#define TSI148_LCSR_INTS_IRQ5S   (1<<5) /* IRQ5 */
 
#define TSI148_LCSR_INTS_IRQ4S   (1<<4) /* IRQ4 */
 
#define TSI148_LCSR_INTS_IRQ3S   (1<<3) /* IRQ3 */
 
#define TSI148_LCSR_INTS_IRQ2S   (1<<2) /* IRQ2 */
 
#define TSI148_LCSR_INTS_IRQ1S   (1<<1) /* IRQ1 */
 
#define TSI148_LCSR_INTC_DMA1C   (1<<25) /* DMA 1 */
 
#define TSI148_LCSR_INTC_DMA0C   (1<<24) /* DMA 0 */
 
#define TSI148_LCSR_INTC_LM3C   (1<<23) /* Location Monitor 3 */
 
#define TSI148_LCSR_INTC_LM2C   (1<<22) /* Location Monitor 2 */
 
#define TSI148_LCSR_INTC_LM1C   (1<<21) /* Location Monitor 1 */
 
#define TSI148_LCSR_INTC_LM0C   (1<<20) /* Location Monitor 0 */
 
#define TSI148_LCSR_INTC_MB3C   (1<<19) /* Mail Box 3 */
 
#define TSI148_LCSR_INTC_MB2C   (1<<18) /* Mail Box 2 */
 
#define TSI148_LCSR_INTC_MB1C   (1<<17) /* Mail Box 1 */
 
#define TSI148_LCSR_INTC_MB0C   (1<<16) /* Mail Box 0 */
 
#define TSI148_LCSR_INTC_PERRC   (1<<13) /* VMEbus Error */
 
#define TSI148_LCSR_INTC_VERRC   (1<<12) /* VMEbus Access Time-out */
 
#define TSI148_LCSR_INTC_VIEC   (1<<11) /* VMEbus IRQ Edge */
 
#define TSI148_LCSR_INTC_IACKC   (1<<10) /* IACK */
 
#define TSI148_LCSR_INTC_SYSFLC   (1<<9) /* System Fail */
 
#define TSI148_LCSR_INTC_ACFLC   (1<<8) /* AC Fail */
 
#define TSI148_LCSR_INTM1_DMA1M_M   (3<<18) /* DMA 1 */
 
#define TSI148_LCSR_INTM1_DMA0M_M   (3<<16) /* DMA 0 */
 
#define TSI148_LCSR_INTM1_LM3M_M   (3<<14) /* Location Monitor 3 */
 
#define TSI148_LCSR_INTM1_LM2M_M   (3<<12) /* Location Monitor 2 */
 
#define TSI148_LCSR_INTM1_LM1M_M   (3<<10) /* Location Monitor 1 */
 
#define TSI148_LCSR_INTM1_LM0M_M   (3<<8) /* Location Monitor 0 */
 
#define TSI148_LCSR_INTM1_MB3M_M   (3<<6) /* Mail Box 3 */
 
#define TSI148_LCSR_INTM1_MB2M_M   (3<<4) /* Mail Box 2 */
 
#define TSI148_LCSR_INTM1_MB1M_M   (3<<2) /* Mail Box 1 */
 
#define TSI148_LCSR_INTM1_MB0M_M   (3<<0) /* Mail Box 0 */
 
#define TSI148_LCSR_INTM2_PERRM_M   (3<<26) /* PCI Bus Error */
 
#define TSI148_LCSR_INTM2_VERRM_M   (3<<24) /* VMEbus Error */
 
#define TSI148_LCSR_INTM2_VIEM_M   (3<<22) /* VMEbus IRQ Edge */
 
#define TSI148_LCSR_INTM2_IACKM_M   (3<<20) /* IACK */
 
#define TSI148_LCSR_INTM2_SYSFLM_M   (3<<18) /* System Fail */
 
#define TSI148_LCSR_INTM2_ACFLM_M   (3<<16) /* AC Fail */
 
#define TSI148_LCSR_INTM2_IRQ7M_M   (3<<14) /* IRQ7 */
 
#define TSI148_LCSR_INTM2_IRQ6M_M   (3<<12) /* IRQ6 */
 
#define TSI148_LCSR_INTM2_IRQ5M_M   (3<<10) /* IRQ5 */
 
#define TSI148_LCSR_INTM2_IRQ4M_M   (3<<8) /* IRQ4 */
 
#define TSI148_LCSR_INTM2_IRQ3M_M   (3<<6) /* IRQ3 */
 
#define TSI148_LCSR_INTM2_IRQ2M_M   (3<<4) /* IRQ2 */
 
#define TSI148_LCSR_INTM2_IRQ1M_M   (3<<2) /* IRQ1 */
 
#define TSI148_LCSR_DCTL_ABT   (1<<27) /* Abort */
 
#define TSI148_LCSR_DCTL_PAU   (1<<26) /* Pause */
 
#define TSI148_LCSR_DCTL_DGO   (1<<25) /* DMA Go */
 
#define TSI148_LCSR_DCTL_MOD   (1<<23) /* Mode */
 
#define TSI148_LCSR_DCTL_VBKS_M   (7<<12) /* VMEbus block Size MASK */
 
#define TSI148_LCSR_DCTL_VBKS_32   (0<<12) /* VMEbus block Size 32 */
 
#define TSI148_LCSR_DCTL_VBKS_64   (1<<12) /* VMEbus block Size 64 */
 
#define TSI148_LCSR_DCTL_VBKS_128   (2<<12) /* VMEbus block Size 128 */
 
#define TSI148_LCSR_DCTL_VBKS_256   (3<<12) /* VMEbus block Size 256 */
 
#define TSI148_LCSR_DCTL_VBKS_512   (4<<12) /* VMEbus block Size 512 */
 
#define TSI148_LCSR_DCTL_VBKS_1024   (5<<12) /* VMEbus block Size 1024 */
 
#define TSI148_LCSR_DCTL_VBKS_2048   (6<<12) /* VMEbus block Size 2048 */
 
#define TSI148_LCSR_DCTL_VBKS_4096   (7<<12) /* VMEbus block Size 4096 */
 
#define TSI148_LCSR_DCTL_VBOT_M   (7<<8) /* VMEbus back-off MASK */
 
#define TSI148_LCSR_DCTL_VBOT_0   (0<<8) /* VMEbus back-off 0us */
 
#define TSI148_LCSR_DCTL_VBOT_1   (1<<8) /* VMEbus back-off 1us */
 
#define TSI148_LCSR_DCTL_VBOT_2   (2<<8) /* VMEbus back-off 2us */
 
#define TSI148_LCSR_DCTL_VBOT_4   (3<<8) /* VMEbus back-off 4us */
 
#define TSI148_LCSR_DCTL_VBOT_8   (4<<8) /* VMEbus back-off 8us */
 
#define TSI148_LCSR_DCTL_VBOT_16   (5<<8) /* VMEbus back-off 16us */
 
#define TSI148_LCSR_DCTL_VBOT_32   (6<<8) /* VMEbus back-off 32us */
 
#define TSI148_LCSR_DCTL_VBOT_64   (7<<8) /* VMEbus back-off 64us */
 
#define TSI148_LCSR_DCTL_PBKS_M   (7<<4) /* PCI block size MASK */
 
#define TSI148_LCSR_DCTL_PBKS_32   (0<<4) /* PCI block size 32 bytes */
 
#define TSI148_LCSR_DCTL_PBKS_64   (1<<4) /* PCI block size 64 bytes */
 
#define TSI148_LCSR_DCTL_PBKS_128   (2<<4) /* PCI block size 128 bytes */
 
#define TSI148_LCSR_DCTL_PBKS_256   (3<<4) /* PCI block size 256 bytes */
 
#define TSI148_LCSR_DCTL_PBKS_512   (4<<4) /* PCI block size 512 bytes */
 
#define TSI148_LCSR_DCTL_PBKS_1024   (5<<4) /* PCI block size 1024 bytes */
 
#define TSI148_LCSR_DCTL_PBKS_2048   (6<<4) /* PCI block size 2048 bytes */
 
#define TSI148_LCSR_DCTL_PBKS_4096   (7<<4) /* PCI block size 4096 bytes */
 
#define TSI148_LCSR_DCTL_PBOT_M   (7<<0) /* PCI back off MASK */
 
#define TSI148_LCSR_DCTL_PBOT_0   (0<<0) /* PCI back off 0us */
 
#define TSI148_LCSR_DCTL_PBOT_1   (1<<0) /* PCI back off 1us */
 
#define TSI148_LCSR_DCTL_PBOT_2   (2<<0) /* PCI back off 2us */
 
#define TSI148_LCSR_DCTL_PBOT_4   (3<<0) /* PCI back off 3us */
 
#define TSI148_LCSR_DCTL_PBOT_8   (4<<0) /* PCI back off 4us */
 
#define TSI148_LCSR_DCTL_PBOT_16   (5<<0) /* PCI back off 8us */
 
#define TSI148_LCSR_DCTL_PBOT_32   (6<<0) /* PCI back off 16us */
 
#define TSI148_LCSR_DCTL_PBOT_64   (7<<0) /* PCI back off 32us */
 
#define TSI148_LCSR_DSTA_SMA   (1<<31) /* PCI Signalled Master Abt */
 
#define TSI148_LCSR_DSTA_RTA   (1<<30) /* PCI Received Target Abt */
 
#define TSI148_LCSR_DSTA_MRC   (1<<29) /* PCI Max Retry Count */
 
#define TSI148_LCSR_DSTA_VBE   (1<<28) /* VMEbus error */
 
#define TSI148_LCSR_DSTA_ABT   (1<<27) /* Abort */
 
#define TSI148_LCSR_DSTA_PAU   (1<<26) /* Pause */
 
#define TSI148_LCSR_DSTA_DON   (1<<25) /* Done */
 
#define TSI148_LCSR_DSTA_BSY   (1<<24) /* Busy */
 
#define TSI148_LCSR_DCLAL_M   (0x3FFFFFF<<6) /* Mask */
 
#define TSI148_LCSR_DSAT_TYP_M   (3<<28) /* Source Bus Type */
 
#define TSI148_LCSR_DSAT_TYP_PCI   (0<<28) /* PCI Bus */
 
#define TSI148_LCSR_DSAT_TYP_VME   (1<<28) /* VMEbus */
 
#define TSI148_LCSR_DSAT_TYP_PAT   (2<<28) /* Data Pattern */
 
#define TSI148_LCSR_DSAT_PSZ   (1<<25) /* Pattern Size */
 
#define TSI148_LCSR_DSAT_NIN   (1<<24) /* No Increment */
 
#define TSI148_LCSR_DSAT_2eSSTM_M   (3<<11) /* 2eSST Trans Rate Mask */
 
#define TSI148_LCSR_DSAT_2eSSTM_160   (0<<11) /* 160 MB/s */
 
#define TSI148_LCSR_DSAT_2eSSTM_267   (1<<11) /* 267 MB/s */
 
#define TSI148_LCSR_DSAT_2eSSTM_320   (2<<11) /* 320 MB/s */
 
#define TSI148_LCSR_DSAT_TM_M   (7<<8) /* Bus Transfer Protocol Mask */
 
#define TSI148_LCSR_DSAT_TM_SCT   (0<<8) /* SCT */
 
#define TSI148_LCSR_DSAT_TM_BLT   (1<<8) /* BLT */
 
#define TSI148_LCSR_DSAT_TM_MBLT   (2<<8) /* MBLT */
 
#define TSI148_LCSR_DSAT_TM_2eVME   (3<<8) /* 2eVME */
 
#define TSI148_LCSR_DSAT_TM_2eSST   (4<<8) /* 2eSST */
 
#define TSI148_LCSR_DSAT_TM_2eSSTB   (5<<8) /* 2eSST Broadcast */
 
#define TSI148_LCSR_DSAT_DBW_M   (3<<6) /* Max Data Width MASK */
 
#define TSI148_LCSR_DSAT_DBW_16   (0<<6) /* 16 Bits */
 
#define TSI148_LCSR_DSAT_DBW_32   (1<<6) /* 32 Bits */
 
#define TSI148_LCSR_DSAT_SUP   (1<<5) /* Supervisory Mode */
 
#define TSI148_LCSR_DSAT_PGM   (1<<4) /* Program Mode */
 
#define TSI148_LCSR_DSAT_AMODE_M   (0xf<<0) /* Address Space Mask */
 
#define TSI148_LCSR_DSAT_AMODE_A16   (0<<0) /* A16 */
 
#define TSI148_LCSR_DSAT_AMODE_A24   (1<<0) /* A24 */
 
#define TSI148_LCSR_DSAT_AMODE_A32   (2<<0) /* A32 */
 
#define TSI148_LCSR_DSAT_AMODE_A64   (4<<0) /* A64 */
 
#define TSI148_LCSR_DSAT_AMODE_CRCSR   (5<<0) /* CR/CSR */
 
#define TSI148_LCSR_DSAT_AMODE_USER1   (8<<0) /* User1 */
 
#define TSI148_LCSR_DSAT_AMODE_USER2   (9<<0) /* User2 */
 
#define TSI148_LCSR_DSAT_AMODE_USER3   (0xa<<0) /* User3 */
 
#define TSI148_LCSR_DSAT_AMODE_USER4   (0xb<<0) /* User4 */
 
#define TSI148_LCSR_DDAT_TYP_PCI   (0<<28) /* Destination PCI Bus */
 
#define TSI148_LCSR_DDAT_TYP_VME   (1<<28) /* Destination VMEbus */
 
#define TSI148_LCSR_DDAT_2eSSTM_M   (3<<11) /* 2eSST Transfer Rate Mask */
 
#define TSI148_LCSR_DDAT_2eSSTM_160   (0<<11) /* 160 MB/s */
 
#define TSI148_LCSR_DDAT_2eSSTM_267   (1<<11) /* 267 MB/s */
 
#define TSI148_LCSR_DDAT_2eSSTM_320   (2<<11) /* 320 MB/s */
 
#define TSI148_LCSR_DDAT_TM_M   (7<<8) /* Bus Transfer Protocol Mask */
 
#define TSI148_LCSR_DDAT_TM_SCT   (0<<8) /* SCT */
 
#define TSI148_LCSR_DDAT_TM_BLT   (1<<8) /* BLT */
 
#define TSI148_LCSR_DDAT_TM_MBLT   (2<<8) /* MBLT */
 
#define TSI148_LCSR_DDAT_TM_2eVME   (3<<8) /* 2eVME */
 
#define TSI148_LCSR_DDAT_TM_2eSST   (4<<8) /* 2eSST */
 
#define TSI148_LCSR_DDAT_TM_2eSSTB   (5<<8) /* 2eSST Broadcast */
 
#define TSI148_LCSR_DDAT_DBW_M   (3<<6) /* Max Data Width MASK */
 
#define TSI148_LCSR_DDAT_DBW_16   (0<<6) /* 16 Bits */
 
#define TSI148_LCSR_DDAT_DBW_32   (1<<6) /* 32 Bits */
 
#define TSI148_LCSR_DDAT_SUP   (1<<5) /* Supervisory/User Access */
 
#define TSI148_LCSR_DDAT_PGM   (1<<4) /* Program/Data Access */
 
#define TSI148_LCSR_DDAT_AMODE_M   (0xf<<0) /* Address Space Mask */
 
#define TSI148_LCSR_DDAT_AMODE_A16   (0<<0) /* A16 */
 
#define TSI148_LCSR_DDAT_AMODE_A24   (1<<0) /* A24 */
 
#define TSI148_LCSR_DDAT_AMODE_A32   (2<<0) /* A32 */
 
#define TSI148_LCSR_DDAT_AMODE_A64   (4<<0) /* A64 */
 
#define TSI148_LCSR_DDAT_AMODE_CRCSR   (5<<0) /* CRC/SR */
 
#define TSI148_LCSR_DDAT_AMODE_USER1   (8<<0) /* User1 */
 
#define TSI148_LCSR_DDAT_AMODE_USER2   (9<<0) /* User2 */
 
#define TSI148_LCSR_DDAT_AMODE_USER3   (0xa<<0) /* User3 */
 
#define TSI148_LCSR_DDAT_AMODE_USER4   (0xb<<0) /* User4 */
 
#define TSI148_LCSR_DNLAL_DNLAL_M   (0x3FFFFFF<<6) /* Address Mask */
 
#define TSI148_LCSR_DNLAL_LLA   (1<<0) /* Last Link Address Indicator */
 
#define TSI148_LCSR_DBS_M   (0x1FFFFF<<0) /* Mask */
 
#define TSI148_GCSR_GCTRL_LRST   (1<<15) /* Local Reset */
 
#define TSI148_GCSR_GCTRL_SFAILEN   (1<<14) /* System Fail enable */
 
#define TSI148_GCSR_GCTRL_BDFAILS   (1<<13) /* Board Fail Status */
 
#define TSI148_GCSR_GCTRL_SCON   (1<<12) /* System Copntroller */
 
#define TSI148_GCSR_GCTRL_MEN   (1<<11) /* Module Enable (READY) */
 
#define TSI148_GCSR_GCTRL_LMI3S   (1<<7) /* Loc Monitor 3 Int Status */
 
#define TSI148_GCSR_GCTRL_LMI2S   (1<<6) /* Loc Monitor 2 Int Status */
 
#define TSI148_GCSR_GCTRL_LMI1S   (1<<5) /* Loc Monitor 1 Int Status */
 
#define TSI148_GCSR_GCTRL_LMI0S   (1<<4) /* Loc Monitor 0 Int Status */
 
#define TSI148_GCSR_GCTRL_MBI3S   (1<<3) /* Mail box 3 Int Status */
 
#define TSI148_GCSR_GCTRL_MBI2S   (1<<2) /* Mail box 2 Int Status */
 
#define TSI148_GCSR_GCTRL_MBI1S   (1<<1) /* Mail box 1 Int Status */
 
#define TSI148_GCSR_GCTRL_MBI0S   (1<<0) /* Mail box 0 Int Status */
 
#define TSI148_GCSR_GAP   (1<<5) /* Geographic Addr Parity */
 
#define TSI148_GCSR_GA_M   (0x1F<<0) /* Geographic Address Mask */
 
#define TSI148_CRCSR_CSRBCR_LRSTC   (1<<7) /* Local Reset Clear */
 
#define TSI148_CRCSR_CSRBCR_SFAILC   (1<<6) /* System Fail Enable Clear */
 
#define TSI148_CRCSR_CSRBCR_BDFAILS   (1<<5) /* Board Fail Status */
 
#define TSI148_CRCSR_CSRBCR_MENC   (1<<4) /* Module Enable Clear */
 
#define TSI148_CRCSR_CSRBCR_BERRSC   (1<<3) /* Bus Error Status Clear */
 
#define TSI148_CRCSR_CSRBSR_LISTS   (1<<7) /* Local Reset Clear */
 
#define TSI148_CRCSR_CSRBSR_SFAILS   (1<<6) /* System Fail Enable Clear */
 
#define TSI148_CRCSR_CSRBSR_BDFAILS   (1<<5) /* Board Fail Status */
 
#define TSI148_CRCSR_CSRBSR_MENS   (1<<4) /* Module Enable Clear */
 
#define TSI148_CRCSR_CSRBSR_BERRS   (1<<3) /* Bus Error Status Clear */
 
#define TSI148_CRCSR_CBAR_M   (0x1F<<3) /* Mask */
 

Macro Definition Documentation

#define PCI_DEVICE_ID_TUNDRA_TSI148   0x148

Definition at line 24 of file vme_tsi148.h.

#define PCI_VENDOR_ID_TUNDRA   0x10e3

Definition at line 20 of file vme_tsi148.h.

#define TSI148_CBAR   0xFFC

Definition at line 536 of file vme_tsi148.h.

#define TSI148_CRCSR_CBAR_M   (0x1F<<3) /* Mask */

Definition at line 1402 of file vme_tsi148.h.

#define TSI148_CRCSR_CSRBCR_BDFAILS   (1<<5) /* Board Fail Status */

Definition at line 1386 of file vme_tsi148.h.

#define TSI148_CRCSR_CSRBCR_BERRSC   (1<<3) /* Bus Error Status Clear */

Definition at line 1388 of file vme_tsi148.h.

#define TSI148_CRCSR_CSRBCR_LRSTC   (1<<7) /* Local Reset Clear */

Definition at line 1384 of file vme_tsi148.h.

#define TSI148_CRCSR_CSRBCR_MENC   (1<<4) /* Module Enable Clear */

Definition at line 1387 of file vme_tsi148.h.

#define TSI148_CRCSR_CSRBCR_SFAILC   (1<<6) /* System Fail Enable Clear */

Definition at line 1385 of file vme_tsi148.h.

#define TSI148_CRCSR_CSRBSR_BDFAILS   (1<<5) /* Board Fail Status */

Definition at line 1395 of file vme_tsi148.h.

#define TSI148_CRCSR_CSRBSR_BERRS   (1<<3) /* Bus Error Status Clear */

Definition at line 1397 of file vme_tsi148.h.

#define TSI148_CRCSR_CSRBSR_LISTS   (1<<7) /* Local Reset Clear */

Definition at line 1393 of file vme_tsi148.h.

#define TSI148_CRCSR_CSRBSR_MENS   (1<<4) /* Module Enable Clear */

Definition at line 1396 of file vme_tsi148.h.

#define TSI148_CRCSR_CSRBSR_SFAILS   (1<<6) /* System Fail Enable Clear */

Definition at line 1394 of file vme_tsi148.h.

#define TSI148_CSRBCR   0xFF4

Definition at line 534 of file vme_tsi148.h.

#define TSI148_CSRBSR   0xFF8

Definition at line 535 of file vme_tsi148.h.

#define TSI148_GCSR_CSR   0x604

Definition at line 505 of file vme_tsi148.h.

#define TSI148_GCSR_GA_M   (0x1F<<0) /* Geographic Address Mask */

Definition at line 1375 of file vme_tsi148.h.

#define TSI148_GCSR_GAP   (1<<5) /* Geographic Addr Parity */

Definition at line 1374 of file vme_tsi148.h.

#define TSI148_GCSR_GCTRL_BDFAILS   (1<<13) /* Board Fail Status */

Definition at line 1361 of file vme_tsi148.h.

#define TSI148_GCSR_GCTRL_LMI0S   (1<<4) /* Loc Monitor 0 Int Status */

Definition at line 1368 of file vme_tsi148.h.

#define TSI148_GCSR_GCTRL_LMI1S   (1<<5) /* Loc Monitor 1 Int Status */

Definition at line 1367 of file vme_tsi148.h.

#define TSI148_GCSR_GCTRL_LMI2S   (1<<6) /* Loc Monitor 2 Int Status */

Definition at line 1366 of file vme_tsi148.h.

#define TSI148_GCSR_GCTRL_LMI3S   (1<<7) /* Loc Monitor 3 Int Status */

Definition at line 1365 of file vme_tsi148.h.

#define TSI148_GCSR_GCTRL_LRST   (1<<15) /* Local Reset */

Definition at line 1359 of file vme_tsi148.h.

#define TSI148_GCSR_GCTRL_MBI0S   (1<<0) /* Mail box 0 Int Status */

Definition at line 1372 of file vme_tsi148.h.

#define TSI148_GCSR_GCTRL_MBI1S   (1<<1) /* Mail box 1 Int Status */

Definition at line 1371 of file vme_tsi148.h.

#define TSI148_GCSR_GCTRL_MBI2S   (1<<2) /* Mail box 2 Int Status */

Definition at line 1370 of file vme_tsi148.h.

#define TSI148_GCSR_GCTRL_MBI3S   (1<<3) /* Mail box 3 Int Status */

Definition at line 1369 of file vme_tsi148.h.

#define TSI148_GCSR_GCTRL_MEN   (1<<11) /* Module Enable (READY) */

Definition at line 1363 of file vme_tsi148.h.

#define TSI148_GCSR_GCTRL_SCON   (1<<12) /* System Copntroller */

Definition at line 1362 of file vme_tsi148.h.

#define TSI148_GCSR_GCTRL_SFAILEN   (1<<14) /* System Fail enable */

Definition at line 1360 of file vme_tsi148.h.

#define TSI148_GCSR_ID   0x600

Definition at line 504 of file vme_tsi148.h.

#define TSI148_GCSR_MBOX0   0x610

Definition at line 514 of file vme_tsi148.h.

#define TSI148_GCSR_MBOX1   0x614

Definition at line 515 of file vme_tsi148.h.

#define TSI148_GCSR_MBOX2   0x618

Definition at line 516 of file vme_tsi148.h.

#define TSI148_GCSR_MBOX3   0x61C

Definition at line 517 of file vme_tsi148.h.

#define TSI148_GCSR_SEMA0   0x608

Definition at line 506 of file vme_tsi148.h.

#define TSI148_GCSR_SEMA1   0x60C

Definition at line 507 of file vme_tsi148.h.

#define TSI148_LCSR_BCL   0x434

Definition at line 409 of file vme_tsi148.h.

#define TSI148_LCSR_BCU   0x430

Definition at line 408 of file vme_tsi148.h.

#define TSI148_LCSR_BPCTR   0x43C

Definition at line 411 of file vme_tsi148.h.

#define TSI148_LCSR_BPCTR_BPCT_M   (0xFFFFFF<<0) /* Mask */

Definition at line 970 of file vme_tsi148.h.

#define TSI148_LCSR_BPGTR   0x438

Definition at line 410 of file vme_tsi148.h.

#define TSI148_LCSR_BPGTR_BPGT_M   (0xFFFF<<0) /* Mask */

Definition at line 965 of file vme_tsi148.h.

#define TSI148_LCSR_CBAL   0x410

Definition at line 384 of file vme_tsi148.h.

#define TSI148_LCSR_CBAL_M   (0xFFFFF<<12)

Definition at line 913 of file vme_tsi148.h.

#define TSI148_LCSR_CBAU   0x40C

Definition at line 383 of file vme_tsi148.h.

#define TSI148_LCSR_CRAT   0x420

Definition at line 394 of file vme_tsi148.h.

#define TSI148_LCSR_CRAT_EN   (1<<7) /* Enable access to CR/CSR */

Definition at line 939 of file vme_tsi148.h.

#define TSI148_LCSR_CRGAT_AS_A16   (0<<4) /* Address Space 16 */

Definition at line 921 of file vme_tsi148.h.

#define TSI148_LCSR_CRGAT_AS_A24   (1<<4) /* Address Space 24 */

Definition at line 922 of file vme_tsi148.h.

#define TSI148_LCSR_CRGAT_AS_A32   (2<<4) /* Address Space 32 */

Definition at line 923 of file vme_tsi148.h.

#define TSI148_LCSR_CRGAT_AS_A64   (4<<4) /* Address Space 64 */

Definition at line 924 of file vme_tsi148.h.

#define TSI148_LCSR_CRGAT_AS_M   (7<<4) /* Address Space */

Definition at line 920 of file vme_tsi148.h.

#define TSI148_LCSR_CRGAT_DATA   (1<<0) /* Data Access */

Definition at line 929 of file vme_tsi148.h.

#define TSI148_LCSR_CRGAT_EN   (1<<7) /* Enable PRG Access */

Definition at line 918 of file vme_tsi148.h.

#define TSI148_LCSR_CRGAT_NPRIV   (1<<2) /* Non-Privliged(User) Access */

Definition at line 927 of file vme_tsi148.h.

#define TSI148_LCSR_CRGAT_PGM   (1<<1) /* Program Access */

Definition at line 928 of file vme_tsi148.h.

#define TSI148_LCSR_CRGAT_SUPR   (1<<3) /* Supervisor Access */

Definition at line 926 of file vme_tsi148.h.

#define TSI148_LCSR_CROL   0x41C

Definition at line 393 of file vme_tsi148.h.

#define TSI148_LCSR_CROL_M   (0x1FFF<<19) /* Mask */

Definition at line 934 of file vme_tsi148.h.

#define TSI148_LCSR_CROU   0x418

Definition at line 392 of file vme_tsi148.h.

#define TSI148_LCSR_CSRAT   0x414

Definition at line 385 of file vme_tsi148.h.

#define TSI148_LCSR_DBS_M   (0x1FFFFF<<0) /* Mask */

Definition at line 1350 of file vme_tsi148.h.

#define TSI148_LCSR_DCDAL0   0x514

Definition at line 434 of file vme_tsi148.h.

#define TSI148_LCSR_DCDAL1   0x594

Definition at line 453 of file vme_tsi148.h.

#define TSI148_LCSR_DCDAU0   0x510

Definition at line 433 of file vme_tsi148.h.

#define TSI148_LCSR_DCDAU1   0x590

Definition at line 452 of file vme_tsi148.h.

#define TSI148_LCSR_DCLAL0   0x51C

Definition at line 436 of file vme_tsi148.h.

#define TSI148_LCSR_DCLAL1   0x59C

Definition at line 455 of file vme_tsi148.h.

#define TSI148_LCSR_DCLAL_M   (0x3FFFFFF<<6) /* Mask */

Definition at line 1260 of file vme_tsi148.h.

#define TSI148_LCSR_DCLAU0   0x518

Definition at line 435 of file vme_tsi148.h.

#define TSI148_LCSR_DCLAU1   0x598

Definition at line 454 of file vme_tsi148.h.

#define TSI148_LCSR_DCNT0   0x540

Definition at line 445 of file vme_tsi148.h.

#define TSI148_LCSR_DCNT1   0x5C0

Definition at line 464 of file vme_tsi148.h.

#define TSI148_LCSR_DCSAL0   0x50C

Definition at line 432 of file vme_tsi148.h.

#define TSI148_LCSR_DCSAL1   0x58C

Definition at line 451 of file vme_tsi148.h.

#define TSI148_LCSR_DCSAU0   0x508

Definition at line 431 of file vme_tsi148.h.

#define TSI148_LCSR_DCSAU1   0x588

Definition at line 450 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL0   0x500

Definition at line 429 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL1   0x580

Definition at line 448 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_ABT   (1<<27) /* Abort */

Definition at line 1199 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_DGO   (1<<25) /* DMA Go */

Definition at line 1201 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_MOD   (1<<23) /* Mode */

Definition at line 1203 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PAU   (1<<26) /* Pause */

Definition at line 1200 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBKS_1024   (5<<4) /* PCI block size 1024 bytes */

Definition at line 1231 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBKS_128   (2<<4) /* PCI block size 128 bytes */

Definition at line 1228 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBKS_2048   (6<<4) /* PCI block size 2048 bytes */

Definition at line 1232 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBKS_256   (3<<4) /* PCI block size 256 bytes */

Definition at line 1229 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBKS_32   (0<<4) /* PCI block size 32 bytes */

Definition at line 1226 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBKS_4096   (7<<4) /* PCI block size 4096 bytes */

Definition at line 1233 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBKS_512   (4<<4) /* PCI block size 512 bytes */

Definition at line 1230 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBKS_64   (1<<4) /* PCI block size 64 bytes */

Definition at line 1227 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBKS_M   (7<<4) /* PCI block size MASK */

Definition at line 1225 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBOT_0   (0<<0) /* PCI back off 0us */

Definition at line 1236 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBOT_1   (1<<0) /* PCI back off 1us */

Definition at line 1237 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBOT_16   (5<<0) /* PCI back off 8us */

Definition at line 1241 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBOT_2   (2<<0) /* PCI back off 2us */

Definition at line 1238 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBOT_32   (6<<0) /* PCI back off 16us */

Definition at line 1242 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBOT_4   (3<<0) /* PCI back off 3us */

Definition at line 1239 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBOT_64   (7<<0) /* PCI back off 32us */

Definition at line 1243 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBOT_8   (4<<0) /* PCI back off 4us */

Definition at line 1240 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_PBOT_M   (7<<0) /* PCI back off MASK */

Definition at line 1235 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBKS_1024   (5<<12) /* VMEbus block Size 1024 */

Definition at line 1211 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBKS_128   (2<<12) /* VMEbus block Size 128 */

Definition at line 1208 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBKS_2048   (6<<12) /* VMEbus block Size 2048 */

Definition at line 1212 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBKS_256   (3<<12) /* VMEbus block Size 256 */

Definition at line 1209 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBKS_32   (0<<12) /* VMEbus block Size 32 */

Definition at line 1206 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBKS_4096   (7<<12) /* VMEbus block Size 4096 */

Definition at line 1213 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBKS_512   (4<<12) /* VMEbus block Size 512 */

Definition at line 1210 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBKS_64   (1<<12) /* VMEbus block Size 64 */

Definition at line 1207 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBKS_M   (7<<12) /* VMEbus block Size MASK */

Definition at line 1205 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBOT_0   (0<<8) /* VMEbus back-off 0us */

Definition at line 1216 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBOT_1   (1<<8) /* VMEbus back-off 1us */

Definition at line 1217 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBOT_16   (5<<8) /* VMEbus back-off 16us */

Definition at line 1221 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBOT_2   (2<<8) /* VMEbus back-off 2us */

Definition at line 1218 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBOT_32   (6<<8) /* VMEbus back-off 32us */

Definition at line 1222 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBOT_4   (3<<8) /* VMEbus back-off 4us */

Definition at line 1219 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBOT_64   (7<<8) /* VMEbus back-off 64us */

Definition at line 1223 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBOT_8   (4<<8) /* VMEbus back-off 8us */

Definition at line 1220 of file vme_tsi148.h.

#define TSI148_LCSR_DCTL_VBOT_M   (7<<8) /* VMEbus back-off MASK */

Definition at line 1215 of file vme_tsi148.h.

#define TSI148_LCSR_DDAL0   0x52C

Definition at line 440 of file vme_tsi148.h.

#define TSI148_LCSR_DDAL1   0x5AC

Definition at line 459 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT0   0x534

Definition at line 442 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT1   0x5B4

Definition at line 461 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_2eSSTM_160   (0<<11) /* 160 MB/s */

Definition at line 1311 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_2eSSTM_267   (1<<11) /* 267 MB/s */

Definition at line 1312 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_2eSSTM_320   (2<<11) /* 320 MB/s */

Definition at line 1313 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_2eSSTM_M   (3<<11) /* 2eSST Transfer Rate Mask */

Definition at line 1310 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_AMODE_A16   (0<<0) /* A16 */

Definition at line 1331 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_AMODE_A24   (1<<0) /* A24 */

Definition at line 1332 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_AMODE_A32   (2<<0) /* A32 */

Definition at line 1333 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_AMODE_A64   (4<<0) /* A64 */

Definition at line 1334 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_AMODE_CRCSR   (5<<0) /* CRC/SR */

Definition at line 1335 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_AMODE_M   (0xf<<0) /* Address Space Mask */

Definition at line 1330 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_AMODE_USER1   (8<<0) /* User1 */

Definition at line 1336 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_AMODE_USER2   (9<<0) /* User2 */

Definition at line 1337 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_AMODE_USER3   (0xa<<0) /* User3 */

Definition at line 1338 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_AMODE_USER4   (0xb<<0) /* User4 */

Definition at line 1339 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_DBW_16   (0<<6) /* 16 Bits */

Definition at line 1324 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_DBW_32   (1<<6) /* 32 Bits */

Definition at line 1325 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_DBW_M   (3<<6) /* Max Data Width MASK */

Definition at line 1323 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_PGM   (1<<4) /* Program/Data Access */

Definition at line 1328 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_SUP   (1<<5) /* Supervisory/User Access */

Definition at line 1327 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_TM_2eSST   (4<<8) /* 2eSST */

Definition at line 1320 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_TM_2eSSTB   (5<<8) /* 2eSST Broadcast */

Definition at line 1321 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_TM_2eVME   (3<<8) /* 2eVME */

Definition at line 1319 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_TM_BLT   (1<<8) /* BLT */

Definition at line 1317 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_TM_M   (7<<8) /* Bus Transfer Protocol Mask */

Definition at line 1315 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_TM_MBLT   (2<<8) /* MBLT */

Definition at line 1318 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_TM_SCT   (0<<8) /* SCT */

Definition at line 1316 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_TYP_PCI   (0<<28) /* Destination PCI Bus */

Definition at line 1307 of file vme_tsi148.h.

#define TSI148_LCSR_DDAT_TYP_VME   (1<<28) /* Destination VMEbus */

Definition at line 1308 of file vme_tsi148.h.

#define TSI148_LCSR_DDAU0   0x528

Definition at line 439 of file vme_tsi148.h.

#define TSI148_LCSR_DDAU1   0x5A8

Definition at line 458 of file vme_tsi148.h.

#define TSI148_LCSR_DDBS0   0x544

Definition at line 446 of file vme_tsi148.h.

#define TSI148_LCSR_DDBS1   0x5C4

Definition at line 465 of file vme_tsi148.h.

#define TSI148_LCSR_DMA0   0x500

Definition at line 467 of file vme_tsi148.h.

#define TSI148_LCSR_DMA1   0x580

Definition at line 468 of file vme_tsi148.h.

#define TSI148_LCSR_DNLAL0   0x53C

Definition at line 444 of file vme_tsi148.h.

#define TSI148_LCSR_DNLAL1   0x5BC

Definition at line 463 of file vme_tsi148.h.

#define TSI148_LCSR_DNLAL_DNLAL_M   (0x3FFFFFF<<6) /* Address Mask */

Definition at line 1344 of file vme_tsi148.h.

#define TSI148_LCSR_DNLAL_LLA   (1<<0) /* Last Link Address Indicator */

Definition at line 1345 of file vme_tsi148.h.

#define TSI148_LCSR_DNLAU0   0x538

Definition at line 443 of file vme_tsi148.h.

#define TSI148_LCSR_DNLAU1   0x5B8

Definition at line 462 of file vme_tsi148.h.

#define TSI148_LCSR_DSAL0   0x524

Definition at line 438 of file vme_tsi148.h.

#define TSI148_LCSR_DSAL1   0x5A4

Definition at line 457 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT0   0x530

Definition at line 441 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT1   0x5B0

Definition at line 460 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_2eSSTM_160   (0<<11) /* 160 MB/s */

Definition at line 1274 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_2eSSTM_267   (1<<11) /* 267 MB/s */

Definition at line 1275 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_2eSSTM_320   (2<<11) /* 320 MB/s */

Definition at line 1276 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_2eSSTM_M   (3<<11) /* 2eSST Trans Rate Mask */

Definition at line 1273 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_AMODE_A16   (0<<0) /* A16 */

Definition at line 1294 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_AMODE_A24   (1<<0) /* A24 */

Definition at line 1295 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_AMODE_A32   (2<<0) /* A32 */

Definition at line 1296 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_AMODE_A64   (4<<0) /* A64 */

Definition at line 1297 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_AMODE_CRCSR   (5<<0) /* CR/CSR */

Definition at line 1298 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_AMODE_M   (0xf<<0) /* Address Space Mask */

Definition at line 1293 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_AMODE_USER1   (8<<0) /* User1 */

Definition at line 1299 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_AMODE_USER2   (9<<0) /* User2 */

Definition at line 1300 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_AMODE_USER3   (0xa<<0) /* User3 */

Definition at line 1301 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_AMODE_USER4   (0xb<<0) /* User4 */

Definition at line 1302 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_DBW_16   (0<<6) /* 16 Bits */

Definition at line 1287 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_DBW_32   (1<<6) /* 32 Bits */

Definition at line 1288 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_DBW_M   (3<<6) /* Max Data Width MASK */

Definition at line 1286 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_NIN   (1<<24) /* No Increment */

Definition at line 1271 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_PGM   (1<<4) /* Program Mode */

Definition at line 1291 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_PSZ   (1<<25) /* Pattern Size */

Definition at line 1270 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_SUP   (1<<5) /* Supervisory Mode */

Definition at line 1290 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_TM_2eSST   (4<<8) /* 2eSST */

Definition at line 1283 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_TM_2eSSTB   (5<<8) /* 2eSST Broadcast */

Definition at line 1284 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_TM_2eVME   (3<<8) /* 2eVME */

Definition at line 1282 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_TM_BLT   (1<<8) /* BLT */

Definition at line 1280 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_TM_M   (7<<8) /* Bus Transfer Protocol Mask */

Definition at line 1278 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_TM_MBLT   (2<<8) /* MBLT */

Definition at line 1281 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_TM_SCT   (0<<8) /* SCT */

Definition at line 1279 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_TYP_M   (3<<28) /* Source Bus Type */

Definition at line 1265 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_TYP_PAT   (2<<28) /* Data Pattern */

Definition at line 1268 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_TYP_PCI   (0<<28) /* PCI Bus */

Definition at line 1266 of file vme_tsi148.h.

#define TSI148_LCSR_DSAT_TYP_VME   (1<<28) /* VMEbus */

Definition at line 1267 of file vme_tsi148.h.

#define TSI148_LCSR_DSAU0   0x520

Definition at line 437 of file vme_tsi148.h.

#define TSI148_LCSR_DSAU1   0x5A0

Definition at line 456 of file vme_tsi148.h.

#define TSI148_LCSR_DSTA0   0x504

Definition at line 430 of file vme_tsi148.h.

#define TSI148_LCSR_DSTA1   0x584

Definition at line 449 of file vme_tsi148.h.

#define TSI148_LCSR_DSTA_ABT   (1<<27) /* Abort */

Definition at line 1252 of file vme_tsi148.h.

#define TSI148_LCSR_DSTA_BSY   (1<<24) /* Busy */

Definition at line 1255 of file vme_tsi148.h.

#define TSI148_LCSR_DSTA_DON   (1<<25) /* Done */

Definition at line 1254 of file vme_tsi148.h.

#define TSI148_LCSR_DSTA_MRC   (1<<29) /* PCI Max Retry Count */

Definition at line 1250 of file vme_tsi148.h.

#define TSI148_LCSR_DSTA_PAU   (1<<26) /* Pause */

Definition at line 1253 of file vme_tsi148.h.

#define TSI148_LCSR_DSTA_RTA   (1<<30) /* PCI Received Target Abt */

Definition at line 1249 of file vme_tsi148.h.

#define TSI148_LCSR_DSTA_SMA   (1<<31) /* PCI Signalled Master Abt */

Definition at line 1248 of file vme_tsi148.h.

#define TSI148_LCSR_DSTA_VBE   (1<<28) /* VMEbus error */

Definition at line 1251 of file vme_tsi148.h.

#define TSI148_LCSR_EDPAL   0x274

Definition at line 275 of file vme_tsi148.h.

#define TSI148_LCSR_EDPAT   0x280

Definition at line 278 of file vme_tsi148.h.

#define TSI148_LCSR_EDPAT_EDPCL   (1<<29)

Definition at line 832 of file vme_tsi148.h.

#define TSI148_LCSR_EDPAU   0x270

Definition at line 274 of file vme_tsi148.h.

#define TSI148_LCSR_EDPXA   0x278

Definition at line 276 of file vme_tsi148.h.

#define TSI148_LCSR_EDPXS   0x27C

Definition at line 277 of file vme_tsi148.h.

#define TSI148_LCSR_GBAL   0x404

Definition at line 376 of file vme_tsi148.h.

#define TSI148_LCSR_GBAL_M   (0x7FFFFFF<<5) /* Mask */

Definition at line 892 of file vme_tsi148.h.

#define TSI148_LCSR_GBAU   0x400

Definition at line 375 of file vme_tsi148.h.

#define TSI148_LCSR_GCSRAT   0x408

Definition at line 377 of file vme_tsi148.h.

#define TSI148_LCSR_GCSRAT_AS_A16   (0<<4) /* Address Space 16 */

Definition at line 900 of file vme_tsi148.h.

#define TSI148_LCSR_GCSRAT_AS_A24   (1<<4) /* Address Space 24 */

Definition at line 901 of file vme_tsi148.h.

#define TSI148_LCSR_GCSRAT_AS_A32   (2<<4) /* Address Space 32 */

Definition at line 902 of file vme_tsi148.h.

#define TSI148_LCSR_GCSRAT_AS_A64   (4<<4) /* Address Space 64 */

Definition at line 903 of file vme_tsi148.h.

#define TSI148_LCSR_GCSRAT_AS_M   (7<<4) /* Address Space Mask */

Definition at line 899 of file vme_tsi148.h.

#define TSI148_LCSR_GCSRAT_DATA   (1<<0) /* DATA set GCSR decoder */

Definition at line 908 of file vme_tsi148.h.

#define TSI148_LCSR_GCSRAT_EN   (1<<7) /* Enable access to GCSR */

Definition at line 897 of file vme_tsi148.h.

#define TSI148_LCSR_GCSRAT_NPRIV   (1<<2) /* Non-Privliged set - CGSR */

Definition at line 906 of file vme_tsi148.h.

#define TSI148_LCSR_GCSRAT_PGM   (1<<1) /* Program set - GCSR decoder */

Definition at line 907 of file vme_tsi148.h.

#define TSI148_LCSR_GCSRAT_SUPR   (1<<3) /* Sup set -GCSR decoder */

Definition at line 905 of file vme_tsi148.h.

#define TSI148_LCSR_INTC   0x454

Definition at line 421 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_ACFLC   (1<<8) /* AC Fail */

Definition at line 1153 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_DMA0C   (1<<24) /* DMA 0 */

Definition at line 1139 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_DMA1C   (1<<25) /* DMA 1 */

Definition at line 1138 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_IACKC   (1<<10) /* IACK */

Definition at line 1151 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_LM0C   (1<<20) /* Location Monitor 0 */

Definition at line 1143 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_LM1C   (1<<21) /* Location Monitor 1 */

Definition at line 1142 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_LM2C   (1<<22) /* Location Monitor 2 */

Definition at line 1141 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_LM3C   (1<<23) /* Location Monitor 3 */

Definition at line 1140 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_MB0C   (1<<16) /* Mail Box 0 */

Definition at line 1147 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_MB1C   (1<<17) /* Mail Box 1 */

Definition at line 1146 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_MB2C   (1<<18) /* Mail Box 2 */

Definition at line 1145 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_MB3C   (1<<19) /* Mail Box 3 */

Definition at line 1144 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_PERRC   (1<<13) /* VMEbus Error */

Definition at line 1148 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_SYSFLC   (1<<9) /* System Fail */

Definition at line 1152 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_VERRC   (1<<12) /* VMEbus Access Time-out */

Definition at line 1149 of file vme_tsi148.h.

#define TSI148_LCSR_INTC_VIEC   (1<<11) /* VMEbus IRQ Edge */

Definition at line 1150 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN   0x448

Definition at line 418 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_ACFLEN   (1<<8) /* AC Fail */

Definition at line 1036 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_DMA0EN   (1<<24) /* DMAC 0 */

Definition at line 1022 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_DMA1EN   (1<<25) /* DMAC 1 */

Definition at line 1021 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_IACKEN   (1<<10) /* IACK */

Definition at line 1034 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_IRQ1EN   (1<<1) /* IRQ1 */

Definition at line 1043 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_IRQ2EN   (1<<2) /* IRQ2 */

Definition at line 1042 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_IRQ3EN   (1<<3) /* IRQ3 */

Definition at line 1041 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_IRQ4EN   (1<<4) /* IRQ4 */

Definition at line 1040 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_IRQ5EN   (1<<5) /* IRQ5 */

Definition at line 1039 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_IRQ6EN   (1<<6) /* IRQ6 */

Definition at line 1038 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_IRQ7EN   (1<<7) /* IRQ7 */

Definition at line 1037 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_LM0EN   (1<<20) /* Location Monitor 0 */

Definition at line 1026 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_LM1EN   (1<<21) /* Location Monitor 1 */

Definition at line 1025 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_LM2EN   (1<<22) /* Location Monitor 2 */

Definition at line 1024 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_LM3EN   (1<<23) /* Location Monitor 3 */

Definition at line 1023 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_MB0EN   (1<<16) /* Mail Box 0 */

Definition at line 1030 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_MB1EN   (1<<17) /* Mail Box 1 */

Definition at line 1029 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_MB2EN   (1<<18) /* Mail Box 2 */

Definition at line 1028 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_MB3EN   (1<<19) /* Mail Box 3 */

Definition at line 1027 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_PERREN   (1<<13) /* PCI/X Error */

Definition at line 1031 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_SYSFLEN   (1<<9) /* System Fail */

Definition at line 1035 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_VERREN   (1<<12) /* VMEbus Error */

Definition at line 1032 of file vme_tsi148.h.

#define TSI148_LCSR_INTEN_VIEEN   (1<<11) /* VMEbus IRQ Edge */

Definition at line 1033 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO   0x44C

Definition at line 419 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_ACFLEO   (1<<8) /* AC Fail */

Definition at line 1076 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_DMA0EO   (1<<24) /* DMAC 0 */

Definition at line 1062 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_DMA1EO   (1<<25) /* DMAC 1 */

Definition at line 1061 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_IACKEO   (1<<10) /* IACK */

Definition at line 1074 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_IRQ1EO   (1<<1) /* IRQ1 */

Definition at line 1083 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_IRQ2EO   (1<<2) /* IRQ2 */

Definition at line 1082 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_IRQ3EO   (1<<3) /* IRQ3 */

Definition at line 1081 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_IRQ4EO   (1<<4) /* IRQ4 */

Definition at line 1080 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_IRQ5EO   (1<<5) /* IRQ5 */

Definition at line 1079 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_IRQ6EO   (1<<6) /* IRQ6 */

Definition at line 1078 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_IRQ7EO   (1<<7) /* IRQ7 */

Definition at line 1077 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_LM0EO   (1<<20) /* Location Monitor 0 */

Definition at line 1066 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_LM1EO   (1<<21) /* Loc Monitor 1 */

Definition at line 1065 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_LM2EO   (1<<22) /* Loc Monitor 2 */

Definition at line 1064 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_LM3EO   (1<<23) /* Loc Monitor 3 */

Definition at line 1063 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_MB0EO   (1<<16) /* Mail Box 0 */

Definition at line 1070 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_MB1EO   (1<<17) /* Mail Box 1 */

Definition at line 1069 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_MB2EO   (1<<18) /* Mail Box 2 */

Definition at line 1068 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_MB3EO   (1<<19) /* Mail Box 3 */

Definition at line 1067 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_PERREO   (1<<13) /* PCI/X Error */

Definition at line 1071 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_SYSFLEO   (1<<9) /* System Fail */

Definition at line 1075 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_VERREO   (1<<12) /* VMEbus Error */

Definition at line 1072 of file vme_tsi148.h.

#define TSI148_LCSR_INTEO_VIEEO   (1<<11) /* VMEbus IRQ Edge */

Definition at line 1073 of file vme_tsi148.h.

#define TSI148_LCSR_INTM1   0x458

Definition at line 422 of file vme_tsi148.h.

#define TSI148_LCSR_INTM1_DMA0M_M   (3<<16) /* DMA 0 */

Definition at line 1169 of file vme_tsi148.h.

#define TSI148_LCSR_INTM1_DMA1M_M   (3<<18) /* DMA 1 */

Definition at line 1168 of file vme_tsi148.h.

#define TSI148_LCSR_INTM1_LM0M_M   (3<<8) /* Location Monitor 0 */

Definition at line 1173 of file vme_tsi148.h.

#define TSI148_LCSR_INTM1_LM1M_M   (3<<10) /* Location Monitor 1 */

Definition at line 1172 of file vme_tsi148.h.

#define TSI148_LCSR_INTM1_LM2M_M   (3<<12) /* Location Monitor 2 */

Definition at line 1171 of file vme_tsi148.h.

#define TSI148_LCSR_INTM1_LM3M_M   (3<<14) /* Location Monitor 3 */

Definition at line 1170 of file vme_tsi148.h.

#define TSI148_LCSR_INTM1_MB0M_M   (3<<0) /* Mail Box 0 */

Definition at line 1177 of file vme_tsi148.h.

#define TSI148_LCSR_INTM1_MB1M_M   (3<<2) /* Mail Box 1 */

Definition at line 1176 of file vme_tsi148.h.

#define TSI148_LCSR_INTM1_MB2M_M   (3<<4) /* Mail Box 2 */

Definition at line 1175 of file vme_tsi148.h.

#define TSI148_LCSR_INTM1_MB3M_M   (3<<6) /* Mail Box 3 */

Definition at line 1174 of file vme_tsi148.h.

#define TSI148_LCSR_INTM2   0x45C

Definition at line 423 of file vme_tsi148.h.

#define TSI148_LCSR_INTM2_ACFLM_M   (3<<16) /* AC Fail */

Definition at line 1187 of file vme_tsi148.h.

#define TSI148_LCSR_INTM2_IACKM_M   (3<<20) /* IACK */

Definition at line 1185 of file vme_tsi148.h.

#define TSI148_LCSR_INTM2_IRQ1M_M   (3<<2) /* IRQ1 */

Definition at line 1194 of file vme_tsi148.h.

#define TSI148_LCSR_INTM2_IRQ2M_M   (3<<4) /* IRQ2 */

Definition at line 1193 of file vme_tsi148.h.

#define TSI148_LCSR_INTM2_IRQ3M_M   (3<<6) /* IRQ3 */

Definition at line 1192 of file vme_tsi148.h.

#define TSI148_LCSR_INTM2_IRQ4M_M   (3<<8) /* IRQ4 */

Definition at line 1191 of file vme_tsi148.h.

#define TSI148_LCSR_INTM2_IRQ5M_M   (3<<10) /* IRQ5 */

Definition at line 1190 of file vme_tsi148.h.

#define TSI148_LCSR_INTM2_IRQ6M_M   (3<<12) /* IRQ6 */

Definition at line 1189 of file vme_tsi148.h.

#define TSI148_LCSR_INTM2_IRQ7M_M   (3<<14) /* IRQ7 */

Definition at line 1188 of file vme_tsi148.h.

#define TSI148_LCSR_INTM2_PERRM_M   (3<<26) /* PCI Bus Error */

Definition at line 1182 of file vme_tsi148.h.

#define TSI148_LCSR_INTM2_SYSFLM_M   (3<<18) /* System Fail */

Definition at line 1186 of file vme_tsi148.h.

#define TSI148_LCSR_INTM2_VERRM_M   (3<<24) /* VMEbus Error */

Definition at line 1183 of file vme_tsi148.h.

#define TSI148_LCSR_INTM2_VIEM_M   (3<<22) /* VMEbus IRQ Edge */

Definition at line 1184 of file vme_tsi148.h.

#define TSI148_LCSR_INTS   0x450

Definition at line 420 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_ACFLS   (1<<8) /* AC Fail */

Definition at line 1116 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_DMA0S   (1<<24) /* DMA 0 */

Definition at line 1102 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_DMA1S   (1<<25) /* DMA 1 */

Definition at line 1101 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_IACKS   (1<<10) /* IACK */

Definition at line 1114 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_IRQ1S   (1<<1) /* IRQ1 */

Definition at line 1123 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_IRQ2S   (1<<2) /* IRQ2 */

Definition at line 1122 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_IRQ3S   (1<<3) /* IRQ3 */

Definition at line 1121 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_IRQ4S   (1<<4) /* IRQ4 */

Definition at line 1120 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_IRQ5S   (1<<5) /* IRQ5 */

Definition at line 1119 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_IRQ6S   (1<<6) /* IRQ6 */

Definition at line 1118 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_IRQ7S   (1<<7) /* IRQ7 */

Definition at line 1117 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_LM0S   (1<<20) /* Location Monitor 0 */

Definition at line 1106 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_LM1S   (1<<21) /* Location Monitor 1 */

Definition at line 1105 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_LM2S   (1<<22) /* Location Monitor 2 */

Definition at line 1104 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_LM3S   (1<<23) /* Location Monitor 3 */

Definition at line 1103 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_MB0S   (1<<16) /* Mail Box 0 */

Definition at line 1110 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_MB1S   (1<<17) /* Mail Box 1 */

Definition at line 1109 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_MB2S   (1<<18) /* Mail Box 2 */

Definition at line 1108 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_MB3S   (1<<19) /* Mail Box 3 */

Definition at line 1107 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_PERRS   (1<<13) /* PCI/X Error */

Definition at line 1111 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_SYSFLS   (1<<9) /* System Fail */

Definition at line 1115 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_VERRS   (1<<12) /* VMEbus Error */

Definition at line 1112 of file vme_tsi148.h.

#define TSI148_LCSR_INTS_VIES   (1<<11) /* VMEbus IRQ Edge */

Definition at line 1113 of file vme_tsi148.h.

#define TSI148_LCSR_IT0   0x300

Definition at line 349 of file vme_tsi148.h.

#define TSI148_LCSR_IT0_ITAT   0x318

Definition at line 290 of file vme_tsi148.h.

#define TSI148_LCSR_IT0_ITEAL   0x30C

Definition at line 287 of file vme_tsi148.h.

#define TSI148_LCSR_IT0_ITEAU   0x308

Definition at line 286 of file vme_tsi148.h.

#define TSI148_LCSR_IT0_ITOFL   0x314

Definition at line 289 of file vme_tsi148.h.

#define TSI148_LCSR_IT0_ITOFU   0x310

Definition at line 288 of file vme_tsi148.h.

#define TSI148_LCSR_IT0_ITSAL   0x304

Definition at line 285 of file vme_tsi148.h.

#define TSI148_LCSR_IT0_ITSAU   0x300

Definition at line 284 of file vme_tsi148.h.

#define TSI148_LCSR_IT1   0x320

Definition at line 350 of file vme_tsi148.h.

#define TSI148_LCSR_IT1_ITAT   0x338

Definition at line 298 of file vme_tsi148.h.

#define TSI148_LCSR_IT1_ITEAL   0x32C

Definition at line 295 of file vme_tsi148.h.

#define TSI148_LCSR_IT1_ITEAU   0x328

Definition at line 294 of file vme_tsi148.h.

#define TSI148_LCSR_IT1_ITOFL   0x334

Definition at line 297 of file vme_tsi148.h.

#define TSI148_LCSR_IT1_ITOFU   0x330

Definition at line 296 of file vme_tsi148.h.

#define TSI148_LCSR_IT1_ITSAL   0x324

Definition at line 293 of file vme_tsi148.h.

#define TSI148_LCSR_IT1_ITSAU   0x320

Definition at line 292 of file vme_tsi148.h.

#define TSI148_LCSR_IT2   0x340

Definition at line 351 of file vme_tsi148.h.

#define TSI148_LCSR_IT2_ITAT   0x358

Definition at line 306 of file vme_tsi148.h.

#define TSI148_LCSR_IT2_ITEAL   0x34C

Definition at line 303 of file vme_tsi148.h.

#define TSI148_LCSR_IT2_ITEAU   0x348

Definition at line 302 of file vme_tsi148.h.

#define TSI148_LCSR_IT2_ITOFL   0x354

Definition at line 305 of file vme_tsi148.h.

#define TSI148_LCSR_IT2_ITOFU   0x350

Definition at line 304 of file vme_tsi148.h.

#define TSI148_LCSR_IT2_ITSAL   0x344

Definition at line 301 of file vme_tsi148.h.

#define TSI148_LCSR_IT2_ITSAU   0x340

Definition at line 300 of file vme_tsi148.h.

#define TSI148_LCSR_IT3   0x360

Definition at line 352 of file vme_tsi148.h.

#define TSI148_LCSR_IT3_ITAT   0x378

Definition at line 314 of file vme_tsi148.h.

#define TSI148_LCSR_IT3_ITEAL   0x36C

Definition at line 311 of file vme_tsi148.h.

#define TSI148_LCSR_IT3_ITEAU   0x368

Definition at line 310 of file vme_tsi148.h.

#define TSI148_LCSR_IT3_ITOFL   0x374

Definition at line 313 of file vme_tsi148.h.

#define TSI148_LCSR_IT3_ITOFU   0x370

Definition at line 312 of file vme_tsi148.h.

#define TSI148_LCSR_IT3_ITSAL   0x364

Definition at line 309 of file vme_tsi148.h.

#define TSI148_LCSR_IT3_ITSAU   0x360

Definition at line 308 of file vme_tsi148.h.

#define TSI148_LCSR_IT4   0x380

Definition at line 353 of file vme_tsi148.h.

#define TSI148_LCSR_IT4_ITAT   0x398

Definition at line 322 of file vme_tsi148.h.

#define TSI148_LCSR_IT4_ITEAL   0x38C

Definition at line 319 of file vme_tsi148.h.

#define TSI148_LCSR_IT4_ITEAU   0x388

Definition at line 318 of file vme_tsi148.h.

#define TSI148_LCSR_IT4_ITOFL   0x394

Definition at line 321 of file vme_tsi148.h.

#define TSI148_LCSR_IT4_ITOFU   0x390

Definition at line 320 of file vme_tsi148.h.

#define TSI148_LCSR_IT4_ITSAL   0x384

Definition at line 317 of file vme_tsi148.h.

#define TSI148_LCSR_IT4_ITSAU   0x380

Definition at line 316 of file vme_tsi148.h.

#define TSI148_LCSR_IT5   0x3A0

Definition at line 354 of file vme_tsi148.h.

#define TSI148_LCSR_IT5_ITAT   0x3B8

Definition at line 330 of file vme_tsi148.h.

#define TSI148_LCSR_IT5_ITEAL   0x3AC

Definition at line 327 of file vme_tsi148.h.

#define TSI148_LCSR_IT5_ITEAU   0x3A8

Definition at line 326 of file vme_tsi148.h.

#define TSI148_LCSR_IT5_ITOFL   0x3B4

Definition at line 329 of file vme_tsi148.h.

#define TSI148_LCSR_IT5_ITOFU   0x3B0

Definition at line 328 of file vme_tsi148.h.

#define TSI148_LCSR_IT5_ITSAL   0x3A4

Definition at line 325 of file vme_tsi148.h.

#define TSI148_LCSR_IT5_ITSAU   0x3A0

Definition at line 324 of file vme_tsi148.h.

#define TSI148_LCSR_IT6   0x3C0

Definition at line 355 of file vme_tsi148.h.

#define TSI148_LCSR_IT6_ITAT   0x3D8

Definition at line 338 of file vme_tsi148.h.

#define TSI148_LCSR_IT6_ITEAL   0x3CC

Definition at line 335 of file vme_tsi148.h.

#define TSI148_LCSR_IT6_ITEAU   0x3C8

Definition at line 334 of file vme_tsi148.h.

#define TSI148_LCSR_IT6_ITOFL   0x3D4

Definition at line 337 of file vme_tsi148.h.

#define TSI148_LCSR_IT6_ITOFU   0x3D0

Definition at line 336 of file vme_tsi148.h.

#define TSI148_LCSR_IT6_ITSAL   0x3C4

Definition at line 333 of file vme_tsi148.h.

#define TSI148_LCSR_IT6_ITSAU   0x3C0

Definition at line 332 of file vme_tsi148.h.

#define TSI148_LCSR_IT7   0x3E0

Definition at line 356 of file vme_tsi148.h.

#define TSI148_LCSR_IT7_ITAT   0x3F8

Definition at line 346 of file vme_tsi148.h.

#define TSI148_LCSR_IT7_ITEAL   0x3EC

Definition at line 343 of file vme_tsi148.h.

#define TSI148_LCSR_IT7_ITEAU   0x3E8

Definition at line 342 of file vme_tsi148.h.

#define TSI148_LCSR_IT7_ITOFL   0x3F4

Definition at line 345 of file vme_tsi148.h.

#define TSI148_LCSR_IT7_ITOFU   0x3F0

Definition at line 344 of file vme_tsi148.h.

#define TSI148_LCSR_IT7_ITSAL   0x3E4

Definition at line 341 of file vme_tsi148.h.

#define TSI148_LCSR_IT7_ITSAU   0x3E0

Definition at line 340 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_2eSST   (1<<10) /* 2eSST Xfer Protocol */

Definition at line 873 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_2eSSTB   (1<<11) /* 2eSST Bcast Xfer Protocol */

Definition at line 872 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_2eSSTM_160   (0<<12) /* 160MB/s 2eSST Xfer Rate */

Definition at line 868 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_2eSSTM_267   (1<<12) /* 267MB/s 2eSST Xfer Rate */

Definition at line 869 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_2eSSTM_320   (2<<12) /* 320MB/s 2eSST Xfer Rate */

Definition at line 870 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_2eSSTM_M   (7<<12) /* 2eSST Xfer Rate Mask */

Definition at line 867 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_2eVME   (1<<9) /* 2eVME Xfer Protocol */

Definition at line 874 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_AS_A16   (0<<4) /* A16 Address Space */

Definition at line 879 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_AS_A24   (1<<4) /* A24 Address Space */

Definition at line 880 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_AS_A32   (2<<4) /* A32 Address Space */

Definition at line 881 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_AS_A64   (4<<4) /* A64 Address Space */

Definition at line 882 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_AS_M   (7<<4) /* Address Space Mask */

Definition at line 878 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_BLT   (1<<7) /* BLT Xfer Protocol */

Definition at line 876 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_DATA   (1<<0) /* Data Access */

Definition at line 887 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_EN   (1<<31) /* Window Enable */

Definition at line 858 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_MBLT   (1<<8) /* MBLT Xfer Protocol */

Definition at line 875 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_NPRIV   (1<<2) /* Non-Priv (User) Access */

Definition at line 885 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_PGM   (1<<1) /* Program Access */

Definition at line 886 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_SUPR   (1<<3) /* Supervisor Access */

Definition at line 884 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_TH   (1<<18) /* Prefetch Threshold */

Definition at line 859 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_VFS_128   (1<<16) /* 128 bytes Virtual FIFO Sz */

Definition at line 863 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_VFS_256   (2<<16) /* 256 bytes Virtual FIFO Sz */

Definition at line 864 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_VFS_512   (3<<16) /* 512 bytes Virtual FIFO Sz */

Definition at line 865 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_VFS_64   (0<<16) /* 64 bytes Virtual FIFO Size */

Definition at line 862 of file vme_tsi148.h.

#define TSI148_LCSR_ITAT_VFS_M   (3<<16) /* Virtual FIFO Size Mask */

Definition at line 861 of file vme_tsi148.h.

#define TSI148_LCSR_ITEAL16_M   (0x0000FFF<<4) /* Mask */

Definition at line 846 of file vme_tsi148.h.

#define TSI148_LCSR_ITEAL24_M   (0x00FFF<<12) /* Mask */

Definition at line 845 of file vme_tsi148.h.

#define TSI148_LCSR_ITEAL6432_M   (0xFFFF<<16) /* Mask */

Definition at line 844 of file vme_tsi148.h.

#define TSI148_LCSR_ITOFFL16_M   (0xFFFFFFF<<4) /* Mask */

Definition at line 853 of file vme_tsi148.h.

#define TSI148_LCSR_ITOFFL24_M   (0xFFFFF<<12) /* Mask */

Definition at line 852 of file vme_tsi148.h.

#define TSI148_LCSR_ITOFFL6432_M   (0xFFFF<<16) /* Mask */

Definition at line 851 of file vme_tsi148.h.

#define TSI148_LCSR_ITSAL16_M   (0x0000FFF<<4) /* Mask */

Definition at line 839 of file vme_tsi148.h.

#define TSI148_LCSR_ITSAL24_M   (0x00FFF<<12) /* Mask */

Definition at line 838 of file vme_tsi148.h.

#define TSI148_LCSR_ITSAL6432_M   (0xFFFF<<16) /* Mask */

Definition at line 837 of file vme_tsi148.h.

#define TSI148_LCSR_LMAT   0x42C

Definition at line 402 of file vme_tsi148.h.

#define TSI148_LCSR_LMAT_AS_A16   (0<<4) /* A16 */

Definition at line 952 of file vme_tsi148.h.

#define TSI148_LCSR_LMAT_AS_A24   (1<<4) /* A24 */

Definition at line 953 of file vme_tsi148.h.

#define TSI148_LCSR_LMAT_AS_A32   (2<<4) /* A32 */

Definition at line 954 of file vme_tsi148.h.

#define TSI148_LCSR_LMAT_AS_A64   (4<<4) /* A64 */

Definition at line 955 of file vme_tsi148.h.

#define TSI148_LCSR_LMAT_AS_M   (7<<4) /* Address Space MASK */

Definition at line 951 of file vme_tsi148.h.

#define TSI148_LCSR_LMAT_DATA   (1<<0) /* Data Access */

Definition at line 960 of file vme_tsi148.h.

#define TSI148_LCSR_LMAT_EN   (1<<7) /* Enable Location Monitor */

Definition at line 949 of file vme_tsi148.h.

#define TSI148_LCSR_LMAT_NPRIV   (1<<2) /* Non-Priv (User) Access */

Definition at line 958 of file vme_tsi148.h.

#define TSI148_LCSR_LMAT_PGM   (1<<1) /* Program Access */

Definition at line 959 of file vme_tsi148.h.

#define TSI148_LCSR_LMAT_SUPR   (1<<3) /* Supervisor Access */

Definition at line 957 of file vme_tsi148.h.

#define TSI148_LCSR_LMBAL   0x428

Definition at line 401 of file vme_tsi148.h.

#define TSI148_LCSR_LMBAL_M   (0x7FFFFFF<<5) /* Mask */

Definition at line 944 of file vme_tsi148.h.

#define TSI148_LCSR_LMBAU   0x424

Definition at line 400 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DCDAL   0x14

Definition at line 479 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DCDAU   0x10

Definition at line 478 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DCLAL   0x1C

Definition at line 481 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DCLAU   0x18

Definition at line 480 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DCNT   0x40

Definition at line 490 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DCSAL   0xC

Definition at line 477 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DCSAU   0x8

Definition at line 476 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DCTL   0x0

Definition at line 474 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DDAL   0x2C

Definition at line 485 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DDAT   0x34

Definition at line 487 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DDAU   0x28

Definition at line 484 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DDBS   0x44

Definition at line 491 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DNLAL   0x3C

Definition at line 489 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DNLAU   0x38

Definition at line 488 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DSAL   0x24

Definition at line 483 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DSAT   0x30

Definition at line 486 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DSAU   0x20

Definition at line 482 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_DSTA   0x4

Definition at line 475 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_ITAT   0x18

Definition at line 369 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_ITEAL   0xC

Definition at line 366 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_ITEAU   0x8

Definition at line 365 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_ITOFL   0x14

Definition at line 368 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_ITOFU   0x10

Definition at line 367 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_ITSAL   0x4

Definition at line 364 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_ITSAU   0x0

Definition at line 363 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_OTAT   0x1C

Definition at line 213 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_OTBS   0x18

Definition at line 212 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_OTEAL   0xC

Definition at line 209 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_OTEAU   0x8

Definition at line 208 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_OTOFL   0x14

Definition at line 211 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_OTOFU   0x10

Definition at line 210 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_OTSAL   0x4

Definition at line 207 of file vme_tsi148.h.

#define TSI148_LCSR_OFFSET_OTSAU   0x0

Definition at line 206 of file vme_tsi148.h.

#define TSI148_LCSR_OT0   0x100

Definition at line 192 of file vme_tsi148.h.

#define TSI148_LCSR_OT0_OTAT   0x11C

Definition at line 127 of file vme_tsi148.h.

#define TSI148_LCSR_OT0_OTBS   0x118

Definition at line 126 of file vme_tsi148.h.

#define TSI148_LCSR_OT0_OTEAL   0x10C

Definition at line 123 of file vme_tsi148.h.

#define TSI148_LCSR_OT0_OTEAU   0x108

Definition at line 122 of file vme_tsi148.h.

#define TSI148_LCSR_OT0_OTOFL   0x114

Definition at line 125 of file vme_tsi148.h.

#define TSI148_LCSR_OT0_OTOFU   0x110

Definition at line 124 of file vme_tsi148.h.

#define TSI148_LCSR_OT0_OTSAL   0x104

Definition at line 121 of file vme_tsi148.h.

#define TSI148_LCSR_OT0_OTSAU   0x100

Definition at line 120 of file vme_tsi148.h.

#define TSI148_LCSR_OT1   0x120

Definition at line 193 of file vme_tsi148.h.

#define TSI148_LCSR_OT1_OTAT   0x13C

Definition at line 136 of file vme_tsi148.h.

#define TSI148_LCSR_OT1_OTBS   0x138

Definition at line 135 of file vme_tsi148.h.

#define TSI148_LCSR_OT1_OTEAL   0x12C

Definition at line 132 of file vme_tsi148.h.

#define TSI148_LCSR_OT1_OTEAU   0x128

Definition at line 131 of file vme_tsi148.h.

#define TSI148_LCSR_OT1_OTOFL   0x134

Definition at line 134 of file vme_tsi148.h.

#define TSI148_LCSR_OT1_OTOFU   0x130

Definition at line 133 of file vme_tsi148.h.

#define TSI148_LCSR_OT1_OTSAL   0x124

Definition at line 130 of file vme_tsi148.h.

#define TSI148_LCSR_OT1_OTSAU   0x120

Definition at line 129 of file vme_tsi148.h.

#define TSI148_LCSR_OT2   0x140

Definition at line 194 of file vme_tsi148.h.

#define TSI148_LCSR_OT2_OTAT   0x15C

Definition at line 145 of file vme_tsi148.h.

#define TSI148_LCSR_OT2_OTBS   0x158

Definition at line 144 of file vme_tsi148.h.

#define TSI148_LCSR_OT2_OTEAL   0x14C

Definition at line 141 of file vme_tsi148.h.

#define TSI148_LCSR_OT2_OTEAU   0x148

Definition at line 140 of file vme_tsi148.h.

#define TSI148_LCSR_OT2_OTOFL   0x154

Definition at line 143 of file vme_tsi148.h.

#define TSI148_LCSR_OT2_OTOFU   0x150

Definition at line 142 of file vme_tsi148.h.

#define TSI148_LCSR_OT2_OTSAL   0x144

Definition at line 139 of file vme_tsi148.h.

#define TSI148_LCSR_OT2_OTSAU   0x140

Definition at line 138 of file vme_tsi148.h.

#define TSI148_LCSR_OT3   0x160

Definition at line 195 of file vme_tsi148.h.

#define TSI148_LCSR_OT3_OTAT   0x17C

Definition at line 154 of file vme_tsi148.h.

#define TSI148_LCSR_OT3_OTBS   0x178

Definition at line 153 of file vme_tsi148.h.

#define TSI148_LCSR_OT3_OTEAL   0x16C

Definition at line 150 of file vme_tsi148.h.

#define TSI148_LCSR_OT3_OTEAU   0x168

Definition at line 149 of file vme_tsi148.h.

#define TSI148_LCSR_OT3_OTOFL   0x174

Definition at line 152 of file vme_tsi148.h.

#define TSI148_LCSR_OT3_OTOFU   0x170

Definition at line 151 of file vme_tsi148.h.

#define TSI148_LCSR_OT3_OTSAL   0x164

Definition at line 148 of file vme_tsi148.h.

#define TSI148_LCSR_OT3_OTSAU   0x160

Definition at line 147 of file vme_tsi148.h.

#define TSI148_LCSR_OT4   0x180

Definition at line 196 of file vme_tsi148.h.

#define TSI148_LCSR_OT4_OTAT   0x19C

Definition at line 163 of file vme_tsi148.h.

#define TSI148_LCSR_OT4_OTBS   0x198

Definition at line 162 of file vme_tsi148.h.

#define TSI148_LCSR_OT4_OTEAL   0x18C

Definition at line 159 of file vme_tsi148.h.

#define TSI148_LCSR_OT4_OTEAU   0x188

Definition at line 158 of file vme_tsi148.h.

#define TSI148_LCSR_OT4_OTOFL   0x194

Definition at line 161 of file vme_tsi148.h.

#define TSI148_LCSR_OT4_OTOFU   0x190

Definition at line 160 of file vme_tsi148.h.

#define TSI148_LCSR_OT4_OTSAL   0x184

Definition at line 157 of file vme_tsi148.h.

#define TSI148_LCSR_OT4_OTSAU   0x180

Definition at line 156 of file vme_tsi148.h.

#define TSI148_LCSR_OT5   0x1A0

Definition at line 197 of file vme_tsi148.h.

#define TSI148_LCSR_OT5_OTAT   0x1BC

Definition at line 172 of file vme_tsi148.h.

#define TSI148_LCSR_OT5_OTBS   0x1B8

Definition at line 171 of file vme_tsi148.h.

#define TSI148_LCSR_OT5_OTEAL   0x1AC

Definition at line 168 of file vme_tsi148.h.

#define TSI148_LCSR_OT5_OTEAU   0x1A8

Definition at line 167 of file vme_tsi148.h.

#define TSI148_LCSR_OT5_OTOFL   0x1B4

Definition at line 170 of file vme_tsi148.h.

#define TSI148_LCSR_OT5_OTOFU   0x1B0

Definition at line 169 of file vme_tsi148.h.

#define TSI148_LCSR_OT5_OTSAL   0x1A4

Definition at line 166 of file vme_tsi148.h.

#define TSI148_LCSR_OT5_OTSAU   0x1A0

Definition at line 165 of file vme_tsi148.h.

#define TSI148_LCSR_OT6   0x1C0

Definition at line 198 of file vme_tsi148.h.

#define TSI148_LCSR_OT6_OTAT   0x1DC

Definition at line 181 of file vme_tsi148.h.

#define TSI148_LCSR_OT6_OTBS   0x1D8

Definition at line 180 of file vme_tsi148.h.

#define TSI148_LCSR_OT6_OTEAL   0x1CC

Definition at line 177 of file vme_tsi148.h.

#define TSI148_LCSR_OT6_OTEAU   0x1C8

Definition at line 176 of file vme_tsi148.h.

#define TSI148_LCSR_OT6_OTOFL   0x1D4

Definition at line 179 of file vme_tsi148.h.

#define TSI148_LCSR_OT6_OTOFU   0x1D0

Definition at line 178 of file vme_tsi148.h.

#define TSI148_LCSR_OT6_OTSAL   0x1C4

Definition at line 175 of file vme_tsi148.h.

#define TSI148_LCSR_OT6_OTSAU   0x1C0

Definition at line 174 of file vme_tsi148.h.

#define TSI148_LCSR_OT7   0x1E0

Definition at line 199 of file vme_tsi148.h.

#define TSI148_LCSR_OT7_OTAT   0x1FC

Definition at line 190 of file vme_tsi148.h.

#define TSI148_LCSR_OT7_OTBS   0x1F8

Definition at line 189 of file vme_tsi148.h.

#define TSI148_LCSR_OT7_OTEAL   0x1EC

Definition at line 186 of file vme_tsi148.h.

#define TSI148_LCSR_OT7_OTEAU   0x1E8

Definition at line 185 of file vme_tsi148.h.

#define TSI148_LCSR_OT7_OTOFL   0x1F4

Definition at line 188 of file vme_tsi148.h.

#define TSI148_LCSR_OT7_OTOFU   0x1F0

Definition at line 187 of file vme_tsi148.h.

#define TSI148_LCSR_OT7_OTSAL   0x1E4

Definition at line 184 of file vme_tsi148.h.

#define TSI148_LCSR_OT7_OTSAU   0x1E0

Definition at line 183 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_2eSSTM_160   (0<<11) /* 160MB/s 2eSST Xfer Rate */

Definition at line 667 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_2eSSTM_267   (1<<11) /* 267MB/s 2eSST Xfer Rate */

Definition at line 668 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_2eSSTM_320   (2<<11) /* 320MB/s 2eSST Xfer Rate */

Definition at line 669 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_2eSSTM_M   (7<<11) /* 2eSST Xfer Rate Mask */

Definition at line 666 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_AMODE_A16   (0<<0) /* A16 Address Space */

Definition at line 687 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_AMODE_A24   (1<<0) /* A24 Address Space */

Definition at line 688 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_AMODE_A32   (2<<0) /* A32 Address Space */

Definition at line 689 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_AMODE_A64   (4<<0) /* A32 Address Space */

Definition at line 690 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_AMODE_CRCSR   (5<<0) /* CR/CSR Address Space */

Definition at line 691 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_AMODE_M   (0xf<<0) /* Address Mode Mask */

Definition at line 686 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_AMODE_USER1   (8<<0) /* User1 Address Space */

Definition at line 692 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_AMODE_USER2   (9<<0) /* User2 Address Space */

Definition at line 693 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_AMODE_USER3   (10<<0) /* User3 Address Space */

Definition at line 694 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_AMODE_USER4   (11<<0) /* User4 Address Space */

Definition at line 695 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_DBW_16   (0<<6) /* 16-bit Data Width */

Definition at line 680 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_DBW_32   (1<<6) /* 32-bit Data Width */

Definition at line 681 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_DBW_M   (3<<6) /* Max Data Width */

Definition at line 679 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_EN   (1<<31) /* Window Enable */

Definition at line 657 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_MRPFD   (1<<18) /* Prefetch Disable */

Definition at line 658 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_PFS_16   (3<<16) /* 16 Cache Lines P Size */

Definition at line 664 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_PFS_2   (0<<16) /* 2 Cache Lines P Size */

Definition at line 661 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_PFS_4   (1<<16) /* 4 Cache Lines P Size */

Definition at line 662 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_PFS_8   (2<<16) /* 8 Cache Lines P Size */

Definition at line 663 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_PFS_M   (3<<16) /* Prefetch Size Mask */

Definition at line 660 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_PGM   (1<<4) /* Program Access */

Definition at line 684 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_SUP   (1<<5) /* Supervisory Access */

Definition at line 683 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_TM_2eSST   (4<<8) /* 2eSST Xfer Protocol */

Definition at line 676 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_TM_2eSSTB   (5<<8) /* 2eSST Bcast Xfer Protocol */

Definition at line 677 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_TM_2eVME   (3<<8) /* 2eVME Xfer Protocol */

Definition at line 675 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_TM_BLT   (1<<8) /* BLT Xfer Protocol */

Definition at line 673 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_TM_M   (7<<8) /* Xfer Protocol Mask */

Definition at line 671 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_TM_MBLT   (2<<8) /* MBLT Xfer Protocol */

Definition at line 674 of file vme_tsi148.h.

#define TSI148_LCSR_OTAT_TM_SCT   (0<<8) /* SCT Xfer Protocol */

Definition at line 672 of file vme_tsi148.h.

#define TSI148_LCSR_OTBS_M   (0xFFFFF<<0) /* Mask */

Definition at line 652 of file vme_tsi148.h.

#define TSI148_LCSR_OTEAL_M   (0xFFFF<<16) /* Mask */

Definition at line 642 of file vme_tsi148.h.

#define TSI148_LCSR_OTOFFL_M   (0xFFFF<<16) /* Mask */

Definition at line 647 of file vme_tsi148.h.

#define TSI148_LCSR_OTSAL_M   (0xFFFF<<16) /* Mask */

Definition at line 637 of file vme_tsi148.h.

#define TSI148_LCSR_PSTAT   0x240

Definition at line 254 of file vme_tsi148.h.

#define TSI148_LCSR_PSTAT_DEVSELS   (1<<2) /* DEVL status */

Definition at line 807 of file vme_tsi148.h.

#define TSI148_LCSR_PSTAT_FRAMES   (1<<4) /* Frame Status */

Definition at line 805 of file vme_tsi148.h.

#define TSI148_LCSR_PSTAT_IRDYS   (1<<3) /* IRDY status */

Definition at line 806 of file vme_tsi148.h.

#define TSI148_LCSR_PSTAT_M66ENS   (1<<5) /* M66ENS 66Mhz enable */

Definition at line 804 of file vme_tsi148.h.

#define TSI148_LCSR_PSTAT_REQ64S   (1<<6) /* Request 64 status set */

Definition at line 803 of file vme_tsi148.h.

#define TSI148_LCSR_PSTAT_STOPS   (1<<1) /* STOP status */

Definition at line 808 of file vme_tsi148.h.

#define TSI148_LCSR_PSTAT_TRDYS   (1<<0) /* TRDY status */

Definition at line 809 of file vme_tsi148.h.

#define TSI148_LCSR_RMWAL   0x224

Definition at line 237 of file vme_tsi148.h.

#define TSI148_LCSR_RMWAU   0x220

Definition at line 236 of file vme_tsi148.h.

#define TSI148_LCSR_RMWC   0x22C

Definition at line 239 of file vme_tsi148.h.

#define TSI148_LCSR_RMWEN   0x228

Definition at line 238 of file vme_tsi148.h.

#define TSI148_LCSR_RMWS   0x230

Definition at line 240 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL   0x238

Definition at line 247 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_ATOEN   (1<<7) /* Arbiter Time-out Enable */

Definition at line 774 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_BID_M   (0x1F<<8) /* Broadcast ID Mask */

Definition at line 772 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_DLT_1024   (7<<24) /* 1024 VCLKS */

Definition at line 759 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_DLT_128   (4<<24) /* 128 VCLKS */

Definition at line 756 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_DLT_16   (1<<24) /* 16 VCLKS */

Definition at line 753 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_DLT_16384   (0xB<<24) /* 16384 VCLKS */

Definition at line 763 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_DLT_2048   (8<<24) /* 2048 VCLKS */

Definition at line 760 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_DLT_256   (5<<24) /* 256 VCLKS */

Definition at line 757 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_DLT_32   (2<<24) /* 32 VCLKS */

Definition at line 754 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_DLT_32768   (0xC<<24) /* 32768 VCLKS */

Definition at line 764 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_DLT_4096   (9<<24) /* 4096 VCLKS */

Definition at line 761 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_DLT_512   (6<<24) /* 512 VCLKS */

Definition at line 758 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_DLT_64   (3<<24) /* 64 VCLKS */

Definition at line 755 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_DLT_8192   (0xA<<24) /* 8192 VCLKS */

Definition at line 762 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_DLT_M   (0xF<<24) /* Deadlock Timer */

Definition at line 751 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_DLT_OFF   (0<<24) /* Deadlock Timer Off */

Definition at line 752 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_GTO_128   (4<<0) /* 128 us */

Definition at line 782 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_GTO_16   (1<<0) /* 16 us */

Definition at line 779 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_GTO_256   (5<<0) /* 256 us */

Definition at line 783 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_GTO_32   (2<<0) /* 32 us */

Definition at line 780 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_GTO_512   (6<<0) /* 512 us */

Definition at line 784 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_GTO_64   (3<<0) /* 64 us */

Definition at line 781 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_GTO_8   (0<<0) /* 8 us */

Definition at line 778 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_GTO_DIS   (7<<0) /* Disabled */

Definition at line 785 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_GTO_M
Value:
(7<<0) /* VMEbus Global Time-out Mask
*/

Definition at line 777 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_LRE   (1<<31) /* Late Retry Enable */

Definition at line 749 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_LRESET   (1<<16) /* Local Reset */

Definition at line 769 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_NERBB
Value:
(1<<20) /* No Early Release of Bus Busy
*/

Definition at line 766 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_ROBIN   (1<<6) /* VMEbus Round Robin */

Definition at line 775 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_SFAILAI   (1<<15) /* SYSFAIL Auto Slot ID */

Definition at line 771 of file vme_tsi148.h.

#define TSI148_LCSR_VCTRL_SRESET   (1<<17) /* System Reset */

Definition at line 768 of file vme_tsi148.h.

#define TSI148_LCSR_VEAL   0x264

Definition at line 267 of file vme_tsi148.h.

#define TSI148_LCSR_VEAT   0x268

Definition at line 268 of file vme_tsi148.h.

#define TSI148_LCSR_VEAT_2EOT   (1<<21) /* 2e Odd Termination */

Definition at line 817 of file vme_tsi148.h.

#define TSI148_LCSR_VEAT_2EST   (1<<20) /* 2e Slave terminated */

Definition at line 818 of file vme_tsi148.h.

#define TSI148_LCSR_VEAT_AM_M   (0x3F<<8) /* Address Mode Mask */

Definition at line 825 of file vme_tsi148.h.

#define TSI148_LCSR_VEAT_BERR   (1<<19) /* Bus Error */

Definition at line 819 of file vme_tsi148.h.

#define TSI148_LCSR_VEAT_DS0   (1<<14) /* DS0_ signal state */

Definition at line 824 of file vme_tsi148.h.

#define TSI148_LCSR_VEAT_DS1   (1<<15) /* DS1_ signal state */

Definition at line 823 of file vme_tsi148.h.

#define TSI148_LCSR_VEAT_IACK   (1<<16) /* IACK_ signal state */

Definition at line 822 of file vme_tsi148.h.

#define TSI148_LCSR_VEAT_LWORD   (1<<18) /* LWORD_ signal state */

Definition at line 820 of file vme_tsi148.h.

#define TSI148_LCSR_VEAT_VEOF   (1<<30) /* Overflow */

Definition at line 815 of file vme_tsi148.h.

#define TSI148_LCSR_VEAT_VES   (1<<31) /* Status */

Definition at line 814 of file vme_tsi148.h.

#define TSI148_LCSR_VEAT_VESCL   (1<<29) /* Status Clear */

Definition at line 816 of file vme_tsi148.h.

#define TSI148_LCSR_VEAT_WRITE   (1<<17) /* WRITE_ signal state */

Definition at line 821 of file vme_tsi148.h.

#define TSI148_LCSR_VEAT_XAM_M   (0xFF<<0) /* Master AMode Mask */

Definition at line 826 of file vme_tsi148.h.

#define TSI148_LCSR_VEAU   0x260

Definition at line 266 of file vme_tsi148.h.

#define TSI148_LCSR_VIACK1   0x204

Definition at line 219 of file vme_tsi148.h.

#define TSI148_LCSR_VIACK2   0x208

Definition at line 220 of file vme_tsi148.h.

#define TSI148_LCSR_VIACK3   0x20C

Definition at line 221 of file vme_tsi148.h.

#define TSI148_LCSR_VIACK4   0x210

Definition at line 222 of file vme_tsi148.h.

#define TSI148_LCSR_VIACK5   0x214

Definition at line 223 of file vme_tsi148.h.

#define TSI148_LCSR_VIACK6   0x218

Definition at line 224 of file vme_tsi148.h.

#define TSI148_LCSR_VIACK7   0x21C

Definition at line 225 of file vme_tsi148.h.

#define TSI148_LCSR_VICR   0x440

Definition at line 412 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_BIP   (1<<15) /* Broadcast Interrupt Pulse */

Definition at line 997 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_CNTS_DIS   (1<<22) /* Cntr Disable */

Definition at line 976 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_CNTS_IRQ1   (2<<22) /* IRQ1 to Cntr */

Definition at line 977 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_CNTS_IRQ2   (3<<22) /* IRQ2 to Cntr */

Definition at line 978 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_CNTS_M   (3<<22) /* Cntr Source MASK */

Definition at line 975 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_EDGIS_DIS   (1<<20) /* Edge interrupt Disable */

Definition at line 981 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_EDGIS_IRQ1   (2<<20) /* IRQ1 to Edge */

Definition at line 982 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_EDGIS_IRQ2   (3<<20) /* IRQ2 to Edge */

Definition at line 983 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_EDGIS_M   (3<<20) /* Edge interrupt MASK */

Definition at line 980 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQ2F_1U   (4<<16) /* 1us Clock */

Definition at line 995 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQ2F_M   (3<<16) /* IRQ2* Function MASK */

Definition at line 991 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQ2F_NORM   (1<<16) /* Normal */

Definition at line 992 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQ2F_PROG   (3<<16) /* Programmable Clock */

Definition at line 994 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQ2F_PULSE   (2<<16) /* Pulse Generator */

Definition at line 993 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQC   (1<<12) /* VMEbus IRQ Clear */

Definition at line 999 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQIF_1U   (4<<18) /* 1us Clock */

Definition at line 989 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQIF_M   (3<<18) /* IRQ1* Function MASK */

Definition at line 985 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQIF_NORM   (1<<18) /* Normal */

Definition at line 986 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQIF_PROG   (3<<18) /* Programmable Clock */

Definition at line 988 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQIF_PULSE   (2<<18) /* Pulse Generator */

Definition at line 987 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQL_1   (1<<8) /* VMEbus SW IRQ Level 1 */

Definition at line 1003 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQL_2   (2<<8) /* VMEbus SW IRQ Level 2 */

Definition at line 1004 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQL_3   (3<<8) /* VMEbus SW IRQ Level 3 */

Definition at line 1005 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQL_4   (4<<8) /* VMEbus SW IRQ Level 4 */

Definition at line 1006 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQL_5   (5<<8) /* VMEbus SW IRQ Level 5 */

Definition at line 1007 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQL_6   (6<<8) /* VMEbus SW IRQ Level 6 */

Definition at line 1008 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQL_7   (7<<8) /* VMEbus SW IRQ Level 7 */

Definition at line 1009 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQL_M   (7<<8) /* VMEbus SW IRQ Level Mask */

Definition at line 1002 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_IRQS   (1<<11) /* VMEbus IRQ Status */

Definition at line 1000 of file vme_tsi148.h.

#define TSI148_LCSR_VICR_STID_M   (0xFF<<0) /* Status/ID Mask */

Definition at line 1016 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL   0x234

Definition at line 246 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_ATO_128   (1<<16) /* 128 us */

Definition at line 709 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_ATO_128M   (6<<16) /* 128 ms */

Definition at line 714 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_ATO_2M   (3<<16) /* 2 ms */

Definition at line 711 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_ATO_32   (0<<16) /* 32 us */

Definition at line 708 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_ATO_32M   (5<<16) /* 32 ms */

Definition at line 713 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_ATO_512   (2<<16) /* 512 us */

Definition at line 710 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_ATO_8M   (4<<16) /* 8 ms */

Definition at line 712 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_ATO_DIS   (7<<16) /* Disabled */

Definition at line 715 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_ATO_M
Value:
(7<<16) /* Master Access Time-out Mask
*/

Definition at line 707 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_DHB   (1<<25) /* Device Has Bus */

Definition at line 702 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_DWB   (1<<24) /* Device Wants Bus */

Definition at line 703 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_RMWEN   (1<<20) /* RMW Enable */

Definition at line 705 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VFAIR   (1<<2) /* VMEbus Master Fair Mode */

Definition at line 743 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VREL_M
Value:
(3<<3) /* VMEbus Master Rel Mode Mask
*/

Definition at line 737 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VREL_T_B_D   (2<<3) /* Time on and BCLR or Done */

Definition at line 740 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VREL_T_D   (0<<3) /* Time on or Done */

Definition at line 738 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VREL_T_D_R   (3<<3) /* Time on or Done and REQ */

Definition at line 741 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VREL_T_R_D   (1<<3) /* Time on and REQ or Done */

Definition at line 739 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VREQL_M
Value:
(3<<0) /* VMEbus Master Req Level Mask
*/

Definition at line 744 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VS   (1<<26) /* VMEbus Stop */

Definition at line 701 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VSA   (1<<27) /* VMEbus Stop Ack */

Definition at line 700 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTOFF_0   (0<<12) /* 0us */

Definition at line 718 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTOFF_1   (1<<12) /* 1us */

Definition at line 719 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTOFF_16   (5<<12) /* 16us */

Definition at line 723 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTOFF_2   (2<<12) /* 2us */

Definition at line 720 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTOFF_32   (6<<12) /* 32us */

Definition at line 724 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTOFF_4   (3<<12) /* 4us */

Definition at line 721 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTOFF_64   (7<<12) /* 64us */

Definition at line 725 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTOFF_8   (4<<12) /* 8us */

Definition at line 722 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTOFF_M   (7<<12) /* VMEbus Master Time off */

Definition at line 717 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTON_128   (5<<8) /* 128us */

Definition at line 733 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTON_16   (2<<8) /* 16us */

Definition at line 730 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTON_256   (6<<8) /* 256us */

Definition at line 734 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTON_32   (3<<8) /* 32us */

Definition at line 731 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTON_4   (0<<8) /* 8us */

Definition at line 728 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTON_512   (7<<8) /* 512us */

Definition at line 735 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTON_64   (4<<8) /* 64us */

Definition at line 732 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTON_8   (1<<8) /* 8us */

Definition at line 729 of file vme_tsi148.h.

#define TSI148_LCSR_VMCTRL_VTON_M   (7<<8) /* VMEbus Master Time On */

Definition at line 727 of file vme_tsi148.h.

#define TSI148_LCSR_VMEFL   0x250

Definition at line 260 of file vme_tsi148.h.

#define TSI148_LCSR_VSTAT   0x23C

Definition at line 248 of file vme_tsi148.h.

#define TSI148_LCSR_VSTAT_ACFAILS   (1<<9) /* AC fail status */

Definition at line 795 of file vme_tsi148.h.

#define TSI148_LCSR_VSTAT_BDFAILS   (1<<11) /* Board Fail Status */

Definition at line 793 of file vme_tsi148.h.

#define TSI148_LCSR_VSTAT_BRDFL   (1<<14) /* Board fail */

Definition at line 791 of file vme_tsi148.h.

#define TSI148_LCSR_VSTAT_CPURST   (1<<15) /* Clear power up reset */

Definition at line 790 of file vme_tsi148.h.

#define TSI148_LCSR_VSTAT_GA_M   (0x1F<<0) /* Geographic Addr Mask */

Definition at line 798 of file vme_tsi148.h.

#define TSI148_LCSR_VSTAT_GAP   (1<<5) /* Geographic Addr Parity */

Definition at line 797 of file vme_tsi148.h.

#define TSI148_LCSR_VSTAT_PURSTS   (1<<12) /* Power up reset status */

Definition at line 792 of file vme_tsi148.h.

#define TSI148_LCSR_VSTAT_SCONS   (1<<8) /* System Cont Status */

Definition at line 796 of file vme_tsi148.h.

#define TSI148_LCSR_VSTAT_SYSFAILS   (1<<10) /* System Fail Status */

Definition at line 794 of file vme_tsi148.h.

#define TSI148_MAX_DMA   2 /* Max DMA Controllers */

Definition at line 32 of file vme_tsi148.h.

#define TSI148_MAX_MAILBOX   4 /* Max Mail Box registers */

Definition at line 33 of file vme_tsi148.h.

#define TSI148_MAX_MASTER   8 /* Max Master Windows */

Definition at line 30 of file vme_tsi148.h.

#define TSI148_MAX_SEMAPHORE   8 /* Max Semaphores */

Definition at line 34 of file vme_tsi148.h.

#define TSI148_MAX_SLAVE   8 /* Max Slave Windows */

Definition at line 31 of file vme_tsi148.h.

#define TSI148_PCFS_CAPP   0x34

Definition at line 106 of file vme_tsi148.h.

#define TSI148_PCFS_CLAS_M   (0xFF<<24) /* Class ID */

Definition at line 568 of file vme_tsi148.h.

#define TSI148_PCFS_CLASS   0x8

Definition at line 99 of file vme_tsi148.h.

#define TSI148_PCFS_CLSZ_M   (0xFF<<0) /* Cache Line Size */

Definition at line 578 of file vme_tsi148.h.

#define TSI148_PCFS_CMMD_IOSP   (1<<0) /* PCI I/O space enable */

Definition at line 552 of file vme_tsi148.h.

#define TSI148_PCFS_CMMD_MEMSP   (1<<1) /* PCI mem space access */

Definition at line 551 of file vme_tsi148.h.

#define TSI148_PCFS_CMMD_MSTR   (1<<2) /* PCI bus master */

Definition at line 550 of file vme_tsi148.h.

#define TSI148_PCFS_CMMD_PERR   (1<<6) /* PERR_L out pin parity */

Definition at line 549 of file vme_tsi148.h.

#define TSI148_PCFS_CMMD_SERR   (1<<8) /* SERR_L out pin ssys err */

Definition at line 548 of file vme_tsi148.h.

#define TSI148_PCFS_CSR   0x4

Definition at line 98 of file vme_tsi148.h.

#define TSI148_PCFS_HEAD_M   (0xFF<<16) /* Master Lat Timer */

Definition at line 576 of file vme_tsi148.h.

#define TSI148_PCFS_ID   0x0

Definition at line 97 of file vme_tsi148.h.

#define TSI148_PCFS_MBARL   0x10

Definition at line 101 of file vme_tsi148.h.

#define TSI148_PCFS_MBARL_BASEL_M   (0xFFFFF<<12) /* Base Addr Lower Mask */

Definition at line 583 of file vme_tsi148.h.

#define TSI148_PCFS_MBARL_IOMEM   (1<<0) /* I/O Space Indicator */

Definition at line 586 of file vme_tsi148.h.

#define TSI148_PCFS_MBARL_MTYPE_M   (3<<1) /* Memory Type Mask */

Definition at line 585 of file vme_tsi148.h.

#define TSI148_PCFS_MBARL_PRE   (1<<3) /* Prefetch */

Definition at line 584 of file vme_tsi148.h.

#define TSI148_PCFS_MBARU   0x14

Definition at line 102 of file vme_tsi148.h.

#define TSI148_PCFS_MISC0   0xC

Definition at line 100 of file vme_tsi148.h.

#define TSI148_PCFS_MISC1   0x3C

Definition at line 108 of file vme_tsi148.h.

#define TSI148_PCFS_MLAT_M   (0xFF<<8) /* Master Lat Timer */

Definition at line 577 of file vme_tsi148.h.

#define TSI148_PCFS_MSIAL_M   (0x3FFFFFFF<<2) /* Mask */

Definition at line 599 of file vme_tsi148.h.

#define TSI148_PCFS_MSICAP_64BAC   (1<<7) /* 64-bit Address Capable */

Definition at line 591 of file vme_tsi148.h.

#define TSI148_PCFS_MSICAP_MMC_M   (7<<1) /* Multiple Msg Capable Mask */

Definition at line 593 of file vme_tsi148.h.

#define TSI148_PCFS_MSICAP_MME_M   (7<<4) /* Multiple Msg Enable Mask */

Definition at line 592 of file vme_tsi148.h.

#define TSI148_PCFS_MSICAP_MSIEN   (1<<0) /* Msg signaled INT Enable */

Definition at line 594 of file vme_tsi148.h.

#define TSI148_PCFS_MSIMD_M   (0xFFFF<<0) /* Mask */

Definition at line 604 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXCAP_DPERE   (1<<0) /* Data Parity Recover Enable */

Definition at line 612 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXCAP_ERO   (1<<1) /* Enable Relaxed Ordering */

Definition at line 611 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXCAP_MMRBC_M   (3<<2) /* Max Mem Read byte cnt */

Definition at line 610 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXCAP_MOST_M   (7<<4) /* Max outstanding Split Tran */

Definition at line 609 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXSTAT_133C   (1<<17) /* 133MHz capable */

Definition at line 624 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXSTAT_64D   (1<<16) /* 64 bit device */

Definition at line 625 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXSTAT_BN_M   (0xFF<<8) /* Bus number */

Definition at line 626 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXSTAT_DC   (1<<20) /* Device Complexity */

Definition at line 621 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXSTAT_DMCRS_M   (7<<26) /* max Cumulative Read Size */

Definition at line 618 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXSTAT_DMMRC_M   (3<<21) /* max mem read byte count */

Definition at line 620 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXSTAT_DMOST_M
Value:
(7<<23) /* max outstanding Split Trans
*/

Definition at line 619 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXSTAT_DN_M   (0x1F<<3) /* Device number */

Definition at line 627 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXSTAT_FN_M   (7<<0) /* Function Number */

Definition at line 628 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXSTAT_RSCEM   (1<<29) /* Received Split Comp Error */

Definition at line 617 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXSTAT_SCD   (1<<18) /* Split completion discard */

Definition at line 623 of file vme_tsi148.h.

#define TSI148_PCFS_PCIXSTAT_USC   (1<<19) /* Unexpected Split comp */

Definition at line 622 of file vme_tsi148.h.

#define TSI148_PCFS_PROGIF_M   (0xFF<<8) /* Sub-Class ID */

Definition at line 570 of file vme_tsi148.h.

#define TSI148_PCFS_REVID_M   (0xFF<<0) /* Rev ID */

Definition at line 571 of file vme_tsi148.h.

#define TSI148_PCFS_STAT_CAPL   (1<<4) /* Capab List - address $34 */

Definition at line 563 of file vme_tsi148.h.

#define TSI148_PCFS_STAT_DPAR   (1<<8) /* Data Parity Err Reported */

Definition at line 560 of file vme_tsi148.h.

#define TSI148_PCFS_STAT_FAST   (1<<7) /* Fast back-to-back Cap */

Definition at line 561 of file vme_tsi148.h.

#define TSI148_PCFS_STAT_P66M   (1<<5) /* 66 MHz Capable */

Definition at line 562 of file vme_tsi148.h.

#define TSI148_PCFS_STAT_RCPVE   (1<<15) /* Detected Parity Error */

Definition at line 554 of file vme_tsi148.h.

#define TSI148_PCFS_STAT_RCVMA   (1<<13) /* Received Master Abort */

Definition at line 556 of file vme_tsi148.h.

#define TSI148_PCFS_STAT_RCVTA   (1<<12) /* Received Target Abort */

Definition at line 557 of file vme_tsi148.h.

#define TSI148_PCFS_STAT_SELTIM   (3<<9) /* DELSEL Timing */

Definition at line 559 of file vme_tsi148.h.

#define TSI148_PCFS_STAT_SIGSE   (1<<14) /* Signalled System Error */

Definition at line 555 of file vme_tsi148.h.

#define TSI148_PCFS_STAT_SIGTA   (1<<11) /* Signalled Target Abort */

Definition at line 558 of file vme_tsi148.h.

#define TSI148_PCFS_SUBCLAS_M   (0xFF<<16) /* Sub-Class ID */

Definition at line 569 of file vme_tsi148.h.

#define TSI148_PCFS_SUBID   0x28

Definition at line 104 of file vme_tsi148.h.

#define TSI148_PCFS_XCAPP   0x40

Definition at line 110 of file vme_tsi148.h.

#define TSI148_PCFS_XSTAT   0x44

Definition at line 111 of file vme_tsi148.h.

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