#include <XCoreInstrInfo.h>
Detailed Description
Definition at line 25 of file XCoreInstrInfo.h.
Constructor & Destructor Documentation
Definition at line 49 of file XCoreInstrInfo.cpp.
Member Function Documentation
| bool XCoreInstrInfo::AnalyzeBranch | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock *& | TBB, | ||
| MachineBasicBlock *& | FBB, | ||
| SmallVectorImpl< MachineOperand > & | Cond, | ||
| bool | AllowModify | ||
| ) | const [override] |
AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:
1. If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null. 2. If this block ends with only an unconditional branch, it sets TBB to be the destination block. 3. If this block ends with an conditional branch and it falls through to an successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches. 4. If this block ends with an conditional branch and an unconditional block, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
Note that RemoveBranch and InsertBranch must be implemented to support cases where this method returns success.
Definition at line 194 of file XCoreInstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::XCore::COND_INVALID, llvm::MachineOperand::CreateImm(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), GetCondFromBranchOpc(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, IsBR_JT(), IsBRU(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
| void XCoreInstrInfo::copyPhysReg | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| DebugLoc | DL, | ||
| unsigned | DestReg, | ||
| unsigned | SrcReg, | ||
| bool | KillSrc | ||
| ) | const [override] |
Definition at line 341 of file XCoreInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::getKillRegState(), and llvm_unreachable.
| const TargetRegisterInfo& llvm::XCoreInstrInfo::getRegisterInfo | ( | ) | const [inline] |
getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).
Definition at line 35 of file XCoreInstrInfo.h.
Referenced by llvm::XCoreSubtarget::getRegisterInfo().
| unsigned XCoreInstrInfo::InsertBranch | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock * | TBB, | ||
| MachineBasicBlock * | FBB, | ||
| const SmallVectorImpl< MachineOperand > & | Cond, | ||
| DebugLoc | DL | ||
| ) | const [override] |
Definition at line 282 of file XCoreInstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::SmallVectorBase::empty(), GetCondBranchFromCond(), getReg(), and llvm::SmallVectorTemplateCommon< T >::size().
| unsigned XCoreInstrInfo::isLoadFromStackSlot | ( | const MachineInstr * | MI, |
| int & | FrameIndex | ||
| ) | const [override] |
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
Definition at line 64 of file XCoreInstrInfo.cpp.
References llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and isZeroImm().
| unsigned XCoreInstrInfo::isStoreToStackSlot | ( | const MachineInstr * | MI, |
| int & | FrameIndex | ||
| ) | const [override] |
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.
Definition at line 85 of file XCoreInstrInfo.cpp.
References llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and isZeroImm().
| MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI, | ||
| unsigned | Reg, | ||
| uint64_t | Value | ||
| ) | const |
Definition at line 440 of file XCoreInstrInfo.cpp.
References llvm::MachineInstrBuilder::addConstantPoolIndex(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::CallingConv::C, llvm::MachineBasicBlock::end(), llvm::ConstantInt::get(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::Type::getInt32Ty(), llvm::MachineBasicBlock::getParent(), isImmMskBitp(), isImmU16(), isImmU6(), llvm::Log2_32(), and N.
Referenced by InsertFPConstInst(), and InsertSPConstInst().
| void XCoreInstrInfo::loadRegFromStackSlot | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI, | ||
| unsigned | DestReg, | ||
| int | FrameIndex, | ||
| const TargetRegisterClass * | RC, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const [override] |
Definition at line 392 of file XCoreInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), and llvm::MachineMemOperand::MOLoad.
| unsigned XCoreInstrInfo::RemoveBranch | ( | MachineBasicBlock & | MBB | ) | const [override] |
Definition at line 314 of file XCoreInstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), I, IsBRU(), and IsCondBranch().
| bool XCoreInstrInfo::ReverseBranchCondition | ( | SmallVectorImpl< MachineOperand > & | Cond | ) | const [override] |
ReverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
Definition at line 417 of file XCoreInstrInfo.cpp.
References GetOppositeBranchCondition(), and llvm::SmallVectorTemplateCommon< T >::size().
| void XCoreInstrInfo::storeRegToStackSlot | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI, | ||
| unsigned | SrcReg, | ||
| bool | isKill, | ||
| int | FrameIndex, | ||
| const TargetRegisterClass * | RC, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const [override] |
Definition at line 368 of file XCoreInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), and llvm::MachineMemOperand::MOStore.
The documentation for this class was generated from the following files:
1.7.6.1