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82571.c
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1 /*******************************************************************************
2 
3  Intel PRO/1000 Linux driver
4  Copyright(c) 1999 - 2012 Intel Corporation.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13  more details.
14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21 
22  Contact Information:
23  Linux NICS <[email protected]>
24  e1000-devel Mailing List <[email protected]>
25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 /*
30  * 82571EB Gigabit Ethernet Controller
31  * 82571EB Gigabit Ethernet Controller (Copper)
32  * 82571EB Gigabit Ethernet Controller (Fiber)
33  * 82571EB Dual Port Gigabit Mezzanine Adapter
34  * 82571EB Quad Port Gigabit Mezzanine Adapter
35  * 82571PT Gigabit PT Quad Port Server ExpressModule
36  * 82572EI Gigabit Ethernet Controller (Copper)
37  * 82572EI Gigabit Ethernet Controller (Fiber)
38  * 82572EI Gigabit Ethernet Controller
39  * 82573V Gigabit Ethernet Controller (Copper)
40  * 82573E Gigabit Ethernet Controller (Copper)
41  * 82573L Gigabit Ethernet Controller
42  * 82574L Gigabit Network Connection
43  * 82583V Gigabit Network Connection
44  */
45 
46 #include "e1000.h"
47 
48 #define ID_LED_RESERVED_F746 0xF746
49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
50  (ID_LED_OFF1_ON2 << 8) | \
51  (ID_LED_DEF1_DEF2 << 4) | \
52  (ID_LED_DEF1_DEF2))
53 
54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
55 #define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */
56 #define E1000_BASE1000T_STATUS 10
57 #define E1000_IDLE_ERROR_COUNT_MASK 0xFF
58 #define E1000_RECEIVE_ERROR_COUNTER 21
59 #define E1000_RECEIVE_ERROR_MAX 0xFFFF
60 
61 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
62 
63 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
64 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
65 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
66 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
67 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
68  u16 words, u16 *data);
69 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
70 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
71 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
72 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
73 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
74 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
75 static s32 e1000_led_on_82574(struct e1000_hw *hw);
76 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
77 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
78 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
79 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
80 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
81 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
82 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
83 
88 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
89 {
90  struct e1000_phy_info *phy = &hw->phy;
91  s32 ret_val;
92 
93  if (hw->phy.media_type != e1000_media_type_copper) {
94  phy->type = e1000_phy_none;
95  return 0;
96  }
97 
98  phy->addr = 1;
99  phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
100  phy->reset_delay_us = 100;
101 
102  phy->ops.power_up = e1000_power_up_phy_copper;
103  phy->ops.power_down = e1000_power_down_phy_copper_82571;
104 
105  switch (hw->mac.type) {
106  case e1000_82571:
107  case e1000_82572:
108  phy->type = e1000_phy_igp_2;
109  break;
110  case e1000_82573:
111  phy->type = e1000_phy_m88;
112  break;
113  case e1000_82574:
114  case e1000_82583:
115  phy->type = e1000_phy_bm;
116  phy->ops.acquire = e1000_get_hw_semaphore_82574;
117  phy->ops.release = e1000_put_hw_semaphore_82574;
118  phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
119  phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
120  break;
121  default:
122  return -E1000_ERR_PHY;
123  break;
124  }
125 
126  /* This can only be done after all function pointers are setup. */
127  ret_val = e1000_get_phy_id_82571(hw);
128  if (ret_val) {
129  e_dbg("Error getting PHY ID\n");
130  return ret_val;
131  }
132 
133  /* Verify phy id */
134  switch (hw->mac.type) {
135  case e1000_82571:
136  case e1000_82572:
137  if (phy->id != IGP01E1000_I_PHY_ID)
138  ret_val = -E1000_ERR_PHY;
139  break;
140  case e1000_82573:
141  if (phy->id != M88E1111_I_PHY_ID)
142  ret_val = -E1000_ERR_PHY;
143  break;
144  case e1000_82574:
145  case e1000_82583:
146  if (phy->id != BME1000_E_PHY_ID_R2)
147  ret_val = -E1000_ERR_PHY;
148  break;
149  default:
150  ret_val = -E1000_ERR_PHY;
151  break;
152  }
153 
154  if (ret_val)
155  e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
156 
157  return ret_val;
158 }
159 
164 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
165 {
166  struct e1000_nvm_info *nvm = &hw->nvm;
167  u32 eecd = er32(EECD);
168  u16 size;
169 
170  nvm->opcode_bits = 8;
171  nvm->delay_usec = 1;
172  switch (nvm->override) {
173  case e1000_nvm_override_spi_large:
174  nvm->page_size = 32;
175  nvm->address_bits = 16;
176  break;
177  case e1000_nvm_override_spi_small:
178  nvm->page_size = 8;
179  nvm->address_bits = 8;
180  break;
181  default:
182  nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
183  nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
184  break;
185  }
186 
187  switch (hw->mac.type) {
188  case e1000_82573:
189  case e1000_82574:
190  case e1000_82583:
191  if (((eecd >> 15) & 0x3) == 0x3) {
192  nvm->type = e1000_nvm_flash_hw;
193  nvm->word_size = 2048;
194  /*
195  * Autonomous Flash update bit must be cleared due
196  * to Flash update issue.
197  */
198  eecd &= ~E1000_EECD_AUPDEN;
199  ew32(EECD, eecd);
200  break;
201  }
202  /* Fall Through */
203  default:
204  nvm->type = e1000_nvm_eeprom_spi;
205  size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
206  E1000_EECD_SIZE_EX_SHIFT);
207  /*
208  * Added to a constant, "size" becomes the left-shift value
209  * for setting word_size.
210  */
211  size += NVM_WORD_SIZE_BASE_SHIFT;
212 
213  /* EEPROM access above 16k is unsupported */
214  if (size > 14)
215  size = 14;
216  nvm->word_size = 1 << size;
217  break;
218  }
219 
220  /* Function Pointers */
221  switch (hw->mac.type) {
222  case e1000_82574:
223  case e1000_82583:
224  nvm->ops.acquire = e1000_get_hw_semaphore_82574;
225  nvm->ops.release = e1000_put_hw_semaphore_82574;
226  break;
227  default:
228  break;
229  }
230 
231  return 0;
232 }
233 
238 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
239 {
240  struct e1000_mac_info *mac = &hw->mac;
241  u32 swsm = 0;
242  u32 swsm2 = 0;
243  bool force_clear_smbi = false;
244 
245  /* Set media type and media-dependent function pointers */
246  switch (hw->adapter->pdev->device) {
247  case E1000_DEV_ID_82571EB_FIBER:
248  case E1000_DEV_ID_82572EI_FIBER:
249  case E1000_DEV_ID_82571EB_QUAD_FIBER:
250  hw->phy.media_type = e1000_media_type_fiber;
251  mac->ops.setup_physical_interface =
252  e1000_setup_fiber_serdes_link_82571;
253  mac->ops.check_for_link = e1000e_check_for_fiber_link;
254  mac->ops.get_link_up_info =
255  e1000e_get_speed_and_duplex_fiber_serdes;
256  break;
257  case E1000_DEV_ID_82571EB_SERDES:
258  case E1000_DEV_ID_82571EB_SERDES_DUAL:
259  case E1000_DEV_ID_82571EB_SERDES_QUAD:
260  case E1000_DEV_ID_82572EI_SERDES:
261  hw->phy.media_type = e1000_media_type_internal_serdes;
262  mac->ops.setup_physical_interface =
263  e1000_setup_fiber_serdes_link_82571;
264  mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
265  mac->ops.get_link_up_info =
266  e1000e_get_speed_and_duplex_fiber_serdes;
267  break;
268  default:
269  hw->phy.media_type = e1000_media_type_copper;
270  mac->ops.setup_physical_interface =
271  e1000_setup_copper_link_82571;
272  mac->ops.check_for_link = e1000e_check_for_copper_link;
273  mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;
274  break;
275  }
276 
277  /* Set mta register count */
278  mac->mta_reg_count = 128;
279  /* Set rar entry count */
280  mac->rar_entry_count = E1000_RAR_ENTRIES;
281  /* Adaptive IFS supported */
282  mac->adaptive_ifs = true;
283 
284  /* MAC-specific function pointers */
285  switch (hw->mac.type) {
286  case e1000_82573:
287  mac->ops.set_lan_id = e1000_set_lan_id_single_port;
288  mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
289  mac->ops.led_on = e1000e_led_on_generic;
290  mac->ops.blink_led = e1000e_blink_led_generic;
291 
292  /* FWSM register */
293  mac->has_fwsm = true;
294  /*
295  * ARC supported; valid only if manageability features are
296  * enabled.
297  */
298  mac->arc_subsystem_valid = !!(er32(FWSM) &
299  E1000_FWSM_MODE_MASK);
300  break;
301  case e1000_82574:
302  case e1000_82583:
303  mac->ops.set_lan_id = e1000_set_lan_id_single_port;
304  mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
305  mac->ops.led_on = e1000_led_on_82574;
306  break;
307  default:
308  mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
309  mac->ops.led_on = e1000e_led_on_generic;
310  mac->ops.blink_led = e1000e_blink_led_generic;
311 
312  /* FWSM register */
313  mac->has_fwsm = true;
314  break;
315  }
316 
317  /*
318  * Ensure that the inter-port SWSM.SMBI lock bit is clear before
319  * first NVM or PHY access. This should be done for single-port
320  * devices, and for one port only on dual-port devices so that
321  * for those devices we can still use the SMBI lock to synchronize
322  * inter-port accesses to the PHY & NVM.
323  */
324  switch (hw->mac.type) {
325  case e1000_82571:
326  case e1000_82572:
327  swsm2 = er32(SWSM2);
328 
329  if (!(swsm2 & E1000_SWSM2_LOCK)) {
330  /* Only do this for the first interface on this card */
331  ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);
332  force_clear_smbi = true;
333  } else {
334  force_clear_smbi = false;
335  }
336  break;
337  default:
338  force_clear_smbi = true;
339  break;
340  }
341 
342  if (force_clear_smbi) {
343  /* Make sure SWSM.SMBI is clear */
344  swsm = er32(SWSM);
345  if (swsm & E1000_SWSM_SMBI) {
346  /* This bit should not be set on a first interface, and
347  * indicates that the bootagent or EFI code has
348  * improperly left this bit enabled
349  */
350  e_dbg("Please update your 82571 Bootagent\n");
351  }
352  ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
353  }
354 
355  /*
356  * Initialize device specific counter of SMBI acquisition
357  * timeouts.
358  */
359  hw->dev_spec.e82571.smb_counter = 0;
360 
361  return 0;
362 }
363 
364 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
365 {
366  struct e1000_hw *hw = &adapter->hw;
367  static int global_quad_port_a; /* global port a indication */
368  struct pci_dev *pdev = adapter->pdev;
369  int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
370  s32 rc;
371 
372  rc = e1000_init_mac_params_82571(hw);
373  if (rc)
374  return rc;
375 
376  rc = e1000_init_nvm_params_82571(hw);
377  if (rc)
378  return rc;
379 
380  rc = e1000_init_phy_params_82571(hw);
381  if (rc)
382  return rc;
383 
384  /* tag quad port adapters first, it's used below */
385  switch (pdev->device) {
386  case E1000_DEV_ID_82571EB_QUAD_COPPER:
387  case E1000_DEV_ID_82571EB_QUAD_FIBER:
388  case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
389  case E1000_DEV_ID_82571PT_QUAD_COPPER:
390  adapter->flags |= FLAG_IS_QUAD_PORT;
391  /* mark the first port */
392  if (global_quad_port_a == 0)
393  adapter->flags |= FLAG_IS_QUAD_PORT_A;
394  /* Reset for multiple quad port adapters */
395  global_quad_port_a++;
396  if (global_quad_port_a == 4)
397  global_quad_port_a = 0;
398  break;
399  default:
400  break;
401  }
402 
403  switch (adapter->hw.mac.type) {
404  case e1000_82571:
405  /* these dual ports don't have WoL on port B at all */
406  if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
407  (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
408  (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
409  (is_port_b))
410  adapter->flags &= ~FLAG_HAS_WOL;
411  /* quad ports only support WoL on port A */
412  if (adapter->flags & FLAG_IS_QUAD_PORT &&
413  (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
414  adapter->flags &= ~FLAG_HAS_WOL;
415  /* Does not support WoL on any port */
416  if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
417  adapter->flags &= ~FLAG_HAS_WOL;
418  break;
419  case e1000_82573:
420  if (pdev->device == E1000_DEV_ID_82573L) {
421  adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
422  adapter->max_hw_frame_size = DEFAULT_JUMBO;
423  }
424  break;
425  default:
426  break;
427  }
428 
429  return 0;
430 }
431 
439 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
440 {
441  struct e1000_phy_info *phy = &hw->phy;
442  s32 ret_val;
443  u16 phy_id = 0;
444 
445  switch (hw->mac.type) {
446  case e1000_82571:
447  case e1000_82572:
448  /*
449  * The 82571 firmware may still be configuring the PHY.
450  * In this case, we cannot access the PHY until the
451  * configuration is done. So we explicitly set the
452  * PHY ID.
453  */
454  phy->id = IGP01E1000_I_PHY_ID;
455  break;
456  case e1000_82573:
457  return e1000e_get_phy_id(hw);
458  break;
459  case e1000_82574:
460  case e1000_82583:
461  ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
462  if (ret_val)
463  return ret_val;
464 
465  phy->id = (u32)(phy_id << 16);
466  udelay(20);
467  ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
468  if (ret_val)
469  return ret_val;
470 
471  phy->id |= (u32)(phy_id);
472  phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
473  break;
474  default:
475  return -E1000_ERR_PHY;
476  break;
477  }
478 
479  return 0;
480 }
481 
488 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
489 {
490  u32 swsm;
491  s32 sw_timeout = hw->nvm.word_size + 1;
492  s32 fw_timeout = hw->nvm.word_size + 1;
493  s32 i = 0;
494 
495  /*
496  * If we have timedout 3 times on trying to acquire
497  * the inter-port SMBI semaphore, there is old code
498  * operating on the other port, and it is not
499  * releasing SMBI. Modify the number of times that
500  * we try for the semaphore to interwork with this
501  * older code.
502  */
503  if (hw->dev_spec.e82571.smb_counter > 2)
504  sw_timeout = 1;
505 
506  /* Get the SW semaphore */
507  while (i < sw_timeout) {
508  swsm = er32(SWSM);
509  if (!(swsm & E1000_SWSM_SMBI))
510  break;
511 
512  udelay(50);
513  i++;
514  }
515 
516  if (i == sw_timeout) {
517  e_dbg("Driver can't access device - SMBI bit is set.\n");
518  hw->dev_spec.e82571.smb_counter++;
519  }
520  /* Get the FW semaphore. */
521  for (i = 0; i < fw_timeout; i++) {
522  swsm = er32(SWSM);
523  ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
524 
525  /* Semaphore acquired if bit latched */
526  if (er32(SWSM) & E1000_SWSM_SWESMBI)
527  break;
528 
529  udelay(50);
530  }
531 
532  if (i == fw_timeout) {
533  /* Release semaphores */
534  e1000_put_hw_semaphore_82571(hw);
535  e_dbg("Driver can't access the NVM\n");
536  return -E1000_ERR_NVM;
537  }
538 
539  return 0;
540 }
541 
548 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
549 {
550  u32 swsm;
551 
552  swsm = er32(SWSM);
553  swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
554  ew32(SWSM, swsm);
555 }
563 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
564 {
565  u32 extcnf_ctrl;
566  s32 i = 0;
567 
568  extcnf_ctrl = er32(EXTCNF_CTRL);
569  extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
570  do {
571  ew32(EXTCNF_CTRL, extcnf_ctrl);
572  extcnf_ctrl = er32(EXTCNF_CTRL);
573 
574  if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
575  break;
576 
577  extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
578 
579  usleep_range(2000, 4000);
580  i++;
581  } while (i < MDIO_OWNERSHIP_TIMEOUT);
582 
583  if (i == MDIO_OWNERSHIP_TIMEOUT) {
584  /* Release semaphores */
585  e1000_put_hw_semaphore_82573(hw);
586  e_dbg("Driver can't access the PHY\n");
587  return -E1000_ERR_PHY;
588  }
589 
590  return 0;
591 }
592 
600 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
601 {
602  u32 extcnf_ctrl;
603 
604  extcnf_ctrl = er32(EXTCNF_CTRL);
605  extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
606  ew32(EXTCNF_CTRL, extcnf_ctrl);
607 }
608 
609 static DEFINE_MUTEX(swflag_mutex);
610 
618 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
619 {
620  s32 ret_val;
621 
622  mutex_lock(&swflag_mutex);
623  ret_val = e1000_get_hw_semaphore_82573(hw);
624  if (ret_val)
625  mutex_unlock(&swflag_mutex);
626  return ret_val;
627 }
628 
636 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
637 {
638  e1000_put_hw_semaphore_82573(hw);
639  mutex_unlock(&swflag_mutex);
640 }
641 
654 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
655 {
656  u32 data = er32(POEMB);
657 
658  if (active)
659  data |= E1000_PHY_CTRL_D0A_LPLU;
660  else
661  data &= ~E1000_PHY_CTRL_D0A_LPLU;
662 
663  ew32(POEMB, data);
664  return 0;
665 }
666 
678 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
679 {
680  u32 data = er32(POEMB);
681 
682  if (!active) {
683  data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
684  } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
685  (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
686  (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
687  data |= E1000_PHY_CTRL_NOND0A_LPLU;
688  }
689 
690  ew32(POEMB, data);
691  return 0;
692 }
693 
703 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
704 {
705  s32 ret_val;
706 
707  ret_val = e1000_get_hw_semaphore_82571(hw);
708  if (ret_val)
709  return ret_val;
710 
711  switch (hw->mac.type) {
712  case e1000_82573:
713  break;
714  default:
715  ret_val = e1000e_acquire_nvm(hw);
716  break;
717  }
718 
719  if (ret_val)
720  e1000_put_hw_semaphore_82571(hw);
721 
722  return ret_val;
723 }
724 
731 static void e1000_release_nvm_82571(struct e1000_hw *hw)
732 {
733  e1000e_release_nvm(hw);
734  e1000_put_hw_semaphore_82571(hw);
735 }
736 
749 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
750  u16 *data)
751 {
752  s32 ret_val;
753 
754  switch (hw->mac.type) {
755  case e1000_82573:
756  case e1000_82574:
757  case e1000_82583:
758  ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
759  break;
760  case e1000_82571:
761  case e1000_82572:
762  ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
763  break;
764  default:
765  ret_val = -E1000_ERR_NVM;
766  break;
767  }
768 
769  return ret_val;
770 }
771 
780 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
781 {
782  u32 eecd;
783  s32 ret_val;
784  u16 i;
785 
786  ret_val = e1000e_update_nvm_checksum_generic(hw);
787  if (ret_val)
788  return ret_val;
789 
790  /*
791  * If our nvm is an EEPROM, then we're done
792  * otherwise, commit the checksum to the flash NVM.
793  */
794  if (hw->nvm.type != e1000_nvm_flash_hw)
795  return 0;
796 
797  /* Check for pending operations. */
798  for (i = 0; i < E1000_FLASH_UPDATES; i++) {
799  usleep_range(1000, 2000);
800  if (!(er32(EECD) & E1000_EECD_FLUPD))
801  break;
802  }
803 
804  if (i == E1000_FLASH_UPDATES)
805  return -E1000_ERR_NVM;
806 
807  /* Reset the firmware if using STM opcode. */
808  if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
809  /*
810  * The enabling of and the actual reset must be done
811  * in two write cycles.
812  */
813  ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
814  e1e_flush();
815  ew32(HICR, E1000_HICR_FW_RESET);
816  }
817 
818  /* Commit the write to flash */
819  eecd = er32(EECD) | E1000_EECD_FLUPD;
820  ew32(EECD, eecd);
821 
822  for (i = 0; i < E1000_FLASH_UPDATES; i++) {
823  usleep_range(1000, 2000);
824  if (!(er32(EECD) & E1000_EECD_FLUPD))
825  break;
826  }
827 
828  if (i == E1000_FLASH_UPDATES)
829  return -E1000_ERR_NVM;
830 
831  return 0;
832 }
833 
841 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
842 {
843  if (hw->nvm.type == e1000_nvm_flash_hw)
844  e1000_fix_nvm_checksum_82571(hw);
845 
846  return e1000e_validate_nvm_checksum_generic(hw);
847 }
848 
863 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
864  u16 words, u16 *data)
865 {
866  struct e1000_nvm_info *nvm = &hw->nvm;
867  u32 i, eewr = 0;
868  s32 ret_val = 0;
869 
870  /*
871  * A check for invalid values: offset too large, too many words,
872  * and not enough words.
873  */
874  if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
875  (words == 0)) {
876  e_dbg("nvm parameter(s) out of bounds\n");
877  return -E1000_ERR_NVM;
878  }
879 
880  for (i = 0; i < words; i++) {
881  eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
882  ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
883  E1000_NVM_RW_REG_START;
884 
885  ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
886  if (ret_val)
887  break;
888 
889  ew32(EEWR, eewr);
890 
891  ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
892  if (ret_val)
893  break;
894  }
895 
896  return ret_val;
897 }
898 
905 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
906 {
907  s32 timeout = PHY_CFG_TIMEOUT;
908 
909  while (timeout) {
910  if (er32(EEMNGCTL) &
911  E1000_NVM_CFG_DONE_PORT_0)
912  break;
913  usleep_range(1000, 2000);
914  timeout--;
915  }
916  if (!timeout) {
917  e_dbg("MNG configuration cycle has not completed.\n");
918  return -E1000_ERR_RESET;
919  }
920 
921  return 0;
922 }
923 
935 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
936 {
937  struct e1000_phy_info *phy = &hw->phy;
938  s32 ret_val;
939  u16 data;
940 
941  ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
942  if (ret_val)
943  return ret_val;
944 
945  if (active) {
946  data |= IGP02E1000_PM_D0_LPLU;
947  ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
948  if (ret_val)
949  return ret_val;
950 
951  /* When LPLU is enabled, we should disable SmartSpeed */
952  ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
953  data &= ~IGP01E1000_PSCFR_SMART_SPEED;
954  ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
955  if (ret_val)
956  return ret_val;
957  } else {
958  data &= ~IGP02E1000_PM_D0_LPLU;
959  ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
960  /*
961  * LPLU and SmartSpeed are mutually exclusive. LPLU is used
962  * during Dx states where the power conservation is most
963  * important. During driver activity we should enable
964  * SmartSpeed, so performance is maintained.
965  */
966  if (phy->smart_speed == e1000_smart_speed_on) {
967  ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
968  &data);
969  if (ret_val)
970  return ret_val;
971 
972  data |= IGP01E1000_PSCFR_SMART_SPEED;
973  ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
974  data);
975  if (ret_val)
976  return ret_val;
977  } else if (phy->smart_speed == e1000_smart_speed_off) {
978  ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
979  &data);
980  if (ret_val)
981  return ret_val;
982 
983  data &= ~IGP01E1000_PSCFR_SMART_SPEED;
984  ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
985  data);
986  if (ret_val)
987  return ret_val;
988  }
989  }
990 
991  return 0;
992 }
993 
1000 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1001 {
1002  u32 ctrl, ctrl_ext, eecd, tctl;
1003  s32 ret_val;
1004 
1005  /*
1006  * Prevent the PCI-E bus from sticking if there is no TLP connection
1007  * on the last TLP read/write transaction when MAC is reset.
1008  */
1009  ret_val = e1000e_disable_pcie_master(hw);
1010  if (ret_val)
1011  e_dbg("PCI-E Master disable polling has failed.\n");
1012 
1013  e_dbg("Masking off all interrupts\n");
1014  ew32(IMC, 0xffffffff);
1015 
1016  ew32(RCTL, 0);
1017  tctl = er32(TCTL);
1018  tctl &= ~E1000_TCTL_EN;
1019  ew32(TCTL, tctl);
1020  e1e_flush();
1021 
1022  usleep_range(10000, 20000);
1023 
1024  /*
1025  * Must acquire the MDIO ownership before MAC reset.
1026  * Ownership defaults to firmware after a reset.
1027  */
1028  switch (hw->mac.type) {
1029  case e1000_82573:
1030  ret_val = e1000_get_hw_semaphore_82573(hw);
1031  break;
1032  case e1000_82574:
1033  case e1000_82583:
1034  ret_val = e1000_get_hw_semaphore_82574(hw);
1035  break;
1036  default:
1037  break;
1038  }
1039  if (ret_val)
1040  e_dbg("Cannot acquire MDIO ownership\n");
1041 
1042  ctrl = er32(CTRL);
1043 
1044  e_dbg("Issuing a global reset to MAC\n");
1045  ew32(CTRL, ctrl | E1000_CTRL_RST);
1046 
1047  /* Must release MDIO ownership and mutex after MAC reset. */
1048  switch (hw->mac.type) {
1049  case e1000_82574:
1050  case e1000_82583:
1051  e1000_put_hw_semaphore_82574(hw);
1052  break;
1053  default:
1054  break;
1055  }
1056 
1057  if (hw->nvm.type == e1000_nvm_flash_hw) {
1058  udelay(10);
1059  ctrl_ext = er32(CTRL_EXT);
1060  ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1061  ew32(CTRL_EXT, ctrl_ext);
1062  e1e_flush();
1063  }
1064 
1065  ret_val = e1000e_get_auto_rd_done(hw);
1066  if (ret_val)
1067  /* We don't want to continue accessing MAC registers. */
1068  return ret_val;
1069 
1070  /*
1071  * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1072  * Need to wait for Phy configuration completion before accessing
1073  * NVM and Phy.
1074  */
1075 
1076  switch (hw->mac.type) {
1077  case e1000_82571:
1078  case e1000_82572:
1079  /*
1080  * REQ and GNT bits need to be cleared when using AUTO_RD
1081  * to access the EEPROM.
1082  */
1083  eecd = er32(EECD);
1084  eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1085  ew32(EECD, eecd);
1086  break;
1087  case e1000_82573:
1088  case e1000_82574:
1089  case e1000_82583:
1090  msleep(25);
1091  break;
1092  default:
1093  break;
1094  }
1095 
1096  /* Clear any pending interrupt events. */
1097  ew32(IMC, 0xffffffff);
1098  er32(ICR);
1099 
1100  if (hw->mac.type == e1000_82571) {
1101  /* Install any alternate MAC address into RAR0 */
1102  ret_val = e1000_check_alt_mac_addr_generic(hw);
1103  if (ret_val)
1104  return ret_val;
1105 
1106  e1000e_set_laa_state_82571(hw, true);
1107  }
1108 
1109  /* Reinitialize the 82571 serdes link state machine */
1110  if (hw->phy.media_type == e1000_media_type_internal_serdes)
1111  hw->mac.serdes_link_state = e1000_serdes_link_down;
1112 
1113  return 0;
1114 }
1115 
1122 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1123 {
1124  struct e1000_mac_info *mac = &hw->mac;
1125  u32 reg_data;
1126  s32 ret_val;
1127  u16 i, rar_count = mac->rar_entry_count;
1128 
1129  e1000_initialize_hw_bits_82571(hw);
1130 
1131  /* Initialize identification LED */
1132  ret_val = mac->ops.id_led_init(hw);
1133  if (ret_val)
1134  e_dbg("Error initializing identification LED\n");
1135  /* This is not fatal and we should not stop init due to this */
1136 
1137  /* Disabling VLAN filtering */
1138  e_dbg("Initializing the IEEE VLAN\n");
1139  mac->ops.clear_vfta(hw);
1140 
1141  /* Setup the receive address. */
1142  /*
1143  * If, however, a locally administered address was assigned to the
1144  * 82571, we must reserve a RAR for it to work around an issue where
1145  * resetting one port will reload the MAC on the other port.
1146  */
1147  if (e1000e_get_laa_state_82571(hw))
1148  rar_count--;
1149  e1000e_init_rx_addrs(hw, rar_count);
1150 
1151  /* Zero out the Multicast HASH table */
1152  e_dbg("Zeroing the MTA\n");
1153  for (i = 0; i < mac->mta_reg_count; i++)
1154  E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1155 
1156  /* Setup link and flow control */
1157  ret_val = mac->ops.setup_link(hw);
1158 
1159  /* Set the transmit descriptor write-back policy */
1160  reg_data = er32(TXDCTL(0));
1161  reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1162  E1000_TXDCTL_FULL_TX_DESC_WB |
1163  E1000_TXDCTL_COUNT_DESC;
1164  ew32(TXDCTL(0), reg_data);
1165 
1166  /* ...for both queues. */
1167  switch (mac->type) {
1168  case e1000_82573:
1169  e1000e_enable_tx_pkt_filtering(hw);
1170  /* fall through */
1171  case e1000_82574:
1172  case e1000_82583:
1173  reg_data = er32(GCR);
1174  reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1175  ew32(GCR, reg_data);
1176  break;
1177  default:
1178  reg_data = er32(TXDCTL(1));
1179  reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1180  E1000_TXDCTL_FULL_TX_DESC_WB |
1181  E1000_TXDCTL_COUNT_DESC;
1182  ew32(TXDCTL(1), reg_data);
1183  break;
1184  }
1185 
1186  /*
1187  * Clear all of the statistics registers (clear on read). It is
1188  * important that we do this after we have tried to establish link
1189  * because the symbol error count will increment wildly if there
1190  * is no link.
1191  */
1192  e1000_clear_hw_cntrs_82571(hw);
1193 
1194  return ret_val;
1195 }
1196 
1203 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1204 {
1205  u32 reg;
1206 
1207  /* Transmit Descriptor Control 0 */
1208  reg = er32(TXDCTL(0));
1209  reg |= (1 << 22);
1210  ew32(TXDCTL(0), reg);
1211 
1212  /* Transmit Descriptor Control 1 */
1213  reg = er32(TXDCTL(1));
1214  reg |= (1 << 22);
1215  ew32(TXDCTL(1), reg);
1216 
1217  /* Transmit Arbitration Control 0 */
1218  reg = er32(TARC(0));
1219  reg &= ~(0xF << 27); /* 30:27 */
1220  switch (hw->mac.type) {
1221  case e1000_82571:
1222  case e1000_82572:
1223  reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1224  break;
1225  case e1000_82574:
1226  case e1000_82583:
1227  reg |= (1 << 26);
1228  break;
1229  default:
1230  break;
1231  }
1232  ew32(TARC(0), reg);
1233 
1234  /* Transmit Arbitration Control 1 */
1235  reg = er32(TARC(1));
1236  switch (hw->mac.type) {
1237  case e1000_82571:
1238  case e1000_82572:
1239  reg &= ~((1 << 29) | (1 << 30));
1240  reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1241  if (er32(TCTL) & E1000_TCTL_MULR)
1242  reg &= ~(1 << 28);
1243  else
1244  reg |= (1 << 28);
1245  ew32(TARC(1), reg);
1246  break;
1247  default:
1248  break;
1249  }
1250 
1251  /* Device Control */
1252  switch (hw->mac.type) {
1253  case e1000_82573:
1254  case e1000_82574:
1255  case e1000_82583:
1256  reg = er32(CTRL);
1257  reg &= ~(1 << 29);
1258  ew32(CTRL, reg);
1259  break;
1260  default:
1261  break;
1262  }
1263 
1264  /* Extended Device Control */
1265  switch (hw->mac.type) {
1266  case e1000_82573:
1267  case e1000_82574:
1268  case e1000_82583:
1269  reg = er32(CTRL_EXT);
1270  reg &= ~(1 << 23);
1271  reg |= (1 << 22);
1272  ew32(CTRL_EXT, reg);
1273  break;
1274  default:
1275  break;
1276  }
1277 
1278  if (hw->mac.type == e1000_82571) {
1279  reg = er32(PBA_ECC);
1280  reg |= E1000_PBA_ECC_CORR_EN;
1281  ew32(PBA_ECC, reg);
1282  }
1283 
1284  /*
1285  * Workaround for hardware errata.
1286  * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1287  */
1288  if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
1289  reg = er32(CTRL_EXT);
1290  reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1291  ew32(CTRL_EXT, reg);
1292  }
1293 
1294  /*
1295  * Disable IPv6 extension header parsing because some malformed
1296  * IPv6 headers can hang the Rx.
1297  */
1298  if (hw->mac.type <= e1000_82573) {
1299  reg = er32(RFCTL);
1300  reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1301  ew32(RFCTL, reg);
1302  }
1303 
1304  /* PCI-Ex Control Registers */
1305  switch (hw->mac.type) {
1306  case e1000_82574:
1307  case e1000_82583:
1308  reg = er32(GCR);
1309  reg |= (1 << 22);
1310  ew32(GCR, reg);
1311 
1312  /*
1313  * Workaround for hardware errata.
1314  * apply workaround for hardware errata documented in errata
1315  * docs Fixes issue where some error prone or unreliable PCIe
1316  * completions are occurring, particularly with ASPM enabled.
1317  * Without fix, issue can cause Tx timeouts.
1318  */
1319  reg = er32(GCR2);
1320  reg |= 1;
1321  ew32(GCR2, reg);
1322  break;
1323  default:
1324  break;
1325  }
1326 }
1327 
1335 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1336 {
1337  u32 offset;
1338  u32 vfta_value = 0;
1339  u32 vfta_offset = 0;
1340  u32 vfta_bit_in_reg = 0;
1341 
1342  switch (hw->mac.type) {
1343  case e1000_82573:
1344  case e1000_82574:
1345  case e1000_82583:
1346  if (hw->mng_cookie.vlan_id != 0) {
1347  /*
1348  * The VFTA is a 4096b bit-field, each identifying
1349  * a single VLAN ID. The following operations
1350  * determine which 32b entry (i.e. offset) into the
1351  * array we want to set the VLAN ID (i.e. bit) of
1352  * the manageability unit.
1353  */
1354  vfta_offset = (hw->mng_cookie.vlan_id >>
1355  E1000_VFTA_ENTRY_SHIFT) &
1356  E1000_VFTA_ENTRY_MASK;
1357  vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1358  E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1359  }
1360  break;
1361  default:
1362  break;
1363  }
1364  for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1365  /*
1366  * If the offset we want to clear is the same offset of the
1367  * manageability VLAN ID, then clear all bits except that of
1368  * the manageability unit.
1369  */
1370  vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1371  E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1372  e1e_flush();
1373  }
1374 }
1375 
1383 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1384 {
1385  u16 data;
1386 
1387  e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1388  return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1389 }
1390 
1397 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1398 {
1399  u32 ctrl;
1400  u32 i;
1401 
1402  ctrl = hw->mac.ledctl_mode2;
1403  if (!(E1000_STATUS_LU & er32(STATUS))) {
1404  /*
1405  * If no link, then turn LED on by setting the invert bit
1406  * for each LED that's "on" (0x0E) in ledctl_mode2.
1407  */
1408  for (i = 0; i < 4; i++)
1409  if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1410  E1000_LEDCTL_MODE_LED_ON)
1411  ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1412  }
1413  ew32(LEDCTL, ctrl);
1414 
1415  return 0;
1416 }
1417 
1424 bool e1000_check_phy_82574(struct e1000_hw *hw)
1425 {
1426  u16 status_1kbt = 0;
1427  u16 receive_errors = 0;
1428  s32 ret_val = 0;
1429 
1430  /*
1431  * Read PHY Receive Error counter first, if its is max - all F's then
1432  * read the Base1000T status register If both are max then PHY is hung.
1433  */
1434  ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1435  if (ret_val)
1436  return false;
1437  if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1438  ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1439  if (ret_val)
1440  return false;
1441  if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1442  E1000_IDLE_ERROR_COUNT_MASK)
1443  return true;
1444  }
1445 
1446  return false;
1447 }
1448 
1459 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1460 {
1461  /*
1462  * 82573 does not have a word in the NVM to determine
1463  * the default flow control setting, so we explicitly
1464  * set it to full.
1465  */
1466  switch (hw->mac.type) {
1467  case e1000_82573:
1468  case e1000_82574:
1469  case e1000_82583:
1470  if (hw->fc.requested_mode == e1000_fc_default)
1471  hw->fc.requested_mode = e1000_fc_full;
1472  break;
1473  default:
1474  break;
1475  }
1476 
1477  return e1000e_setup_link_generic(hw);
1478 }
1479 
1488 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1489 {
1490  u32 ctrl;
1491  s32 ret_val;
1492 
1493  ctrl = er32(CTRL);
1494  ctrl |= E1000_CTRL_SLU;
1495  ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1496  ew32(CTRL, ctrl);
1497 
1498  switch (hw->phy.type) {
1499  case e1000_phy_m88:
1500  case e1000_phy_bm:
1501  ret_val = e1000e_copper_link_setup_m88(hw);
1502  break;
1503  case e1000_phy_igp_2:
1504  ret_val = e1000e_copper_link_setup_igp(hw);
1505  break;
1506  default:
1507  return -E1000_ERR_PHY;
1508  break;
1509  }
1510 
1511  if (ret_val)
1512  return ret_val;
1513 
1514  return e1000e_setup_copper_link(hw);
1515 }
1516 
1524 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1525 {
1526  switch (hw->mac.type) {
1527  case e1000_82571:
1528  case e1000_82572:
1529  /*
1530  * If SerDes loopback mode is entered, there is no form
1531  * of reset to take the adapter out of that mode. So we
1532  * have to explicitly take the adapter out of loopback
1533  * mode. This prevents drivers from twiddling their thumbs
1534  * if another tool failed to take it out of loopback mode.
1535  */
1536  ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1537  break;
1538  default:
1539  break;
1540  }
1541 
1542  return e1000e_setup_fiber_serdes_link(hw);
1543 }
1544 
1564 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1565 {
1566  struct e1000_mac_info *mac = &hw->mac;
1567  u32 rxcw;
1568  u32 ctrl;
1569  u32 status;
1570  u32 txcw;
1571  u32 i;
1572  s32 ret_val = 0;
1573 
1574  ctrl = er32(CTRL);
1575  status = er32(STATUS);
1576  rxcw = er32(RXCW);
1577  /* SYNCH bit and IV bit are sticky */
1578  udelay(10);
1579  rxcw = er32(RXCW);
1580 
1581  if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1582 
1583  /* Receiver is synchronized with no invalid bits. */
1584  switch (mac->serdes_link_state) {
1585  case e1000_serdes_link_autoneg_complete:
1586  if (!(status & E1000_STATUS_LU)) {
1587  /*
1588  * We have lost link, retry autoneg before
1589  * reporting link failure
1590  */
1591  mac->serdes_link_state =
1592  e1000_serdes_link_autoneg_progress;
1593  mac->serdes_has_link = false;
1594  e_dbg("AN_UP -> AN_PROG\n");
1595  } else {
1596  mac->serdes_has_link = true;
1597  }
1598  break;
1599 
1600  case e1000_serdes_link_forced_up:
1601  /*
1602  * If we are receiving /C/ ordered sets, re-enable
1603  * auto-negotiation in the TXCW register and disable
1604  * forced link in the Device Control register in an
1605  * attempt to auto-negotiate with our link partner.
1606  */
1607  if (rxcw & E1000_RXCW_C) {
1608  /* Enable autoneg, and unforce link up */
1609  ew32(TXCW, mac->txcw);
1610  ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1611  mac->serdes_link_state =
1612  e1000_serdes_link_autoneg_progress;
1613  mac->serdes_has_link = false;
1614  e_dbg("FORCED_UP -> AN_PROG\n");
1615  } else {
1616  mac->serdes_has_link = true;
1617  }
1618  break;
1619 
1620  case e1000_serdes_link_autoneg_progress:
1621  if (rxcw & E1000_RXCW_C) {
1622  /*
1623  * We received /C/ ordered sets, meaning the
1624  * link partner has autonegotiated, and we can
1625  * trust the Link Up (LU) status bit.
1626  */
1627  if (status & E1000_STATUS_LU) {
1628  mac->serdes_link_state =
1629  e1000_serdes_link_autoneg_complete;
1630  e_dbg("AN_PROG -> AN_UP\n");
1631  mac->serdes_has_link = true;
1632  } else {
1633  /* Autoneg completed, but failed. */
1634  mac->serdes_link_state =
1635  e1000_serdes_link_down;
1636  e_dbg("AN_PROG -> DOWN\n");
1637  }
1638  } else {
1639  /*
1640  * The link partner did not autoneg.
1641  * Force link up and full duplex, and change
1642  * state to forced.
1643  */
1644  ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1645  ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1646  ew32(CTRL, ctrl);
1647 
1648  /* Configure Flow Control after link up. */
1649  ret_val = e1000e_config_fc_after_link_up(hw);
1650  if (ret_val) {
1651  e_dbg("Error config flow control\n");
1652  break;
1653  }
1654  mac->serdes_link_state =
1655  e1000_serdes_link_forced_up;
1656  mac->serdes_has_link = true;
1657  e_dbg("AN_PROG -> FORCED_UP\n");
1658  }
1659  break;
1660 
1661  case e1000_serdes_link_down:
1662  default:
1663  /*
1664  * The link was down but the receiver has now gained
1665  * valid sync, so lets see if we can bring the link
1666  * up.
1667  */
1668  ew32(TXCW, mac->txcw);
1669  ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1670  mac->serdes_link_state =
1671  e1000_serdes_link_autoneg_progress;
1672  mac->serdes_has_link = false;
1673  e_dbg("DOWN -> AN_PROG\n");
1674  break;
1675  }
1676  } else {
1677  if (!(rxcw & E1000_RXCW_SYNCH)) {
1678  mac->serdes_has_link = false;
1679  mac->serdes_link_state = e1000_serdes_link_down;
1680  e_dbg("ANYSTATE -> DOWN\n");
1681  } else {
1682  /*
1683  * Check several times, if SYNCH bit and CONFIG
1684  * bit both are consistently 1 then simply ignore
1685  * the IV bit and restart Autoneg
1686  */
1687  for (i = 0; i < AN_RETRY_COUNT; i++) {
1688  udelay(10);
1689  rxcw = er32(RXCW);
1690  if ((rxcw & E1000_RXCW_SYNCH) &&
1691  (rxcw & E1000_RXCW_C))
1692  continue;
1693 
1694  if (rxcw & E1000_RXCW_IV) {
1695  mac->serdes_has_link = false;
1696  mac->serdes_link_state =
1697  e1000_serdes_link_down;
1698  e_dbg("ANYSTATE -> DOWN\n");
1699  break;
1700  }
1701  }
1702 
1703  if (i == AN_RETRY_COUNT) {
1704  txcw = er32(TXCW);
1705  txcw |= E1000_TXCW_ANE;
1706  ew32(TXCW, txcw);
1707  mac->serdes_link_state =
1708  e1000_serdes_link_autoneg_progress;
1709  mac->serdes_has_link = false;
1710  e_dbg("ANYSTATE -> AN_PROG\n");
1711  }
1712  }
1713  }
1714 
1715  return ret_val;
1716 }
1717 
1726 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1727 {
1728  s32 ret_val;
1729 
1730  ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1731  if (ret_val) {
1732  e_dbg("NVM Read Error\n");
1733  return ret_val;
1734  }
1735 
1736  switch (hw->mac.type) {
1737  case e1000_82573:
1738  case e1000_82574:
1739  case e1000_82583:
1740  if (*data == ID_LED_RESERVED_F746)
1741  *data = ID_LED_DEFAULT_82573;
1742  break;
1743  default:
1744  if (*data == ID_LED_RESERVED_0000 ||
1745  *data == ID_LED_RESERVED_FFFF)
1746  *data = ID_LED_DEFAULT;
1747  break;
1748  }
1749 
1750  return 0;
1751 }
1752 
1759 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1760 {
1761  if (hw->mac.type != e1000_82571)
1762  return false;
1763 
1764  return hw->dev_spec.e82571.laa_is_present;
1765 }
1766 
1774 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1775 {
1776  if (hw->mac.type != e1000_82571)
1777  return;
1778 
1779  hw->dev_spec.e82571.laa_is_present = state;
1780 
1781  /* If workaround is activated... */
1782  if (state)
1783  /*
1784  * Hold a copy of the LAA in RAR[14] This is done so that
1785  * between the time RAR[0] gets clobbered and the time it
1786  * gets fixed, the actual LAA is in one of the RARs and no
1787  * incoming packets directed to this port are dropped.
1788  * Eventually the LAA will be in RAR[0] and RAR[14].
1789  */
1790  hw->mac.ops.rar_set(hw, hw->mac.addr,
1791  hw->mac.rar_entry_count - 1);
1792 }
1793 
1804 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1805 {
1806  struct e1000_nvm_info *nvm = &hw->nvm;
1807  s32 ret_val;
1808  u16 data;
1809 
1810  if (nvm->type != e1000_nvm_flash_hw)
1811  return 0;
1812 
1813  /*
1814  * Check bit 4 of word 10h. If it is 0, firmware is done updating
1815  * 10h-12h. Checksum may need to be fixed.
1816  */
1817  ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1818  if (ret_val)
1819  return ret_val;
1820 
1821  if (!(data & 0x10)) {
1822  /*
1823  * Read 0x23 and check bit 15. This bit is a 1
1824  * when the checksum has already been fixed. If
1825  * the checksum is still wrong and this bit is a
1826  * 1, we need to return bad checksum. Otherwise,
1827  * we need to set this bit to a 1 and update the
1828  * checksum.
1829  */
1830  ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1831  if (ret_val)
1832  return ret_val;
1833 
1834  if (!(data & 0x8000)) {
1835  data |= 0x8000;
1836  ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1837  if (ret_val)
1838  return ret_val;
1839  ret_val = e1000e_update_nvm_checksum(hw);
1840  }
1841  }
1842 
1843  return 0;
1844 }
1845 
1850 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1851 {
1852  if (hw->mac.type == e1000_82571) {
1853  s32 ret_val = 0;
1854 
1855  /*
1856  * If there's an alternate MAC address place it in RAR0
1857  * so that it will override the Si installed default perm
1858  * address.
1859  */
1860  ret_val = e1000_check_alt_mac_addr_generic(hw);
1861  if (ret_val)
1862  return ret_val;
1863  }
1864 
1865  return e1000_read_mac_addr_generic(hw);
1866 }
1867 
1875 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1876 {
1877  struct e1000_phy_info *phy = &hw->phy;
1878  struct e1000_mac_info *mac = &hw->mac;
1879 
1880  if (!phy->ops.check_reset_block)
1881  return;
1882 
1883  /* If the management interface is not enabled, then power down */
1884  if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1885  e1000_power_down_phy_copper(hw);
1886 }
1887 
1894 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1895 {
1896  e1000e_clear_hw_cntrs_base(hw);
1897 
1898  er32(PRC64);
1899  er32(PRC127);
1900  er32(PRC255);
1901  er32(PRC511);
1902  er32(PRC1023);
1903  er32(PRC1522);
1904  er32(PTC64);
1905  er32(PTC127);
1906  er32(PTC255);
1907  er32(PTC511);
1908  er32(PTC1023);
1909  er32(PTC1522);
1910 
1911  er32(ALGNERRC);
1912  er32(RXERRC);
1913  er32(TNCRS);
1914  er32(CEXTERR);
1915  er32(TSCTC);
1916  er32(TSCTFC);
1917 
1918  er32(MGTPRC);
1919  er32(MGTPDC);
1920  er32(MGTPTC);
1921 
1922  er32(IAC);
1923  er32(ICRXOC);
1924 
1925  er32(ICRXPTC);
1926  er32(ICRXATC);
1927  er32(ICTXPTC);
1928  er32(ICTXATC);
1929  er32(ICTXQEC);
1930  er32(ICTXQMTC);
1931  er32(ICRXDMTC);
1932 }
1933 
1934 static const struct e1000_mac_operations e82571_mac_ops = {
1935  /* .check_mng_mode: mac type dependent */
1936  /* .check_for_link: media type dependent */
1937  .id_led_init = e1000e_id_led_init_generic,
1938  .cleanup_led = e1000e_cleanup_led_generic,
1939  .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1940  .get_bus_info = e1000e_get_bus_info_pcie,
1941  .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1942  /* .get_link_up_info: media type dependent */
1943  /* .led_on: mac type dependent */
1944  .led_off = e1000e_led_off_generic,
1945  .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1946  .write_vfta = e1000_write_vfta_generic,
1947  .clear_vfta = e1000_clear_vfta_82571,
1948  .reset_hw = e1000_reset_hw_82571,
1949  .init_hw = e1000_init_hw_82571,
1950  .setup_link = e1000_setup_link_82571,
1951  /* .setup_physical_interface: media type dependent */
1952  .setup_led = e1000e_setup_led_generic,
1953  .config_collision_dist = e1000e_config_collision_dist_generic,
1954  .read_mac_addr = e1000_read_mac_addr_82571,
1955  .rar_set = e1000e_rar_set_generic,
1956 };
1957 
1958 static const struct e1000_phy_operations e82_phy_ops_igp = {
1959  .acquire = e1000_get_hw_semaphore_82571,
1960  .check_polarity = e1000_check_polarity_igp,
1961  .check_reset_block = e1000e_check_reset_block_generic,
1962  .commit = NULL,
1963  .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1964  .get_cfg_done = e1000_get_cfg_done_82571,
1965  .get_cable_length = e1000e_get_cable_length_igp_2,
1966  .get_info = e1000e_get_phy_info_igp,
1967  .read_reg = e1000e_read_phy_reg_igp,
1968  .release = e1000_put_hw_semaphore_82571,
1969  .reset = e1000e_phy_hw_reset_generic,
1970  .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1971  .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1972  .write_reg = e1000e_write_phy_reg_igp,
1973  .cfg_on_link_up = NULL,
1974 };
1975 
1976 static const struct e1000_phy_operations e82_phy_ops_m88 = {
1977  .acquire = e1000_get_hw_semaphore_82571,
1978  .check_polarity = e1000_check_polarity_m88,
1979  .check_reset_block = e1000e_check_reset_block_generic,
1980  .commit = e1000e_phy_sw_reset,
1981  .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1982  .get_cfg_done = e1000e_get_cfg_done,
1983  .get_cable_length = e1000e_get_cable_length_m88,
1984  .get_info = e1000e_get_phy_info_m88,
1985  .read_reg = e1000e_read_phy_reg_m88,
1986  .release = e1000_put_hw_semaphore_82571,
1987  .reset = e1000e_phy_hw_reset_generic,
1988  .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1989  .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1990  .write_reg = e1000e_write_phy_reg_m88,
1991  .cfg_on_link_up = NULL,
1992 };
1993 
1994 static const struct e1000_phy_operations e82_phy_ops_bm = {
1995  .acquire = e1000_get_hw_semaphore_82571,
1996  .check_polarity = e1000_check_polarity_m88,
1997  .check_reset_block = e1000e_check_reset_block_generic,
1998  .commit = e1000e_phy_sw_reset,
1999  .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
2000  .get_cfg_done = e1000e_get_cfg_done,
2001  .get_cable_length = e1000e_get_cable_length_m88,
2002  .get_info = e1000e_get_phy_info_m88,
2003  .read_reg = e1000e_read_phy_reg_bm2,
2004  .release = e1000_put_hw_semaphore_82571,
2005  .reset = e1000e_phy_hw_reset_generic,
2006  .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
2007  .set_d3_lplu_state = e1000e_set_d3_lplu_state,
2008  .write_reg = e1000e_write_phy_reg_bm2,
2009  .cfg_on_link_up = NULL,
2010 };
2011 
2012 static const struct e1000_nvm_operations e82571_nvm_ops = {
2013  .acquire = e1000_acquire_nvm_82571,
2014  .read = e1000e_read_nvm_eerd,
2015  .release = e1000_release_nvm_82571,
2016  .reload = e1000e_reload_nvm_generic,
2017  .update = e1000_update_nvm_checksum_82571,
2018  .valid_led_default = e1000_valid_led_default_82571,
2019  .validate = e1000_validate_nvm_checksum_82571,
2020  .write = e1000_write_nvm_82571,
2021 };
2022 
2023 const struct e1000_info e1000_82571_info = {
2024  .mac = e1000_82571,
2025  .flags = FLAG_HAS_HW_VLAN_FILTER
2026  | FLAG_HAS_JUMBO_FRAMES
2027  | FLAG_HAS_WOL
2028  | FLAG_APME_IN_CTRL3
2029  | FLAG_HAS_CTRLEXT_ON_LOAD
2030  | FLAG_HAS_SMART_POWER_DOWN
2031  | FLAG_RESET_OVERWRITES_LAA /* errata */
2032  | FLAG_TARC_SPEED_MODE_BIT /* errata */
2033  | FLAG_APME_CHECK_PORT_B,
2034  .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
2035  | FLAG2_DMA_BURST,
2036  .pba = 38,
2037  .max_hw_frame_size = DEFAULT_JUMBO,
2038  .get_variants = e1000_get_variants_82571,
2039  .mac_ops = &e82571_mac_ops,
2040  .phy_ops = &e82_phy_ops_igp,
2041  .nvm_ops = &e82571_nvm_ops,
2042 };
2043 
2044 const struct e1000_info e1000_82572_info = {
2045  .mac = e1000_82572,
2046  .flags = FLAG_HAS_HW_VLAN_FILTER
2047  | FLAG_HAS_JUMBO_FRAMES
2048  | FLAG_HAS_WOL
2049  | FLAG_APME_IN_CTRL3
2050  | FLAG_HAS_CTRLEXT_ON_LOAD
2051  | FLAG_TARC_SPEED_MODE_BIT, /* errata */
2052  .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
2053  | FLAG2_DMA_BURST,
2054  .pba = 38,
2055  .max_hw_frame_size = DEFAULT_JUMBO,
2056  .get_variants = e1000_get_variants_82571,
2057  .mac_ops = &e82571_mac_ops,
2058  .phy_ops = &e82_phy_ops_igp,
2059  .nvm_ops = &e82571_nvm_ops,
2060 };
2061 
2062 const struct e1000_info e1000_82573_info = {
2063  .mac = e1000_82573,
2064  .flags = FLAG_HAS_HW_VLAN_FILTER
2065  | FLAG_HAS_WOL
2066  | FLAG_APME_IN_CTRL3
2067  | FLAG_HAS_SMART_POWER_DOWN
2068  | FLAG_HAS_AMT
2069  | FLAG_HAS_SWSM_ON_LOAD,
2070  .flags2 = FLAG2_DISABLE_ASPM_L1
2071  | FLAG2_DISABLE_ASPM_L0S,
2072  .pba = 20,
2073  .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
2074  .get_variants = e1000_get_variants_82571,
2075  .mac_ops = &e82571_mac_ops,
2076  .phy_ops = &e82_phy_ops_m88,
2077  .nvm_ops = &e82571_nvm_ops,
2078 };
2079 
2080 const struct e1000_info e1000_82574_info = {
2081  .mac = e1000_82574,
2082  .flags = FLAG_HAS_HW_VLAN_FILTER
2083  | FLAG_HAS_MSIX
2084  | FLAG_HAS_JUMBO_FRAMES
2085  | FLAG_HAS_WOL
2086  | FLAG_APME_IN_CTRL3
2087  | FLAG_HAS_SMART_POWER_DOWN
2088  | FLAG_HAS_AMT
2089  | FLAG_HAS_CTRLEXT_ON_LOAD,
2090  .flags2 = FLAG2_CHECK_PHY_HANG
2091  | FLAG2_DISABLE_ASPM_L0S
2092  | FLAG2_DISABLE_ASPM_L1
2093  | FLAG2_NO_DISABLE_RX
2094  | FLAG2_DMA_BURST,
2095  .pba = 32,
2096  .max_hw_frame_size = DEFAULT_JUMBO,
2097  .get_variants = e1000_get_variants_82571,
2098  .mac_ops = &e82571_mac_ops,
2099  .phy_ops = &e82_phy_ops_bm,
2100  .nvm_ops = &e82571_nvm_ops,
2101 };
2102 
2103 const struct e1000_info e1000_82583_info = {
2104  .mac = e1000_82583,
2105  .flags = FLAG_HAS_HW_VLAN_FILTER
2106  | FLAG_HAS_WOL
2107  | FLAG_APME_IN_CTRL3
2108  | FLAG_HAS_SMART_POWER_DOWN
2109  | FLAG_HAS_AMT
2110  | FLAG_HAS_JUMBO_FRAMES
2111  | FLAG_HAS_CTRLEXT_ON_LOAD,
2112  .flags2 = FLAG2_DISABLE_ASPM_L0S
2113  | FLAG2_NO_DISABLE_RX,
2114  .pba = 32,
2115  .max_hw_frame_size = DEFAULT_JUMBO,
2116  .get_variants = e1000_get_variants_82571,
2117  .mac_ops = &e82571_mac_ops,
2118  .phy_ops = &e82_phy_ops_bm,
2119  .nvm_ops = &e82571_nvm_ops,
2120 };
2121 
Generated on Thu Jan 10 2013 14:02:11 for Linux Kernel by   doxygen 1.8.2