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| #define | CS8427_BASE_ADDR 0x10 /* base I2C address */ |
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| #define | CS8427_REG_AUTOINC 0x80 /* flag - autoincrement */ |
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| #define | CS8427_REG_CONTROL1 0x01 |
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| #define | CS8427_REG_CONTROL2 0x02 |
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| #define | CS8427_REG_DATAFLOW 0x03 |
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| #define | CS8427_REG_CLOCKSOURCE 0x04 |
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| #define | CS8427_REG_SERIALINPUT 0x05 |
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| #define | CS8427_REG_SERIALOUTPUT 0x06 |
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| #define | CS8427_REG_INT1STATUS 0x07 |
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| #define | CS8427_REG_INT2STATUS 0x08 |
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| #define | CS8427_REG_INT1MASK 0x09 |
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| #define | CS8427_REG_INT1MODEMSB 0x0a |
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| #define | CS8427_REG_INT1MODELSB 0x0b |
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| #define | CS8427_REG_INT2MASK 0x0c |
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| #define | CS8427_REG_INT2MODEMSB 0x0d |
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| #define | CS8427_REG_INT2MODELSB 0x0e |
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| #define | CS8427_REG_RECVCSDATA 0x0f |
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| #define | CS8427_REG_RECVERRORS 0x10 |
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| #define | CS8427_REG_RECVERRMASK 0x11 |
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| #define | CS8427_REG_CSDATABUF 0x12 |
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| #define | CS8427_REG_UDATABUF 0x13 |
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| #define | CS8427_REG_QSUBCODE 0x14 /* 0x14-0x1d (10 bytes) */ |
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| #define | CS8427_REG_OMCKRMCKRATIO 0x1e |
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| #define | CS8427_REG_CORU_DATABUF 0x20 /* 24 byte buffer area */ |
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| #define | CS8427_REG_ID_AND_VER 0x7f |
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| #define | CS8427_SWCLK (1<<7) /* 0 = RMCK default, 1 = OMCK output on RMCK pin */ |
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| #define | CS8427_VSET (1<<6) /* 0 = valid PCM data, 1 = invalid PCM data */ |
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| #define | CS8427_MUTESAO (1<<5) /* mute control for the serial audio output port, 0 = disabled, 1 = enabled */ |
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| #define | CS8427_MUTEAES (1<<4) /* mute control for the AES transmitter output, 0 = disabled, 1 = enabled */ |
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| #define | CS8427_INTMASK (3<<1) /* interrupt output pin setup mask */ |
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| #define | CS8427_INTACTHIGH (0<<1) /* active high */ |
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| #define | CS8427_INTACTLOW (1<<1) /* active low */ |
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| #define | CS8427_INTOPENDRAIN (2<<1) /* open drain, active low */ |
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| #define | CS8427_TCBLDIR (1<<0) /* 0 = TCBL is an input, 1 = TCBL is an output */ |
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| #define | CS8427_HOLDMASK (3<<5) /* action when a receiver error occurs */ |
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| #define | CS8427_HOLDLASTSAMPLE (0<<5) /* hold the last valid sample */ |
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| #define | CS8427_HOLDZERO (1<<5) /* replace the current audio sample with zero (mute) */ |
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| #define | CS8427_HOLDNOCHANGE (2<<5) /* do not change the received audio sample */ |
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| #define | CS8427_RMCKF (1<<4) /* 0 = 256*Fsi, 1 = 128*Fsi */ |
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| #define | CS8427_MMR (1<<3) /* AES3 receiver operation, 0 = stereo, 1 = mono */ |
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| #define | CS8427_MMT (1<<2) /* AES3 transmitter operation, 0 = stereo, 1 = mono */ |
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| #define | CS8427_MMTCS (1<<1) /* 0 = use A + B CS data, 1 = use MMTLR CS data */ |
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| #define | CS8427_MMTLR (1<<0) /* 0 = use A CS data, 1 = use B CS data */ |
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| #define | CS8427_TXOFF (1<<6) /* AES3 transmitter Output, 0 = normal operation, 1 = off (0V) */ |
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| #define | CS8427_AESBP (1<<5) /* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */ |
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| #define | CS8427_TXDMASK (3<<3) /* AES3 Transmitter Data Source Mask */ |
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| #define | CS8427_TXDSERIAL (1<<3) /* TXD - serial audio input port */ |
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| #define | CS8427_TXAES3DRECEIVER (2<<3) /* TXD - AES3 receiver */ |
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| #define | CS8427_SPDMASK (3<<1) /* Serial Audio Output Port Data Source Mask */ |
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| #define | CS8427_SPDSERIAL (1<<1) /* SPD - serial audio input port */ |
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| #define | CS8427_SPDAES3RECEIVER (2<<1) /* SPD - AES3 receiver */ |
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| #define | CS8427_RUN (1<<6) /* 0 = clock off, 1 = clock on */ |
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| #define | CS8427_CLKMASK (3<<4) /* OMCK frequency mask */ |
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| #define | CS8427_CLK256 (0<<4) /* 256*Fso */ |
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| #define | CS8427_CLK384 (1<<4) /* 384*Fso */ |
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| #define | CS8427_CLK512 (2<<4) /* 512*Fso */ |
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| #define | CS8427_OUTC (1<<3) /* Output Time Base, 0 = OMCK, 1 = recovered input clock */ |
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| #define | CS8427_INC (1<<2) /* Input Time Base Clock Source, 0 = recoverd input clock, 1 = OMCK input pin */ |
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| #define | CS8427_RXDMASK (3<<0) /* Recovered Input Clock Source Mask */ |
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| #define | CS8427_RXDILRCK (0<<0) /* 256*Fsi from ILRCK pin */ |
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| #define | CS8427_RXDAES3INPUT (1<<0) /* 256*Fsi from AES3 input */ |
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| #define | CS8427_EXTCLOCKRESET (2<<0) /* bypass PLL, 256*Fsi clock, synchronous reset */ |
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| #define | CS8427_EXTCLOCK (3<<0) /* bypass PLL, 256*Fsi clock */ |
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| #define | CS8427_SIMS (1<<7) /* 0 = slave, 1 = master mode */ |
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| #define | CS8427_SISF (1<<6) /* ISCLK freq, 0 = 64*Fsi, 1 = 128*Fsi */ |
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| #define | CS8427_SIRESMASK (3<<4) /* Resolution of the input data for right justified formats */ |
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| #define | CS8427_SIRES24 (0<<4) /* SIRES 24-bit */ |
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| #define | CS8427_SIRES20 (1<<4) /* SIRES 20-bit */ |
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| #define | CS8427_SIRES16 (2<<4) /* SIRES 16-bit */ |
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| #define | CS8427_SIJUST (1<<3) /* Justification of SDIN data relative to ILRCK, 0 = left-justified, 1 = right-justified */ |
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| #define | CS8427_SIDEL (1<<2) /* Delay of SDIN data relative to ILRCK for left-justified data formats, 0 = first ISCLK period, 1 = second ISCLK period */ |
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| #define | CS8427_SISPOL (1<<1) /* ICLK clock polarity, 0 = rising edge of ISCLK, 1 = falling edge of ISCLK */ |
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| #define | CS8427_SILRPOL (1<<0) /* ILRCK clock polarity, 0 = SDIN data left channel when ILRCK is high, 1 = SDIN right when ILRCK is high */ |
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| #define | CS8427_SOMS (1<<7) /* 0 = slave, 1 = master mode */ |
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| #define | CS8427_SOSF (1<<6) /* OSCLK freq, 0 = 64*Fso, 1 = 128*Fso */ |
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| #define | CS8427_SORESMASK (3<<4) /* Resolution of the output data on SDOUT and AES3 output */ |
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| #define | CS8427_SORES24 (0<<4) /* SIRES 24-bit */ |
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| #define | CS8427_SORES20 (1<<4) /* SIRES 20-bit */ |
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| #define | CS8427_SORES16 (2<<4) /* SIRES 16-bit */ |
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| #define | CS8427_SORESDIRECT (2<<4) /* SIRES direct copy from AES3 receiver */ |
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| #define | CS8427_SOJUST (1<<3) /* Justification of SDOUT data relative to OLRCK, 0 = left-justified, 1 = right-justified */ |
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| #define | CS8427_SODEL (1<<2) /* Delay of SDOUT data relative to OLRCK for left-justified data formats, 0 = first OSCLK period, 1 = second OSCLK period */ |
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| #define | CS8427_SOSPOL (1<<1) /* OSCLK clock polarity, 0 = rising edge of ISCLK, 1 = falling edge of ISCLK */ |
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| #define | CS8427_SOLRPOL (1<<0) /* OLRCK clock polarity, 0 = SDOUT data left channel when OLRCK is high, 1 = SDOUT right when OLRCK is high */ |
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| #define | CS8427_TSLIP (1<<7) /* AES3 transmitter source data slip interrupt */ |
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| #define | CS8427_OSLIP (1<<6) /* Serial audio output port data slip interrupt */ |
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| #define | CS8427_DETC (1<<2) /* D to E C-buffer transfer interrupt */ |
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| #define | CS8427_EFTC (1<<1) /* E to F C-buffer transfer interrupt */ |
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| #define | CS8427_RERR (1<<0) /* A receiver error has occurred */ |
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| #define | CS8427_DETU (1<<3) /* D to E U-buffer transfer interrupt */ |
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| #define | CS8427_EFTU (1<<2) /* E to F U-buffer transfer interrupt */ |
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| #define | CS8427_QCH (1<<1) /* A new block of Q-subcode data is available for reading */ |
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| #define | CS8427_INTMODERISINGMSB 0 |
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| #define | CS8427_INTMODERESINGLSB 0 |
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| #define | CS8427_INTMODEFALLINGMSB 0 |
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| #define | CS8427_INTMODEFALLINGLSB 1 |
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| #define | CS8427_INTMODELEVELMSB 1 |
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| #define | CS8427_INTMODELEVELLSB 0 |
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| #define | CS8427_AUXMASK (15<<4) /* auxiliary data field width */ |
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| #define | CS8427_AUXSHIFT 4 |
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| #define | CS8427_PRO (1<<3) /* Channel status block format indicator */ |
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| #define | CS8427_AUDIO (1<<2) /* Audio indicator (0 = audio, 1 = nonaudio */ |
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| #define | CS8427_COPY (1<<1) /* 0 = copyright asserted, 1 = copyright not asserted */ |
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| #define | CS8427_ORIG (1<<0) /* SCMS generation indicator, 0 = 1st generation or highter, 1 = original */ |
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| #define | CS8427_QCRC (1<<6) /* Q-subcode data CRC error indicator */ |
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| #define | CS8427_CCRC (1<<5) /* Chancnel Status Block Cyclick Redundancy Check Bit */ |
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| #define | CS8427_UNLOCK (1<<4) /* PLL lock status bit */ |
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| #define | CS8427_V (1<<3) /* 0 = valid data */ |
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| #define | CS8427_CONF (1<<2) /* Confidence bit */ |
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| #define | CS8427_BIP (1<<1) /* Bi-phase error bit */ |
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| #define | CS8427_PAR (1<<0) /* Parity error */ |
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| #define | CS8427_BSEL (1<<5) /* 0 = CS data, 1 = U data */ |
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| #define | CS8427_CBMR (1<<4) /* 0 = overwrite first 5 bytes for CS D to E buffer, 1 = prevent */ |
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| #define | CS8427_DETCI (1<<3) /* D to E CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */ |
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| #define | CS8427_EFTCI (1<<2) /* E to F CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */ |
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| #define | CS8427_CAM (1<<1) /* CS data buffer control port access mode bit, 0 = one byte, 1 = two byte */ |
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| #define | CS8427_CHS (1<<0) /* Channel select bit, 0 = Channel A, 1 = Channel B */ |
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| #define | CS8427_UD (1<<4) /* User data pin (U) direction, 0 = input, 1 = output */ |
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| #define | CS8427_UBMMASK (3<<2) /* Operating mode of the AES3 U bit manager */ |
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| #define | CS8427_UBMZEROS (0<<2) /* transmit all zeros mode */ |
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| #define | CS8427_UBMBLOCK (1<<2) /* block mode */ |
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| #define | CS8427_DETUI (1<<1) /* D to E U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */ |
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| #define | CS8427_EFTUI (1<<1) /* E to F U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */ |
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| #define | CS8427_IDMASK (15<<4) |
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| #define | CS8427_IDSHIFT 4 |
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| #define | CS8427_VERMASK (15<<0) |
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| #define | CS8427_VERSHIFT 0 |
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| #define | CS8427_VER8427A 0x71 |
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1.8.2