Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
intel_display.c
Go to the documentation of this file.
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  * Eric Anholt <[email protected]>
25  */
26 
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43 
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45 
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49 
50 typedef struct {
51  /* given values */
52  int n;
53  int m1, m2;
54  int p1, p2;
55  /* derived values */
56  int dot;
57  int vco;
58  int m;
59  int p;
61 
62 typedef struct {
63  int min, max;
65 
66 typedef struct {
67  int dot_limit;
68  int p2_slow, p2_fast;
69 } intel_p2_t;
70 
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
76  bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 };
79 
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82 
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85  int target, int refclk, intel_clock_t *match_clock,
86  intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89  int target, int refclk, intel_clock_t *match_clock,
90  intel_clock_t *best_clock);
91 
92 static bool
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94  int target, int refclk, intel_clock_t *match_clock,
95  intel_clock_t *best_clock);
96 static bool
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98  int target, int refclk, intel_clock_t *match_clock,
99  intel_clock_t *best_clock);
100 
101 static bool
102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103  int target, int refclk, intel_clock_t *match_clock,
104  intel_clock_t *best_clock);
105 
106 static inline u32 /* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device *dev)
108 {
109  if (IS_GEN5(dev)) {
110  struct drm_i915_private *dev_priv = dev->dev_private;
112  } else
113  return 27;
114 }
115 
116 static const intel_limit_t intel_limits_i8xx_dvo = {
117  .dot = { .min = 25000, .max = 350000 },
118  .vco = { .min = 930000, .max = 1400000 },
119  .n = { .min = 3, .max = 16 },
120  .m = { .min = 96, .max = 140 },
121  .m1 = { .min = 18, .max = 26 },
122  .m2 = { .min = 6, .max = 16 },
123  .p = { .min = 4, .max = 128 },
124  .p1 = { .min = 2, .max = 33 },
125  .p2 = { .dot_limit = 165000,
126  .p2_slow = 4, .p2_fast = 2 },
127  .find_pll = intel_find_best_PLL,
128 };
129 
130 static const intel_limit_t intel_limits_i8xx_lvds = {
131  .dot = { .min = 25000, .max = 350000 },
132  .vco = { .min = 930000, .max = 1400000 },
133  .n = { .min = 3, .max = 16 },
134  .m = { .min = 96, .max = 140 },
135  .m1 = { .min = 18, .max = 26 },
136  .m2 = { .min = 6, .max = 16 },
137  .p = { .min = 4, .max = 128 },
138  .p1 = { .min = 1, .max = 6 },
139  .p2 = { .dot_limit = 165000,
140  .p2_slow = 14, .p2_fast = 7 },
141  .find_pll = intel_find_best_PLL,
142 };
143 
144 static const intel_limit_t intel_limits_i9xx_sdvo = {
145  .dot = { .min = 20000, .max = 400000 },
146  .vco = { .min = 1400000, .max = 2800000 },
147  .n = { .min = 1, .max = 6 },
148  .m = { .min = 70, .max = 120 },
149  .m1 = { .min = 10, .max = 22 },
150  .m2 = { .min = 5, .max = 9 },
151  .p = { .min = 5, .max = 80 },
152  .p1 = { .min = 1, .max = 8 },
153  .p2 = { .dot_limit = 200000,
154  .p2_slow = 10, .p2_fast = 5 },
155  .find_pll = intel_find_best_PLL,
156 };
157 
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159  .dot = { .min = 20000, .max = 400000 },
160  .vco = { .min = 1400000, .max = 2800000 },
161  .n = { .min = 1, .max = 6 },
162  .m = { .min = 70, .max = 120 },
163  .m1 = { .min = 10, .max = 22 },
164  .m2 = { .min = 5, .max = 9 },
165  .p = { .min = 7, .max = 98 },
166  .p1 = { .min = 1, .max = 8 },
167  .p2 = { .dot_limit = 112000,
168  .p2_slow = 14, .p2_fast = 7 },
169  .find_pll = intel_find_best_PLL,
170 };
171 
172 
173 static const intel_limit_t intel_limits_g4x_sdvo = {
174  .dot = { .min = 25000, .max = 270000 },
175  .vco = { .min = 1750000, .max = 3500000},
176  .n = { .min = 1, .max = 4 },
177  .m = { .min = 104, .max = 138 },
178  .m1 = { .min = 17, .max = 23 },
179  .m2 = { .min = 5, .max = 11 },
180  .p = { .min = 10, .max = 30 },
181  .p1 = { .min = 1, .max = 3},
182  .p2 = { .dot_limit = 270000,
183  .p2_slow = 10,
184  .p2_fast = 10
185  },
186  .find_pll = intel_g4x_find_best_PLL,
187 };
188 
189 static const intel_limit_t intel_limits_g4x_hdmi = {
190  .dot = { .min = 22000, .max = 400000 },
191  .vco = { .min = 1750000, .max = 3500000},
192  .n = { .min = 1, .max = 4 },
193  .m = { .min = 104, .max = 138 },
194  .m1 = { .min = 16, .max = 23 },
195  .m2 = { .min = 5, .max = 11 },
196  .p = { .min = 5, .max = 80 },
197  .p1 = { .min = 1, .max = 8},
198  .p2 = { .dot_limit = 165000,
199  .p2_slow = 10, .p2_fast = 5 },
200  .find_pll = intel_g4x_find_best_PLL,
201 };
202 
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
204  .dot = { .min = 20000, .max = 115000 },
205  .vco = { .min = 1750000, .max = 3500000 },
206  .n = { .min = 1, .max = 3 },
207  .m = { .min = 104, .max = 138 },
208  .m1 = { .min = 17, .max = 23 },
209  .m2 = { .min = 5, .max = 11 },
210  .p = { .min = 28, .max = 112 },
211  .p1 = { .min = 2, .max = 8 },
212  .p2 = { .dot_limit = 0,
213  .p2_slow = 14, .p2_fast = 14
214  },
215  .find_pll = intel_g4x_find_best_PLL,
216 };
217 
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
219  .dot = { .min = 80000, .max = 224000 },
220  .vco = { .min = 1750000, .max = 3500000 },
221  .n = { .min = 1, .max = 3 },
222  .m = { .min = 104, .max = 138 },
223  .m1 = { .min = 17, .max = 23 },
224  .m2 = { .min = 5, .max = 11 },
225  .p = { .min = 14, .max = 42 },
226  .p1 = { .min = 2, .max = 6 },
227  .p2 = { .dot_limit = 0,
228  .p2_slow = 7, .p2_fast = 7
229  },
230  .find_pll = intel_g4x_find_best_PLL,
231 };
232 
233 static const intel_limit_t intel_limits_g4x_display_port = {
234  .dot = { .min = 161670, .max = 227000 },
235  .vco = { .min = 1750000, .max = 3500000},
236  .n = { .min = 1, .max = 2 },
237  .m = { .min = 97, .max = 108 },
238  .m1 = { .min = 0x10, .max = 0x12 },
239  .m2 = { .min = 0x05, .max = 0x06 },
240  .p = { .min = 10, .max = 20 },
241  .p1 = { .min = 1, .max = 2},
242  .p2 = { .dot_limit = 0,
243  .p2_slow = 10, .p2_fast = 10 },
244  .find_pll = intel_find_pll_g4x_dp,
245 };
246 
247 static const intel_limit_t intel_limits_pineview_sdvo = {
248  .dot = { .min = 20000, .max = 400000},
249  .vco = { .min = 1700000, .max = 3500000 },
250  /* Pineview's Ncounter is a ring counter */
251  .n = { .min = 3, .max = 6 },
252  .m = { .min = 2, .max = 256 },
253  /* Pineview only has one combined m divider, which we treat as m2. */
254  .m1 = { .min = 0, .max = 0 },
255  .m2 = { .min = 0, .max = 254 },
256  .p = { .min = 5, .max = 80 },
257  .p1 = { .min = 1, .max = 8 },
258  .p2 = { .dot_limit = 200000,
259  .p2_slow = 10, .p2_fast = 5 },
260  .find_pll = intel_find_best_PLL,
261 };
262 
263 static const intel_limit_t intel_limits_pineview_lvds = {
264  .dot = { .min = 20000, .max = 400000 },
265  .vco = { .min = 1700000, .max = 3500000 },
266  .n = { .min = 3, .max = 6 },
267  .m = { .min = 2, .max = 256 },
268  .m1 = { .min = 0, .max = 0 },
269  .m2 = { .min = 0, .max = 254 },
270  .p = { .min = 7, .max = 112 },
271  .p1 = { .min = 1, .max = 8 },
272  .p2 = { .dot_limit = 112000,
273  .p2_slow = 14, .p2_fast = 14 },
274  .find_pll = intel_find_best_PLL,
275 };
276 
277 /* Ironlake / Sandybridge
278  *
279  * We calculate clock using (register_value + 2) for N/M1/M2, so here
280  * the range value for them is (actual_value - 2).
281  */
282 static const intel_limit_t intel_limits_ironlake_dac = {
283  .dot = { .min = 25000, .max = 350000 },
284  .vco = { .min = 1760000, .max = 3510000 },
285  .n = { .min = 1, .max = 5 },
286  .m = { .min = 79, .max = 127 },
287  .m1 = { .min = 12, .max = 22 },
288  .m2 = { .min = 5, .max = 9 },
289  .p = { .min = 5, .max = 80 },
290  .p1 = { .min = 1, .max = 8 },
291  .p2 = { .dot_limit = 225000,
292  .p2_slow = 10, .p2_fast = 5 },
293  .find_pll = intel_g4x_find_best_PLL,
294 };
295 
296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
297  .dot = { .min = 25000, .max = 350000 },
298  .vco = { .min = 1760000, .max = 3510000 },
299  .n = { .min = 1, .max = 3 },
300  .m = { .min = 79, .max = 118 },
301  .m1 = { .min = 12, .max = 22 },
302  .m2 = { .min = 5, .max = 9 },
303  .p = { .min = 28, .max = 112 },
304  .p1 = { .min = 2, .max = 8 },
305  .p2 = { .dot_limit = 225000,
306  .p2_slow = 14, .p2_fast = 14 },
307  .find_pll = intel_g4x_find_best_PLL,
308 };
309 
310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
311  .dot = { .min = 25000, .max = 350000 },
312  .vco = { .min = 1760000, .max = 3510000 },
313  .n = { .min = 1, .max = 3 },
314  .m = { .min = 79, .max = 127 },
315  .m1 = { .min = 12, .max = 22 },
316  .m2 = { .min = 5, .max = 9 },
317  .p = { .min = 14, .max = 56 },
318  .p1 = { .min = 2, .max = 8 },
319  .p2 = { .dot_limit = 225000,
320  .p2_slow = 7, .p2_fast = 7 },
321  .find_pll = intel_g4x_find_best_PLL,
322 };
323 
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
326  .dot = { .min = 25000, .max = 350000 },
327  .vco = { .min = 1760000, .max = 3510000 },
328  .n = { .min = 1, .max = 2 },
329  .m = { .min = 79, .max = 126 },
330  .m1 = { .min = 12, .max = 22 },
331  .m2 = { .min = 5, .max = 9 },
332  .p = { .min = 28, .max = 112 },
333  .p1 = { .min = 2, .max = 8 },
334  .p2 = { .dot_limit = 225000,
335  .p2_slow = 14, .p2_fast = 14 },
336  .find_pll = intel_g4x_find_best_PLL,
337 };
338 
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
340  .dot = { .min = 25000, .max = 350000 },
341  .vco = { .min = 1760000, .max = 3510000 },
342  .n = { .min = 1, .max = 3 },
343  .m = { .min = 79, .max = 126 },
344  .m1 = { .min = 12, .max = 22 },
345  .m2 = { .min = 5, .max = 9 },
346  .p = { .min = 14, .max = 42 },
347  .p1 = { .min = 2, .max = 6 },
348  .p2 = { .dot_limit = 225000,
349  .p2_slow = 7, .p2_fast = 7 },
350  .find_pll = intel_g4x_find_best_PLL,
351 };
352 
353 static const intel_limit_t intel_limits_ironlake_display_port = {
354  .dot = { .min = 25000, .max = 350000 },
355  .vco = { .min = 1760000, .max = 3510000},
356  .n = { .min = 1, .max = 2 },
357  .m = { .min = 81, .max = 90 },
358  .m1 = { .min = 12, .max = 22 },
359  .m2 = { .min = 5, .max = 9 },
360  .p = { .min = 10, .max = 20 },
361  .p1 = { .min = 1, .max = 2},
362  .p2 = { .dot_limit = 0,
363  .p2_slow = 10, .p2_fast = 10 },
364  .find_pll = intel_find_pll_ironlake_dp,
365 };
366 
367 static const intel_limit_t intel_limits_vlv_dac = {
368  .dot = { .min = 25000, .max = 270000 },
369  .vco = { .min = 4000000, .max = 6000000 },
370  .n = { .min = 1, .max = 7 },
371  .m = { .min = 22, .max = 450 }, /* guess */
372  .m1 = { .min = 2, .max = 3 },
373  .m2 = { .min = 11, .max = 156 },
374  .p = { .min = 10, .max = 30 },
375  .p1 = { .min = 2, .max = 3 },
376  .p2 = { .dot_limit = 270000,
377  .p2_slow = 2, .p2_fast = 20 },
378  .find_pll = intel_vlv_find_best_pll,
379 };
380 
381 static const intel_limit_t intel_limits_vlv_hdmi = {
382  .dot = { .min = 20000, .max = 165000 },
383  .vco = { .min = 5994000, .max = 4000000 },
384  .n = { .min = 1, .max = 7 },
385  .m = { .min = 60, .max = 300 }, /* guess */
386  .m1 = { .min = 2, .max = 3 },
387  .m2 = { .min = 11, .max = 156 },
388  .p = { .min = 10, .max = 30 },
389  .p1 = { .min = 2, .max = 3 },
390  .p2 = { .dot_limit = 270000,
391  .p2_slow = 2, .p2_fast = 20 },
392  .find_pll = intel_vlv_find_best_pll,
393 };
394 
395 static const intel_limit_t intel_limits_vlv_dp = {
396  .dot = { .min = 162000, .max = 270000 },
397  .vco = { .min = 5994000, .max = 4000000 },
398  .n = { .min = 1, .max = 7 },
399  .m = { .min = 60, .max = 300 }, /* guess */
400  .m1 = { .min = 2, .max = 3 },
401  .m2 = { .min = 11, .max = 156 },
402  .p = { .min = 10, .max = 30 },
403  .p1 = { .min = 2, .max = 3 },
404  .p2 = { .dot_limit = 270000,
405  .p2_slow = 2, .p2_fast = 20 },
406  .find_pll = intel_vlv_find_best_pll,
407 };
408 
409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410 {
411  unsigned long flags;
412  u32 val = 0;
413 
414  spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415  if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416  DRM_ERROR("DPIO idle wait timed out\n");
417  goto out_unlock;
418  }
419 
420  I915_WRITE(DPIO_REG, reg);
422  DPIO_BYTE);
423  if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424  DRM_ERROR("DPIO read wait timed out\n");
425  goto out_unlock;
426  }
427  val = I915_READ(DPIO_DATA);
428 
429 out_unlock:
430  spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431  return val;
432 }
433 
434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435  u32 val)
436 {
437  unsigned long flags;
438 
439  spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440  if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441  DRM_ERROR("DPIO idle wait timed out\n");
442  goto out_unlock;
443  }
444 
445  I915_WRITE(DPIO_DATA, val);
446  I915_WRITE(DPIO_REG, reg);
448  DPIO_BYTE);
449  if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450  DRM_ERROR("DPIO write wait timed out\n");
451 
452 out_unlock:
453  spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454 }
455 
456 static void vlv_init_dpio(struct drm_device *dev)
457 {
458  struct drm_i915_private *dev_priv = dev->dev_private;
459 
460  /* Reset the DPIO config */
461  I915_WRITE(DPIO_CTL, 0);
463  I915_WRITE(DPIO_CTL, 1);
465 }
466 
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468 {
469  DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470  return 1;
471 }
472 
473 static const struct dmi_system_id intel_dual_link_lvds[] = {
474  {
475  .callback = intel_dual_link_lvds_callback,
476  .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477  .matches = {
478  DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479  DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480  },
481  },
482  { } /* terminating entry */
483 };
484 
485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486  unsigned int reg)
487 {
488  unsigned int val;
489 
490  /* use the module option value if specified */
491  if (i915_lvds_channel_mode > 0)
492  return i915_lvds_channel_mode == 2;
493 
494  if (dmi_check_system(intel_dual_link_lvds))
495  return true;
496 
497  if (dev_priv->lvds_val)
498  val = dev_priv->lvds_val;
499  else {
500  /* BIOS should set the proper LVDS register value at boot, but
501  * in reality, it doesn't set the value when the lid is closed;
502  * we need to check "the value to be set" in VBT when LVDS
503  * register is uninitialized.
504  */
505  val = I915_READ(reg);
506  if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
507  val = dev_priv->bios_lvds_val;
508  dev_priv->lvds_val = val;
509  }
510  return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511 }
512 
513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514  int refclk)
515 {
516  struct drm_device *dev = crtc->dev;
517  struct drm_i915_private *dev_priv = dev->dev_private;
518  const intel_limit_t *limit;
519 
521  if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
522  /* LVDS dual channel */
523  if (refclk == 100000)
524  limit = &intel_limits_ironlake_dual_lvds_100m;
525  else
526  limit = &intel_limits_ironlake_dual_lvds;
527  } else {
528  if (refclk == 100000)
529  limit = &intel_limits_ironlake_single_lvds_100m;
530  else
531  limit = &intel_limits_ironlake_single_lvds;
532  }
533  } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
534  HAS_eDP)
535  limit = &intel_limits_ironlake_display_port;
536  else
537  limit = &intel_limits_ironlake_dac;
538 
539  return limit;
540 }
541 
542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543 {
544  struct drm_device *dev = crtc->dev;
545  struct drm_i915_private *dev_priv = dev->dev_private;
546  const intel_limit_t *limit;
547 
549  if (is_dual_link_lvds(dev_priv, LVDS))
550  /* LVDS with dual channel */
551  limit = &intel_limits_g4x_dual_channel_lvds;
552  else
553  /* LVDS with dual channel */
554  limit = &intel_limits_g4x_single_channel_lvds;
555  } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
557  limit = &intel_limits_g4x_hdmi;
558  } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
559  limit = &intel_limits_g4x_sdvo;
560  } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
561  limit = &intel_limits_g4x_display_port;
562  } else /* The option is for other outputs */
563  limit = &intel_limits_i9xx_sdvo;
564 
565  return limit;
566 }
567 
568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
569 {
570  struct drm_device *dev = crtc->dev;
571  const intel_limit_t *limit;
572 
573  if (HAS_PCH_SPLIT(dev))
574  limit = intel_ironlake_limit(crtc, refclk);
575  else if (IS_G4X(dev)) {
576  limit = intel_g4x_limit(crtc);
577  } else if (IS_PINEVIEW(dev)) {
579  limit = &intel_limits_pineview_lvds;
580  else
581  limit = &intel_limits_pineview_sdvo;
582  } else if (IS_VALLEYVIEW(dev)) {
584  limit = &intel_limits_vlv_dac;
585  else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586  limit = &intel_limits_vlv_hdmi;
587  else
588  limit = &intel_limits_vlv_dp;
589  } else if (!IS_GEN2(dev)) {
591  limit = &intel_limits_i9xx_lvds;
592  else
593  limit = &intel_limits_i9xx_sdvo;
594  } else {
596  limit = &intel_limits_i8xx_lvds;
597  else
598  limit = &intel_limits_i8xx_dvo;
599  }
600  return limit;
601 }
602 
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk, intel_clock_t *clock)
605 {
606  clock->m = clock->m2 + 2;
607  clock->p = clock->p1 * clock->p2;
608  clock->vco = refclk * clock->m / clock->n;
609  clock->dot = clock->vco / clock->p;
610 }
611 
612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613 {
614  if (IS_PINEVIEW(dev)) {
615  pineview_clock(refclk, clock);
616  return;
617  }
618  clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619  clock->p = clock->p1 * clock->p2;
620  clock->vco = refclk * clock->m / (clock->n + 2);
621  clock->dot = clock->vco / clock->p;
622 }
623 
627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
628 {
629  struct drm_device *dev = crtc->dev;
630  struct intel_encoder *encoder;
631 
632  for_each_encoder_on_crtc(dev, crtc, encoder)
633  if (encoder->type == type)
634  return true;
635 
636  return false;
637 }
638 
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
640 
645 static bool intel_PLL_is_valid(struct drm_device *dev,
646  const intel_limit_t *limit,
647  const intel_clock_t *clock)
648 {
649  if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
650  INTELPllInvalid("p1 out of range\n");
651  if (clock->p < limit->p.min || limit->p.max < clock->p)
652  INTELPllInvalid("p out of range\n");
653  if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
654  INTELPllInvalid("m2 out of range\n");
655  if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
656  INTELPllInvalid("m1 out of range\n");
657  if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
658  INTELPllInvalid("m1 <= m2\n");
659  if (clock->m < limit->m.min || limit->m.max < clock->m)
660  INTELPllInvalid("m out of range\n");
661  if (clock->n < limit->n.min || limit->n.max < clock->n)
662  INTELPllInvalid("n out of range\n");
663  if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664  INTELPllInvalid("vco out of range\n");
665  /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666  * connector, etc., rather than just a single range.
667  */
668  if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
669  INTELPllInvalid("dot out of range\n");
670 
671  return true;
672 }
673 
674 static bool
675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
676  int target, int refclk, intel_clock_t *match_clock,
677  intel_clock_t *best_clock)
678 
679 {
680  struct drm_device *dev = crtc->dev;
681  struct drm_i915_private *dev_priv = dev->dev_private;
683  int err = target;
684 
686  (I915_READ(LVDS)) != 0) {
687  /*
688  * For LVDS, if the panel is on, just rely on its current
689  * settings for dual-channel. We haven't figured out how to
690  * reliably set up different single/dual channel state, if we
691  * even can.
692  */
693  if (is_dual_link_lvds(dev_priv, LVDS))
694  clock.p2 = limit->p2.p2_fast;
695  else
696  clock.p2 = limit->p2.p2_slow;
697  } else {
698  if (target < limit->p2.dot_limit)
699  clock.p2 = limit->p2.p2_slow;
700  else
701  clock.p2 = limit->p2.p2_fast;
702  }
703 
704  memset(best_clock, 0, sizeof(*best_clock));
705 
706  for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707  clock.m1++) {
708  for (clock.m2 = limit->m2.min;
709  clock.m2 <= limit->m2.max; clock.m2++) {
710  /* m1 is always 0 in Pineview */
711  if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
712  break;
713  for (clock.n = limit->n.min;
714  clock.n <= limit->n.max; clock.n++) {
715  for (clock.p1 = limit->p1.min;
716  clock.p1 <= limit->p1.max; clock.p1++) {
717  int this_err;
718 
719  intel_clock(dev, refclk, &clock);
720  if (!intel_PLL_is_valid(dev, limit,
721  &clock))
722  continue;
723  if (match_clock &&
724  clock.p != match_clock->p)
725  continue;
726 
727  this_err = abs(clock.dot - target);
728  if (this_err < err) {
729  *best_clock = clock;
730  err = this_err;
731  }
732  }
733  }
734  }
735  }
736 
737  return (err != target);
738 }
739 
740 static bool
741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742  int target, int refclk, intel_clock_t *match_clock,
743  intel_clock_t *best_clock)
744 {
745  struct drm_device *dev = crtc->dev;
746  struct drm_i915_private *dev_priv = dev->dev_private;
748  int max_n;
749  bool found;
750  /* approximately equals target * 0.00585 */
751  int err_most = (target >> 8) + (target >> 9);
752  found = false;
753 
755  int lvds_reg;
756 
757  if (HAS_PCH_SPLIT(dev))
758  lvds_reg = PCH_LVDS;
759  else
760  lvds_reg = LVDS;
761  if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
763  clock.p2 = limit->p2.p2_fast;
764  else
765  clock.p2 = limit->p2.p2_slow;
766  } else {
767  if (target < limit->p2.dot_limit)
768  clock.p2 = limit->p2.p2_slow;
769  else
770  clock.p2 = limit->p2.p2_fast;
771  }
772 
773  memset(best_clock, 0, sizeof(*best_clock));
774  max_n = limit->n.max;
775  /* based on hardware requirement, prefer smaller n to precision */
776  for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777  /* based on hardware requirement, prefere larger m1,m2 */
778  for (clock.m1 = limit->m1.max;
779  clock.m1 >= limit->m1.min; clock.m1--) {
780  for (clock.m2 = limit->m2.max;
781  clock.m2 >= limit->m2.min; clock.m2--) {
782  for (clock.p1 = limit->p1.max;
783  clock.p1 >= limit->p1.min; clock.p1--) {
784  int this_err;
785 
786  intel_clock(dev, refclk, &clock);
787  if (!intel_PLL_is_valid(dev, limit,
788  &clock))
789  continue;
790  if (match_clock &&
791  clock.p != match_clock->p)
792  continue;
793 
794  this_err = abs(clock.dot - target);
795  if (this_err < err_most) {
796  *best_clock = clock;
797  err_most = this_err;
798  max_n = clock.n;
799  found = true;
800  }
801  }
802  }
803  }
804  }
805  return found;
806 }
807 
808 static bool
809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
810  int target, int refclk, intel_clock_t *match_clock,
811  intel_clock_t *best_clock)
812 {
813  struct drm_device *dev = crtc->dev;
815 
816  if (target < 200000) {
817  clock.n = 1;
818  clock.p1 = 2;
819  clock.p2 = 10;
820  clock.m1 = 12;
821  clock.m2 = 9;
822  } else {
823  clock.n = 2;
824  clock.p1 = 1;
825  clock.p2 = 10;
826  clock.m1 = 14;
827  clock.m2 = 8;
828  }
829  intel_clock(dev, refclk, &clock);
830  memcpy(best_clock, &clock, sizeof(intel_clock_t));
831  return true;
832 }
833 
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
835 static bool
836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837  int target, int refclk, intel_clock_t *match_clock,
838  intel_clock_t *best_clock)
839 {
841  if (target < 200000) {
842  clock.p1 = 2;
843  clock.p2 = 10;
844  clock.n = 2;
845  clock.m1 = 23;
846  clock.m2 = 8;
847  } else {
848  clock.p1 = 1;
849  clock.p2 = 10;
850  clock.n = 1;
851  clock.m1 = 14;
852  clock.m2 = 2;
853  }
854  clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855  clock.p = (clock.p1 * clock.p2);
856  clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857  clock.vco = 0;
858  memcpy(best_clock, &clock, sizeof(intel_clock_t));
859  return true;
860 }
861 static bool
862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863  int target, int refclk, intel_clock_t *match_clock,
864  intel_clock_t *best_clock)
865 {
866  u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867  u32 m, n, fastclk;
868  u32 updrate, minupdate, fracbits, p;
869  unsigned long bestppm, ppm, absppm;
870  int dotclk, flag;
871 
872  flag = 0;
873  dotclk = target * 1000;
874  bestppm = 1000000;
875  ppm = absppm = 0;
876  fastclk = dotclk / (2*100);
877  updrate = 0;
878  minupdate = 19200;
879  fracbits = 1;
880  n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881  bestm1 = bestm2 = bestp1 = bestp2 = 0;
882 
883  /* based on hardware requirement, prefer smaller n to precision */
884  for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885  updrate = refclk / n;
886  for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887  for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888  if (p2 > 10)
889  p2 = p2 - 1;
890  p = p1 * p2;
891  /* based on hardware requirement, prefer bigger m1,m2 values */
892  for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893  m2 = (((2*(fastclk * p * n / m1 )) +
894  refclk) / (2*refclk));
895  m = m1 * m2;
896  vco = updrate * m;
897  if (vco >= limit->vco.min && vco < limit->vco.max) {
898  ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899  absppm = (ppm > 0) ? ppm : (-ppm);
900  if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901  bestppm = 0;
902  flag = 1;
903  }
904  if (absppm < bestppm - 10) {
905  bestppm = absppm;
906  flag = 1;
907  }
908  if (flag) {
909  bestn = n;
910  bestm1 = m1;
911  bestm2 = m2;
912  bestp1 = p1;
913  bestp2 = p2;
914  flag = 0;
915  }
916  }
917  }
918  }
919  }
920  }
921  best_clock->n = bestn;
922  best_clock->m1 = bestm1;
923  best_clock->m2 = bestm2;
924  best_clock->p1 = bestp1;
925  best_clock->p2 = bestp2;
926 
927  return true;
928 }
929 
930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931 {
932  struct drm_i915_private *dev_priv = dev->dev_private;
933  u32 frame, frame_reg = PIPEFRAME(pipe);
934 
935  frame = I915_READ(frame_reg);
936 
937  if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938  DRM_DEBUG_KMS("vblank wait timed out\n");
939 }
940 
949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
950 {
951  struct drm_i915_private *dev_priv = dev->dev_private;
952  int pipestat_reg = PIPESTAT(pipe);
953 
954  if (INTEL_INFO(dev)->gen >= 5) {
955  ironlake_wait_for_vblank(dev, pipe);
956  return;
957  }
958 
959  /* Clear existing vblank status. Note this will clear any other
960  * sticky status fields as well.
961  *
962  * This races with i915_driver_irq_handler() with the result
963  * that either function could miss a vblank event. Here it is not
964  * fatal, as we will either wait upon the next vblank interrupt or
965  * timeout. Generally speaking intel_wait_for_vblank() is only
966  * called during modeset at which time the GPU should be idle and
967  * should *not* be performing page flips and thus not waiting on
968  * vblanks...
969  * Currently, the result of us stealing a vblank from the irq
970  * handler is that a single frame will be skipped during swapbuffers.
971  */
972  I915_WRITE(pipestat_reg,
973  I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974 
975  /* Wait for vblank interrupt bit to set */
976  if (wait_for(I915_READ(pipestat_reg) &
978  50))
979  DRM_DEBUG_KMS("vblank wait timed out\n");
980 }
981 
982 /*
983  * intel_wait_for_pipe_off - wait for pipe to turn off
984  * @dev: drm device
985  * @pipe: pipe to wait for
986  *
987  * After disabling a pipe, we can't wait for vblank in the usual way,
988  * spinning on the vblank interrupt status bit, since we won't actually
989  * see an interrupt when the pipe is disabled.
990  *
991  * On Gen4 and above:
992  * wait for the pipe register state bit to turn off
993  *
994  * Otherwise:
995  * wait for the display line value to settle (it usually
996  * ends up stopping at the start of the next frame).
997  *
998  */
999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001  struct drm_i915_private *dev_priv = dev->dev_private;
1002 
1003  if (INTEL_INFO(dev)->gen >= 4) {
1004  int reg = PIPECONF(pipe);
1005 
1006  /* Wait for the Pipe State to go off */
1007  if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008  100))
1009  WARN(1, "pipe_off wait timed out\n");
1010  } else {
1011  u32 last_line, line_mask;
1012  int reg = PIPEDSL(pipe);
1013  unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014 
1015  if (IS_GEN2(dev))
1016  line_mask = DSL_LINEMASK_GEN2;
1017  else
1018  line_mask = DSL_LINEMASK_GEN3;
1019 
1020  /* Wait for the display line to settle */
1021  do {
1022  last_line = I915_READ(reg) & line_mask;
1023  mdelay(5);
1024  } while (((I915_READ(reg) & line_mask) != last_line) &&
1025  time_after(timeout, jiffies));
1026  if (time_after(jiffies, timeout))
1027  WARN(1, "pipe_off wait timed out\n");
1028  }
1029 }
1030 
1031 static const char *state_string(bool enabled)
1032 {
1033  return enabled ? "on" : "off";
1034 }
1035 
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038  enum pipe pipe, bool state)
1039 {
1040  int reg;
1041  u32 val;
1042  bool cur_state;
1043 
1044  reg = DPLL(pipe);
1045  val = I915_READ(reg);
1046  cur_state = !!(val & DPLL_VCO_ENABLE);
1047  WARN(cur_state != state,
1048  "PLL state assertion failure (expected %s, current %s)\n",
1049  state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053 
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056  struct intel_pch_pll *pll,
1057  struct intel_crtc *crtc,
1058  bool state)
1059 {
1060  u32 val;
1061  bool cur_state;
1062 
1063  if (HAS_PCH_LPT(dev_priv->dev)) {
1064  DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065  return;
1066  }
1067 
1068  if (WARN (!pll,
1069  "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070  return;
1071 
1072  val = I915_READ(pll->pll_reg);
1073  cur_state = !!(val & DPLL_VCO_ENABLE);
1074  WARN(cur_state != state,
1075  "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076  pll->pll_reg, state_string(state), state_string(cur_state), val);
1077 
1078  /* Make sure the selected PLL is correctly attached to the transcoder */
1079  if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080  u32 pch_dpll;
1081 
1082  pch_dpll = I915_READ(PCH_DPLL_SEL);
1083  cur_state = pll->pll_reg == _PCH_DPLL_B;
1084  if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085  "PLL[%d] not attached to this transcoder %d: %08x\n",
1086  cur_state, crtc->pipe, pch_dpll)) {
1087  cur_state = !!(val >> (4*crtc->pipe + 3));
1088  WARN(cur_state != state,
1089  "PLL[%d] not %s on this transcoder %d: %08x\n",
1090  pll->pll_reg == _PCH_DPLL_B,
1091  state_string(state),
1092  crtc->pipe,
1093  val);
1094  }
1095  }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099 
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101  enum pipe pipe, bool state)
1102 {
1103  int reg;
1104  u32 val;
1105  bool cur_state;
1106 
1107  if (IS_HASWELL(dev_priv->dev)) {
1108  /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109  reg = DDI_FUNC_CTL(pipe);
1110  val = I915_READ(reg);
1111  cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112  } else {
1113  reg = FDI_TX_CTL(pipe);
1114  val = I915_READ(reg);
1115  cur_state = !!(val & FDI_TX_ENABLE);
1116  }
1117  WARN(cur_state != state,
1118  "FDI TX state assertion failure (expected %s, current %s)\n",
1119  state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123 
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125  enum pipe pipe, bool state)
1126 {
1127  int reg;
1128  u32 val;
1129  bool cur_state;
1130 
1131  if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132  DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133  return;
1134  } else {
1135  reg = FDI_RX_CTL(pipe);
1136  val = I915_READ(reg);
1137  cur_state = !!(val & FDI_RX_ENABLE);
1138  }
1139  WARN(cur_state != state,
1140  "FDI RX state assertion failure (expected %s, current %s)\n",
1141  state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145 
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147  enum pipe pipe)
1148 {
1149  int reg;
1150  u32 val;
1151 
1152  /* ILK FDI PLL is always enabled */
1153  if (dev_priv->info->gen == 5)
1154  return;
1155 
1156  /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157  if (IS_HASWELL(dev_priv->dev))
1158  return;
1159 
1160  reg = FDI_TX_CTL(pipe);
1161  val = I915_READ(reg);
1162  WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164 
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166  enum pipe pipe)
1167 {
1168  int reg;
1169  u32 val;
1170 
1171  if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172  DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173  return;
1174  }
1175  reg = FDI_RX_CTL(pipe);
1176  val = I915_READ(reg);
1177  WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179 
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181  enum pipe pipe)
1182 {
1183  int pp_reg, lvds_reg;
1184  u32 val;
1185  enum pipe panel_pipe = PIPE_A;
1186  bool locked = true;
1187 
1188  if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189  pp_reg = PCH_PP_CONTROL;
1190  lvds_reg = PCH_LVDS;
1191  } else {
1192  pp_reg = PP_CONTROL;
1193  lvds_reg = LVDS;
1194  }
1195 
1196  val = I915_READ(pp_reg);
1197  if (!(val & PANEL_POWER_ON) ||
1198  ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199  locked = false;
1200 
1201  if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202  panel_pipe = PIPE_B;
1203 
1204  WARN(panel_pipe == pipe && locked,
1205  "panel assertion failure, pipe %c regs locked\n",
1206  pipe_name(pipe));
1207 }
1208 
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210  enum pipe pipe, bool state)
1211 {
1212  int reg;
1213  u32 val;
1214  bool cur_state;
1215 
1216  /* if we need the pipe A quirk it must be always on */
1217  if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218  state = true;
1219 
1220  reg = PIPECONF(pipe);
1221  val = I915_READ(reg);
1222  cur_state = !!(val & PIPECONF_ENABLE);
1223  WARN(cur_state != state,
1224  "pipe %c assertion failure (expected %s, current %s)\n",
1225  pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227 
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229  enum plane plane, bool state)
1230 {
1231  int reg;
1232  u32 val;
1233  bool cur_state;
1234 
1235  reg = DSPCNTR(plane);
1236  val = I915_READ(reg);
1237  cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238  WARN(cur_state != state,
1239  "plane %c assertion failure (expected %s, current %s)\n",
1240  plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242 
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245 
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247  enum pipe pipe)
1248 {
1249  int reg, i;
1250  u32 val;
1251  int cur_pipe;
1252 
1253  /* Planes are fixed to pipes on ILK+ */
1254  if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255  reg = DSPCNTR(pipe);
1256  val = I915_READ(reg);
1257  WARN((val & DISPLAY_PLANE_ENABLE),
1258  "plane %c assertion failure, should be disabled but not\n",
1259  plane_name(pipe));
1260  return;
1261  }
1262 
1263  /* Need to check both planes against the pipe */
1264  for (i = 0; i < 2; i++) {
1265  reg = DSPCNTR(i);
1266  val = I915_READ(reg);
1267  cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1269  WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270  "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271  plane_name(i), pipe_name(pipe));
1272  }
1273 }
1274 
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277  u32 val;
1278  bool enabled;
1279 
1280  if (HAS_PCH_LPT(dev_priv->dev)) {
1281  DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282  return;
1283  }
1284 
1285  val = I915_READ(PCH_DREF_CONTROL);
1286  enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1288  WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290 
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292  enum pipe pipe)
1293 {
1294  int reg;
1295  u32 val;
1296  bool enabled;
1297 
1298  reg = TRANSCONF(pipe);
1299  val = I915_READ(reg);
1300  enabled = !!(val & TRANS_ENABLE);
1301  WARN(enabled,
1302  "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303  pipe_name(pipe));
1304 }
1305 
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307  enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309  if ((val & DP_PORT_EN) == 0)
1310  return false;
1311 
1312  if (HAS_PCH_CPT(dev_priv->dev)) {
1313  u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314  u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315  if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316  return false;
1317  } else {
1318  if ((val & DP_PIPE_MASK) != (pipe << 30))
1319  return false;
1320  }
1321  return true;
1322 }
1323 
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325  enum pipe pipe, u32 val)
1326 {
1327  if ((val & PORT_ENABLE) == 0)
1328  return false;
1329 
1330  if (HAS_PCH_CPT(dev_priv->dev)) {
1331  if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332  return false;
1333  } else {
1334  if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335  return false;
1336  }
1337  return true;
1338 }
1339 
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341  enum pipe pipe, u32 val)
1342 {
1343  if ((val & LVDS_PORT_EN) == 0)
1344  return false;
1345 
1346  if (HAS_PCH_CPT(dev_priv->dev)) {
1347  if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348  return false;
1349  } else {
1350  if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351  return false;
1352  }
1353  return true;
1354 }
1355 
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357  enum pipe pipe, u32 val)
1358 {
1359  if ((val & ADPA_DAC_ENABLE) == 0)
1360  return false;
1361  if (HAS_PCH_CPT(dev_priv->dev)) {
1362  if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363  return false;
1364  } else {
1365  if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366  return false;
1367  }
1368  return true;
1369 }
1370 
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372  enum pipe pipe, int reg, u32 port_sel)
1373 {
1374  u32 val = I915_READ(reg);
1375  WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376  "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377  reg, pipe_name(pipe));
1378 
1379  WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380  && (val & DP_PIPEB_SELECT),
1381  "IBX PCH dp port still using transcoder B\n");
1382 }
1383 
1384 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1385  enum pipe pipe, int reg)
1386 {
1387  u32 val = I915_READ(reg);
1388  WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1389  "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1390  reg, pipe_name(pipe));
1391 
1392  WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393  && (val & SDVO_PIPE_B_SELECT),
1394  "IBX PCH hdmi port still using transcoder B\n");
1395 }
1396 
1397 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1398  enum pipe pipe)
1399 {
1400  int reg;
1401  u32 val;
1402 
1403  assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1404  assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1405  assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1406 
1407  reg = PCH_ADPA;
1408  val = I915_READ(reg);
1409  WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1410  "PCH VGA enabled on transcoder %c, should be disabled\n",
1411  pipe_name(pipe));
1412 
1413  reg = PCH_LVDS;
1414  val = I915_READ(reg);
1415  WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1416  "PCH LVDS enabled on transcoder %c, should be disabled\n",
1417  pipe_name(pipe));
1418 
1419  assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1420  assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1421  assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1422 }
1423 
1437 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1438 {
1439  int reg;
1440  u32 val;
1441 
1442  /* No really, not for ILK+ */
1443  BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1444 
1445  /* PLL is protected by panel, make sure we can write it */
1446  if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1447  assert_panel_unlocked(dev_priv, pipe);
1448 
1449  reg = DPLL(pipe);
1450  val = I915_READ(reg);
1451  val |= DPLL_VCO_ENABLE;
1452 
1453  /* We do this three times for luck */
1454  I915_WRITE(reg, val);
1455  POSTING_READ(reg);
1456  udelay(150); /* wait for warmup */
1457  I915_WRITE(reg, val);
1458  POSTING_READ(reg);
1459  udelay(150); /* wait for warmup */
1460  I915_WRITE(reg, val);
1461  POSTING_READ(reg);
1462  udelay(150); /* wait for warmup */
1463 }
1464 
1474 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1475 {
1476  int reg;
1477  u32 val;
1478 
1479  /* Don't disable pipe A or pipe A PLLs if needed */
1480  if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1481  return;
1482 
1483  /* Make sure the pipe isn't still relying on us */
1484  assert_pipe_disabled(dev_priv, pipe);
1485 
1486  reg = DPLL(pipe);
1487  val = I915_READ(reg);
1488  val &= ~DPLL_VCO_ENABLE;
1489  I915_WRITE(reg, val);
1490  POSTING_READ(reg);
1491 }
1492 
1493 /* SBI access */
1494 static void
1495 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1496 {
1497  unsigned long flags;
1498 
1499  spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1500  if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1501  100)) {
1502  DRM_ERROR("timeout waiting for SBI to become ready\n");
1503  goto out_unlock;
1504  }
1505 
1507  (reg << 16));
1509  value);
1511  SBI_BUSY |
1512  SBI_CTL_OP_CRWR);
1513 
1514  if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1515  100)) {
1516  DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1517  goto out_unlock;
1518  }
1519 
1520 out_unlock:
1521  spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1522 }
1523 
1524 static u32
1525 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1526 {
1527  unsigned long flags;
1528  u32 value = 0;
1529 
1530  spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1531  if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1532  100)) {
1533  DRM_ERROR("timeout waiting for SBI to become ready\n");
1534  goto out_unlock;
1535  }
1536 
1538  (reg << 16));
1540  SBI_BUSY |
1541  SBI_CTL_OP_CRRD);
1542 
1543  if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1544  100)) {
1545  DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1546  goto out_unlock;
1547  }
1548 
1549  value = I915_READ(SBI_DATA);
1550 
1551 out_unlock:
1552  spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1553  return value;
1554 }
1555 
1564 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1565 {
1566  struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1567  struct intel_pch_pll *pll;
1568  int reg;
1569  u32 val;
1570 
1571  /* PCH PLLs only available on ILK, SNB and IVB */
1572  BUG_ON(dev_priv->info->gen < 5);
1573  pll = intel_crtc->pch_pll;
1574  if (pll == NULL)
1575  return;
1576 
1577  if (WARN_ON(pll->refcount == 0))
1578  return;
1579 
1580  DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1581  pll->pll_reg, pll->active, pll->on,
1582  intel_crtc->base.base.id);
1583 
1584  /* PCH refclock must be enabled first */
1585  assert_pch_refclk_enabled(dev_priv);
1586 
1587  if (pll->active++ && pll->on) {
1588  assert_pch_pll_enabled(dev_priv, pll, NULL);
1589  return;
1590  }
1591 
1592  DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1593 
1594  reg = pll->pll_reg;
1595  val = I915_READ(reg);
1596  val |= DPLL_VCO_ENABLE;
1597  I915_WRITE(reg, val);
1598  POSTING_READ(reg);
1599  udelay(200);
1600 
1601  pll->on = true;
1602 }
1603 
1604 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1605 {
1606  struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1607  struct intel_pch_pll *pll = intel_crtc->pch_pll;
1608  int reg;
1609  u32 val;
1610 
1611  /* PCH only available on ILK+ */
1612  BUG_ON(dev_priv->info->gen < 5);
1613  if (pll == NULL)
1614  return;
1615 
1616  if (WARN_ON(pll->refcount == 0))
1617  return;
1618 
1619  DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1620  pll->pll_reg, pll->active, pll->on,
1621  intel_crtc->base.base.id);
1622 
1623  if (WARN_ON(pll->active == 0)) {
1624  assert_pch_pll_disabled(dev_priv, pll, NULL);
1625  return;
1626  }
1627 
1628  if (--pll->active) {
1629  assert_pch_pll_enabled(dev_priv, pll, NULL);
1630  return;
1631  }
1632 
1633  DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1634 
1635  /* Make sure transcoder isn't still depending on us */
1636  assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1637 
1638  reg = pll->pll_reg;
1639  val = I915_READ(reg);
1640  val &= ~DPLL_VCO_ENABLE;
1641  I915_WRITE(reg, val);
1642  POSTING_READ(reg);
1643  udelay(200);
1644 
1645  pll->on = false;
1646 }
1647 
1648 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1649  enum pipe pipe)
1650 {
1651  int reg;
1652  u32 val, pipeconf_val;
1653  struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1654 
1655  /* PCH only available on ILK+ */
1656  BUG_ON(dev_priv->info->gen < 5);
1657 
1658  /* Make sure PCH DPLL is enabled */
1659  assert_pch_pll_enabled(dev_priv,
1660  to_intel_crtc(crtc)->pch_pll,
1661  to_intel_crtc(crtc));
1662 
1663  /* FDI must be feeding us bits for PCH ports */
1664  assert_fdi_tx_enabled(dev_priv, pipe);
1665  assert_fdi_rx_enabled(dev_priv, pipe);
1666 
1667  if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1668  DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1669  return;
1670  }
1671  reg = TRANSCONF(pipe);
1672  val = I915_READ(reg);
1673  pipeconf_val = I915_READ(PIPECONF(pipe));
1674 
1675  if (HAS_PCH_IBX(dev_priv->dev)) {
1676  /*
1677  * make the BPC in transcoder be consistent with
1678  * that in pipeconf reg.
1679  */
1680  val &= ~PIPE_BPC_MASK;
1681  val |= pipeconf_val & PIPE_BPC_MASK;
1682  }
1683 
1684  val &= ~TRANS_INTERLACE_MASK;
1685  if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1686  if (HAS_PCH_IBX(dev_priv->dev) &&
1689  else
1690  val |= TRANS_INTERLACED;
1691  else
1692  val |= TRANS_PROGRESSIVE;
1693 
1694  I915_WRITE(reg, val | TRANS_ENABLE);
1695  if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696  DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697 }
1698 
1699 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1700  enum pipe pipe)
1701 {
1702  int reg;
1703  u32 val;
1704 
1705  /* FDI relies on the transcoder */
1706  assert_fdi_tx_disabled(dev_priv, pipe);
1707  assert_fdi_rx_disabled(dev_priv, pipe);
1708 
1709  /* Ports must be off as well */
1710  assert_pch_ports_disabled(dev_priv, pipe);
1711 
1712  reg = TRANSCONF(pipe);
1713  val = I915_READ(reg);
1714  val &= ~TRANS_ENABLE;
1715  I915_WRITE(reg, val);
1716  /* wait for PCH transcoder off, transcoder state */
1717  if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1718  DRM_ERROR("failed to disable transcoder %d\n", pipe);
1719 }
1720 
1735 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1736  bool pch_port)
1737 {
1738  int reg;
1739  u32 val;
1740 
1741  /*
1742  * A pipe without a PLL won't actually be able to drive bits from
1743  * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1744  * need the check.
1745  */
1746  if (!HAS_PCH_SPLIT(dev_priv->dev))
1747  assert_pll_enabled(dev_priv, pipe);
1748  else {
1749  if (pch_port) {
1750  /* if driving the PCH, we need FDI enabled */
1751  assert_fdi_rx_pll_enabled(dev_priv, pipe);
1752  assert_fdi_tx_pll_enabled(dev_priv, pipe);
1753  }
1754  /* FIXME: assert CPU port conditions for SNB+ */
1755  }
1756 
1757  reg = PIPECONF(pipe);
1758  val = I915_READ(reg);
1759  if (val & PIPECONF_ENABLE)
1760  return;
1761 
1762  I915_WRITE(reg, val | PIPECONF_ENABLE);
1763  intel_wait_for_vblank(dev_priv->dev, pipe);
1764 }
1765 
1778 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1779  enum pipe pipe)
1780 {
1781  int reg;
1782  u32 val;
1783 
1784  /*
1785  * Make sure planes won't keep trying to pump pixels to us,
1786  * or we might hang the display.
1787  */
1788  assert_planes_disabled(dev_priv, pipe);
1789 
1790  /* Don't disable pipe A or pipe A PLLs if needed */
1791  if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1792  return;
1793 
1794  reg = PIPECONF(pipe);
1795  val = I915_READ(reg);
1796  if ((val & PIPECONF_ENABLE) == 0)
1797  return;
1798 
1799  I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1800  intel_wait_for_pipe_off(dev_priv->dev, pipe);
1801 }
1802 
1803 /*
1804  * Plane regs are double buffered, going from enabled->disabled needs a
1805  * trigger in order to latch. The display address reg provides this.
1806  */
1808  enum plane plane)
1809 {
1810  I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1811  I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1812 }
1813 
1822 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1823  enum plane plane, enum pipe pipe)
1824 {
1825  int reg;
1826  u32 val;
1827 
1828  /* If the pipe isn't enabled, we can't pump pixels and may hang */
1829  assert_pipe_enabled(dev_priv, pipe);
1830 
1831  reg = DSPCNTR(plane);
1832  val = I915_READ(reg);
1833  if (val & DISPLAY_PLANE_ENABLE)
1834  return;
1835 
1836  I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1837  intel_flush_display_plane(dev_priv, plane);
1838  intel_wait_for_vblank(dev_priv->dev, pipe);
1839 }
1840 
1849 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1850  enum plane plane, enum pipe pipe)
1851 {
1852  int reg;
1853  u32 val;
1854 
1855  reg = DSPCNTR(plane);
1856  val = I915_READ(reg);
1857  if ((val & DISPLAY_PLANE_ENABLE) == 0)
1858  return;
1859 
1860  I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1861  intel_flush_display_plane(dev_priv, plane);
1862  intel_wait_for_vblank(dev_priv->dev, pipe);
1863 }
1864 
1865 int
1867  struct drm_i915_gem_object *obj,
1868  struct intel_ring_buffer *pipelined)
1869 {
1870  struct drm_i915_private *dev_priv = dev->dev_private;
1871  u32 alignment;
1872  int ret;
1873 
1874  switch (obj->tiling_mode) {
1875  case I915_TILING_NONE:
1876  if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1877  alignment = 128 * 1024;
1878  else if (INTEL_INFO(dev)->gen >= 4)
1879  alignment = 4 * 1024;
1880  else
1881  alignment = 64 * 1024;
1882  break;
1883  case I915_TILING_X:
1884  /* pin() will align the object as required by fence */
1885  alignment = 0;
1886  break;
1887  case I915_TILING_Y:
1888  /* FIXME: Is this true? */
1889  DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1890  return -EINVAL;
1891  default:
1892  BUG();
1893  }
1894 
1895  dev_priv->mm.interruptible = false;
1896  ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1897  if (ret)
1898  goto err_interruptible;
1899 
1900  /* Install a fence for tiled scan-out. Pre-i965 always needs a
1901  * fence, whereas 965+ only requires a fence if using
1902  * framebuffer compression. For simplicity, we always install
1903  * a fence as the cost is not that onerous.
1904  */
1905  ret = i915_gem_object_get_fence(obj);
1906  if (ret)
1907  goto err_unpin;
1908 
1909  i915_gem_object_pin_fence(obj);
1910 
1911  dev_priv->mm.interruptible = true;
1912  return 0;
1913 
1914 err_unpin:
1915  i915_gem_object_unpin(obj);
1916 err_interruptible:
1917  dev_priv->mm.interruptible = true;
1918  return ret;
1919 }
1920 
1922 {
1923  i915_gem_object_unpin_fence(obj);
1924  i915_gem_object_unpin(obj);
1925 }
1926 
1927 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1928  * is assumed to be a power-of-two. */
1929 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1930  unsigned int bpp,
1931  unsigned int pitch)
1932 {
1933  int tile_rows, tiles;
1934 
1935  tile_rows = *y / 8;
1936  *y %= 8;
1937  tiles = *x / (512/bpp);
1938  *x %= 512/bpp;
1939 
1940  return tile_rows * pitch * 8 + tiles * 4096;
1941 }
1942 
1943 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944  int x, int y)
1945 {
1946  struct drm_device *dev = crtc->dev;
1947  struct drm_i915_private *dev_priv = dev->dev_private;
1948  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949  struct intel_framebuffer *intel_fb;
1950  struct drm_i915_gem_object *obj;
1951  int plane = intel_crtc->plane;
1952  unsigned long linear_offset;
1953  u32 dspcntr;
1954  u32 reg;
1955 
1956  switch (plane) {
1957  case 0:
1958  case 1:
1959  break;
1960  default:
1961  DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1962  return -EINVAL;
1963  }
1964 
1965  intel_fb = to_intel_framebuffer(fb);
1966  obj = intel_fb->obj;
1967 
1968  reg = DSPCNTR(plane);
1969  dspcntr = I915_READ(reg);
1970  /* Mask out pixel format bits in case we change it */
1971  dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972  switch (fb->bits_per_pixel) {
1973  case 8:
1974  dspcntr |= DISPPLANE_8BPP;
1975  break;
1976  case 16:
1977  if (fb->depth == 15)
1978  dspcntr |= DISPPLANE_15_16BPP;
1979  else
1980  dspcntr |= DISPPLANE_16BPP;
1981  break;
1982  case 24:
1983  case 32:
1984  dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1985  break;
1986  default:
1987  DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1988  return -EINVAL;
1989  }
1990  if (INTEL_INFO(dev)->gen >= 4) {
1991  if (obj->tiling_mode != I915_TILING_NONE)
1992  dspcntr |= DISPPLANE_TILED;
1993  else
1994  dspcntr &= ~DISPPLANE_TILED;
1995  }
1996 
1997  I915_WRITE(reg, dspcntr);
1998 
1999  linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2000 
2001  if (INTEL_INFO(dev)->gen >= 4) {
2002  intel_crtc->dspaddr_offset =
2003  gen4_compute_dspaddr_offset_xtiled(&x, &y,
2004  fb->bits_per_pixel / 8,
2005  fb->pitches[0]);
2006  linear_offset -= intel_crtc->dspaddr_offset;
2007  } else {
2008  intel_crtc->dspaddr_offset = linear_offset;
2009  }
2010 
2011  DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2012  obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2013  I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2014  if (INTEL_INFO(dev)->gen >= 4) {
2016  obj->gtt_offset + intel_crtc->dspaddr_offset);
2017  I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2018  I915_WRITE(DSPLINOFF(plane), linear_offset);
2019  } else
2020  I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2021  POSTING_READ(reg);
2022 
2023  return 0;
2024 }
2025 
2026 static int ironlake_update_plane(struct drm_crtc *crtc,
2027  struct drm_framebuffer *fb, int x, int y)
2028 {
2029  struct drm_device *dev = crtc->dev;
2030  struct drm_i915_private *dev_priv = dev->dev_private;
2031  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032  struct intel_framebuffer *intel_fb;
2033  struct drm_i915_gem_object *obj;
2034  int plane = intel_crtc->plane;
2035  unsigned long linear_offset;
2036  u32 dspcntr;
2037  u32 reg;
2038 
2039  switch (plane) {
2040  case 0:
2041  case 1:
2042  case 2:
2043  break;
2044  default:
2045  DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2046  return -EINVAL;
2047  }
2048 
2049  intel_fb = to_intel_framebuffer(fb);
2050  obj = intel_fb->obj;
2051 
2052  reg = DSPCNTR(plane);
2053  dspcntr = I915_READ(reg);
2054  /* Mask out pixel format bits in case we change it */
2055  dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056  switch (fb->bits_per_pixel) {
2057  case 8:
2058  dspcntr |= DISPPLANE_8BPP;
2059  break;
2060  case 16:
2061  if (fb->depth != 16)
2062  return -EINVAL;
2063 
2064  dspcntr |= DISPPLANE_16BPP;
2065  break;
2066  case 24:
2067  case 32:
2068  if (fb->depth == 24)
2069  dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2070  else if (fb->depth == 30)
2071  dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2072  else
2073  return -EINVAL;
2074  break;
2075  default:
2076  DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2077  return -EINVAL;
2078  }
2079 
2080  if (obj->tiling_mode != I915_TILING_NONE)
2081  dspcntr |= DISPPLANE_TILED;
2082  else
2083  dspcntr &= ~DISPPLANE_TILED;
2084 
2085  /* must disable */
2086  dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2087 
2088  I915_WRITE(reg, dspcntr);
2089 
2090  linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2091  intel_crtc->dspaddr_offset =
2092  gen4_compute_dspaddr_offset_xtiled(&x, &y,
2093  fb->bits_per_pixel / 8,
2094  fb->pitches[0]);
2095  linear_offset -= intel_crtc->dspaddr_offset;
2096 
2097  DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2098  obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2099  I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2101  obj->gtt_offset + intel_crtc->dspaddr_offset);
2102  I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2103  I915_WRITE(DSPLINOFF(plane), linear_offset);
2104  POSTING_READ(reg);
2105 
2106  return 0;
2107 }
2108 
2109 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2110 static int
2111 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112  int x, int y, enum mode_set_atomic state)
2113 {
2114  struct drm_device *dev = crtc->dev;
2115  struct drm_i915_private *dev_priv = dev->dev_private;
2116 
2117  if (dev_priv->display.disable_fbc)
2118  dev_priv->display.disable_fbc(dev);
2119  intel_increase_pllclock(crtc);
2120 
2121  return dev_priv->display.update_plane(crtc, fb, x, y);
2122 }
2123 
2124 static int
2125 intel_finish_fb(struct drm_framebuffer *old_fb)
2126 {
2127  struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2128  struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2129  bool was_interruptible = dev_priv->mm.interruptible;
2130  int ret;
2131 
2132  wait_event(dev_priv->pending_flip_queue,
2133  atomic_read(&dev_priv->mm.wedged) ||
2134  atomic_read(&obj->pending_flip) == 0);
2135 
2136  /* Big Hammer, we also need to ensure that any pending
2137  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2138  * current scanout is retired before unpinning the old
2139  * framebuffer.
2140  *
2141  * This should only fail upon a hung GPU, in which case we
2142  * can safely continue.
2143  */
2144  dev_priv->mm.interruptible = false;
2145  ret = i915_gem_object_finish_gpu(obj);
2146  dev_priv->mm.interruptible = was_interruptible;
2147 
2148  return ret;
2149 }
2150 
2151 static int
2152 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2153  struct drm_framebuffer *fb)
2154 {
2155  struct drm_device *dev = crtc->dev;
2156  struct drm_i915_private *dev_priv = dev->dev_private;
2157  struct drm_i915_master_private *master_priv;
2158  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2159  struct drm_framebuffer *old_fb;
2160  int ret;
2161 
2162  /* no fb bound */
2163  if (!fb) {
2164  DRM_ERROR("No FB bound\n");
2165  return 0;
2166  }
2167 
2168  if(intel_crtc->plane > dev_priv->num_pipe) {
2169  DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2170  intel_crtc->plane,
2171  dev_priv->num_pipe);
2172  return -EINVAL;
2173  }
2174 
2175  mutex_lock(&dev->struct_mutex);
2176  ret = intel_pin_and_fence_fb_obj(dev,
2177  to_intel_framebuffer(fb)->obj,
2178  NULL);
2179  if (ret != 0) {
2180  mutex_unlock(&dev->struct_mutex);
2181  DRM_ERROR("pin & fence failed\n");
2182  return ret;
2183  }
2184 
2185  if (crtc->fb)
2186  intel_finish_fb(crtc->fb);
2187 
2188  ret = dev_priv->display.update_plane(crtc, fb, x, y);
2189  if (ret) {
2191  mutex_unlock(&dev->struct_mutex);
2192  DRM_ERROR("failed to update base address\n");
2193  return ret;
2194  }
2195 
2196  old_fb = crtc->fb;
2197  crtc->fb = fb;
2198  crtc->x = x;
2199  crtc->y = y;
2200 
2201  if (old_fb) {
2202  intel_wait_for_vblank(dev, intel_crtc->pipe);
2204  }
2205 
2206  intel_update_fbc(dev);
2207  mutex_unlock(&dev->struct_mutex);
2208 
2209  if (!dev->primary->master)
2210  return 0;
2211 
2212  master_priv = dev->primary->master->driver_priv;
2213  if (!master_priv->sarea_priv)
2214  return 0;
2215 
2216  if (intel_crtc->pipe) {
2217  master_priv->sarea_priv->pipeB_x = x;
2218  master_priv->sarea_priv->pipeB_y = y;
2219  } else {
2220  master_priv->sarea_priv->pipeA_x = x;
2221  master_priv->sarea_priv->pipeA_y = y;
2222  }
2223 
2224  return 0;
2225 }
2226 
2227 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2228 {
2229  struct drm_device *dev = crtc->dev;
2230  struct drm_i915_private *dev_priv = dev->dev_private;
2231  u32 dpa_ctl;
2232 
2233  DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2234  dpa_ctl = I915_READ(DP_A);
2235  dpa_ctl &= ~DP_PLL_FREQ_MASK;
2236 
2237  if (clock < 200000) {
2238  u32 temp;
2239  dpa_ctl |= DP_PLL_FREQ_160MHZ;
2240  /* workaround for 160Mhz:
2241  1) program 0x4600c bits 15:0 = 0x8124
2242  2) program 0x46010 bit 0 = 1
2243  3) program 0x46034 bit 24 = 1
2244  4) program 0x64000 bit 14 = 1
2245  */
2246  temp = I915_READ(0x4600c);
2247  temp &= 0xffff0000;
2248  I915_WRITE(0x4600c, temp | 0x8124);
2249 
2250  temp = I915_READ(0x46010);
2251  I915_WRITE(0x46010, temp | 1);
2252 
2253  temp = I915_READ(0x46034);
2254  I915_WRITE(0x46034, temp | (1 << 24));
2255  } else {
2256  dpa_ctl |= DP_PLL_FREQ_270MHZ;
2257  }
2258  I915_WRITE(DP_A, dpa_ctl);
2259 
2260  POSTING_READ(DP_A);
2261  udelay(500);
2262 }
2263 
2264 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2265 {
2266  struct drm_device *dev = crtc->dev;
2267  struct drm_i915_private *dev_priv = dev->dev_private;
2268  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269  int pipe = intel_crtc->pipe;
2270  u32 reg, temp;
2271 
2272  /* enable normal train */
2273  reg = FDI_TX_CTL(pipe);
2274  temp = I915_READ(reg);
2275  if (IS_IVYBRIDGE(dev)) {
2276  temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2278  } else {
2279  temp &= ~FDI_LINK_TRAIN_NONE;
2281  }
2282  I915_WRITE(reg, temp);
2283 
2284  reg = FDI_RX_CTL(pipe);
2285  temp = I915_READ(reg);
2286  if (HAS_PCH_CPT(dev)) {
2288  temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2289  } else {
2290  temp &= ~FDI_LINK_TRAIN_NONE;
2291  temp |= FDI_LINK_TRAIN_NONE;
2292  }
2294 
2295  /* wait one idle pattern time */
2296  POSTING_READ(reg);
2297  udelay(1000);
2298 
2299  /* IVB wants error correction enabled */
2300  if (IS_IVYBRIDGE(dev))
2303 }
2304 
2305 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2306 {
2307  struct drm_i915_private *dev_priv = dev->dev_private;
2308  u32 flags = I915_READ(SOUTH_CHICKEN1);
2309 
2310  flags |= FDI_PHASE_SYNC_OVR(pipe);
2311  I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2312  flags |= FDI_PHASE_SYNC_EN(pipe);
2313  I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2315 }
2316 
2317 /* The FDI link training functions for ILK/Ibexpeak. */
2318 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2319 {
2320  struct drm_device *dev = crtc->dev;
2321  struct drm_i915_private *dev_priv = dev->dev_private;
2322  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323  int pipe = intel_crtc->pipe;
2324  int plane = intel_crtc->plane;
2325  u32 reg, temp, tries;
2326 
2327  /* FDI needs bits from pipe & plane first */
2328  assert_pipe_enabled(dev_priv, pipe);
2329  assert_plane_enabled(dev_priv, plane);
2330 
2331  /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2332  for train result */
2333  reg = FDI_RX_IMR(pipe);
2334  temp = I915_READ(reg);
2335  temp &= ~FDI_RX_SYMBOL_LOCK;
2336  temp &= ~FDI_RX_BIT_LOCK;
2337  I915_WRITE(reg, temp);
2338  I915_READ(reg);
2339  udelay(150);
2340 
2341  /* enable CPU FDI TX and PCH FDI RX */
2342  reg = FDI_TX_CTL(pipe);
2343  temp = I915_READ(reg);
2344  temp &= ~(7 << 19);
2345  temp |= (intel_crtc->fdi_lanes - 1) << 19;
2346  temp &= ~FDI_LINK_TRAIN_NONE;
2347  temp |= FDI_LINK_TRAIN_PATTERN_1;
2348  I915_WRITE(reg, temp | FDI_TX_ENABLE);
2349 
2350  reg = FDI_RX_CTL(pipe);
2351  temp = I915_READ(reg);
2352  temp &= ~FDI_LINK_TRAIN_NONE;
2353  temp |= FDI_LINK_TRAIN_PATTERN_1;
2354  I915_WRITE(reg, temp | FDI_RX_ENABLE);
2355 
2356  POSTING_READ(reg);
2357  udelay(150);
2358 
2359  /* Ironlake workaround, enable clock pointer after FDI enable*/
2360  if (HAS_PCH_IBX(dev)) {
2364  }
2365 
2366  reg = FDI_RX_IIR(pipe);
2367  for (tries = 0; tries < 5; tries++) {
2368  temp = I915_READ(reg);
2369  DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2370 
2371  if ((temp & FDI_RX_BIT_LOCK)) {
2372  DRM_DEBUG_KMS("FDI train 1 done.\n");
2373  I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2374  break;
2375  }
2376  }
2377  if (tries == 5)
2378  DRM_ERROR("FDI train 1 fail!\n");
2379 
2380  /* Train 2 */
2381  reg = FDI_TX_CTL(pipe);
2382  temp = I915_READ(reg);
2383  temp &= ~FDI_LINK_TRAIN_NONE;
2384  temp |= FDI_LINK_TRAIN_PATTERN_2;
2385  I915_WRITE(reg, temp);
2386 
2387  reg = FDI_RX_CTL(pipe);
2388  temp = I915_READ(reg);
2389  temp &= ~FDI_LINK_TRAIN_NONE;
2390  temp |= FDI_LINK_TRAIN_PATTERN_2;
2391  I915_WRITE(reg, temp);
2392 
2393  POSTING_READ(reg);
2394  udelay(150);
2395 
2396  reg = FDI_RX_IIR(pipe);
2397  for (tries = 0; tries < 5; tries++) {
2398  temp = I915_READ(reg);
2399  DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2400 
2401  if (temp & FDI_RX_SYMBOL_LOCK) {
2402  I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2403  DRM_DEBUG_KMS("FDI train 2 done.\n");
2404  break;
2405  }
2406  }
2407  if (tries == 5)
2408  DRM_ERROR("FDI train 2 fail!\n");
2409 
2410  DRM_DEBUG_KMS("FDI train done\n");
2411 
2412 }
2413 
2414 static const int snb_b_fdi_train_param[] = {
2419 };
2420 
2421 /* The FDI link training functions for SNB/Cougarpoint. */
2422 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2423 {
2424  struct drm_device *dev = crtc->dev;
2425  struct drm_i915_private *dev_priv = dev->dev_private;
2426  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2427  int pipe = intel_crtc->pipe;
2428  u32 reg, temp, i, retry;
2429 
2430  /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431  for train result */
2432  reg = FDI_RX_IMR(pipe);
2433  temp = I915_READ(reg);
2434  temp &= ~FDI_RX_SYMBOL_LOCK;
2435  temp &= ~FDI_RX_BIT_LOCK;
2436  I915_WRITE(reg, temp);
2437 
2438  POSTING_READ(reg);
2439  udelay(150);
2440 
2441  /* enable CPU FDI TX and PCH FDI RX */
2442  reg = FDI_TX_CTL(pipe);
2443  temp = I915_READ(reg);
2444  temp &= ~(7 << 19);
2445  temp |= (intel_crtc->fdi_lanes - 1) << 19;
2446  temp &= ~FDI_LINK_TRAIN_NONE;
2447  temp |= FDI_LINK_TRAIN_PATTERN_1;
2448  temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2449  /* SNB-B */
2451  I915_WRITE(reg, temp | FDI_TX_ENABLE);
2452 
2453  reg = FDI_RX_CTL(pipe);
2454  temp = I915_READ(reg);
2455  if (HAS_PCH_CPT(dev)) {
2458  } else {
2459  temp &= ~FDI_LINK_TRAIN_NONE;
2460  temp |= FDI_LINK_TRAIN_PATTERN_1;
2461  }
2462  I915_WRITE(reg, temp | FDI_RX_ENABLE);
2463 
2464  POSTING_READ(reg);
2465  udelay(150);
2466 
2467  if (HAS_PCH_CPT(dev))
2468  cpt_phase_pointer_enable(dev, pipe);
2469 
2470  for (i = 0; i < 4; i++) {
2471  reg = FDI_TX_CTL(pipe);
2472  temp = I915_READ(reg);
2473  temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2474  temp |= snb_b_fdi_train_param[i];
2475  I915_WRITE(reg, temp);
2476 
2477  POSTING_READ(reg);
2478  udelay(500);
2479 
2480  for (retry = 0; retry < 5; retry++) {
2481  reg = FDI_RX_IIR(pipe);
2482  temp = I915_READ(reg);
2483  DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484  if (temp & FDI_RX_BIT_LOCK) {
2485  I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2486  DRM_DEBUG_KMS("FDI train 1 done.\n");
2487  break;
2488  }
2489  udelay(50);
2490  }
2491  if (retry < 5)
2492  break;
2493  }
2494  if (i == 4)
2495  DRM_ERROR("FDI train 1 fail!\n");
2496 
2497  /* Train 2 */
2498  reg = FDI_TX_CTL(pipe);
2499  temp = I915_READ(reg);
2500  temp &= ~FDI_LINK_TRAIN_NONE;
2501  temp |= FDI_LINK_TRAIN_PATTERN_2;
2502  if (IS_GEN6(dev)) {
2503  temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2504  /* SNB-B */
2506  }
2507  I915_WRITE(reg, temp);
2508 
2509  reg = FDI_RX_CTL(pipe);
2510  temp = I915_READ(reg);
2511  if (HAS_PCH_CPT(dev)) {
2514  } else {
2515  temp &= ~FDI_LINK_TRAIN_NONE;
2516  temp |= FDI_LINK_TRAIN_PATTERN_2;
2517  }
2518  I915_WRITE(reg, temp);
2519 
2520  POSTING_READ(reg);
2521  udelay(150);
2522 
2523  for (i = 0; i < 4; i++) {
2524  reg = FDI_TX_CTL(pipe);
2525  temp = I915_READ(reg);
2526  temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527  temp |= snb_b_fdi_train_param[i];
2528  I915_WRITE(reg, temp);
2529 
2530  POSTING_READ(reg);
2531  udelay(500);
2532 
2533  for (retry = 0; retry < 5; retry++) {
2534  reg = FDI_RX_IIR(pipe);
2535  temp = I915_READ(reg);
2536  DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537  if (temp & FDI_RX_SYMBOL_LOCK) {
2538  I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539  DRM_DEBUG_KMS("FDI train 2 done.\n");
2540  break;
2541  }
2542  udelay(50);
2543  }
2544  if (retry < 5)
2545  break;
2546  }
2547  if (i == 4)
2548  DRM_ERROR("FDI train 2 fail!\n");
2549 
2550  DRM_DEBUG_KMS("FDI train done.\n");
2551 }
2552 
2553 /* Manual link training for Ivy Bridge A0 parts */
2554 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2555 {
2556  struct drm_device *dev = crtc->dev;
2557  struct drm_i915_private *dev_priv = dev->dev_private;
2558  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559  int pipe = intel_crtc->pipe;
2560  u32 reg, temp, i;
2561 
2562  /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2563  for train result */
2564  reg = FDI_RX_IMR(pipe);
2565  temp = I915_READ(reg);
2566  temp &= ~FDI_RX_SYMBOL_LOCK;
2567  temp &= ~FDI_RX_BIT_LOCK;
2568  I915_WRITE(reg, temp);
2569 
2570  POSTING_READ(reg);
2571  udelay(150);
2572 
2573  /* enable CPU FDI TX and PCH FDI RX */
2574  reg = FDI_TX_CTL(pipe);
2575  temp = I915_READ(reg);
2576  temp &= ~(7 << 19);
2577  temp |= (intel_crtc->fdi_lanes - 1) << 19;
2580  temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582  temp |= FDI_COMPOSITE_SYNC;
2583  I915_WRITE(reg, temp | FDI_TX_ENABLE);
2584 
2585  reg = FDI_RX_CTL(pipe);
2586  temp = I915_READ(reg);
2587  temp &= ~FDI_LINK_TRAIN_AUTO;
2590  temp |= FDI_COMPOSITE_SYNC;
2591  I915_WRITE(reg, temp | FDI_RX_ENABLE);
2592 
2593  POSTING_READ(reg);
2594  udelay(150);
2595 
2596  if (HAS_PCH_CPT(dev))
2597  cpt_phase_pointer_enable(dev, pipe);
2598 
2599  for (i = 0; i < 4; i++) {
2600  reg = FDI_TX_CTL(pipe);
2601  temp = I915_READ(reg);
2602  temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603  temp |= snb_b_fdi_train_param[i];
2604  I915_WRITE(reg, temp);
2605 
2606  POSTING_READ(reg);
2607  udelay(500);
2608 
2609  reg = FDI_RX_IIR(pipe);
2610  temp = I915_READ(reg);
2611  DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2612 
2613  if (temp & FDI_RX_BIT_LOCK ||
2614  (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2615  I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2616  DRM_DEBUG_KMS("FDI train 1 done.\n");
2617  break;
2618  }
2619  }
2620  if (i == 4)
2621  DRM_ERROR("FDI train 1 fail!\n");
2622 
2623  /* Train 2 */
2624  reg = FDI_TX_CTL(pipe);
2625  temp = I915_READ(reg);
2626  temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2628  temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2630  I915_WRITE(reg, temp);
2631 
2632  reg = FDI_RX_CTL(pipe);
2633  temp = I915_READ(reg);
2636  I915_WRITE(reg, temp);
2637 
2638  POSTING_READ(reg);
2639  udelay(150);
2640 
2641  for (i = 0; i < 4; i++) {
2642  reg = FDI_TX_CTL(pipe);
2643  temp = I915_READ(reg);
2644  temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645  temp |= snb_b_fdi_train_param[i];
2646  I915_WRITE(reg, temp);
2647 
2648  POSTING_READ(reg);
2649  udelay(500);
2650 
2651  reg = FDI_RX_IIR(pipe);
2652  temp = I915_READ(reg);
2653  DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2654 
2655  if (temp & FDI_RX_SYMBOL_LOCK) {
2656  I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657  DRM_DEBUG_KMS("FDI train 2 done.\n");
2658  break;
2659  }
2660  }
2661  if (i == 4)
2662  DRM_ERROR("FDI train 2 fail!\n");
2663 
2664  DRM_DEBUG_KMS("FDI train done.\n");
2665 }
2666 
2667 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2668 {
2669  struct drm_device *dev = intel_crtc->base.dev;
2670  struct drm_i915_private *dev_priv = dev->dev_private;
2671  int pipe = intel_crtc->pipe;
2672  u32 reg, temp;
2673 
2674  /* Write the TU size bits so error detection works */
2675  I915_WRITE(FDI_RX_TUSIZE1(pipe),
2677 
2678  /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2679  reg = FDI_RX_CTL(pipe);
2680  temp = I915_READ(reg);
2681  temp &= ~((0x7 << 19) | (0x7 << 16));
2682  temp |= (intel_crtc->fdi_lanes - 1) << 19;
2683  temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2684  I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2685 
2686  POSTING_READ(reg);
2687  udelay(200);
2688 
2689  /* Switch from Rawclk to PCDclk */
2690  temp = I915_READ(reg);
2691  I915_WRITE(reg, temp | FDI_PCDCLK);
2692 
2693  POSTING_READ(reg);
2694  udelay(200);
2695 
2696  /* On Haswell, the PLL configuration for ports and pipes is handled
2697  * separately, as part of DDI setup */
2698  if (!IS_HASWELL(dev)) {
2699  /* Enable CPU FDI TX PLL, always on for Ironlake */
2700  reg = FDI_TX_CTL(pipe);
2701  temp = I915_READ(reg);
2702  if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2703  I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2704 
2705  POSTING_READ(reg);
2706  udelay(100);
2707  }
2708  }
2709 }
2710 
2711 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2712 {
2713  struct drm_device *dev = intel_crtc->base.dev;
2714  struct drm_i915_private *dev_priv = dev->dev_private;
2715  int pipe = intel_crtc->pipe;
2716  u32 reg, temp;
2717 
2718  /* Switch from PCDclk to Rawclk */
2719  reg = FDI_RX_CTL(pipe);
2720  temp = I915_READ(reg);
2721  I915_WRITE(reg, temp & ~FDI_PCDCLK);
2722 
2723  /* Disable CPU FDI TX PLL */
2724  reg = FDI_TX_CTL(pipe);
2725  temp = I915_READ(reg);
2726  I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2727 
2728  POSTING_READ(reg);
2729  udelay(100);
2730 
2731  reg = FDI_RX_CTL(pipe);
2732  temp = I915_READ(reg);
2733  I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2734 
2735  /* Wait for the clocks to turn off. */
2736  POSTING_READ(reg);
2737  udelay(100);
2738 }
2739 
2740 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2741 {
2742  struct drm_i915_private *dev_priv = dev->dev_private;
2743  u32 flags = I915_READ(SOUTH_CHICKEN1);
2744 
2745  flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2746  I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2747  flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2748  I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2750 }
2751 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2752 {
2753  struct drm_device *dev = crtc->dev;
2754  struct drm_i915_private *dev_priv = dev->dev_private;
2755  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756  int pipe = intel_crtc->pipe;
2757  u32 reg, temp;
2758 
2759  /* disable CPU FDI tx and PCH FDI rx */
2760  reg = FDI_TX_CTL(pipe);
2761  temp = I915_READ(reg);
2762  I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2763  POSTING_READ(reg);
2764 
2765  reg = FDI_RX_CTL(pipe);
2766  temp = I915_READ(reg);
2767  temp &= ~(0x7 << 16);
2768  temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2769  I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2770 
2771  POSTING_READ(reg);
2772  udelay(100);
2773 
2774  /* Ironlake workaround, disable clock pointer after downing FDI */
2775  if (HAS_PCH_IBX(dev)) {
2777  I915_WRITE(FDI_RX_CHICKEN(pipe),
2778  I915_READ(FDI_RX_CHICKEN(pipe) &
2780  } else if (HAS_PCH_CPT(dev)) {
2781  cpt_phase_pointer_disable(dev, pipe);
2782  }
2783 
2784  /* still set train pattern 1 */
2785  reg = FDI_TX_CTL(pipe);
2786  temp = I915_READ(reg);
2787  temp &= ~FDI_LINK_TRAIN_NONE;
2788  temp |= FDI_LINK_TRAIN_PATTERN_1;
2789  I915_WRITE(reg, temp);
2790 
2791  reg = FDI_RX_CTL(pipe);
2792  temp = I915_READ(reg);
2793  if (HAS_PCH_CPT(dev)) {
2796  } else {
2797  temp &= ~FDI_LINK_TRAIN_NONE;
2798  temp |= FDI_LINK_TRAIN_PATTERN_1;
2799  }
2800  /* BPC in FDI rx is consistent with that in PIPECONF */
2801  temp &= ~(0x07 << 16);
2802  temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2803  I915_WRITE(reg, temp);
2804 
2805  POSTING_READ(reg);
2806  udelay(100);
2807 }
2808 
2809 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2810 {
2811  struct drm_device *dev = crtc->dev;
2812  struct drm_i915_private *dev_priv = dev->dev_private;
2813  unsigned long flags;
2814  bool pending;
2815 
2816  if (atomic_read(&dev_priv->mm.wedged))
2817  return false;
2818 
2819  spin_lock_irqsave(&dev->event_lock, flags);
2820  pending = to_intel_crtc(crtc)->unpin_work != NULL;
2821  spin_unlock_irqrestore(&dev->event_lock, flags);
2822 
2823  return pending;
2824 }
2825 
2826 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2827 {
2828  struct drm_device *dev = crtc->dev;
2829  struct drm_i915_private *dev_priv = dev->dev_private;
2830 
2831  if (crtc->fb == NULL)
2832  return;
2833 
2834  wait_event(dev_priv->pending_flip_queue,
2835  !intel_crtc_has_pending_flip(crtc));
2836 
2837  mutex_lock(&dev->struct_mutex);
2838  intel_finish_fb(crtc->fb);
2839  mutex_unlock(&dev->struct_mutex);
2840 }
2841 
2842 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2843 {
2844  struct drm_device *dev = crtc->dev;
2845  struct intel_encoder *intel_encoder;
2846 
2847  /*
2848  * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2849  * must be driven by its own crtc; no sharing is possible.
2850  */
2851  for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2852 
2853  /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2854  * CPU handles all others */
2855  if (IS_HASWELL(dev)) {
2856  /* It is still unclear how this will work on PPT, so throw up a warning */
2857  WARN_ON(!HAS_PCH_LPT(dev));
2858 
2859  if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2860  DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2861  return true;
2862  } else {
2863  DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2864  intel_encoder->type);
2865  return false;
2866  }
2867  }
2868 
2869  switch (intel_encoder->type) {
2870  case INTEL_OUTPUT_EDP:
2871  if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2872  return false;
2873  continue;
2874  }
2875  }
2876 
2877  return true;
2878 }
2879 
2880 /* Program iCLKIP clock to the desired frequency */
2881 static void lpt_program_iclkip(struct drm_crtc *crtc)
2882 {
2883  struct drm_device *dev = crtc->dev;
2884  struct drm_i915_private *dev_priv = dev->dev_private;
2885  u32 divsel, phaseinc, auxdiv, phasedir = 0;
2886  u32 temp;
2887 
2888  /* It is necessary to ungate the pixclk gate prior to programming
2889  * the divisors, and gate it back when it is done.
2890  */
2892 
2893  /* Disable SSCCTL */
2894  intel_sbi_write(dev_priv, SBI_SSCCTL6,
2895  intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2897 
2898  /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2899  if (crtc->mode.clock == 20000) {
2900  auxdiv = 1;
2901  divsel = 0x41;
2902  phaseinc = 0x20;
2903  } else {
2904  /* The iCLK virtual clock root frequency is in MHz,
2905  * but the crtc->mode.clock in in KHz. To get the divisors,
2906  * it is necessary to divide one by another, so we
2907  * convert the virtual clock precision to KHz here for higher
2908  * precision.
2909  */
2910  u32 iclk_virtual_root_freq = 172800 * 1000;
2911  u32 iclk_pi_range = 64;
2912  u32 desired_divisor, msb_divisor_value, pi_value;
2913 
2914  desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2915  msb_divisor_value = desired_divisor / iclk_pi_range;
2916  pi_value = desired_divisor % iclk_pi_range;
2917 
2918  auxdiv = 0;
2919  divsel = msb_divisor_value - 2;
2920  phaseinc = pi_value;
2921  }
2922 
2923  /* This should not happen with any sane values */
2926  WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2928 
2929  DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2930  crtc->mode.clock,
2931  auxdiv,
2932  divsel,
2933  phasedir,
2934  phaseinc);
2935 
2936  /* Program SSCDIVINTPHASE6 */
2937  temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2939  temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2941  temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2942  temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2944 
2945  intel_sbi_write(dev_priv,
2947  temp);
2948 
2949  /* Program SSCAUXDIV */
2950  temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2951  temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2952  temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2953  intel_sbi_write(dev_priv,
2955  temp);
2956 
2957 
2958  /* Enable modulator and associated divider */
2959  temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2960  temp &= ~SBI_SSCCTL_DISABLE;
2961  intel_sbi_write(dev_priv,
2962  SBI_SSCCTL6,
2963  temp);
2964 
2965  /* Wait for initialization time */
2966  udelay(24);
2967 
2969 }
2970 
2971 /*
2972  * Enable PCH resources required for PCH ports:
2973  * - PCH PLLs
2974  * - FDI training & RX/TX
2975  * - update transcoder timings
2976  * - DP transcoding bits
2977  * - transcoder
2978  */
2979 static void ironlake_pch_enable(struct drm_crtc *crtc)
2980 {
2981  struct drm_device *dev = crtc->dev;
2982  struct drm_i915_private *dev_priv = dev->dev_private;
2983  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2984  int pipe = intel_crtc->pipe;
2985  u32 reg, temp;
2986 
2987  assert_transcoder_disabled(dev_priv, pipe);
2988 
2989  /* For PCH output, training FDI link */
2990  dev_priv->display.fdi_link_train(crtc);
2991 
2992  intel_enable_pch_pll(intel_crtc);
2993 
2994  if (HAS_PCH_LPT(dev)) {
2995  DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2996  lpt_program_iclkip(crtc);
2997  } else if (HAS_PCH_CPT(dev)) {
2998  u32 sel;
2999 
3000  temp = I915_READ(PCH_DPLL_SEL);
3001  switch (pipe) {
3002  default:
3003  case 0:
3004  temp |= TRANSA_DPLL_ENABLE;
3005  sel = TRANSA_DPLLB_SEL;
3006  break;
3007  case 1:
3008  temp |= TRANSB_DPLL_ENABLE;
3009  sel = TRANSB_DPLLB_SEL;
3010  break;
3011  case 2:
3012  temp |= TRANSC_DPLL_ENABLE;
3013  sel = TRANSC_DPLLB_SEL;
3014  break;
3015  }
3016  if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3017  temp |= sel;
3018  else
3019  temp &= ~sel;
3020  I915_WRITE(PCH_DPLL_SEL, temp);
3021  }
3022 
3023  /* set transcoder timing, panel must allow it */
3024  assert_panel_unlocked(dev_priv, pipe);
3025  I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3026  I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3027  I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3028 
3029  I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3030  I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3031  I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3033 
3034  if (!IS_HASWELL(dev))
3035  intel_fdi_normal_train(crtc);
3036 
3037  /* For PCH DP, enable TRANS_DP_CTL */
3038  if (HAS_PCH_CPT(dev) &&
3041  u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3042  reg = TRANS_DP_CTL(pipe);
3043  temp = I915_READ(reg);
3044  temp &= ~(TRANS_DP_PORT_SEL_MASK |
3047  temp |= (TRANS_DP_OUTPUT_ENABLE |
3049  temp |= bpc << 9; /* same format but at 11:9 */
3050 
3051  if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3053  if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3055 
3056  switch (intel_trans_dp_port_sel(crtc)) {
3057  case PCH_DP_B:
3058  temp |= TRANS_DP_PORT_SEL_B;
3059  break;
3060  case PCH_DP_C:
3061  temp |= TRANS_DP_PORT_SEL_C;
3062  break;
3063  case PCH_DP_D:
3064  temp |= TRANS_DP_PORT_SEL_D;
3065  break;
3066  default:
3067  DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3068  temp |= TRANS_DP_PORT_SEL_B;
3069  break;
3070  }
3071 
3072  I915_WRITE(reg, temp);
3073  }
3074 
3075  intel_enable_transcoder(dev_priv, pipe);
3076 }
3077 
3078 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3079 {
3080  struct intel_pch_pll *pll = intel_crtc->pch_pll;
3081 
3082  if (pll == NULL)
3083  return;
3084 
3085  if (pll->refcount == 0) {
3086  WARN(1, "bad PCH PLL refcount\n");
3087  return;
3088  }
3089 
3090  --pll->refcount;
3091  intel_crtc->pch_pll = NULL;
3092 }
3093 
3094 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3095 {
3096  struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3097  struct intel_pch_pll *pll;
3098  int i;
3099 
3100  pll = intel_crtc->pch_pll;
3101  if (pll) {
3102  DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3103  intel_crtc->base.base.id, pll->pll_reg);
3104  goto prepare;
3105  }
3106 
3107  if (HAS_PCH_IBX(dev_priv->dev)) {
3108  /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3109  i = intel_crtc->pipe;
3110  pll = &dev_priv->pch_plls[i];
3111 
3112  DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3113  intel_crtc->base.base.id, pll->pll_reg);
3114 
3115  goto found;
3116  }
3117 
3118  for (i = 0; i < dev_priv->num_pch_pll; i++) {
3119  pll = &dev_priv->pch_plls[i];
3120 
3121  /* Only want to check enabled timings first */
3122  if (pll->refcount == 0)
3123  continue;
3124 
3125  if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3126  fp == I915_READ(pll->fp0_reg)) {
3127  DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3128  intel_crtc->base.base.id,
3129  pll->pll_reg, pll->refcount, pll->active);
3130 
3131  goto found;
3132  }
3133  }
3134 
3135  /* Ok no matching timings, maybe there's a free one? */
3136  for (i = 0; i < dev_priv->num_pch_pll; i++) {
3137  pll = &dev_priv->pch_plls[i];
3138  if (pll->refcount == 0) {
3139  DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3140  intel_crtc->base.base.id, pll->pll_reg);
3141  goto found;
3142  }
3143  }
3144 
3145  return NULL;
3146 
3147 found:
3148  intel_crtc->pch_pll = pll;
3149  pll->refcount++;
3150  DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3151 prepare: /* separate function? */
3152  DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3153 
3154  /* Wait for the clocks to stabilize before rewriting the regs */
3155  I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3156  POSTING_READ(pll->pll_reg);
3157  udelay(150);
3158 
3159  I915_WRITE(pll->fp0_reg, fp);
3160  I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3161  pll->on = false;
3162  return pll;
3163 }
3164 
3165 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3166 {
3167  struct drm_i915_private *dev_priv = dev->dev_private;
3168  int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3169  u32 temp;
3170 
3171  temp = I915_READ(dslreg);
3172  udelay(500);
3173  if (wait_for(I915_READ(dslreg) != temp, 5)) {
3174  /* Without this, mode sets may fail silently on FDI */
3176  udelay(250);
3177  I915_WRITE(tc2reg, 0);
3178  if (wait_for(I915_READ(dslreg) != temp, 5))
3179  DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3180  }
3181 }
3182 
3183 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3184 {
3185  struct drm_device *dev = crtc->dev;
3186  struct drm_i915_private *dev_priv = dev->dev_private;
3187  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3188  struct intel_encoder *encoder;
3189  int pipe = intel_crtc->pipe;
3190  int plane = intel_crtc->plane;
3191  u32 temp;
3192  bool is_pch_port;
3193 
3194  WARN_ON(!crtc->enabled);
3195 
3196  if (intel_crtc->active)
3197  return;
3198 
3199  intel_crtc->active = true;
3201 
3203  temp = I915_READ(PCH_LVDS);
3204  if ((temp & LVDS_PORT_EN) == 0)
3205  I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3206  }
3207 
3208  is_pch_port = intel_crtc_driving_pch(crtc);
3209 
3210  if (is_pch_port) {
3211  ironlake_fdi_pll_enable(intel_crtc);
3212  } else {
3213  assert_fdi_tx_disabled(dev_priv, pipe);
3214  assert_fdi_rx_disabled(dev_priv, pipe);
3215  }
3216 
3217  for_each_encoder_on_crtc(dev, crtc, encoder)
3218  if (encoder->pre_enable)
3219  encoder->pre_enable(encoder);
3220 
3221  /* Enable panel fitting for LVDS */
3222  if (dev_priv->pch_pf_size &&
3224  /* Force use of hard-coded filter coefficients
3225  * as some pre-programmed values are broken,
3226  * e.g. x201.
3227  */
3229  I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3230  I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3231  }
3232 
3233  /*
3234  * On ILK+ LUT must be loaded before the pipe is running but with
3235  * clocks enabled
3236  */
3237  intel_crtc_load_lut(crtc);
3238 
3239  intel_enable_pipe(dev_priv, pipe, is_pch_port);
3240  intel_enable_plane(dev_priv, plane, pipe);
3241 
3242  if (is_pch_port)
3243  ironlake_pch_enable(crtc);
3244 
3245  mutex_lock(&dev->struct_mutex);
3246  intel_update_fbc(dev);
3247  mutex_unlock(&dev->struct_mutex);
3248 
3249  intel_crtc_update_cursor(crtc, true);
3250 
3251  for_each_encoder_on_crtc(dev, crtc, encoder)
3252  encoder->enable(encoder);
3253 
3254  if (HAS_PCH_CPT(dev))
3255  intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3256 
3257  /*
3258  * There seems to be a race in PCH platform hw (at least on some
3259  * outputs) where an enabled pipe still completes any pageflip right
3260  * away (as if the pipe is off) instead of waiting for vblank. As soon
3261  * as the first vblank happend, everything works as expected. Hence just
3262  * wait for one vblank before returning to avoid strange things
3263  * happening.
3264  */
3265  intel_wait_for_vblank(dev, intel_crtc->pipe);
3266 }
3267 
3268 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3269 {
3270  struct drm_device *dev = crtc->dev;
3271  struct drm_i915_private *dev_priv = dev->dev_private;
3272  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3273  struct intel_encoder *encoder;
3274  int pipe = intel_crtc->pipe;
3275  int plane = intel_crtc->plane;
3276  u32 reg, temp;
3277 
3278 
3279  if (!intel_crtc->active)
3280  return;
3281 
3282  for_each_encoder_on_crtc(dev, crtc, encoder)
3283  encoder->disable(encoder);
3284 
3285  intel_crtc_wait_for_pending_flips(crtc);
3286  drm_vblank_off(dev, pipe);
3287  intel_crtc_update_cursor(crtc, false);
3288 
3289  intel_disable_plane(dev_priv, plane, pipe);
3290 
3291  if (dev_priv->cfb_plane == plane)
3292  intel_disable_fbc(dev);
3293 
3294  intel_disable_pipe(dev_priv, pipe);
3295 
3296  /* Disable PF */
3297  I915_WRITE(PF_CTL(pipe), 0);
3298  I915_WRITE(PF_WIN_SZ(pipe), 0);
3299 
3300  for_each_encoder_on_crtc(dev, crtc, encoder)
3301  if (encoder->post_disable)
3302  encoder->post_disable(encoder);
3303 
3304  ironlake_fdi_disable(crtc);
3305 
3306  intel_disable_transcoder(dev_priv, pipe);
3307 
3308  if (HAS_PCH_CPT(dev)) {
3309  /* disable TRANS_DP_CTL */
3310  reg = TRANS_DP_CTL(pipe);
3311  temp = I915_READ(reg);
3313  temp |= TRANS_DP_PORT_SEL_NONE;
3314  I915_WRITE(reg, temp);
3315 
3316  /* disable DPLL_SEL */
3317  temp = I915_READ(PCH_DPLL_SEL);
3318  switch (pipe) {
3319  case 0:
3320  temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3321  break;
3322  case 1:
3323  temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3324  break;
3325  case 2:
3326  /* C shares PLL A or B */
3327  temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3328  break;
3329  default:
3330  BUG(); /* wtf */
3331  }
3332  I915_WRITE(PCH_DPLL_SEL, temp);
3333  }
3334 
3335  /* disable PCH DPLL */
3336  intel_disable_pch_pll(intel_crtc);
3337 
3338  ironlake_fdi_pll_disable(intel_crtc);
3339 
3340  intel_crtc->active = false;
3342 
3343  mutex_lock(&dev->struct_mutex);
3344  intel_update_fbc(dev);
3345  mutex_unlock(&dev->struct_mutex);
3346 }
3347 
3348 static void ironlake_crtc_off(struct drm_crtc *crtc)
3349 {
3350  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351  intel_put_pch_pll(intel_crtc);
3352 }
3353 
3354 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3355 {
3356  if (!enable && intel_crtc->overlay) {
3357  struct drm_device *dev = intel_crtc->base.dev;
3358  struct drm_i915_private *dev_priv = dev->dev_private;
3359 
3360  mutex_lock(&dev->struct_mutex);
3361  dev_priv->mm.interruptible = false;
3362  (void) intel_overlay_switch_off(intel_crtc->overlay);
3363  dev_priv->mm.interruptible = true;
3364  mutex_unlock(&dev->struct_mutex);
3365  }
3366 
3367  /* Let userspace switch the overlay on again. In most cases userspace
3368  * has to recompute where to put it anyway.
3369  */
3370 }
3371 
3372 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3373 {
3374  struct drm_device *dev = crtc->dev;
3375  struct drm_i915_private *dev_priv = dev->dev_private;
3376  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3377  struct intel_encoder *encoder;
3378  int pipe = intel_crtc->pipe;
3379  int plane = intel_crtc->plane;
3380 
3381  WARN_ON(!crtc->enabled);
3382 
3383  if (intel_crtc->active)
3384  return;
3385 
3386  intel_crtc->active = true;
3388 
3389  intel_enable_pll(dev_priv, pipe);
3390  intel_enable_pipe(dev_priv, pipe, false);
3391  intel_enable_plane(dev_priv, plane, pipe);
3392 
3393  intel_crtc_load_lut(crtc);
3394  intel_update_fbc(dev);
3395 
3396  /* Give the overlay scaler a chance to enable if it's on this pipe */
3397  intel_crtc_dpms_overlay(intel_crtc, true);
3398  intel_crtc_update_cursor(crtc, true);
3399 
3400  for_each_encoder_on_crtc(dev, crtc, encoder)
3401  encoder->enable(encoder);
3402 }
3403 
3404 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3405 {
3406  struct drm_device *dev = crtc->dev;
3407  struct drm_i915_private *dev_priv = dev->dev_private;
3408  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3409  struct intel_encoder *encoder;
3410  int pipe = intel_crtc->pipe;
3411  int plane = intel_crtc->plane;
3412 
3413 
3414  if (!intel_crtc->active)
3415  return;
3416 
3417  for_each_encoder_on_crtc(dev, crtc, encoder)
3418  encoder->disable(encoder);
3419 
3420  /* Give the overlay scaler a chance to disable if it's on this pipe */
3421  intel_crtc_wait_for_pending_flips(crtc);
3422  drm_vblank_off(dev, pipe);
3423  intel_crtc_dpms_overlay(intel_crtc, false);
3424  intel_crtc_update_cursor(crtc, false);
3425 
3426  if (dev_priv->cfb_plane == plane)
3427  intel_disable_fbc(dev);
3428 
3429  intel_disable_plane(dev_priv, plane, pipe);
3430  intel_disable_pipe(dev_priv, pipe);
3431  intel_disable_pll(dev_priv, pipe);
3432 
3433  intel_crtc->active = false;
3434  intel_update_fbc(dev);
3436 }
3437 
3438 static void i9xx_crtc_off(struct drm_crtc *crtc)
3439 {
3440 }
3441 
3442 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3443  bool enabled)
3444 {
3445  struct drm_device *dev = crtc->dev;
3446  struct drm_i915_master_private *master_priv;
3447  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3448  int pipe = intel_crtc->pipe;
3449 
3450  if (!dev->primary->master)
3451  return;
3452 
3453  master_priv = dev->primary->master->driver_priv;
3454  if (!master_priv->sarea_priv)
3455  return;
3456 
3457  switch (pipe) {
3458  case 0:
3459  master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3460  master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3461  break;
3462  case 1:
3463  master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3464  master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3465  break;
3466  default:
3467  DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3468  break;
3469  }
3470 }
3471 
3476 {
3477  struct drm_device *dev = crtc->dev;
3478  struct drm_i915_private *dev_priv = dev->dev_private;
3479  struct intel_encoder *intel_encoder;
3480  bool enable = false;
3481 
3482  for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3483  enable |= intel_encoder->connectors_active;
3484 
3485  if (enable)
3486  dev_priv->display.crtc_enable(crtc);
3487  else
3488  dev_priv->display.crtc_disable(crtc);
3489 
3490  intel_crtc_update_sarea(crtc, enable);
3491 }
3492 
3493 static void intel_crtc_noop(struct drm_crtc *crtc)
3494 {
3495 }
3496 
3497 static void intel_crtc_disable(struct drm_crtc *crtc)
3498 {
3499  struct drm_device *dev = crtc->dev;
3500  struct drm_connector *connector;
3501  struct drm_i915_private *dev_priv = dev->dev_private;
3502 
3503  /* crtc should still be enabled when we disable it. */
3504  WARN_ON(!crtc->enabled);
3505 
3506  dev_priv->display.crtc_disable(crtc);
3507  intel_crtc_update_sarea(crtc, false);
3508  dev_priv->display.off(crtc);
3509 
3510  assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3511  assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3512 
3513  if (crtc->fb) {
3514  mutex_lock(&dev->struct_mutex);
3516  mutex_unlock(&dev->struct_mutex);
3517  crtc->fb = NULL;
3518  }
3519 
3520  /* Update computed state. */
3521  list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3522  if (!connector->encoder || !connector->encoder->crtc)
3523  continue;
3524 
3525  if (connector->encoder->crtc != crtc)
3526  continue;
3527 
3528  connector->dpms = DRM_MODE_DPMS_OFF;
3529  to_intel_encoder(connector->encoder)->connectors_active = false;
3530  }
3531 }
3532 
3534 {
3535  struct drm_crtc *crtc;
3536 
3537  list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3538  if (crtc->enabled)
3539  intel_crtc_disable(crtc);
3540  }
3541 }
3542 
3543 void intel_encoder_noop(struct drm_encoder *encoder)
3544 {
3545 }
3546 
3547 void intel_encoder_destroy(struct drm_encoder *encoder)
3548 {
3549  struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3550 
3551  drm_encoder_cleanup(encoder);
3552  kfree(intel_encoder);
3553 }
3554 
3555 /* Simple dpms helper for encodres with just one connector, no cloning and only
3556  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3557  * state of the entire output pipe. */
3558 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3559 {
3560  if (mode == DRM_MODE_DPMS_ON) {
3561  encoder->connectors_active = true;
3562 
3563  intel_crtc_update_dpms(encoder->base.crtc);
3564  } else {
3565  encoder->connectors_active = false;
3566 
3567  intel_crtc_update_dpms(encoder->base.crtc);
3568  }
3569 }
3570 
3571 /* Cross check the actual hw state with our own modeset state tracking (and it's
3572  * internal consistency). */
3573 static void intel_connector_check_state(struct intel_connector *connector)
3574 {
3575  if (connector->get_hw_state(connector)) {
3576  struct intel_encoder *encoder = connector->encoder;
3577  struct drm_crtc *crtc;
3578  bool encoder_enabled;
3579  enum pipe pipe;
3580 
3581  DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3582  connector->base.base.id,
3583  drm_get_connector_name(&connector->base));
3584 
3585  WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3586  "wrong connector dpms state\n");
3587  WARN(connector->base.encoder != &encoder->base,
3588  "active connector not linked to encoder\n");
3589  WARN(!encoder->connectors_active,
3590  "encoder->connectors_active not set\n");
3591 
3592  encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3593  WARN(!encoder_enabled, "encoder not enabled\n");
3594  if (WARN_ON(!encoder->base.crtc))
3595  return;
3596 
3597  crtc = encoder->base.crtc;
3598 
3599  WARN(!crtc->enabled, "crtc not enabled\n");
3600  WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3601  WARN(pipe != to_intel_crtc(crtc)->pipe,
3602  "encoder active on the wrong pipe\n");
3603  }
3604 }
3605 
3606 /* Even simpler default implementation, if there's really no special case to
3607  * consider. */
3608 void intel_connector_dpms(struct drm_connector *connector, int mode)
3609 {
3610  struct intel_encoder *encoder = intel_attached_encoder(connector);
3611 
3612  /* All the simple cases only support two dpms states. */
3613  if (mode != DRM_MODE_DPMS_ON)
3614  mode = DRM_MODE_DPMS_OFF;
3615 
3616  if (mode == connector->dpms)
3617  return;
3618 
3619  connector->dpms = mode;
3620 
3621  /* Only need to change hw state when actually enabled */
3622  if (encoder->base.crtc)
3623  intel_encoder_dpms(encoder, mode);
3624  else
3625  WARN_ON(encoder->connectors_active != false);
3626 
3627  intel_modeset_check_state(connector->dev);
3628 }
3629 
3630 /* Simple connector->get_hw_state implementation for encoders that support only
3631  * one connector and no cloning and hence the encoder state determines the state
3632  * of the connector. */
3634 {
3635  enum pipe pipe = 0;
3636  struct intel_encoder *encoder = connector->encoder;
3637 
3638  return encoder->get_hw_state(encoder, &pipe);
3639 }
3640 
3641 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3642  const struct drm_display_mode *mode,
3643  struct drm_display_mode *adjusted_mode)
3644 {
3645  struct drm_device *dev = crtc->dev;
3646 
3647  if (HAS_PCH_SPLIT(dev)) {
3648  /* FDI link clock is fixed at 2.7G */
3649  if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3650  return false;
3651  }
3652 
3653  /* All interlaced capable intel hw wants timings in frames. Note though
3654  * that intel_lvds_mode_fixup does some funny tricks with the crtc
3655  * timings, so we need to be careful not to clobber these.*/
3656  if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3657  drm_mode_set_crtcinfo(adjusted_mode, 0);
3658 
3659  /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3660  * with a hsync front porch of 0.
3661  */
3662  if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3663  adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3664  return false;
3665 
3666  return true;
3667 }
3668 
3669 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3670 {
3671  return 400000; /* FIXME */
3672 }
3673 
3674 static int i945_get_display_clock_speed(struct drm_device *dev)
3675 {
3676  return 400000;
3677 }
3678 
3679 static int i915_get_display_clock_speed(struct drm_device *dev)
3680 {
3681  return 333000;
3682 }
3683 
3684 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3685 {
3686  return 200000;
3687 }
3688 
3689 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3690 {
3691  u16 gcfgc = 0;
3692 
3693  pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3694 
3695  if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3696  return 133000;
3697  else {
3698  switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3700  return 333000;
3701  default:
3703  return 190000;
3704  }
3705  }
3706 }
3707 
3708 static int i865_get_display_clock_speed(struct drm_device *dev)
3709 {
3710  return 266000;
3711 }
3712 
3713 static int i855_get_display_clock_speed(struct drm_device *dev)
3714 {
3715  u16 hpllcc = 0;
3716  /* Assume that the hardware is in the high speed state. This
3717  * should be the default.
3718  */
3719  switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3720  case GC_CLOCK_133_200:
3721  case GC_CLOCK_100_200:
3722  return 200000;
3723  case GC_CLOCK_166_250:
3724  return 250000;
3725  case GC_CLOCK_100_133:
3726  return 133000;
3727  }
3728 
3729  /* Shouldn't happen */
3730  return 0;
3731 }
3732 
3733 static int i830_get_display_clock_speed(struct drm_device *dev)
3734 {
3735  return 133000;
3736 }
3737 
3738 struct fdi_m_n {
3744 };
3745 
3746 static void
3747 fdi_reduce_ratio(u32 *num, u32 *den)
3748 {
3749  while (*num > 0xffffff || *den > 0xffffff) {
3750  *num >>= 1;
3751  *den >>= 1;
3752  }
3753 }
3754 
3755 static void
3756 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3757  int link_clock, struct fdi_m_n *m_n)
3758 {
3759  m_n->tu = 64; /* default size */
3760 
3761  /* BUG_ON(pixel_clock > INT_MAX / 36); */
3762  m_n->gmch_m = bits_per_pixel * pixel_clock;
3763  m_n->gmch_n = link_clock * nlanes * 8;
3764  fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3765 
3766  m_n->link_m = pixel_clock;
3767  m_n->link_n = link_clock;
3768  fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3769 }
3770 
3771 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3772 {
3773  if (i915_panel_use_ssc >= 0)
3774  return i915_panel_use_ssc != 0;
3775  return dev_priv->lvds_use_ssc
3776  && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3777 }
3778 
3800 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3801  struct drm_framebuffer *fb,
3802  unsigned int *pipe_bpp,
3803  struct drm_display_mode *mode)
3804 {
3805  struct drm_device *dev = crtc->dev;
3806  struct drm_i915_private *dev_priv = dev->dev_private;
3807  struct drm_connector *connector;
3808  struct intel_encoder *intel_encoder;
3809  unsigned int display_bpc = UINT_MAX, bpc;
3810 
3811  /* Walk the encoders & connectors on this crtc, get min bpc */
3812  for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3813 
3814  if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3815  unsigned int lvds_bpc;
3816 
3819  lvds_bpc = 8;
3820  else
3821  lvds_bpc = 6;
3822 
3823  if (lvds_bpc < display_bpc) {
3824  DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3825  display_bpc = lvds_bpc;
3826  }
3827  continue;
3828  }
3829 
3830  /* Not one of the known troublemakers, check the EDID */
3831  list_for_each_entry(connector, &dev->mode_config.connector_list,
3832  head) {
3833  if (connector->encoder != &intel_encoder->base)
3834  continue;
3835 
3836  /* Don't use an invalid EDID bpc value */
3837  if (connector->display_info.bpc &&
3838  connector->display_info.bpc < display_bpc) {
3839  DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3840  display_bpc = connector->display_info.bpc;
3841  }
3842  }
3843 
3844  if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3845  /* Use VBT settings if we have an eDP panel */
3846  unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3847 
3848  if (edp_bpc && edp_bpc < display_bpc) {
3849  DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3850  display_bpc = edp_bpc;
3851  }
3852  continue;
3853  }
3854 
3855  /*
3856  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3857  * through, clamp it down. (Note: >12bpc will be caught below.)
3858  */
3859  if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3860  if (display_bpc > 8 && display_bpc < 12) {
3861  DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3862  display_bpc = 12;
3863  } else {
3864  DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3865  display_bpc = 8;
3866  }
3867  }
3868  }
3869 
3871  DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3872  display_bpc = 6;
3873  }
3874 
3875  /*
3876  * We could just drive the pipe at the highest bpc all the time and
3877  * enable dithering as needed, but that costs bandwidth. So choose
3878  * the minimum value that expresses the full color range of the fb but
3879  * also stays within the max display bpc discovered above.
3880  */
3881 
3882  switch (fb->depth) {
3883  case 8:
3884  bpc = 8; /* since we go through a colormap */
3885  break;
3886  case 15:
3887  case 16:
3888  bpc = 6; /* min is 18bpp */
3889  break;
3890  case 24:
3891  bpc = 8;
3892  break;
3893  case 30:
3894  bpc = 10;
3895  break;
3896  case 48:
3897  bpc = 12;
3898  break;
3899  default:
3900  DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3901  bpc = min((unsigned int)8, display_bpc);
3902  break;
3903  }
3904 
3905  display_bpc = min(display_bpc, bpc);
3906 
3907  DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3908  bpc, display_bpc);
3909 
3910  *pipe_bpp = display_bpc * 3;
3911 
3912  return display_bpc != bpc;
3913 }
3914 
3915 static int vlv_get_refclk(struct drm_crtc *crtc)
3916 {
3917  struct drm_device *dev = crtc->dev;
3918  struct drm_i915_private *dev_priv = dev->dev_private;
3919  int refclk = 27000; /* for DP & HDMI */
3920 
3921  return 100000; /* only one validated so far */
3922 
3924  refclk = 96000;
3925  } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3926  if (intel_panel_use_ssc(dev_priv))
3927  refclk = 100000;
3928  else
3929  refclk = 96000;
3930  } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3931  refclk = 100000;
3932  }
3933 
3934  return refclk;
3935 }
3936 
3937 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3938 {
3939  struct drm_device *dev = crtc->dev;
3940  struct drm_i915_private *dev_priv = dev->dev_private;
3941  int refclk;
3942 
3943  if (IS_VALLEYVIEW(dev)) {
3944  refclk = vlv_get_refclk(crtc);
3945  } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3946  intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3947  refclk = dev_priv->lvds_ssc_freq * 1000;
3948  DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3949  refclk / 1000);
3950  } else if (!IS_GEN2(dev)) {
3951  refclk = 96000;
3952  } else {
3953  refclk = 48000;
3954  }
3955 
3956  return refclk;
3957 }
3958 
3959 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3960  intel_clock_t *clock)
3961 {
3962  /* SDVO TV has fixed PLL values depend on its clock range,
3963  this mirrors vbios setting. */
3964  if (adjusted_mode->clock >= 100000
3965  && adjusted_mode->clock < 140500) {
3966  clock->p1 = 2;
3967  clock->p2 = 10;
3968  clock->n = 3;
3969  clock->m1 = 16;
3970  clock->m2 = 8;
3971  } else if (adjusted_mode->clock >= 140500
3972  && adjusted_mode->clock <= 200000) {
3973  clock->p1 = 1;
3974  clock->p2 = 10;
3975  clock->n = 6;
3976  clock->m1 = 12;
3977  clock->m2 = 8;
3978  }
3979 }
3980 
3981 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3982  intel_clock_t *clock,
3983  intel_clock_t *reduced_clock)
3984 {
3985  struct drm_device *dev = crtc->dev;
3986  struct drm_i915_private *dev_priv = dev->dev_private;
3987  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3988  int pipe = intel_crtc->pipe;
3989  u32 fp, fp2 = 0;
3990 
3991  if (IS_PINEVIEW(dev)) {
3992  fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3993  if (reduced_clock)
3994  fp2 = (1 << reduced_clock->n) << 16 |
3995  reduced_clock->m1 << 8 | reduced_clock->m2;
3996  } else {
3997  fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3998  if (reduced_clock)
3999  fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4000  reduced_clock->m2;
4001  }
4002 
4003  I915_WRITE(FP0(pipe), fp);
4004 
4005  intel_crtc->lowfreq_avail = false;
4007  reduced_clock && i915_powersave) {
4008  I915_WRITE(FP1(pipe), fp2);
4009  intel_crtc->lowfreq_avail = true;
4010  } else {
4011  I915_WRITE(FP1(pipe), fp);
4012  }
4013 }
4014 
4015 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4016  struct drm_display_mode *adjusted_mode)
4017 {
4018  struct drm_device *dev = crtc->dev;
4019  struct drm_i915_private *dev_priv = dev->dev_private;
4020  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4021  int pipe = intel_crtc->pipe;
4022  u32 temp;
4023 
4024  temp = I915_READ(LVDS);
4025  temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4026  if (pipe == 1) {
4027  temp |= LVDS_PIPEB_SELECT;
4028  } else {
4029  temp &= ~LVDS_PIPEB_SELECT;
4030  }
4031  /* set the corresponsding LVDS_BORDER bit */
4032  temp |= dev_priv->lvds_border_bits;
4033  /* Set the B0-B3 data pairs corresponding to whether we're going to
4034  * set the DPLLs for dual-channel mode or not.
4035  */
4036  if (clock->p2 == 7)
4038  else
4040 
4041  /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4042  * appropriately here, but we need to look more thoroughly into how
4043  * panels behave in the two modes.
4044  */
4045  /* set the dithering flag on LVDS as needed */
4046  if (INTEL_INFO(dev)->gen >= 4) {
4047  if (dev_priv->lvds_dither)
4048  temp |= LVDS_ENABLE_DITHER;
4049  else
4050  temp &= ~LVDS_ENABLE_DITHER;
4051  }
4053  if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4054  temp |= LVDS_HSYNC_POLARITY;
4055  if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4056  temp |= LVDS_VSYNC_POLARITY;
4057  I915_WRITE(LVDS, temp);
4058 }
4059 
4060 static void vlv_update_pll(struct drm_crtc *crtc,
4061  struct drm_display_mode *mode,
4062  struct drm_display_mode *adjusted_mode,
4063  intel_clock_t *clock, intel_clock_t *reduced_clock,
4064  int refclk, int num_connectors)
4065 {
4066  struct drm_device *dev = crtc->dev;
4067  struct drm_i915_private *dev_priv = dev->dev_private;
4068  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4069  int pipe = intel_crtc->pipe;
4070  u32 dpll, mdiv, pdiv;
4071  u32 bestn, bestm1, bestm2, bestp1, bestp2;
4072  bool is_hdmi;
4073 
4074  is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4075 
4076  bestn = clock->n;
4077  bestm1 = clock->m1;
4078  bestm2 = clock->m2;
4079  bestp1 = clock->p1;
4080  bestp2 = clock->p2;
4081 
4082  /* Enable DPIO clock input */
4085  I915_WRITE(DPLL(pipe), dpll);
4086  POSTING_READ(DPLL(pipe));
4087 
4088  mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4089  mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4090  mdiv |= ((bestn << DPIO_N_SHIFT));
4091  mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4092  mdiv |= (1 << DPIO_K_SHIFT);
4093  mdiv |= DPIO_ENABLE_CALIBRATION;
4094  intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4095 
4096  intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4097 
4099  (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4101  intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4102 
4103  intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4104 
4105  dpll |= DPLL_VCO_ENABLE;
4106  I915_WRITE(DPLL(pipe), dpll);
4107  POSTING_READ(DPLL(pipe));
4108  if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4109  DRM_ERROR("DPLL %d failed to lock\n", pipe);
4110 
4111  if (is_hdmi) {
4112  u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4113 
4114  if (temp > 1)
4115  temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4116  else
4117  temp = 0;
4118 
4119  I915_WRITE(DPLL_MD(pipe), temp);
4120  POSTING_READ(DPLL_MD(pipe));
4121  }
4122 
4123  intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4124 }
4125 
4126 static void i9xx_update_pll(struct drm_crtc *crtc,
4127  struct drm_display_mode *mode,
4128  struct drm_display_mode *adjusted_mode,
4129  intel_clock_t *clock, intel_clock_t *reduced_clock,
4130  int num_connectors)
4131 {
4132  struct drm_device *dev = crtc->dev;
4133  struct drm_i915_private *dev_priv = dev->dev_private;
4134  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4135  int pipe = intel_crtc->pipe;
4136  u32 dpll;
4137  bool is_sdvo;
4138 
4139  is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4141 
4142  dpll = DPLL_VGA_MODE_DIS;
4143 
4145  dpll |= DPLLB_MODE_LVDS;
4146  else
4147  dpll |= DPLLB_MODE_DAC_SERIAL;
4148  if (is_sdvo) {
4149  int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4150  if (pixel_multiplier > 1) {
4151  if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4152  dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4153  }
4154  dpll |= DPLL_DVO_HIGH_SPEED;
4155  }
4157  dpll |= DPLL_DVO_HIGH_SPEED;
4158 
4159  /* compute bitmask from p1 value */
4160  if (IS_PINEVIEW(dev))
4161  dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4162  else {
4163  dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4164  if (IS_G4X(dev) && reduced_clock)
4165  dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4166  }
4167  switch (clock->p2) {
4168  case 5:
4170  break;
4171  case 7:
4172  dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4173  break;
4174  case 10:
4176  break;
4177  case 14:
4179  break;
4180  }
4181  if (INTEL_INFO(dev)->gen >= 4)
4182  dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4183 
4184  if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4185  dpll |= PLL_REF_INPUT_TVCLKINBC;
4186  else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4187  /* XXX: just matching BIOS for now */
4188  /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4189  dpll |= 3;
4190  else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4191  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4193  else
4194  dpll |= PLL_REF_INPUT_DREFCLK;
4195 
4196  dpll |= DPLL_VCO_ENABLE;
4197  I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4198  POSTING_READ(DPLL(pipe));
4199  udelay(150);
4200 
4201  /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4202  * This is an exception to the general rule that mode_set doesn't turn
4203  * things on.
4204  */
4206  intel_update_lvds(crtc, clock, adjusted_mode);
4207 
4209  intel_dp_set_m_n(crtc, mode, adjusted_mode);
4210 
4211  I915_WRITE(DPLL(pipe), dpll);
4212 
4213  /* Wait for the clocks to stabilize. */
4214  POSTING_READ(DPLL(pipe));
4215  udelay(150);
4216 
4217  if (INTEL_INFO(dev)->gen >= 4) {
4218  u32 temp = 0;
4219  if (is_sdvo) {
4220  temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4221  if (temp > 1)
4222  temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4223  else
4224  temp = 0;
4225  }
4226  I915_WRITE(DPLL_MD(pipe), temp);
4227  } else {
4228  /* The pixel multiplier can only be updated once the
4229  * DPLL is enabled and the clocks are stable.
4230  *
4231  * So write it again.
4232  */
4233  I915_WRITE(DPLL(pipe), dpll);
4234  }
4235 }
4236 
4237 static void i8xx_update_pll(struct drm_crtc *crtc,
4238  struct drm_display_mode *adjusted_mode,
4239  intel_clock_t *clock,
4240  int num_connectors)
4241 {
4242  struct drm_device *dev = crtc->dev;
4243  struct drm_i915_private *dev_priv = dev->dev_private;
4244  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4245  int pipe = intel_crtc->pipe;
4246  u32 dpll;
4247 
4248  dpll = DPLL_VGA_MODE_DIS;
4249 
4251  dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4252  } else {
4253  if (clock->p1 == 2)
4254  dpll |= PLL_P1_DIVIDE_BY_TWO;
4255  else
4256  dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4257  if (clock->p2 == 4)
4258  dpll |= PLL_P2_DIVIDE_BY_4;
4259  }
4260 
4262  /* XXX: just matching BIOS for now */
4263  /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4264  dpll |= 3;
4265  else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4266  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4268  else
4269  dpll |= PLL_REF_INPUT_DREFCLK;
4270 
4271  dpll |= DPLL_VCO_ENABLE;
4272  I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4273  POSTING_READ(DPLL(pipe));
4274  udelay(150);
4275 
4276  /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4277  * This is an exception to the general rule that mode_set doesn't turn
4278  * things on.
4279  */
4281  intel_update_lvds(crtc, clock, adjusted_mode);
4282 
4283  I915_WRITE(DPLL(pipe), dpll);
4284 
4285  /* Wait for the clocks to stabilize. */
4286  POSTING_READ(DPLL(pipe));
4287  udelay(150);
4288 
4289  /* The pixel multiplier can only be updated once the
4290  * DPLL is enabled and the clocks are stable.
4291  *
4292  * So write it again.
4293  */
4294  I915_WRITE(DPLL(pipe), dpll);
4295 }
4296 
4297 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4298  struct drm_display_mode *mode,
4299  struct drm_display_mode *adjusted_mode,
4300  int x, int y,
4301  struct drm_framebuffer *fb)
4302 {
4303  struct drm_device *dev = crtc->dev;
4304  struct drm_i915_private *dev_priv = dev->dev_private;
4305  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4306  int pipe = intel_crtc->pipe;
4307  int plane = intel_crtc->plane;
4308  int refclk, num_connectors = 0;
4309  intel_clock_t clock, reduced_clock;
4310  u32 dspcntr, pipeconf, vsyncshift;
4311  bool ok, has_reduced_clock = false, is_sdvo = false;
4312  bool is_lvds = false, is_tv = false, is_dp = false;
4313  struct intel_encoder *encoder;
4314  const intel_limit_t *limit;
4315  int ret;
4316 
4317  for_each_encoder_on_crtc(dev, crtc, encoder) {
4318  switch (encoder->type) {
4319  case INTEL_OUTPUT_LVDS:
4320  is_lvds = true;
4321  break;
4322  case INTEL_OUTPUT_SDVO:
4323  case INTEL_OUTPUT_HDMI:
4324  is_sdvo = true;
4325  if (encoder->needs_tv_clock)
4326  is_tv = true;
4327  break;
4328  case INTEL_OUTPUT_TVOUT:
4329  is_tv = true;
4330  break;
4332  is_dp = true;
4333  break;
4334  }
4335 
4336  num_connectors++;
4337  }
4338 
4339  refclk = i9xx_get_refclk(crtc, num_connectors);
4340 
4341  /*
4342  * Returns a set of divisors for the desired target clock with the given
4343  * refclk, or FALSE. The returned values represent the clock equation:
4344  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4345  */
4346  limit = intel_limit(crtc, refclk);
4347  ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4348  &clock);
4349  if (!ok) {
4350  DRM_ERROR("Couldn't find PLL settings for mode!\n");
4351  return -EINVAL;
4352  }
4353 
4354  /* Ensure that the cursor is valid for the new mode before changing... */
4355  intel_crtc_update_cursor(crtc, true);
4356 
4357  if (is_lvds && dev_priv->lvds_downclock_avail) {
4358  /*
4359  * Ensure we match the reduced clock's P to the target clock.
4360  * If the clocks don't match, we can't switch the display clock
4361  * by using the FP0/FP1. In such case we will disable the LVDS
4362  * downclock feature.
4363  */
4364  has_reduced_clock = limit->find_pll(limit, crtc,
4365  dev_priv->lvds_downclock,
4366  refclk,
4367  &clock,
4368  &reduced_clock);
4369  }
4370 
4371  if (is_sdvo && is_tv)
4372  i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4373 
4374  i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4375  &reduced_clock : NULL);
4376 
4377  if (IS_GEN2(dev))
4378  i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4379  else if (IS_VALLEYVIEW(dev))
4380  vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4381  refclk, num_connectors);
4382  else
4383  i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4384  has_reduced_clock ? &reduced_clock : NULL,
4385  num_connectors);
4386 
4387  /* setup pipeconf */
4388  pipeconf = I915_READ(PIPECONF(pipe));
4389 
4390  /* Set up the display plane register */
4391  dspcntr = DISPPLANE_GAMMA_ENABLE;
4392 
4393  if (pipe == 0)
4394  dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4395  else
4396  dspcntr |= DISPPLANE_SEL_PIPE_B;
4397 
4398  if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4399  /* Enable pixel doubling when the dot clock is > 90% of the (display)
4400  * core speed.
4401  *
4402  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4403  * pipe == 0 check?
4404  */
4405  if (mode->clock >
4406  dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4407  pipeconf |= PIPECONF_DOUBLE_WIDE;
4408  else
4409  pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4410  }
4411 
4412  /* default to 8bpc */
4413  pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4414  if (is_dp) {
4415  if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4416  pipeconf |= PIPECONF_BPP_6 |
4419  }
4420  }
4421 
4422  DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4424 
4425  if (HAS_PIPE_CXSR(dev)) {
4426  if (intel_crtc->lowfreq_avail) {
4427  DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4428  pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4429  } else {
4430  DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4431  pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4432  }
4433  }
4434 
4435  pipeconf &= ~PIPECONF_INTERLACE_MASK;
4436  if (!IS_GEN2(dev) &&
4437  adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4439  /* the chip adds 2 halflines automatically */
4440  adjusted_mode->crtc_vtotal -= 1;
4441  adjusted_mode->crtc_vblank_end -= 1;
4442  vsyncshift = adjusted_mode->crtc_hsync_start
4443  - adjusted_mode->crtc_htotal/2;
4444  } else {
4445  pipeconf |= PIPECONF_PROGRESSIVE;
4446  vsyncshift = 0;
4447  }
4448 
4449  if (!IS_GEN3(dev))
4450  I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4451 
4452  I915_WRITE(HTOTAL(pipe),
4453  (adjusted_mode->crtc_hdisplay - 1) |
4454  ((adjusted_mode->crtc_htotal - 1) << 16));
4455  I915_WRITE(HBLANK(pipe),
4456  (adjusted_mode->crtc_hblank_start - 1) |
4457  ((adjusted_mode->crtc_hblank_end - 1) << 16));
4458  I915_WRITE(HSYNC(pipe),
4459  (adjusted_mode->crtc_hsync_start - 1) |
4460  ((adjusted_mode->crtc_hsync_end - 1) << 16));
4461 
4462  I915_WRITE(VTOTAL(pipe),
4463  (adjusted_mode->crtc_vdisplay - 1) |
4464  ((adjusted_mode->crtc_vtotal - 1) << 16));
4465  I915_WRITE(VBLANK(pipe),
4466  (adjusted_mode->crtc_vblank_start - 1) |
4467  ((adjusted_mode->crtc_vblank_end - 1) << 16));
4468  I915_WRITE(VSYNC(pipe),
4469  (adjusted_mode->crtc_vsync_start - 1) |
4470  ((adjusted_mode->crtc_vsync_end - 1) << 16));
4471 
4472  /* pipesrc and dspsize control the size that is scaled from,
4473  * which should always be the user's requested size.
4474  */
4475  I915_WRITE(DSPSIZE(plane),
4476  ((mode->vdisplay - 1) << 16) |
4477  (mode->hdisplay - 1));
4478  I915_WRITE(DSPPOS(plane), 0);
4479  I915_WRITE(PIPESRC(pipe),
4480  ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4481 
4482  I915_WRITE(PIPECONF(pipe), pipeconf);
4483  POSTING_READ(PIPECONF(pipe));
4484  intel_enable_pipe(dev_priv, pipe, false);
4485 
4486  intel_wait_for_vblank(dev, pipe);
4487 
4488  I915_WRITE(DSPCNTR(plane), dspcntr);
4489  POSTING_READ(DSPCNTR(plane));
4490 
4491  ret = intel_pipe_set_base(crtc, x, y, fb);
4492 
4494 
4495  return ret;
4496 }
4497 
4498 /*
4499  * Initialize reference clocks when the driver loads
4500  */
4502 {
4503  struct drm_i915_private *dev_priv = dev->dev_private;
4504  struct drm_mode_config *mode_config = &dev->mode_config;
4505  struct intel_encoder *encoder;
4506  u32 temp;
4507  bool has_lvds = false;
4508  bool has_cpu_edp = false;
4509  bool has_pch_edp = false;
4510  bool has_panel = false;
4511  bool has_ck505 = false;
4512  bool can_ssc = false;
4513 
4514  /* We need to take the global config into account */
4515  list_for_each_entry(encoder, &mode_config->encoder_list,
4516  base.head) {
4517  switch (encoder->type) {
4518  case INTEL_OUTPUT_LVDS:
4519  has_panel = true;
4520  has_lvds = true;
4521  break;
4522  case INTEL_OUTPUT_EDP:
4523  has_panel = true;
4524  if (intel_encoder_is_pch_edp(&encoder->base))
4525  has_pch_edp = true;
4526  else
4527  has_cpu_edp = true;
4528  break;
4529  }
4530  }
4531 
4532  if (HAS_PCH_IBX(dev)) {
4533  has_ck505 = dev_priv->display_clock_mode;
4534  can_ssc = has_ck505;
4535  } else {
4536  has_ck505 = false;
4537  can_ssc = true;
4538  }
4539 
4540  DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4541  has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4542  has_ck505);
4543 
4544  /* Ironlake: try to setup display ref clock before DPLL
4545  * enabling. This is only under driver's control after
4546  * PCH B stepping, previous chipset stepping should be
4547  * ignoring this setting.
4548  */
4549  temp = I915_READ(PCH_DREF_CONTROL);
4550  /* Always enable nonspread source */
4551  temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4552 
4553  if (has_ck505)
4555  else
4557 
4558  if (has_panel) {
4559  temp &= ~DREF_SSC_SOURCE_MASK;
4560  temp |= DREF_SSC_SOURCE_ENABLE;
4561 
4562  /* SSC must be turned on before enabling the CPU output */
4563  if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4564  DRM_DEBUG_KMS("Using SSC on panel\n");
4565  temp |= DREF_SSC1_ENABLE;
4566  } else
4567  temp &= ~DREF_SSC1_ENABLE;
4568 
4569  /* Get SSC going before enabling the outputs */
4572  udelay(200);
4573 
4574  temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4575 
4576  /* Enable CPU source on CPU attached eDP */
4577  if (has_cpu_edp) {
4578  if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4579  DRM_DEBUG_KMS("Using SSC on eDP\n");
4581  }
4582  else
4584  } else
4586 
4589  udelay(200);
4590  } else {
4591  DRM_DEBUG_KMS("Disabling SSC entirely\n");
4592 
4593  temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4594 
4595  /* Turn off CPU output */
4597 
4600  udelay(200);
4601 
4602  /* Turn off the SSC source */
4603  temp &= ~DREF_SSC_SOURCE_MASK;
4604  temp |= DREF_SSC_SOURCE_DISABLE;
4605 
4606  /* Turn off SSC1 */
4607  temp &= ~ DREF_SSC1_ENABLE;
4608 
4611  udelay(200);
4612  }
4613 }
4614 
4615 static int ironlake_get_refclk(struct drm_crtc *crtc)
4616 {
4617  struct drm_device *dev = crtc->dev;
4618  struct drm_i915_private *dev_priv = dev->dev_private;
4619  struct intel_encoder *encoder;
4620  struct intel_encoder *edp_encoder = NULL;
4621  int num_connectors = 0;
4622  bool is_lvds = false;
4623 
4624  for_each_encoder_on_crtc(dev, crtc, encoder) {
4625  switch (encoder->type) {
4626  case INTEL_OUTPUT_LVDS:
4627  is_lvds = true;
4628  break;
4629  case INTEL_OUTPUT_EDP:
4630  edp_encoder = encoder;
4631  break;
4632  }
4633  num_connectors++;
4634  }
4635 
4636  if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4637  DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4638  dev_priv->lvds_ssc_freq);
4639  return dev_priv->lvds_ssc_freq * 1000;
4640  }
4641 
4642  return 120000;
4643 }
4644 
4645 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4646  struct drm_display_mode *adjusted_mode,
4647  bool dither)
4648 {
4649  struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4650  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4651  int pipe = intel_crtc->pipe;
4652  uint32_t val;
4653 
4654  val = I915_READ(PIPECONF(pipe));
4655 
4656  val &= ~PIPE_BPC_MASK;
4657  switch (intel_crtc->bpp) {
4658  case 18:
4659  val |= PIPE_6BPC;
4660  break;
4661  case 24:
4662  val |= PIPE_8BPC;
4663  break;
4664  case 30:
4665  val |= PIPE_10BPC;
4666  break;
4667  case 36:
4668  val |= PIPE_12BPC;
4669  break;
4670  default:
4671  val |= PIPE_8BPC;
4672  break;
4673  }
4674 
4676  if (dither)
4678 
4679  val &= ~PIPECONF_INTERLACE_MASK;
4680  if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4681  val |= PIPECONF_INTERLACED_ILK;
4682  else
4683  val |= PIPECONF_PROGRESSIVE;
4684 
4685  I915_WRITE(PIPECONF(pipe), val);
4686  POSTING_READ(PIPECONF(pipe));
4687 }
4688 
4689 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4690  struct drm_display_mode *adjusted_mode,
4691  intel_clock_t *clock,
4692  bool *has_reduced_clock,
4693  intel_clock_t *reduced_clock)
4694 {
4695  struct drm_device *dev = crtc->dev;
4696  struct drm_i915_private *dev_priv = dev->dev_private;
4697  struct intel_encoder *intel_encoder;
4698  int refclk;
4699  const intel_limit_t *limit;
4700  bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4701 
4702  for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4703  switch (intel_encoder->type) {
4704  case INTEL_OUTPUT_LVDS:
4705  is_lvds = true;
4706  break;
4707  case INTEL_OUTPUT_SDVO:
4708  case INTEL_OUTPUT_HDMI:
4709  is_sdvo = true;
4710  if (intel_encoder->needs_tv_clock)
4711  is_tv = true;
4712  break;
4713  case INTEL_OUTPUT_TVOUT:
4714  is_tv = true;
4715  break;
4716  }
4717  }
4718 
4719  refclk = ironlake_get_refclk(crtc);
4720 
4721  /*
4722  * Returns a set of divisors for the desired target clock with the given
4723  * refclk, or FALSE. The returned values represent the clock equation:
4724  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4725  */
4726  limit = intel_limit(crtc, refclk);
4727  ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4728  clock);
4729  if (!ret)
4730  return false;
4731 
4732  if (is_lvds && dev_priv->lvds_downclock_avail) {
4733  /*
4734  * Ensure we match the reduced clock's P to the target clock.
4735  * If the clocks don't match, we can't switch the display clock
4736  * by using the FP0/FP1. In such case we will disable the LVDS
4737  * downclock feature.
4738  */
4739  *has_reduced_clock = limit->find_pll(limit, crtc,
4740  dev_priv->lvds_downclock,
4741  refclk,
4742  clock,
4743  reduced_clock);
4744  }
4745 
4746  if (is_sdvo && is_tv)
4747  i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4748 
4749  return true;
4750 }
4751 
4752 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4753  struct drm_display_mode *mode,
4754  struct drm_display_mode *adjusted_mode,
4755  int x, int y,
4756  struct drm_framebuffer *fb)
4757 {
4758  struct drm_device *dev = crtc->dev;
4759  struct drm_i915_private *dev_priv = dev->dev_private;
4760  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4761  int pipe = intel_crtc->pipe;
4762  int plane = intel_crtc->plane;
4763  int num_connectors = 0;
4764  intel_clock_t clock, reduced_clock;
4765  u32 dpll, fp = 0, fp2 = 0;
4766  bool ok, has_reduced_clock = false, is_sdvo = false;
4767  bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4768  struct intel_encoder *encoder, *edp_encoder = NULL;
4769  int ret;
4770  struct fdi_m_n m_n = {0};
4771  u32 temp;
4772  int target_clock, pixel_multiplier, lane, link_bw, factor;
4773  unsigned int pipe_bpp;
4774  bool dither;
4775  bool is_cpu_edp = false, is_pch_edp = false;
4776 
4777  for_each_encoder_on_crtc(dev, crtc, encoder) {
4778  switch (encoder->type) {
4779  case INTEL_OUTPUT_LVDS:
4780  is_lvds = true;
4781  break;
4782  case INTEL_OUTPUT_SDVO:
4783  case INTEL_OUTPUT_HDMI:
4784  is_sdvo = true;
4785  if (encoder->needs_tv_clock)
4786  is_tv = true;
4787  break;
4788  case INTEL_OUTPUT_TVOUT:
4789  is_tv = true;
4790  break;
4791  case INTEL_OUTPUT_ANALOG:
4792  is_crt = true;
4793  break;
4795  is_dp = true;
4796  break;
4797  case INTEL_OUTPUT_EDP:
4798  is_dp = true;
4799  if (intel_encoder_is_pch_edp(&encoder->base))
4800  is_pch_edp = true;
4801  else
4802  is_cpu_edp = true;
4803  edp_encoder = encoder;
4804  break;
4805  }
4806 
4807  num_connectors++;
4808  }
4809 
4810  ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
4811  &has_reduced_clock, &reduced_clock);
4812  if (!ok) {
4813  DRM_ERROR("Couldn't find PLL settings for mode!\n");
4814  return -EINVAL;
4815  }
4816 
4817  /* Ensure that the cursor is valid for the new mode before changing... */
4818  intel_crtc_update_cursor(crtc, true);
4819 
4820  /* FDI link */
4821  pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4822  lane = 0;
4823  /* CPU eDP doesn't require FDI link, so just set DP M/N
4824  according to current link config */
4825  if (is_cpu_edp) {
4826  intel_edp_link_config(edp_encoder, &lane, &link_bw);
4827  } else {
4828  /* FDI is a binary signal running at ~2.7GHz, encoding
4829  * each output octet as 10 bits. The actual frequency
4830  * is stored as a divider into a 100MHz clock, and the
4831  * mode pixel clock is stored in units of 1KHz.
4832  * Hence the bw of each lane in terms of the mode signal
4833  * is:
4834  */
4835  link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4836  }
4837 
4838  /* [e]DP over FDI requires target mode clock instead of link clock. */
4839  if (edp_encoder)
4840  target_clock = intel_edp_target_clock(edp_encoder, mode);
4841  else if (is_dp)
4842  target_clock = mode->clock;
4843  else
4844  target_clock = adjusted_mode->clock;
4845 
4846  /* determine panel color depth */
4847  dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp,
4848  adjusted_mode);
4849  if (is_lvds && dev_priv->lvds_dither)
4850  dither = true;
4851 
4852  if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 &&
4853  pipe_bpp != 36) {
4854  WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4855  pipe_bpp);
4856  pipe_bpp = 24;
4857  }
4858  intel_crtc->bpp = pipe_bpp;
4859 
4860  if (!lane) {
4861  /*
4862  * Account for spread spectrum to avoid
4863  * oversubscribing the link. Max center spread
4864  * is 2.5%; use 5% for safety's sake.
4865  */
4866  u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4867  lane = bps / (link_bw * 8) + 1;
4868  }
4869 
4870  intel_crtc->fdi_lanes = lane;
4871 
4872  if (pixel_multiplier > 1)
4873  link_bw *= pixel_multiplier;
4874  ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4875  &m_n);
4876 
4877  fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4878  if (has_reduced_clock)
4879  fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4880  reduced_clock.m2;
4881 
4882  /* Enable autotuning of the PLL clock (if permissible) */
4883  factor = 21;
4884  if (is_lvds) {
4885  if ((intel_panel_use_ssc(dev_priv) &&
4886  dev_priv->lvds_ssc_freq == 100) ||
4888  factor = 25;
4889  } else if (is_sdvo && is_tv)
4890  factor = 20;
4891 
4892  if (clock.m < factor * clock.n)
4893  fp |= FP_CB_TUNE;
4894 
4895  dpll = 0;
4896 
4897  if (is_lvds)
4898  dpll |= DPLLB_MODE_LVDS;
4899  else
4900  dpll |= DPLLB_MODE_DAC_SERIAL;
4901  if (is_sdvo) {
4902  int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4903  if (pixel_multiplier > 1) {
4904  dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4905  }
4906  dpll |= DPLL_DVO_HIGH_SPEED;
4907  }
4908  if (is_dp && !is_cpu_edp)
4909  dpll |= DPLL_DVO_HIGH_SPEED;
4910 
4911  /* compute bitmask from p1 value */
4912  dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4913  /* also FPA1 */
4914  dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4915 
4916  switch (clock.p2) {
4917  case 5:
4919  break;
4920  case 7:
4921  dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4922  break;
4923  case 10:
4925  break;
4926  case 14:
4928  break;
4929  }
4930 
4931  if (is_sdvo && is_tv)
4932  dpll |= PLL_REF_INPUT_TVCLKINBC;
4933  else if (is_tv)
4934  /* XXX: just matching BIOS for now */
4935  /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4936  dpll |= 3;
4937  else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4939  else
4940  dpll |= PLL_REF_INPUT_DREFCLK;
4941 
4942  DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4944 
4945  /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4946  * pre-Haswell/LPT generation */
4947  if (HAS_PCH_LPT(dev)) {
4948  DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4949  pipe);
4950  } else if (!is_cpu_edp) {
4951  struct intel_pch_pll *pll;
4952 
4953  pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4954  if (pll == NULL) {
4955  DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4956  pipe);
4957  return -EINVAL;
4958  }
4959  } else
4960  intel_put_pch_pll(intel_crtc);
4961 
4962  /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4963  * This is an exception to the general rule that mode_set doesn't turn
4964  * things on.
4965  */
4966  if (is_lvds) {
4967  temp = I915_READ(PCH_LVDS);
4968  temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4969  if (HAS_PCH_CPT(dev)) {
4970  temp &= ~PORT_TRANS_SEL_MASK;
4971  temp |= PORT_TRANS_SEL_CPT(pipe);
4972  } else {
4973  if (pipe == 1)
4974  temp |= LVDS_PIPEB_SELECT;
4975  else
4976  temp &= ~LVDS_PIPEB_SELECT;
4977  }
4978 
4979  /* set the corresponsding LVDS_BORDER bit */
4980  temp |= dev_priv->lvds_border_bits;
4981  /* Set the B0-B3 data pairs corresponding to whether we're going to
4982  * set the DPLLs for dual-channel mode or not.
4983  */
4984  if (clock.p2 == 7)
4986  else
4988 
4989  /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4990  * appropriately here, but we need to look more thoroughly into how
4991  * panels behave in the two modes.
4992  */
4994  if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4995  temp |= LVDS_HSYNC_POLARITY;
4996  if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4997  temp |= LVDS_VSYNC_POLARITY;
4998  I915_WRITE(PCH_LVDS, temp);
4999  }
5000 
5001  if (is_dp && !is_cpu_edp) {
5002  intel_dp_set_m_n(crtc, mode, adjusted_mode);
5003  } else {
5004  /* For non-DP output, clear any trans DP clock recovery setting.*/
5005  I915_WRITE(TRANSDATA_M1(pipe), 0);
5006  I915_WRITE(TRANSDATA_N1(pipe), 0);
5007  I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5008  I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5009  }
5010 
5011  if (intel_crtc->pch_pll) {
5012  I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5013 
5014  /* Wait for the clocks to stabilize. */
5015  POSTING_READ(intel_crtc->pch_pll->pll_reg);
5016  udelay(150);
5017 
5018  /* The pixel multiplier can only be updated once the
5019  * DPLL is enabled and the clocks are stable.
5020  *
5021  * So write it again.
5022  */
5023  I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5024  }
5025 
5026  intel_crtc->lowfreq_avail = false;
5027  if (intel_crtc->pch_pll) {
5028  if (is_lvds && has_reduced_clock && i915_powersave) {
5029  I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5030  intel_crtc->lowfreq_avail = true;
5031  } else {
5032  I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5033  }
5034  }
5035 
5036  if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5037  /* the chip adds 2 halflines automatically */
5038  adjusted_mode->crtc_vtotal -= 1;
5039  adjusted_mode->crtc_vblank_end -= 1;
5040  I915_WRITE(VSYNCSHIFT(pipe),
5041  adjusted_mode->crtc_hsync_start
5042  - adjusted_mode->crtc_htotal/2);
5043  } else {
5044  I915_WRITE(VSYNCSHIFT(pipe), 0);
5045  }
5046 
5047  I915_WRITE(HTOTAL(pipe),
5048  (adjusted_mode->crtc_hdisplay - 1) |
5049  ((adjusted_mode->crtc_htotal - 1) << 16));
5050  I915_WRITE(HBLANK(pipe),
5051  (adjusted_mode->crtc_hblank_start - 1) |
5052  ((adjusted_mode->crtc_hblank_end - 1) << 16));
5053  I915_WRITE(HSYNC(pipe),
5054  (adjusted_mode->crtc_hsync_start - 1) |
5055  ((adjusted_mode->crtc_hsync_end - 1) << 16));
5056 
5057  I915_WRITE(VTOTAL(pipe),
5058  (adjusted_mode->crtc_vdisplay - 1) |
5059  ((adjusted_mode->crtc_vtotal - 1) << 16));
5060  I915_WRITE(VBLANK(pipe),
5061  (adjusted_mode->crtc_vblank_start - 1) |
5062  ((adjusted_mode->crtc_vblank_end - 1) << 16));
5063  I915_WRITE(VSYNC(pipe),
5064  (adjusted_mode->crtc_vsync_start - 1) |
5065  ((adjusted_mode->crtc_vsync_end - 1) << 16));
5066 
5067  /* pipesrc controls the size that is scaled from, which should
5068  * always be the user's requested size.
5069  */
5070  I915_WRITE(PIPESRC(pipe),
5071  ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5072 
5073  I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5074  I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5075  I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5076  I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5077 
5078  if (is_cpu_edp)
5079  ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5080 
5081  ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5082 
5083  intel_wait_for_vblank(dev, pipe);
5084 
5085  /* Set up the display plane register */
5087  POSTING_READ(DSPCNTR(plane));
5088 
5089  ret = intel_pipe_set_base(crtc, x, y, fb);
5090 
5092 
5093  intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5094 
5095  return ret;
5096 }
5097 
5098 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5099  struct drm_display_mode *mode,
5100  struct drm_display_mode *adjusted_mode,
5101  int x, int y,
5102  struct drm_framebuffer *fb)
5103 {
5104  struct drm_device *dev = crtc->dev;
5105  struct drm_i915_private *dev_priv = dev->dev_private;
5106  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5107  int pipe = intel_crtc->pipe;
5108  int ret;
5109 
5110  drm_vblank_pre_modeset(dev, pipe);
5111 
5112  ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5113  x, y, fb);
5114  drm_vblank_post_modeset(dev, pipe);
5115 
5116  return ret;
5117 }
5118 
5119 static bool intel_eld_uptodate(struct drm_connector *connector,
5120  int reg_eldv, uint32_t bits_eldv,
5121  int reg_elda, uint32_t bits_elda,
5122  int reg_edid)
5123 {
5124  struct drm_i915_private *dev_priv = connector->dev->dev_private;
5125  uint8_t *eld = connector->eld;
5126  uint32_t i;
5127 
5128  i = I915_READ(reg_eldv);
5129  i &= bits_eldv;
5130 
5131  if (!eld[0])
5132  return !i;
5133 
5134  if (!i)
5135  return false;
5136 
5137  i = I915_READ(reg_elda);
5138  i &= ~bits_elda;
5139  I915_WRITE(reg_elda, i);
5140 
5141  for (i = 0; i < eld[2]; i++)
5142  if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5143  return false;
5144 
5145  return true;
5146 }
5147 
5148 static void g4x_write_eld(struct drm_connector *connector,
5149  struct drm_crtc *crtc)
5150 {
5151  struct drm_i915_private *dev_priv = connector->dev->dev_private;
5152  uint8_t *eld = connector->eld;
5153  uint32_t eldv;
5154  uint32_t len;
5155  uint32_t i;
5156 
5158 
5159  if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5160  eldv = G4X_ELDV_DEVCL_DEVBLC;
5161  else
5162  eldv = G4X_ELDV_DEVCTG;
5163 
5164  if (intel_eld_uptodate(connector,
5165  G4X_AUD_CNTL_ST, eldv,
5168  return;
5169 
5171  i &= ~(eldv | G4X_ELD_ADDR);
5172  len = (i >> 9) & 0x1f; /* ELD buffer size */
5174 
5175  if (!eld[0])
5176  return;
5177 
5178  len = min_t(uint8_t, eld[2], len);
5179  DRM_DEBUG_DRIVER("ELD size %d\n", len);
5180  for (i = 0; i < len; i++)
5181  I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5182 
5184  i |= eldv;
5186 }
5187 
5188 static void haswell_write_eld(struct drm_connector *connector,
5189  struct drm_crtc *crtc)
5190 {
5191  struct drm_i915_private *dev_priv = connector->dev->dev_private;
5192  uint8_t *eld = connector->eld;
5193  struct drm_device *dev = crtc->dev;
5194  uint32_t eldv;
5195  uint32_t i;
5196  int len;
5197  int pipe = to_intel_crtc(crtc)->pipe;
5198  int tmp;
5199 
5200  int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5201  int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5202  int aud_config = HSW_AUD_CFG(pipe);
5203  int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5204 
5205 
5206  DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5207 
5208  /* Audio output enable */
5209  DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5210  tmp = I915_READ(aud_cntrl_st2);
5211  tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5212  I915_WRITE(aud_cntrl_st2, tmp);
5213 
5214  /* Wait for 1 vertical blank */
5215  intel_wait_for_vblank(dev, pipe);
5216 
5217  /* Set ELD valid state */
5218  tmp = I915_READ(aud_cntrl_st2);
5219  DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5220  tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5221  I915_WRITE(aud_cntrl_st2, tmp);
5222  tmp = I915_READ(aud_cntrl_st2);
5223  DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5224 
5225  /* Enable HDMI mode */
5226  tmp = I915_READ(aud_config);
5227  DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5228  /* clear N_programing_enable and N_value_index */
5230  I915_WRITE(aud_config, tmp);
5231 
5232  DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5233 
5234  eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5235 
5237  DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5238  eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5239  I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5240  } else
5241  I915_WRITE(aud_config, 0);
5242 
5243  if (intel_eld_uptodate(connector,
5244  aud_cntrl_st2, eldv,
5245  aud_cntl_st, IBX_ELD_ADDRESS,
5246  hdmiw_hdmiedid))
5247  return;
5248 
5249  i = I915_READ(aud_cntrl_st2);
5250  i &= ~eldv;
5251  I915_WRITE(aud_cntrl_st2, i);
5252 
5253  if (!eld[0])
5254  return;
5255 
5256  i = I915_READ(aud_cntl_st);
5257  i &= ~IBX_ELD_ADDRESS;
5258  I915_WRITE(aud_cntl_st, i);
5259  i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5260  DRM_DEBUG_DRIVER("port num:%d\n", i);
5261 
5262  len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5263  DRM_DEBUG_DRIVER("ELD size %d\n", len);
5264  for (i = 0; i < len; i++)
5265  I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5266 
5267  i = I915_READ(aud_cntrl_st2);
5268  i |= eldv;
5269  I915_WRITE(aud_cntrl_st2, i);
5270 
5271 }
5272 
5273 static void ironlake_write_eld(struct drm_connector *connector,
5274  struct drm_crtc *crtc)
5275 {
5276  struct drm_i915_private *dev_priv = connector->dev->dev_private;
5277  uint8_t *eld = connector->eld;
5278  uint32_t eldv;
5279  uint32_t i;
5280  int len;
5281  int hdmiw_hdmiedid;
5282  int aud_config;
5283  int aud_cntl_st;
5284  int aud_cntrl_st2;
5285  int pipe = to_intel_crtc(crtc)->pipe;
5286 
5287  if (HAS_PCH_IBX(connector->dev)) {
5288  hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5289  aud_config = IBX_AUD_CFG(pipe);
5290  aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5291  aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5292  } else {
5293  hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5294  aud_config = CPT_AUD_CFG(pipe);
5295  aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5296  aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5297  }
5298 
5299  DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5300 
5301  i = I915_READ(aud_cntl_st);
5302  i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5303  if (!i) {
5304  DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5305  /* operate blindly on all ports */
5306  eldv = IBX_ELD_VALIDB;
5307  eldv |= IBX_ELD_VALIDB << 4;
5308  eldv |= IBX_ELD_VALIDB << 8;
5309  } else {
5310  DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5311  eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5312  }
5313 
5315  DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5316  eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5317  I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5318  } else
5319  I915_WRITE(aud_config, 0);
5320 
5321  if (intel_eld_uptodate(connector,
5322  aud_cntrl_st2, eldv,
5323  aud_cntl_st, IBX_ELD_ADDRESS,
5324  hdmiw_hdmiedid))
5325  return;
5326 
5327  i = I915_READ(aud_cntrl_st2);
5328  i &= ~eldv;
5329  I915_WRITE(aud_cntrl_st2, i);
5330 
5331  if (!eld[0])
5332  return;
5333 
5334  i = I915_READ(aud_cntl_st);
5335  i &= ~IBX_ELD_ADDRESS;
5336  I915_WRITE(aud_cntl_st, i);
5337 
5338  len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5339  DRM_DEBUG_DRIVER("ELD size %d\n", len);
5340  for (i = 0; i < len; i++)
5341  I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5342 
5343  i = I915_READ(aud_cntrl_st2);
5344  i |= eldv;
5345  I915_WRITE(aud_cntrl_st2, i);
5346 }
5347 
5348 void intel_write_eld(struct drm_encoder *encoder,
5349  struct drm_display_mode *mode)
5350 {
5351  struct drm_crtc *crtc = encoder->crtc;
5352  struct drm_connector *connector;
5353  struct drm_device *dev = encoder->dev;
5354  struct drm_i915_private *dev_priv = dev->dev_private;
5355 
5356  connector = drm_select_eld(encoder, mode);
5357  if (!connector)
5358  return;
5359 
5360  DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5361  connector->base.id,
5362  drm_get_connector_name(connector),
5363  connector->encoder->base.id,
5364  drm_get_encoder_name(connector->encoder));
5365 
5366  connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5367 
5368  if (dev_priv->display.write_eld)
5369  dev_priv->display.write_eld(connector, crtc);
5370 }
5371 
5373 void intel_crtc_load_lut(struct drm_crtc *crtc)
5374 {
5375  struct drm_device *dev = crtc->dev;
5376  struct drm_i915_private *dev_priv = dev->dev_private;
5377  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5378  int palreg = PALETTE(intel_crtc->pipe);
5379  int i;
5380 
5381  /* The clocks have to be on to load the palette. */
5382  if (!crtc->enabled || !intel_crtc->active)
5383  return;
5384 
5385  /* use legacy palette for Ironlake */
5386  if (HAS_PCH_SPLIT(dev))
5387  palreg = LGC_PALETTE(intel_crtc->pipe);
5388 
5389  for (i = 0; i < 256; i++) {
5390  I915_WRITE(palreg + 4 * i,
5391  (intel_crtc->lut_r[i] << 16) |
5392  (intel_crtc->lut_g[i] << 8) |
5393  intel_crtc->lut_b[i]);
5394  }
5395 }
5396 
5397 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5398 {
5399  struct drm_device *dev = crtc->dev;
5400  struct drm_i915_private *dev_priv = dev->dev_private;
5401  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5402  bool visible = base != 0;
5403  u32 cntl;
5404 
5405  if (intel_crtc->cursor_visible == visible)
5406  return;
5407 
5408  cntl = I915_READ(_CURACNTR);
5409  if (visible) {
5410  /* On these chipsets we can only modify the base whilst
5411  * the cursor is disabled.
5412  */
5413  I915_WRITE(_CURABASE, base);
5414 
5415  cntl &= ~(CURSOR_FORMAT_MASK);
5416  /* XXX width must be 64, stride 256 => 0x00 << 28 */
5417  cntl |= CURSOR_ENABLE |
5420  } else
5421  cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5422  I915_WRITE(_CURACNTR, cntl);
5423 
5424  intel_crtc->cursor_visible = visible;
5425 }
5426 
5427 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5428 {
5429  struct drm_device *dev = crtc->dev;
5430  struct drm_i915_private *dev_priv = dev->dev_private;
5431  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5432  int pipe = intel_crtc->pipe;
5433  bool visible = base != 0;
5434 
5435  if (intel_crtc->cursor_visible != visible) {
5436  uint32_t cntl = I915_READ(CURCNTR(pipe));
5437  if (base) {
5438  cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5440  cntl |= pipe << 28; /* Connect to correct pipe */
5441  } else {
5442  cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5443  cntl |= CURSOR_MODE_DISABLE;
5444  }
5445  I915_WRITE(CURCNTR(pipe), cntl);
5446 
5447  intel_crtc->cursor_visible = visible;
5448  }
5449  /* and commit changes on next vblank */
5450  I915_WRITE(CURBASE(pipe), base);
5451 }
5452 
5453 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5454 {
5455  struct drm_device *dev = crtc->dev;
5456  struct drm_i915_private *dev_priv = dev->dev_private;
5457  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5458  int pipe = intel_crtc->pipe;
5459  bool visible = base != 0;
5460 
5461  if (intel_crtc->cursor_visible != visible) {
5462  uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5463  if (base) {
5464  cntl &= ~CURSOR_MODE;
5466  } else {
5467  cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5468  cntl |= CURSOR_MODE_DISABLE;
5469  }
5470  I915_WRITE(CURCNTR_IVB(pipe), cntl);
5471 
5472  intel_crtc->cursor_visible = visible;
5473  }
5474  /* and commit changes on next vblank */
5475  I915_WRITE(CURBASE_IVB(pipe), base);
5476 }
5477 
5478 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5479 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5480  bool on)
5481 {
5482  struct drm_device *dev = crtc->dev;
5483  struct drm_i915_private *dev_priv = dev->dev_private;
5484  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5485  int pipe = intel_crtc->pipe;
5486  int x = intel_crtc->cursor_x;
5487  int y = intel_crtc->cursor_y;
5488  u32 base, pos;
5489  bool visible;
5490 
5491  pos = 0;
5492 
5493  if (on && crtc->enabled && crtc->fb) {
5494  base = intel_crtc->cursor_addr;
5495  if (x > (int) crtc->fb->width)
5496  base = 0;
5497 
5498  if (y > (int) crtc->fb->height)
5499  base = 0;
5500  } else
5501  base = 0;
5502 
5503  if (x < 0) {
5504  if (x + intel_crtc->cursor_width < 0)
5505  base = 0;
5506 
5507  pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5508  x = -x;
5509  }
5510  pos |= x << CURSOR_X_SHIFT;
5511 
5512  if (y < 0) {
5513  if (y + intel_crtc->cursor_height < 0)
5514  base = 0;
5515 
5516  pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5517  y = -y;
5518  }
5519  pos |= y << CURSOR_Y_SHIFT;
5520 
5521  visible = base != 0;
5522  if (!visible && !intel_crtc->cursor_visible)
5523  return;
5524 
5525  if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5526  I915_WRITE(CURPOS_IVB(pipe), pos);
5527  ivb_update_cursor(crtc, base);
5528  } else {
5529  I915_WRITE(CURPOS(pipe), pos);
5530  if (IS_845G(dev) || IS_I865G(dev))
5531  i845_update_cursor(crtc, base);
5532  else
5533  i9xx_update_cursor(crtc, base);
5534  }
5535 }
5536 
5537 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5538  struct drm_file *file,
5539  uint32_t handle,
5541 {
5542  struct drm_device *dev = crtc->dev;
5543  struct drm_i915_private *dev_priv = dev->dev_private;
5544  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5545  struct drm_i915_gem_object *obj;
5546  uint32_t addr;
5547  int ret;
5548 
5549  /* if we want to turn off the cursor ignore width and height */
5550  if (!handle) {
5551  DRM_DEBUG_KMS("cursor off\n");
5552  addr = 0;
5553  obj = NULL;
5554  mutex_lock(&dev->struct_mutex);
5555  goto finish;
5556  }
5557 
5558  /* Currently we only support 64x64 cursors */
5559  if (width != 64 || height != 64) {
5560  DRM_ERROR("we currently only support 64x64 cursors\n");
5561  return -EINVAL;
5562  }
5563 
5564  obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5565  if (&obj->base == NULL)
5566  return -ENOENT;
5567 
5568  if (obj->base.size < width * height * 4) {
5569  DRM_ERROR("buffer is to small\n");
5570  ret = -ENOMEM;
5571  goto fail;
5572  }
5573 
5574  /* we only need to pin inside GTT if cursor is non-phy */
5575  mutex_lock(&dev->struct_mutex);
5576  if (!dev_priv->info->cursor_needs_physical) {
5577  if (obj->tiling_mode) {
5578  DRM_ERROR("cursor cannot be tiled\n");
5579  ret = -EINVAL;
5580  goto fail_locked;
5581  }
5582 
5584  if (ret) {
5585  DRM_ERROR("failed to move cursor bo into the GTT\n");
5586  goto fail_locked;
5587  }
5588 
5589  ret = i915_gem_object_put_fence(obj);
5590  if (ret) {
5591  DRM_ERROR("failed to release fence for cursor");
5592  goto fail_unpin;
5593  }
5594 
5595  addr = obj->gtt_offset;
5596  } else {
5597  int align = IS_I830(dev) ? 16 * 1024 : 256;
5598  ret = i915_gem_attach_phys_object(dev, obj,
5599  (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5600  align);
5601  if (ret) {
5602  DRM_ERROR("failed to attach phys object\n");
5603  goto fail_locked;
5604  }
5605  addr = obj->phys_obj->handle->busaddr;
5606  }
5607 
5608  if (IS_GEN2(dev))
5609  I915_WRITE(CURSIZE, (height << 12) | width);
5610 
5611  finish:
5612  if (intel_crtc->cursor_bo) {
5613  if (dev_priv->info->cursor_needs_physical) {
5614  if (intel_crtc->cursor_bo != obj)
5615  i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5616  } else
5617  i915_gem_object_unpin(intel_crtc->cursor_bo);
5618  drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5619  }
5620 
5621  mutex_unlock(&dev->struct_mutex);
5622 
5623  intel_crtc->cursor_addr = addr;
5624  intel_crtc->cursor_bo = obj;
5625  intel_crtc->cursor_width = width;
5626  intel_crtc->cursor_height = height;
5627 
5628  intel_crtc_update_cursor(crtc, true);
5629 
5630  return 0;
5631 fail_unpin:
5632  i915_gem_object_unpin(obj);
5633 fail_locked:
5634  mutex_unlock(&dev->struct_mutex);
5635 fail:
5636  drm_gem_object_unreference_unlocked(&obj->base);
5637  return ret;
5638 }
5639 
5640 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5641 {
5642  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5643 
5644  intel_crtc->cursor_x = x;
5645  intel_crtc->cursor_y = y;
5646 
5647  intel_crtc_update_cursor(crtc, true);
5648 
5649  return 0;
5650 }
5651 
5654  u16 blue, int regno)
5655 {
5656  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5657 
5658  intel_crtc->lut_r[regno] = red >> 8;
5659  intel_crtc->lut_g[regno] = green >> 8;
5660  intel_crtc->lut_b[regno] = blue >> 8;
5661 }
5662 
5664  u16 *blue, int regno)
5665 {
5666  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5667 
5668  *red = intel_crtc->lut_r[regno] << 8;
5669  *green = intel_crtc->lut_g[regno] << 8;
5670  *blue = intel_crtc->lut_b[regno] << 8;
5671 }
5672 
5673 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5675 {
5676  int end = (start + size > 256) ? 256 : start + size, i;
5677  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5678 
5679  for (i = start; i < end; i++) {
5680  intel_crtc->lut_r[i] = red[i] >> 8;
5681  intel_crtc->lut_g[i] = green[i] >> 8;
5682  intel_crtc->lut_b[i] = blue[i] >> 8;
5683  }
5684 
5685  intel_crtc_load_lut(crtc);
5686 }
5687 
5702 /* VESA 640x480x72Hz mode to set on the pipe */
5703 static struct drm_display_mode load_detect_mode = {
5704  DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5705  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5706 };
5707 
5708 static struct drm_framebuffer *
5709 intel_framebuffer_create(struct drm_device *dev,
5710  struct drm_mode_fb_cmd2 *mode_cmd,
5711  struct drm_i915_gem_object *obj)
5712 {
5713  struct intel_framebuffer *intel_fb;
5714  int ret;
5715 
5716  intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5717  if (!intel_fb) {
5718  drm_gem_object_unreference_unlocked(&obj->base);
5719  return ERR_PTR(-ENOMEM);
5720  }
5721 
5722  ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5723  if (ret) {
5724  drm_gem_object_unreference_unlocked(&obj->base);
5725  kfree(intel_fb);
5726  return ERR_PTR(ret);
5727  }
5728 
5729  return &intel_fb->base;
5730 }
5731 
5732 static u32
5733 intel_framebuffer_pitch_for_width(int width, int bpp)
5734 {
5735  u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5736  return ALIGN(pitch, 64);
5737 }
5738 
5739 static u32
5740 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5741 {
5742  u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5743  return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5744 }
5745 
5746 static struct drm_framebuffer *
5747 intel_framebuffer_create_for_mode(struct drm_device *dev,
5748  struct drm_display_mode *mode,
5749  int depth, int bpp)
5750 {
5751  struct drm_i915_gem_object *obj;
5752  struct drm_mode_fb_cmd2 mode_cmd;
5753 
5754  obj = i915_gem_alloc_object(dev,
5755  intel_framebuffer_size_for_mode(mode, bpp));
5756  if (obj == NULL)
5757  return ERR_PTR(-ENOMEM);
5758 
5759  mode_cmd.width = mode->hdisplay;
5760  mode_cmd.height = mode->vdisplay;
5761  mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5762  bpp);
5763  mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5764 
5765  return intel_framebuffer_create(dev, &mode_cmd, obj);
5766 }
5767 
5768 static struct drm_framebuffer *
5769 mode_fits_in_fbdev(struct drm_device *dev,
5770  struct drm_display_mode *mode)
5771 {
5772  struct drm_i915_private *dev_priv = dev->dev_private;
5773  struct drm_i915_gem_object *obj;
5774  struct drm_framebuffer *fb;
5775 
5776  if (dev_priv->fbdev == NULL)
5777  return NULL;
5778 
5779  obj = dev_priv->fbdev->ifb.obj;
5780  if (obj == NULL)
5781  return NULL;
5782 
5783  fb = &dev_priv->fbdev->ifb.base;
5784  if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5785  fb->bits_per_pixel))
5786  return NULL;
5787 
5788  if (obj->base.size < mode->vdisplay * fb->pitches[0])
5789  return NULL;
5790 
5791  return fb;
5792 }
5793 
5795  struct drm_display_mode *mode,
5796  struct intel_load_detect_pipe *old)
5797 {
5798  struct intel_crtc *intel_crtc;
5799  struct intel_encoder *intel_encoder =
5800  intel_attached_encoder(connector);
5801  struct drm_crtc *possible_crtc;
5802  struct drm_encoder *encoder = &intel_encoder->base;
5803  struct drm_crtc *crtc = NULL;
5804  struct drm_device *dev = encoder->dev;
5805  struct drm_framebuffer *fb;
5806  int i = -1;
5807 
5808  DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5809  connector->base.id, drm_get_connector_name(connector),
5810  encoder->base.id, drm_get_encoder_name(encoder));
5811 
5812  /*
5813  * Algorithm gets a little messy:
5814  *
5815  * - if the connector already has an assigned crtc, use it (but make
5816  * sure it's on first)
5817  *
5818  * - try to find the first unused crtc that can drive this connector,
5819  * and use that if we find one
5820  */
5821 
5822  /* See if we already have a CRTC for this connector */
5823  if (encoder->crtc) {
5824  crtc = encoder->crtc;
5825 
5826  old->dpms_mode = connector->dpms;
5827  old->load_detect_temp = false;
5828 
5829  /* Make sure the crtc and connector are running */
5830  if (connector->dpms != DRM_MODE_DPMS_ON)
5831  connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
5832 
5833  return true;
5834  }
5835 
5836  /* Find an unused one (if possible) */
5837  list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5838  i++;
5839  if (!(encoder->possible_crtcs & (1 << i)))
5840  continue;
5841  if (!possible_crtc->enabled) {
5842  crtc = possible_crtc;
5843  break;
5844  }
5845  }
5846 
5847  /*
5848  * If we didn't find an unused CRTC, don't use any.
5849  */
5850  if (!crtc) {
5851  DRM_DEBUG_KMS("no pipe available for load-detect\n");
5852  return false;
5853  }
5854 
5855  intel_encoder->new_crtc = to_intel_crtc(crtc);
5856  to_intel_connector(connector)->new_encoder = intel_encoder;
5857 
5858  intel_crtc = to_intel_crtc(crtc);
5859  old->dpms_mode = connector->dpms;
5860  old->load_detect_temp = true;
5861  old->release_fb = NULL;
5862 
5863  if (!mode)
5864  mode = &load_detect_mode;
5865 
5866  /* We need a framebuffer large enough to accommodate all accesses
5867  * that the plane may generate whilst we perform load detection.
5868  * We can not rely on the fbcon either being present (we get called
5869  * during its initialisation to detect all boot displays, or it may
5870  * not even exist) or that it is large enough to satisfy the
5871  * requested mode.
5872  */
5873  fb = mode_fits_in_fbdev(dev, mode);
5874  if (fb == NULL) {
5875  DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5876  fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5877  old->release_fb = fb;
5878  } else
5879  DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5880  if (IS_ERR(fb)) {
5881  DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5882  goto fail;
5883  }
5884 
5885  if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
5886  DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5887  if (old->release_fb)
5888  old->release_fb->funcs->destroy(old->release_fb);
5889  goto fail;
5890  }
5891 
5892  /* let the connector get through one full cycle before testing */
5893  intel_wait_for_vblank(dev, intel_crtc->pipe);
5894 
5895  return true;
5896 fail:
5897  connector->encoder = NULL;
5898  encoder->crtc = NULL;
5899  return false;
5900 }
5901 
5903  struct intel_load_detect_pipe *old)
5904 {
5905  struct intel_encoder *intel_encoder =
5906  intel_attached_encoder(connector);
5907  struct drm_encoder *encoder = &intel_encoder->base;
5908 
5909  DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5910  connector->base.id, drm_get_connector_name(connector),
5911  encoder->base.id, drm_get_encoder_name(encoder));
5912 
5913  if (old->load_detect_temp) {
5914  struct drm_crtc *crtc = encoder->crtc;
5915 
5916  to_intel_connector(connector)->new_encoder = NULL;
5917  intel_encoder->new_crtc = NULL;
5918  intel_set_mode(crtc, NULL, 0, 0, NULL);
5919 
5920  if (old->release_fb)
5921  old->release_fb->funcs->destroy(old->release_fb);
5922 
5923  return;
5924  }
5925 
5926  /* Switch crtc and encoder back off if necessary */
5927  if (old->dpms_mode != DRM_MODE_DPMS_ON)
5928  connector->funcs->dpms(connector, old->dpms_mode);
5929 }
5930 
5931 /* Returns the clock of the currently programmed mode of the given pipe. */
5932 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5933 {
5934  struct drm_i915_private *dev_priv = dev->dev_private;
5935  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5936  int pipe = intel_crtc->pipe;
5937  u32 dpll = I915_READ(DPLL(pipe));
5938  u32 fp;
5940 
5941  if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5942  fp = I915_READ(FP0(pipe));
5943  else
5944  fp = I915_READ(FP1(pipe));
5945 
5946  clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5947  if (IS_PINEVIEW(dev)) {
5948  clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5949  clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5950  } else {
5951  clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5952  clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5953  }
5954 
5955  if (!IS_GEN2(dev)) {
5956  if (IS_PINEVIEW(dev))
5957  clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5959  else
5960  clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5962 
5963  switch (dpll & DPLL_MODE_MASK) {
5964  case DPLLB_MODE_DAC_SERIAL:
5965  clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5966  5 : 10;
5967  break;
5968  case DPLLB_MODE_LVDS:
5969  clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5970  7 : 14;
5971  break;
5972  default:
5973  DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5974  "mode\n", (int)(dpll & DPLL_MODE_MASK));
5975  return 0;
5976  }
5977 
5978  /* XXX: Handle the 100Mhz refclk */
5979  intel_clock(dev, 96000, &clock);
5980  } else {
5981  bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5982 
5983  if (is_lvds) {
5984  clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5986  clock.p2 = 14;
5987 
5988  if ((dpll & PLL_REF_INPUT_MASK) ==
5990  /* XXX: might not be 66MHz */
5991  intel_clock(dev, 66000, &clock);
5992  } else
5993  intel_clock(dev, 48000, &clock);
5994  } else {
5995  if (dpll & PLL_P1_DIVIDE_BY_TWO)
5996  clock.p1 = 2;
5997  else {
5998  clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6000  }
6001  if (dpll & PLL_P2_DIVIDE_BY_4)
6002  clock.p2 = 4;
6003  else
6004  clock.p2 = 2;
6005 
6006  intel_clock(dev, 48000, &clock);
6007  }
6008  }
6009 
6010  /* XXX: It would be nice to validate the clocks, but we can't reuse
6011  * i830PllIsValid() because it relies on the xf86_config connector
6012  * configuration being accurate, which it isn't necessarily.
6013  */
6014 
6015  return clock.dot;
6016 }
6017 
6020  struct drm_crtc *crtc)
6021 {
6022  struct drm_i915_private *dev_priv = dev->dev_private;
6023  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6024  int pipe = intel_crtc->pipe;
6025  struct drm_display_mode *mode;
6026  int htot = I915_READ(HTOTAL(pipe));
6027  int hsync = I915_READ(HSYNC(pipe));
6028  int vtot = I915_READ(VTOTAL(pipe));
6029  int vsync = I915_READ(VSYNC(pipe));
6030 
6031  mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6032  if (!mode)
6033  return NULL;
6034 
6035  mode->clock = intel_crtc_clock_get(dev, crtc);
6036  mode->hdisplay = (htot & 0xffff) + 1;
6037  mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6038  mode->hsync_start = (hsync & 0xffff) + 1;
6039  mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6040  mode->vdisplay = (vtot & 0xffff) + 1;
6041  mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6042  mode->vsync_start = (vsync & 0xffff) + 1;
6043  mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6044 
6045  drm_mode_set_name(mode);
6046 
6047  return mode;
6048 }
6049 
6050 static void intel_increase_pllclock(struct drm_crtc *crtc)
6051 {
6052  struct drm_device *dev = crtc->dev;
6053  drm_i915_private_t *dev_priv = dev->dev_private;
6054  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6055  int pipe = intel_crtc->pipe;
6056  int dpll_reg = DPLL(pipe);
6057  int dpll;
6058 
6059  if (HAS_PCH_SPLIT(dev))
6060  return;
6061 
6062  if (!dev_priv->lvds_downclock_avail)
6063  return;
6064 
6065  dpll = I915_READ(dpll_reg);
6066  if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6067  DRM_DEBUG_DRIVER("upclocking LVDS\n");
6068 
6069  assert_panel_unlocked(dev_priv, pipe);
6070 
6071  dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6072  I915_WRITE(dpll_reg, dpll);
6073  intel_wait_for_vblank(dev, pipe);
6074 
6075  dpll = I915_READ(dpll_reg);
6076  if (dpll & DISPLAY_RATE_SELECT_FPA1)
6077  DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6078  }
6079 }
6080 
6081 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6082 {
6083  struct drm_device *dev = crtc->dev;
6084  drm_i915_private_t *dev_priv = dev->dev_private;
6085  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6086 
6087  if (HAS_PCH_SPLIT(dev))
6088  return;
6089 
6090  if (!dev_priv->lvds_downclock_avail)
6091  return;
6092 
6093  /*
6094  * Since this is called by a timer, we should never get here in
6095  * the manual case.
6096  */
6097  if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6098  int pipe = intel_crtc->pipe;
6099  int dpll_reg = DPLL(pipe);
6100  int dpll;
6101 
6102  DRM_DEBUG_DRIVER("downclocking LVDS\n");
6103 
6104  assert_panel_unlocked(dev_priv, pipe);
6105 
6106  dpll = I915_READ(dpll_reg);
6107  dpll |= DISPLAY_RATE_SELECT_FPA1;
6108  I915_WRITE(dpll_reg, dpll);
6109  intel_wait_for_vblank(dev, pipe);
6110  dpll = I915_READ(dpll_reg);
6111  if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6112  DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6113  }
6114 
6115 }
6116 
6117 void intel_mark_busy(struct drm_device *dev)
6118 {
6119  i915_update_gfx_val(dev->dev_private);
6120 }
6121 
6122 void intel_mark_idle(struct drm_device *dev)
6123 {
6124 }
6125 
6127 {
6128  struct drm_device *dev = obj->base.dev;
6129  struct drm_crtc *crtc;
6130 
6131  if (!i915_powersave)
6132  return;
6133 
6134  list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6135  if (!crtc->fb)
6136  continue;
6137 
6138  if (to_intel_framebuffer(crtc->fb)->obj == obj)
6139  intel_increase_pllclock(crtc);
6140  }
6141 }
6142 
6144 {
6145  struct drm_device *dev = obj->base.dev;
6146  struct drm_crtc *crtc;
6147 
6148  if (!i915_powersave)
6149  return;
6150 
6151  list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6152  if (!crtc->fb)
6153  continue;
6154 
6155  if (to_intel_framebuffer(crtc->fb)->obj == obj)
6156  intel_decrease_pllclock(crtc);
6157  }
6158 }
6159 
6160 static void intel_crtc_destroy(struct drm_crtc *crtc)
6161 {
6162  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6163  struct drm_device *dev = crtc->dev;
6164  struct intel_unpin_work *work;
6165  unsigned long flags;
6166 
6167  spin_lock_irqsave(&dev->event_lock, flags);
6168  work = intel_crtc->unpin_work;
6169  intel_crtc->unpin_work = NULL;
6170  spin_unlock_irqrestore(&dev->event_lock, flags);
6171 
6172  if (work) {
6173  cancel_work_sync(&work->work);
6174  kfree(work);
6175  }
6176 
6177  drm_crtc_cleanup(crtc);
6178 
6179  kfree(intel_crtc);
6180 }
6181 
6182 static void intel_unpin_work_fn(struct work_struct *__work)
6183 {
6184  struct intel_unpin_work *work =
6185  container_of(__work, struct intel_unpin_work, work);
6186 
6187  mutex_lock(&work->dev->struct_mutex);
6189  drm_gem_object_unreference(&work->pending_flip_obj->base);
6190  drm_gem_object_unreference(&work->old_fb_obj->base);
6191 
6192  intel_update_fbc(work->dev);
6193  mutex_unlock(&work->dev->struct_mutex);
6194  kfree(work);
6195 }
6196 
6197 static void do_intel_finish_page_flip(struct drm_device *dev,
6198  struct drm_crtc *crtc)
6199 {
6200  drm_i915_private_t *dev_priv = dev->dev_private;
6201  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6202  struct intel_unpin_work *work;
6203  struct drm_i915_gem_object *obj;
6204  struct drm_pending_vblank_event *e;
6205  struct timeval tvbl;
6206  unsigned long flags;
6207 
6208  /* Ignore early vblank irqs */
6209  if (intel_crtc == NULL)
6210  return;
6211 
6212  spin_lock_irqsave(&dev->event_lock, flags);
6213  work = intel_crtc->unpin_work;
6214  if (work == NULL || !work->pending) {
6215  spin_unlock_irqrestore(&dev->event_lock, flags);
6216  return;
6217  }
6218 
6219  intel_crtc->unpin_work = NULL;
6220 
6221  if (work->event) {
6222  e = work->event;
6223  e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6224 
6225  e->event.tv_sec = tvbl.tv_sec;
6226  e->event.tv_usec = tvbl.tv_usec;
6227 
6228  list_add_tail(&e->base.link,
6229  &e->base.file_priv->event_list);
6230  wake_up_interruptible(&e->base.file_priv->event_wait);
6231  }
6232 
6233  drm_vblank_put(dev, intel_crtc->pipe);
6234 
6235  spin_unlock_irqrestore(&dev->event_lock, flags);
6236 
6237  obj = work->old_fb_obj;
6238 
6239  atomic_clear_mask(1 << intel_crtc->plane,
6240  &obj->pending_flip.counter);
6241 
6242  wake_up(&dev_priv->pending_flip_queue);
6243  schedule_work(&work->work);
6244 
6245  trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6246 }
6247 
6248 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6249 {
6250  drm_i915_private_t *dev_priv = dev->dev_private;
6251  struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6252 
6253  do_intel_finish_page_flip(dev, crtc);
6254 }
6255 
6256 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6257 {
6258  drm_i915_private_t *dev_priv = dev->dev_private;
6259  struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6260 
6261  do_intel_finish_page_flip(dev, crtc);
6262 }
6263 
6264 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6265 {
6266  drm_i915_private_t *dev_priv = dev->dev_private;
6267  struct intel_crtc *intel_crtc =
6268  to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6269  unsigned long flags;
6270 
6271  spin_lock_irqsave(&dev->event_lock, flags);
6272  if (intel_crtc->unpin_work) {
6273  if ((++intel_crtc->unpin_work->pending) > 1)
6274  DRM_ERROR("Prepared flip multiple times\n");
6275  } else {
6276  DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6277  }
6278  spin_unlock_irqrestore(&dev->event_lock, flags);
6279 }
6280 
6281 static int intel_gen2_queue_flip(struct drm_device *dev,
6282  struct drm_crtc *crtc,
6283  struct drm_framebuffer *fb,
6284  struct drm_i915_gem_object *obj)
6285 {
6286  struct drm_i915_private *dev_priv = dev->dev_private;
6287  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6288  u32 flip_mask;
6289  struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6290  int ret;
6291 
6292  ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6293  if (ret)
6294  goto err;
6295 
6296  ret = intel_ring_begin(ring, 6);
6297  if (ret)
6298  goto err_unpin;
6299 
6300  /* Can't queue multiple flips, so wait for the previous
6301  * one to finish before executing the next.
6302  */
6303  if (intel_crtc->plane)
6304  flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6305  else
6306  flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6307  intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6308  intel_ring_emit(ring, MI_NOOP);
6309  intel_ring_emit(ring, MI_DISPLAY_FLIP |
6310  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6311  intel_ring_emit(ring, fb->pitches[0]);
6312  intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6313  intel_ring_emit(ring, 0); /* aux display base address, unused */
6314  intel_ring_advance(ring);
6315  return 0;
6316 
6317 err_unpin:
6318  intel_unpin_fb_obj(obj);
6319 err:
6320  return ret;
6321 }
6322 
6323 static int intel_gen3_queue_flip(struct drm_device *dev,
6324  struct drm_crtc *crtc,
6325  struct drm_framebuffer *fb,
6326  struct drm_i915_gem_object *obj)
6327 {
6328  struct drm_i915_private *dev_priv = dev->dev_private;
6329  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6330  u32 flip_mask;
6331  struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6332  int ret;
6333 
6334  ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6335  if (ret)
6336  goto err;
6337 
6338  ret = intel_ring_begin(ring, 6);
6339  if (ret)
6340  goto err_unpin;
6341 
6342  if (intel_crtc->plane)
6343  flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6344  else
6345  flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6346  intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6347  intel_ring_emit(ring, MI_NOOP);
6348  intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6349  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6350  intel_ring_emit(ring, fb->pitches[0]);
6351  intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6352  intel_ring_emit(ring, MI_NOOP);
6353 
6354  intel_ring_advance(ring);
6355  return 0;
6356 
6357 err_unpin:
6358  intel_unpin_fb_obj(obj);
6359 err:
6360  return ret;
6361 }
6362 
6363 static int intel_gen4_queue_flip(struct drm_device *dev,
6364  struct drm_crtc *crtc,
6365  struct drm_framebuffer *fb,
6366  struct drm_i915_gem_object *obj)
6367 {
6368  struct drm_i915_private *dev_priv = dev->dev_private;
6369  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6370  uint32_t pf, pipesrc;
6371  struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6372  int ret;
6373 
6374  ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6375  if (ret)
6376  goto err;
6377 
6378  ret = intel_ring_begin(ring, 4);
6379  if (ret)
6380  goto err_unpin;
6381 
6382  /* i965+ uses the linear or tiled offsets from the
6383  * Display Registers (which do not change across a page-flip)
6384  * so we need only reprogram the base address.
6385  */
6386  intel_ring_emit(ring, MI_DISPLAY_FLIP |
6387  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6388  intel_ring_emit(ring, fb->pitches[0]);
6389  intel_ring_emit(ring,
6390  (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6391  obj->tiling_mode);
6392 
6393  /* XXX Enabling the panel-fitter across page-flip is so far
6394  * untested on non-native modes, so ignore it for now.
6395  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6396  */
6397  pf = 0;
6398  pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6399  intel_ring_emit(ring, pf | pipesrc);
6400  intel_ring_advance(ring);
6401  return 0;
6402 
6403 err_unpin:
6404  intel_unpin_fb_obj(obj);
6405 err:
6406  return ret;
6407 }
6408 
6409 static int intel_gen6_queue_flip(struct drm_device *dev,
6410  struct drm_crtc *crtc,
6411  struct drm_framebuffer *fb,
6412  struct drm_i915_gem_object *obj)
6413 {
6414  struct drm_i915_private *dev_priv = dev->dev_private;
6415  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6416  struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6417  uint32_t pf, pipesrc;
6418  int ret;
6419 
6420  ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6421  if (ret)
6422  goto err;
6423 
6424  ret = intel_ring_begin(ring, 4);
6425  if (ret)
6426  goto err_unpin;
6427 
6428  intel_ring_emit(ring, MI_DISPLAY_FLIP |
6429  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6430  intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6431  intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6432 
6433  /* Contrary to the suggestions in the documentation,
6434  * "Enable Panel Fitter" does not seem to be required when page
6435  * flipping with a non-native mode, and worse causes a normal
6436  * modeset to fail.
6437  * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6438  */
6439  pf = 0;
6440  pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6441  intel_ring_emit(ring, pf | pipesrc);
6442  intel_ring_advance(ring);
6443  return 0;
6444 
6445 err_unpin:
6446  intel_unpin_fb_obj(obj);
6447 err:
6448  return ret;
6449 }
6450 
6451 /*
6452  * On gen7 we currently use the blit ring because (in early silicon at least)
6453  * the render ring doesn't give us interrpts for page flip completion, which
6454  * means clients will hang after the first flip is queued. Fortunately the
6455  * blit ring generates interrupts properly, so use it instead.
6456  */
6457 static int intel_gen7_queue_flip(struct drm_device *dev,
6458  struct drm_crtc *crtc,
6459  struct drm_framebuffer *fb,
6460  struct drm_i915_gem_object *obj)
6461 {
6462  struct drm_i915_private *dev_priv = dev->dev_private;
6463  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6464  struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6465  uint32_t plane_bit = 0;
6466  int ret;
6467 
6468  ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6469  if (ret)
6470  goto err;
6471 
6472  switch(intel_crtc->plane) {
6473  case PLANE_A:
6474  plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6475  break;
6476  case PLANE_B:
6477  plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6478  break;
6479  case PLANE_C:
6480  plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6481  break;
6482  default:
6483  WARN_ONCE(1, "unknown plane in flip command\n");
6484  ret = -ENODEV;
6485  goto err_unpin;
6486  }
6487 
6488  ret = intel_ring_begin(ring, 4);
6489  if (ret)
6490  goto err_unpin;
6491 
6492  intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6493  intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6494  intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6495  intel_ring_emit(ring, (MI_NOOP));
6496  intel_ring_advance(ring);
6497  return 0;
6498 
6499 err_unpin:
6500  intel_unpin_fb_obj(obj);
6501 err:
6502  return ret;
6503 }
6504 
6505 static int intel_default_queue_flip(struct drm_device *dev,
6506  struct drm_crtc *crtc,
6507  struct drm_framebuffer *fb,
6508  struct drm_i915_gem_object *obj)
6509 {
6510  return -ENODEV;
6511 }
6512 
6513 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6514  struct drm_framebuffer *fb,
6515  struct drm_pending_vblank_event *event)
6516 {
6517  struct drm_device *dev = crtc->dev;
6518  struct drm_i915_private *dev_priv = dev->dev_private;
6519  struct intel_framebuffer *intel_fb;
6520  struct drm_i915_gem_object *obj;
6521  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6522  struct intel_unpin_work *work;
6523  unsigned long flags;
6524  int ret;
6525 
6526  /* Can't change pixel format via MI display flips. */
6527  if (fb->pixel_format != crtc->fb->pixel_format)
6528  return -EINVAL;
6529 
6530  /*
6531  * TILEOFF/LINOFF registers can't be changed via MI display flips.
6532  * Note that pitch changes could also affect these register.
6533  */
6534  if (INTEL_INFO(dev)->gen > 3 &&
6535  (fb->offsets[0] != crtc->fb->offsets[0] ||
6536  fb->pitches[0] != crtc->fb->pitches[0]))
6537  return -EINVAL;
6538 
6539  work = kzalloc(sizeof *work, GFP_KERNEL);
6540  if (work == NULL)
6541  return -ENOMEM;
6542 
6543  work->event = event;
6544  work->dev = crtc->dev;
6545  intel_fb = to_intel_framebuffer(crtc->fb);
6546  work->old_fb_obj = intel_fb->obj;
6547  INIT_WORK(&work->work, intel_unpin_work_fn);
6548 
6549  ret = drm_vblank_get(dev, intel_crtc->pipe);
6550  if (ret)
6551  goto free_work;
6552 
6553  /* We borrow the event spin lock for protecting unpin_work */
6554  spin_lock_irqsave(&dev->event_lock, flags);
6555  if (intel_crtc->unpin_work) {
6556  spin_unlock_irqrestore(&dev->event_lock, flags);
6557  kfree(work);
6558  drm_vblank_put(dev, intel_crtc->pipe);
6559 
6560  DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6561  return -EBUSY;
6562  }
6563  intel_crtc->unpin_work = work;
6564  spin_unlock_irqrestore(&dev->event_lock, flags);
6565 
6566  intel_fb = to_intel_framebuffer(fb);
6567  obj = intel_fb->obj;
6568 
6569  ret = i915_mutex_lock_interruptible(dev);
6570  if (ret)
6571  goto cleanup;
6572 
6573  /* Reference the objects for the scheduled work. */
6574  drm_gem_object_reference(&work->old_fb_obj->base);
6575  drm_gem_object_reference(&obj->base);
6576 
6577  crtc->fb = fb;
6578 
6579  work->pending_flip_obj = obj;
6580 
6581  work->enable_stall_check = true;
6582 
6583  /* Block clients from rendering to the new back buffer until
6584  * the flip occurs and the object is no longer visible.
6585  */
6586  atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6587 
6588  ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6589  if (ret)
6590  goto cleanup_pending;
6591 
6592  intel_disable_fbc(dev);
6593  intel_mark_fb_busy(obj);
6594  mutex_unlock(&dev->struct_mutex);
6595 
6596  trace_i915_flip_request(intel_crtc->plane, obj);
6597 
6598  return 0;
6599 
6600 cleanup_pending:
6601  atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6602  drm_gem_object_unreference(&work->old_fb_obj->base);
6603  drm_gem_object_unreference(&obj->base);
6604  mutex_unlock(&dev->struct_mutex);
6605 
6606 cleanup:
6607  spin_lock_irqsave(&dev->event_lock, flags);
6608  intel_crtc->unpin_work = NULL;
6609  spin_unlock_irqrestore(&dev->event_lock, flags);
6610 
6611  drm_vblank_put(dev, intel_crtc->pipe);
6612 free_work:
6613  kfree(work);
6614 
6615  return ret;
6616 }
6617 
6618 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6619  .mode_set_base_atomic = intel_pipe_set_base_atomic,
6620  .load_lut = intel_crtc_load_lut,
6621  .disable = intel_crtc_noop,
6622 };
6623 
6624 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6625 {
6626  struct intel_encoder *other_encoder;
6627  struct drm_crtc *crtc = &encoder->new_crtc->base;
6628 
6629  if (WARN_ON(!crtc))
6630  return false;
6631 
6632  list_for_each_entry(other_encoder,
6633  &crtc->dev->mode_config.encoder_list,
6634  base.head) {
6635 
6636  if (&other_encoder->new_crtc->base != crtc ||
6637  encoder == other_encoder)
6638  continue;
6639  else
6640  return true;
6641  }
6642 
6643  return false;
6644 }
6645 
6646 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6647  struct drm_crtc *crtc)
6648 {
6649  struct drm_device *dev;
6650  struct drm_crtc *tmp;
6651  int crtc_mask = 1;
6652 
6653  WARN(!crtc, "checking null crtc?\n");
6654 
6655  dev = crtc->dev;
6656 
6657  list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6658  if (tmp == crtc)
6659  break;
6660  crtc_mask <<= 1;
6661  }
6662 
6663  if (encoder->possible_crtcs & crtc_mask)
6664  return true;
6665  return false;
6666 }
6667 
6674 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6675 {
6676  struct intel_encoder *encoder;
6677  struct intel_connector *connector;
6678 
6679  list_for_each_entry(connector, &dev->mode_config.connector_list,
6680  base.head) {
6681  connector->new_encoder =
6682  to_intel_encoder(connector->base.encoder);
6683  }
6684 
6685  list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6686  base.head) {
6687  encoder->new_crtc =
6688  to_intel_crtc(encoder->base.crtc);
6689  }
6690 }
6691 
6697 static void intel_modeset_commit_output_state(struct drm_device *dev)
6698 {
6699  struct intel_encoder *encoder;
6700  struct intel_connector *connector;
6701 
6702  list_for_each_entry(connector, &dev->mode_config.connector_list,
6703  base.head) {
6704  connector->base.encoder = &connector->new_encoder->base;
6705  }
6706 
6707  list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6708  base.head) {
6709  encoder->base.crtc = &encoder->new_crtc->base;
6710  }
6711 }
6712 
6713 static struct drm_display_mode *
6714 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6715  struct drm_display_mode *mode)
6716 {
6717  struct drm_device *dev = crtc->dev;
6718  struct drm_display_mode *adjusted_mode;
6719  struct drm_encoder_helper_funcs *encoder_funcs;
6720  struct intel_encoder *encoder;
6721 
6722  adjusted_mode = drm_mode_duplicate(dev, mode);
6723  if (!adjusted_mode)
6724  return ERR_PTR(-ENOMEM);
6725 
6726  /* Pass our mode to the connectors and the CRTC to give them a chance to
6727  * adjust it according to limitations or connector properties, and also
6728  * a chance to reject the mode entirely.
6729  */
6730  list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6731  base.head) {
6732 
6733  if (&encoder->new_crtc->base != crtc)
6734  continue;
6735  encoder_funcs = encoder->base.helper_private;
6736  if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
6737  adjusted_mode))) {
6738  DRM_DEBUG_KMS("Encoder fixup failed\n");
6739  goto fail;
6740  }
6741  }
6742 
6743  if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6744  DRM_DEBUG_KMS("CRTC fixup failed\n");
6745  goto fail;
6746  }
6747  DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6748 
6749  return adjusted_mode;
6750 fail:
6751  drm_mode_destroy(dev, adjusted_mode);
6752  return ERR_PTR(-EINVAL);
6753 }
6754 
6755 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
6756  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
6757 static void
6758 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
6759  unsigned *prepare_pipes, unsigned *disable_pipes)
6760 {
6761  struct intel_crtc *intel_crtc;
6762  struct drm_device *dev = crtc->dev;
6763  struct intel_encoder *encoder;
6764  struct intel_connector *connector;
6765  struct drm_crtc *tmp_crtc;
6766 
6767  *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
6768 
6769  /* Check which crtcs have changed outputs connected to them, these need
6770  * to be part of the prepare_pipes mask. We don't (yet) support global
6771  * modeset across multiple crtcs, so modeset_pipes will only have one
6772  * bit set at most. */
6773  list_for_each_entry(connector, &dev->mode_config.connector_list,
6774  base.head) {
6775  if (connector->base.encoder == &connector->new_encoder->base)
6776  continue;
6777 
6778  if (connector->base.encoder) {
6779  tmp_crtc = connector->base.encoder->crtc;
6780 
6781  *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6782  }
6783 
6784  if (connector->new_encoder)
6785  *prepare_pipes |=
6786  1 << connector->new_encoder->new_crtc->pipe;
6787  }
6788 
6789  list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6790  base.head) {
6791  if (encoder->base.crtc == &encoder->new_crtc->base)
6792  continue;
6793 
6794  if (encoder->base.crtc) {
6795  tmp_crtc = encoder->base.crtc;
6796 
6797  *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6798  }
6799 
6800  if (encoder->new_crtc)
6801  *prepare_pipes |= 1 << encoder->new_crtc->pipe;
6802  }
6803 
6804  /* Check for any pipes that will be fully disabled ... */
6805  list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6806  base.head) {
6807  bool used = false;
6808 
6809  /* Don't try to disable disabled crtcs. */
6810  if (!intel_crtc->base.enabled)
6811  continue;
6812 
6813  list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6814  base.head) {
6815  if (encoder->new_crtc == intel_crtc)
6816  used = true;
6817  }
6818 
6819  if (!used)
6820  *disable_pipes |= 1 << intel_crtc->pipe;
6821  }
6822 
6823 
6824  /* set_mode is also used to update properties on life display pipes. */
6825  intel_crtc = to_intel_crtc(crtc);
6826  if (crtc->enabled)
6827  *prepare_pipes |= 1 << intel_crtc->pipe;
6828 
6829  /* We only support modeset on one single crtc, hence we need to do that
6830  * only for the passed in crtc iff we change anything else than just
6831  * disable crtcs.
6832  *
6833  * This is actually not true, to be fully compatible with the old crtc
6834  * helper we automatically disable _any_ output (i.e. doesn't need to be
6835  * connected to the crtc we're modesetting on) if it's disconnected.
6836  * Which is a rather nutty api (since changed the output configuration
6837  * without userspace's explicit request can lead to confusion), but
6838  * alas. Hence we currently need to modeset on all pipes we prepare. */
6839  if (*prepare_pipes)
6840  *modeset_pipes = *prepare_pipes;
6841 
6842  /* ... and mask these out. */
6843  *modeset_pipes &= ~(*disable_pipes);
6844  *prepare_pipes &= ~(*disable_pipes);
6845 }
6846 
6847 static bool intel_crtc_in_use(struct drm_crtc *crtc)
6848 {
6849  struct drm_encoder *encoder;
6850  struct drm_device *dev = crtc->dev;
6851 
6852  list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
6853  if (encoder->crtc == crtc)
6854  return true;
6855 
6856  return false;
6857 }
6858 
6859 static void
6860 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
6861 {
6862  struct intel_encoder *intel_encoder;
6863  struct intel_crtc *intel_crtc;
6864  struct drm_connector *connector;
6865 
6866  list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
6867  base.head) {
6868  if (!intel_encoder->base.crtc)
6869  continue;
6870 
6871  intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
6872 
6873  if (prepare_pipes & (1 << intel_crtc->pipe))
6874  intel_encoder->connectors_active = false;
6875  }
6876 
6877  intel_modeset_commit_output_state(dev);
6878 
6879  /* Update computed state. */
6880  list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6881  base.head) {
6882  intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
6883  }
6884 
6885  list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6886  if (!connector->encoder || !connector->encoder->crtc)
6887  continue;
6888 
6889  intel_crtc = to_intel_crtc(connector->encoder->crtc);
6890 
6891  if (prepare_pipes & (1 << intel_crtc->pipe)) {
6892  struct drm_property *dpms_property =
6893  dev->mode_config.dpms_property;
6894 
6895  connector->dpms = DRM_MODE_DPMS_ON;
6897  dpms_property,
6899 
6900  intel_encoder = to_intel_encoder(connector->encoder);
6901  intel_encoder->connectors_active = true;
6902  }
6903  }
6904 
6905 }
6906 
6907 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
6908  list_for_each_entry((intel_crtc), \
6909  &(dev)->mode_config.crtc_list, \
6910  base.head) \
6911  if (mask & (1 <<(intel_crtc)->pipe)) \
6912 
6913 void
6915 {
6916  struct intel_crtc *crtc;
6917  struct intel_encoder *encoder;
6918  struct intel_connector *connector;
6919 
6920  list_for_each_entry(connector, &dev->mode_config.connector_list,
6921  base.head) {
6922  /* This also checks the encoder/connector hw state with the
6923  * ->get_hw_state callbacks. */
6924  intel_connector_check_state(connector);
6925 
6926  WARN(&connector->new_encoder->base != connector->base.encoder,
6927  "connector's staged encoder doesn't match current encoder\n");
6928  }
6929 
6930  list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6931  base.head) {
6932  bool enabled = false;
6933  bool active = false;
6934  enum pipe pipe, tracked_pipe;
6935 
6936  DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
6937  encoder->base.base.id,
6938  drm_get_encoder_name(&encoder->base));
6939 
6940  WARN(&encoder->new_crtc->base != encoder->base.crtc,
6941  "encoder's stage crtc doesn't match current crtc\n");
6942  WARN(encoder->connectors_active && !encoder->base.crtc,
6943  "encoder's active_connectors set, but no crtc\n");
6944 
6945  list_for_each_entry(connector, &dev->mode_config.connector_list,
6946  base.head) {
6947  if (connector->base.encoder != &encoder->base)
6948  continue;
6949  enabled = true;
6950  if (connector->base.dpms != DRM_MODE_DPMS_OFF)
6951  active = true;
6952  }
6953  WARN(!!encoder->base.crtc != enabled,
6954  "encoder's enabled state mismatch "
6955  "(expected %i, found %i)\n",
6956  !!encoder->base.crtc, enabled);
6957  WARN(active && !encoder->base.crtc,
6958  "active encoder with no crtc\n");
6959 
6960  WARN(encoder->connectors_active != active,
6961  "encoder's computed active state doesn't match tracked active state "
6962  "(expected %i, found %i)\n", active, encoder->connectors_active);
6963 
6964  active = encoder->get_hw_state(encoder, &pipe);
6965  WARN(active != encoder->connectors_active,
6966  "encoder's hw state doesn't match sw tracking "
6967  "(expected %i, found %i)\n",
6968  encoder->connectors_active, active);
6969 
6970  if (!encoder->base.crtc)
6971  continue;
6972 
6973  tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
6974  WARN(active && pipe != tracked_pipe,
6975  "active encoder's pipe doesn't match"
6976  "(expected %i, found %i)\n",
6977  tracked_pipe, pipe);
6978 
6979  }
6980 
6981  list_for_each_entry(crtc, &dev->mode_config.crtc_list,
6982  base.head) {
6983  bool enabled = false;
6984  bool active = false;
6985 
6986  DRM_DEBUG_KMS("[CRTC:%d]\n",
6987  crtc->base.base.id);
6988 
6989  WARN(crtc->active && !crtc->base.enabled,
6990  "active crtc, but not enabled in sw tracking\n");
6991 
6992  list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6993  base.head) {
6994  if (encoder->base.crtc != &crtc->base)
6995  continue;
6996  enabled = true;
6997  if (encoder->connectors_active)
6998  active = true;
6999  }
7000  WARN(active != crtc->active,
7001  "crtc's computed active state doesn't match tracked active state "
7002  "(expected %i, found %i)\n", active, crtc->active);
7003  WARN(enabled != crtc->base.enabled,
7004  "crtc's computed enabled state doesn't match tracked enabled state "
7005  "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7006 
7007  assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7008  }
7009 }
7010 
7011 bool intel_set_mode(struct drm_crtc *crtc,
7012  struct drm_display_mode *mode,
7013  int x, int y, struct drm_framebuffer *fb)
7014 {
7015  struct drm_device *dev = crtc->dev;
7016  drm_i915_private_t *dev_priv = dev->dev_private;
7017  struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7018  struct drm_encoder_helper_funcs *encoder_funcs;
7019  struct drm_encoder *encoder;
7020  struct intel_crtc *intel_crtc;
7021  unsigned disable_pipes, prepare_pipes, modeset_pipes;
7022  bool ret = true;
7023 
7024  intel_modeset_affected_pipes(crtc, &modeset_pipes,
7025  &prepare_pipes, &disable_pipes);
7026 
7027  DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7028  modeset_pipes, prepare_pipes, disable_pipes);
7029 
7030  for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7031  intel_crtc_disable(&intel_crtc->base);
7032 
7033  saved_hwmode = crtc->hwmode;
7034  saved_mode = crtc->mode;
7035 
7036  /* Hack: Because we don't (yet) support global modeset on multiple
7037  * crtcs, we don't keep track of the new mode for more than one crtc.
7038  * Hence simply check whether any bit is set in modeset_pipes in all the
7039  * pieces of code that are not yet converted to deal with mutliple crtcs
7040  * changing their mode at the same time. */
7041  adjusted_mode = NULL;
7042  if (modeset_pipes) {
7043  adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7044  if (IS_ERR(adjusted_mode)) {
7045  return false;
7046  }
7047  }
7048 
7049  for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7050  if (intel_crtc->base.enabled)
7051  dev_priv->display.crtc_disable(&intel_crtc->base);
7052  }
7053 
7054  /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7055  * to set it here already despite that we pass it down the callchain.
7056  */
7057  if (modeset_pipes)
7058  crtc->mode = *mode;
7059 
7060  /* Only after disabling all output pipelines that will be changed can we
7061  * update the the output configuration. */
7062  intel_modeset_update_state(dev, prepare_pipes);
7063 
7064  /* Set up the DPLL and any encoders state that needs to adjust or depend
7065  * on the DPLL.
7066  */
7067  for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7068  ret = !intel_crtc_mode_set(&intel_crtc->base,
7069  mode, adjusted_mode,
7070  x, y, fb);
7071  if (!ret)
7072  goto done;
7073 
7074  list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7075 
7076  if (encoder->crtc != &intel_crtc->base)
7077  continue;
7078 
7079  DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7080  encoder->base.id, drm_get_encoder_name(encoder),
7081  mode->base.id, mode->name);
7082  encoder_funcs = encoder->helper_private;
7083  encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7084  }
7085  }
7086 
7087  /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7088  for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7089  dev_priv->display.crtc_enable(&intel_crtc->base);
7090 
7091  if (modeset_pipes) {
7092  /* Store real post-adjustment hardware mode. */
7093  crtc->hwmode = *adjusted_mode;
7094 
7095  /* Calculate and store various constants which
7096  * are later needed by vblank and swap-completion
7097  * timestamping. They are derived from true hwmode.
7098  */
7100  }
7101 
7102  /* FIXME: add subpixel order */
7103 done:
7104  drm_mode_destroy(dev, adjusted_mode);
7105  if (!ret && crtc->enabled) {
7106  crtc->hwmode = saved_hwmode;
7107  crtc->mode = saved_mode;
7108  } else {
7110  }
7111 
7112  return ret;
7113 }
7114 
7115 #undef for_each_intel_crtc_masked
7116 
7117 static void intel_set_config_free(struct intel_set_config *config)
7118 {
7119  if (!config)
7120  return;
7121 
7122  kfree(config->save_connector_encoders);
7123  kfree(config->save_encoder_crtcs);
7124  kfree(config);
7125 }
7126 
7127 static int intel_set_config_save_state(struct drm_device *dev,
7128  struct intel_set_config *config)
7129 {
7130  struct drm_encoder *encoder;
7131  struct drm_connector *connector;
7132  int count;
7133 
7134  config->save_encoder_crtcs =
7135  kcalloc(dev->mode_config.num_encoder,
7136  sizeof(struct drm_crtc *), GFP_KERNEL);
7137  if (!config->save_encoder_crtcs)
7138  return -ENOMEM;
7139 
7140  config->save_connector_encoders =
7141  kcalloc(dev->mode_config.num_connector,
7142  sizeof(struct drm_encoder *), GFP_KERNEL);
7143  if (!config->save_connector_encoders)
7144  return -ENOMEM;
7145 
7146  /* Copy data. Note that driver private data is not affected.
7147  * Should anything bad happen only the expected state is
7148  * restored, not the drivers personal bookkeeping.
7149  */
7150  count = 0;
7151  list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7152  config->save_encoder_crtcs[count++] = encoder->crtc;
7153  }
7154 
7155  count = 0;
7156  list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7157  config->save_connector_encoders[count++] = connector->encoder;
7158  }
7159 
7160  return 0;
7161 }
7162 
7163 static void intel_set_config_restore_state(struct drm_device *dev,
7164  struct intel_set_config *config)
7165 {
7166  struct intel_encoder *encoder;
7167  struct intel_connector *connector;
7168  int count;
7169 
7170  count = 0;
7171  list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7172  encoder->new_crtc =
7173  to_intel_crtc(config->save_encoder_crtcs[count++]);
7174  }
7175 
7176  count = 0;
7177  list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7178  connector->new_encoder =
7179  to_intel_encoder(config->save_connector_encoders[count++]);
7180  }
7181 }
7182 
7183 static void
7184 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7185  struct intel_set_config *config)
7186 {
7187 
7188  /* We should be able to check here if the fb has the same properties
7189  * and then just flip_or_move it */
7190  if (set->crtc->fb != set->fb) {
7191  /* If we have no fb then treat it as a full mode set */
7192  if (set->crtc->fb == NULL) {
7193  DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7194  config->mode_changed = true;
7195  } else if (set->fb == NULL) {
7196  config->mode_changed = true;
7197  } else if (set->fb->depth != set->crtc->fb->depth) {
7198  config->mode_changed = true;
7199  } else if (set->fb->bits_per_pixel !=
7200  set->crtc->fb->bits_per_pixel) {
7201  config->mode_changed = true;
7202  } else
7203  config->fb_changed = true;
7204  }
7205 
7206  if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7207  config->fb_changed = true;
7208 
7209  if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7210  DRM_DEBUG_KMS("modes are different, full mode set\n");
7211  drm_mode_debug_printmodeline(&set->crtc->mode);
7213  config->mode_changed = true;
7214  }
7215 }
7216 
7217 static int
7218 intel_modeset_stage_output_state(struct drm_device *dev,
7219  struct drm_mode_set *set,
7220  struct intel_set_config *config)
7221 {
7222  struct drm_crtc *new_crtc;
7223  struct intel_connector *connector;
7224  struct intel_encoder *encoder;
7225  int count, ro;
7226 
7227  /* The upper layers ensure that we either disabl a crtc or have a list
7228  * of connectors. For paranoia, double-check this. */
7229  WARN_ON(!set->fb && (set->num_connectors != 0));
7230  WARN_ON(set->fb && (set->num_connectors == 0));
7231 
7232  count = 0;
7233  list_for_each_entry(connector, &dev->mode_config.connector_list,
7234  base.head) {
7235  /* Otherwise traverse passed in connector list and get encoders
7236  * for them. */
7237  for (ro = 0; ro < set->num_connectors; ro++) {
7238  if (set->connectors[ro] == &connector->base) {
7239  connector->new_encoder = connector->encoder;
7240  break;
7241  }
7242  }
7243 
7244  /* If we disable the crtc, disable all its connectors. Also, if
7245  * the connector is on the changing crtc but not on the new
7246  * connector list, disable it. */
7247  if ((!set->fb || ro == set->num_connectors) &&
7248  connector->base.encoder &&
7249  connector->base.encoder->crtc == set->crtc) {
7250  connector->new_encoder = NULL;
7251 
7252  DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7253  connector->base.base.id,
7254  drm_get_connector_name(&connector->base));
7255  }
7256 
7257 
7258  if (&connector->new_encoder->base != connector->base.encoder) {
7259  DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7260  config->mode_changed = true;
7261  }
7262 
7263  /* Disable all disconnected encoders. */
7264  if (connector->base.status == connector_status_disconnected)
7265  connector->new_encoder = NULL;
7266  }
7267  /* connector->new_encoder is now updated for all connectors. */
7268 
7269  /* Update crtc of enabled connectors. */
7270  count = 0;
7271  list_for_each_entry(connector, &dev->mode_config.connector_list,
7272  base.head) {
7273  if (!connector->new_encoder)
7274  continue;
7275 
7276  new_crtc = connector->new_encoder->base.crtc;
7277 
7278  for (ro = 0; ro < set->num_connectors; ro++) {
7279  if (set->connectors[ro] == &connector->base)
7280  new_crtc = set->crtc;
7281  }
7282 
7283  /* Make sure the new CRTC will work with the encoder */
7284  if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7285  new_crtc)) {
7286  return -EINVAL;
7287  }
7288  connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7289 
7290  DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7291  connector->base.base.id,
7292  drm_get_connector_name(&connector->base),
7293  new_crtc->base.id);
7294  }
7295 
7296  /* Check for any encoders that needs to be disabled. */
7297  list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7298  base.head) {
7299  list_for_each_entry(connector,
7300  &dev->mode_config.connector_list,
7301  base.head) {
7302  if (connector->new_encoder == encoder) {
7303  WARN_ON(!connector->new_encoder->new_crtc);
7304 
7305  goto next_encoder;
7306  }
7307  }
7308  encoder->new_crtc = NULL;
7309 next_encoder:
7310  /* Only now check for crtc changes so we don't miss encoders
7311  * that will be disabled. */
7312  if (&encoder->new_crtc->base != encoder->base.crtc) {
7313  DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7314  config->mode_changed = true;
7315  }
7316  }
7317  /* Now we've also updated encoder->new_crtc for all encoders. */
7318 
7319  return 0;
7320 }
7321 
7322 static int intel_crtc_set_config(struct drm_mode_set *set)
7323 {
7324  struct drm_device *dev;
7325  struct drm_mode_set save_set;
7326  struct intel_set_config *config;
7327  int ret;
7328 
7329  BUG_ON(!set);
7330  BUG_ON(!set->crtc);
7331  BUG_ON(!set->crtc->helper_private);
7332 
7333  if (!set->mode)
7334  set->fb = NULL;
7335 
7336  /* The fb helper likes to play gross jokes with ->mode_set_config.
7337  * Unfortunately the crtc helper doesn't do much at all for this case,
7338  * so we have to cope with this madness until the fb helper is fixed up. */
7339  if (set->fb && set->num_connectors == 0)
7340  return 0;
7341 
7342  if (set->fb) {
7343  DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7344  set->crtc->base.id, set->fb->base.id,
7345  (int)set->num_connectors, set->x, set->y);
7346  } else {
7347  DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7348  }
7349 
7350  dev = set->crtc->dev;
7351 
7352  ret = -ENOMEM;
7353  config = kzalloc(sizeof(*config), GFP_KERNEL);
7354  if (!config)
7355  goto out_config;
7356 
7357  ret = intel_set_config_save_state(dev, config);
7358  if (ret)
7359  goto out_config;
7360 
7361  save_set.crtc = set->crtc;
7362  save_set.mode = &set->crtc->mode;
7363  save_set.x = set->crtc->x;
7364  save_set.y = set->crtc->y;
7365  save_set.fb = set->crtc->fb;
7366 
7367  /* Compute whether we need a full modeset, only an fb base update or no
7368  * change at all. In the future we might also check whether only the
7369  * mode changed, e.g. for LVDS where we only change the panel fitter in
7370  * such cases. */
7371  intel_set_config_compute_mode_changes(set, config);
7372 
7373  ret = intel_modeset_stage_output_state(dev, set, config);
7374  if (ret)
7375  goto fail;
7376 
7377  if (config->mode_changed) {
7378  if (set->mode) {
7379  DRM_DEBUG_KMS("attempting to set mode from"
7380  " userspace\n");
7382  }
7383 
7384  if (!intel_set_mode(set->crtc, set->mode,
7385  set->x, set->y, set->fb)) {
7386  DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7387  set->crtc->base.id);
7388  ret = -EINVAL;
7389  goto fail;
7390  }
7391  } else if (config->fb_changed) {
7392  ret = intel_pipe_set_base(set->crtc,
7393  set->x, set->y, set->fb);
7394  }
7395 
7396  intel_set_config_free(config);
7397 
7398  return 0;
7399 
7400 fail:
7401  intel_set_config_restore_state(dev, config);
7402 
7403  /* Try to restore the config */
7404  if (config->mode_changed &&
7405  !intel_set_mode(save_set.crtc, save_set.mode,
7406  save_set.x, save_set.y, save_set.fb))
7407  DRM_ERROR("failed to restore config after modeset failure\n");
7408 
7409 out_config:
7410  intel_set_config_free(config);
7411  return ret;
7412 }
7413 
7414 static const struct drm_crtc_funcs intel_crtc_funcs = {
7415  .cursor_set = intel_crtc_cursor_set,
7416  .cursor_move = intel_crtc_cursor_move,
7417  .gamma_set = intel_crtc_gamma_set,
7418  .set_config = intel_crtc_set_config,
7419  .destroy = intel_crtc_destroy,
7420  .page_flip = intel_crtc_page_flip,
7421 };
7422 
7423 static void intel_pch_pll_init(struct drm_device *dev)
7424 {
7425  drm_i915_private_t *dev_priv = dev->dev_private;
7426  int i;
7427 
7428  if (dev_priv->num_pch_pll == 0) {
7429  DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7430  return;
7431  }
7432 
7433  for (i = 0; i < dev_priv->num_pch_pll; i++) {
7434  dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7435  dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7436  dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7437  }
7438 }
7439 
7440 static void intel_crtc_init(struct drm_device *dev, int pipe)
7441 {
7442  drm_i915_private_t *dev_priv = dev->dev_private;
7443  struct intel_crtc *intel_crtc;
7444  int i;
7445 
7446  intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7447  if (intel_crtc == NULL)
7448  return;
7449 
7450  drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7451 
7452  drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7453  for (i = 0; i < 256; i++) {
7454  intel_crtc->lut_r[i] = i;
7455  intel_crtc->lut_g[i] = i;
7456  intel_crtc->lut_b[i] = i;
7457  }
7458 
7459  /* Swap pipes & planes for FBC on pre-965 */
7460  intel_crtc->pipe = pipe;
7461  intel_crtc->plane = pipe;
7462  if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7463  DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7464  intel_crtc->plane = !pipe;
7465  }
7466 
7467  BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7468  dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7469  dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7470  dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7471 
7472  intel_crtc->bpp = 24; /* default for pre-Ironlake */
7473 
7474  drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7475 }
7476 
7478  struct drm_file *file)
7479 {
7480  struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7481  struct drm_mode_object *drmmode_obj;
7482  struct intel_crtc *crtc;
7483 
7484  if (!drm_core_check_feature(dev, DRIVER_MODESET))
7485  return -ENODEV;
7486 
7487  drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7489 
7490  if (!drmmode_obj) {
7491  DRM_ERROR("no such CRTC id\n");
7492  return -EINVAL;
7493  }
7494 
7495  crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7496  pipe_from_crtc_id->pipe = crtc->pipe;
7497 
7498  return 0;
7499 }
7500 
7501 static int intel_encoder_clones(struct intel_encoder *encoder)
7502 {
7503  struct drm_device *dev = encoder->base.dev;
7504  struct intel_encoder *source_encoder;
7505  int index_mask = 0;
7506  int entry = 0;
7507 
7508  list_for_each_entry(source_encoder,
7509  &dev->mode_config.encoder_list, base.head) {
7510 
7511  if (encoder == source_encoder)
7512  index_mask |= (1 << entry);
7513 
7514  /* Intel hw has only one MUX where enocoders could be cloned. */
7515  if (encoder->cloneable && source_encoder->cloneable)
7516  index_mask |= (1 << entry);
7517 
7518  entry++;
7519  }
7520 
7521  return index_mask;
7522 }
7523 
7524 static bool has_edp_a(struct drm_device *dev)
7525 {
7526  struct drm_i915_private *dev_priv = dev->dev_private;
7527 
7528  if (!IS_MOBILE(dev))
7529  return false;
7530 
7531  if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7532  return false;
7533 
7534  if (IS_GEN5(dev) &&
7536  return false;
7537 
7538  return true;
7539 }
7540 
7541 static void intel_setup_outputs(struct drm_device *dev)
7542 {
7543  struct drm_i915_private *dev_priv = dev->dev_private;
7544  struct intel_encoder *encoder;
7545  bool dpd_is_edp = false;
7546  bool has_lvds;
7547 
7548  has_lvds = intel_lvds_init(dev);
7549  if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7550  /* disable the panel fitter on everything but LVDS */
7552  }
7553 
7554  if (HAS_PCH_SPLIT(dev)) {
7555  dpd_is_edp = intel_dpd_is_edp(dev);
7556 
7557  if (has_edp_a(dev))
7558  intel_dp_init(dev, DP_A, PORT_A);
7559 
7560  if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7561  intel_dp_init(dev, PCH_DP_D, PORT_D);
7562  }
7563 
7564  intel_crt_init(dev);
7565 
7566  if (IS_HASWELL(dev)) {
7567  int found;
7568 
7569  /* Haswell uses DDI functions to detect digital outputs */
7571  /* DDI A only supports eDP */
7572  if (found)
7573  intel_ddi_init(dev, PORT_A);
7574 
7575  /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7576  * register */
7577  found = I915_READ(SFUSE_STRAP);
7578 
7579  if (found & SFUSE_STRAP_DDIB_DETECTED)
7580  intel_ddi_init(dev, PORT_B);
7581  if (found & SFUSE_STRAP_DDIC_DETECTED)
7582  intel_ddi_init(dev, PORT_C);
7583  if (found & SFUSE_STRAP_DDID_DETECTED)
7584  intel_ddi_init(dev, PORT_D);
7585  } else if (HAS_PCH_SPLIT(dev)) {
7586  int found;
7587 
7588  if (I915_READ(HDMIB) & PORT_DETECTED) {
7589  /* PCH SDVOB multiplex with HDMIB */
7590  found = intel_sdvo_init(dev, PCH_SDVOB, true);
7591  if (!found)
7592  intel_hdmi_init(dev, HDMIB, PORT_B);
7593  if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7594  intel_dp_init(dev, PCH_DP_B, PORT_B);
7595  }
7596 
7597  if (I915_READ(HDMIC) & PORT_DETECTED)
7598  intel_hdmi_init(dev, HDMIC, PORT_C);
7599 
7600  if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7601  intel_hdmi_init(dev, HDMID, PORT_D);
7602 
7603  if (I915_READ(PCH_DP_C) & DP_DETECTED)
7604  intel_dp_init(dev, PCH_DP_C, PORT_C);
7605 
7606  if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7607  intel_dp_init(dev, PCH_DP_D, PORT_D);
7608  } else if (IS_VALLEYVIEW(dev)) {
7609  int found;
7610 
7611  if (I915_READ(SDVOB) & PORT_DETECTED) {
7612  /* SDVOB multiplex with HDMIB */
7613  found = intel_sdvo_init(dev, SDVOB, true);
7614  if (!found)
7615  intel_hdmi_init(dev, SDVOB, PORT_B);
7616  if (!found && (I915_READ(DP_B) & DP_DETECTED))
7617  intel_dp_init(dev, DP_B, PORT_B);
7618  }
7619 
7620  if (I915_READ(SDVOC) & PORT_DETECTED)
7621  intel_hdmi_init(dev, SDVOC, PORT_C);
7622 
7623  /* Shares lanes with HDMI on SDVOC */
7624  if (I915_READ(DP_C) & DP_DETECTED)
7625  intel_dp_init(dev, DP_C, PORT_C);
7626  } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7627  bool found = false;
7628 
7629  if (I915_READ(SDVOB) & SDVO_DETECTED) {
7630  DRM_DEBUG_KMS("probing SDVOB\n");
7631  found = intel_sdvo_init(dev, SDVOB, true);
7632  if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7633  DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7634  intel_hdmi_init(dev, SDVOB, PORT_B);
7635  }
7636 
7637  if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7638  DRM_DEBUG_KMS("probing DP_B\n");
7639  intel_dp_init(dev, DP_B, PORT_B);
7640  }
7641  }
7642 
7643  /* Before G4X SDVOC doesn't have its own detect register */
7644 
7645  if (I915_READ(SDVOB) & SDVO_DETECTED) {
7646  DRM_DEBUG_KMS("probing SDVOC\n");
7647  found = intel_sdvo_init(dev, SDVOC, false);
7648  }
7649 
7650  if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7651 
7652  if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7653  DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7654  intel_hdmi_init(dev, SDVOC, PORT_C);
7655  }
7656  if (SUPPORTS_INTEGRATED_DP(dev)) {
7657  DRM_DEBUG_KMS("probing DP_C\n");
7658  intel_dp_init(dev, DP_C, PORT_C);
7659  }
7660  }
7661 
7662  if (SUPPORTS_INTEGRATED_DP(dev) &&
7663  (I915_READ(DP_D) & DP_DETECTED)) {
7664  DRM_DEBUG_KMS("probing DP_D\n");
7665  intel_dp_init(dev, DP_D, PORT_D);
7666  }
7667  } else if (IS_GEN2(dev))
7668  intel_dvo_init(dev);
7669 
7670  if (SUPPORTS_TV(dev))
7671  intel_tv_init(dev);
7672 
7673  list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7674  encoder->base.possible_crtcs = encoder->crtc_mask;
7675  encoder->base.possible_clones =
7676  intel_encoder_clones(encoder);
7677  }
7678 
7679  if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7681 }
7682 
7683 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7684 {
7685  struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7686 
7688  drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7689 
7690  kfree(intel_fb);
7691 }
7692 
7693 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7694  struct drm_file *file,
7695  unsigned int *handle)
7696 {
7697  struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7698  struct drm_i915_gem_object *obj = intel_fb->obj;
7699 
7700  return drm_gem_handle_create(file, &obj->base, handle);
7701 }
7702 
7703 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7704  .destroy = intel_user_framebuffer_destroy,
7705  .create_handle = intel_user_framebuffer_create_handle,
7706 };
7707 
7709  struct intel_framebuffer *intel_fb,
7710  struct drm_mode_fb_cmd2 *mode_cmd,
7711  struct drm_i915_gem_object *obj)
7712 {
7713  int ret;
7714 
7715  if (obj->tiling_mode == I915_TILING_Y)
7716  return -EINVAL;
7717 
7718  if (mode_cmd->pitches[0] & 63)
7719  return -EINVAL;
7720 
7721  switch (mode_cmd->pixel_format) {
7722  case DRM_FORMAT_RGB332:
7723  case DRM_FORMAT_RGB565:
7724  case DRM_FORMAT_XRGB8888:
7725  case DRM_FORMAT_XBGR8888:
7726  case DRM_FORMAT_ARGB8888:
7729  /* RGB formats are common across chipsets */
7730  break;
7731  case DRM_FORMAT_YUYV:
7732  case DRM_FORMAT_UYVY:
7733  case DRM_FORMAT_YVYU:
7734  case DRM_FORMAT_VYUY:
7735  break;
7736  default:
7737  DRM_DEBUG_KMS("unsupported pixel format %u\n",
7738  mode_cmd->pixel_format);
7739  return -EINVAL;
7740  }
7741 
7742  ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7743  if (ret) {
7744  DRM_ERROR("framebuffer init failed %d\n", ret);
7745  return ret;
7746  }
7747 
7748  drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7749  intel_fb->obj = obj;
7750  return 0;
7751 }
7752 
7753 static struct drm_framebuffer *
7754 intel_user_framebuffer_create(struct drm_device *dev,
7755  struct drm_file *filp,
7756  struct drm_mode_fb_cmd2 *mode_cmd)
7757 {
7758  struct drm_i915_gem_object *obj;
7759 
7760  obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7761  mode_cmd->handles[0]));
7762  if (&obj->base == NULL)
7763  return ERR_PTR(-ENOENT);
7764 
7765  return intel_framebuffer_create(dev, mode_cmd, obj);
7766 }
7767 
7768 static const struct drm_mode_config_funcs intel_mode_funcs = {
7769  .fb_create = intel_user_framebuffer_create,
7770  .output_poll_changed = intel_fb_output_poll_changed,
7771 };
7772 
7773 /* Set up chip specific display functions */
7774 static void intel_init_display(struct drm_device *dev)
7775 {
7776  struct drm_i915_private *dev_priv = dev->dev_private;
7777 
7778  /* We always want a DPMS function */
7779  if (HAS_PCH_SPLIT(dev)) {
7780  dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7781  dev_priv->display.crtc_enable = ironlake_crtc_enable;
7782  dev_priv->display.crtc_disable = ironlake_crtc_disable;
7783  dev_priv->display.off = ironlake_crtc_off;
7784  dev_priv->display.update_plane = ironlake_update_plane;
7785  } else {
7786  dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7787  dev_priv->display.crtc_enable = i9xx_crtc_enable;
7788  dev_priv->display.crtc_disable = i9xx_crtc_disable;
7789  dev_priv->display.off = i9xx_crtc_off;
7790  dev_priv->display.update_plane = i9xx_update_plane;
7791  }
7792 
7793  /* Returns the core display clock speed */
7794  if (IS_VALLEYVIEW(dev))
7795  dev_priv->display.get_display_clock_speed =
7796  valleyview_get_display_clock_speed;
7797  else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7798  dev_priv->display.get_display_clock_speed =
7799  i945_get_display_clock_speed;
7800  else if (IS_I915G(dev))
7801  dev_priv->display.get_display_clock_speed =
7802  i915_get_display_clock_speed;
7803  else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7804  dev_priv->display.get_display_clock_speed =
7805  i9xx_misc_get_display_clock_speed;
7806  else if (IS_I915GM(dev))
7807  dev_priv->display.get_display_clock_speed =
7808  i915gm_get_display_clock_speed;
7809  else if (IS_I865G(dev))
7810  dev_priv->display.get_display_clock_speed =
7811  i865_get_display_clock_speed;
7812  else if (IS_I85X(dev))
7813  dev_priv->display.get_display_clock_speed =
7814  i855_get_display_clock_speed;
7815  else /* 852, 830 */
7816  dev_priv->display.get_display_clock_speed =
7817  i830_get_display_clock_speed;
7818 
7819  if (HAS_PCH_SPLIT(dev)) {
7820  if (IS_GEN5(dev)) {
7821  dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7822  dev_priv->display.write_eld = ironlake_write_eld;
7823  } else if (IS_GEN6(dev)) {
7824  dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7825  dev_priv->display.write_eld = ironlake_write_eld;
7826  } else if (IS_IVYBRIDGE(dev)) {
7827  /* FIXME: detect B0+ stepping and use auto training */
7828  dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7829  dev_priv->display.write_eld = ironlake_write_eld;
7830  } else if (IS_HASWELL(dev)) {
7831  dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7832  dev_priv->display.write_eld = haswell_write_eld;
7833  } else
7834  dev_priv->display.update_wm = NULL;
7835  } else if (IS_G4X(dev)) {
7836  dev_priv->display.write_eld = g4x_write_eld;
7837  }
7838 
7839  /* Default just returns -ENODEV to indicate unsupported */
7840  dev_priv->display.queue_flip = intel_default_queue_flip;
7841 
7842  switch (INTEL_INFO(dev)->gen) {
7843  case 2:
7844  dev_priv->display.queue_flip = intel_gen2_queue_flip;
7845  break;
7846 
7847  case 3:
7848  dev_priv->display.queue_flip = intel_gen3_queue_flip;
7849  break;
7850 
7851  case 4:
7852  case 5:
7853  dev_priv->display.queue_flip = intel_gen4_queue_flip;
7854  break;
7855 
7856  case 6:
7857  dev_priv->display.queue_flip = intel_gen6_queue_flip;
7858  break;
7859  case 7:
7860  dev_priv->display.queue_flip = intel_gen7_queue_flip;
7861  break;
7862  }
7863 }
7864 
7865 /*
7866  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7867  * resume, or other times. This quirk makes sure that's the case for
7868  * affected systems.
7869  */
7870 static void quirk_pipea_force(struct drm_device *dev)
7871 {
7872  struct drm_i915_private *dev_priv = dev->dev_private;
7873 
7874  dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7875  DRM_INFO("applying pipe a force quirk\n");
7876 }
7877 
7878 /*
7879  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7880  */
7881 static void quirk_ssc_force_disable(struct drm_device *dev)
7882 {
7883  struct drm_i915_private *dev_priv = dev->dev_private;
7884  dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7885  DRM_INFO("applying lvds SSC disable quirk\n");
7886 }
7887 
7888 /*
7889  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7890  * brightness value
7891  */
7892 static void quirk_invert_brightness(struct drm_device *dev)
7893 {
7894  struct drm_i915_private *dev_priv = dev->dev_private;
7895  dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7896  DRM_INFO("applying inverted panel brightness quirk\n");
7897 }
7898 
7899 struct intel_quirk {
7900  int device;
7903  void (*hook)(struct drm_device *dev);
7904 };
7905 
7906 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
7908  void (*hook)(struct drm_device *dev);
7909  const struct dmi_system_id (*dmi_id_list)[];
7910 };
7911 
7912 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
7913 {
7914  DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
7915  return 1;
7916 }
7917 
7918 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
7919  {
7920  .dmi_id_list = &(const struct dmi_system_id[]) {
7921  {
7922  .callback = intel_dmi_reverse_brightness,
7923  .ident = "NCR Corporation",
7924  .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
7926  },
7927  },
7928  { } /* terminating entry */
7929  },
7930  .hook = quirk_invert_brightness,
7931  },
7932 };
7933 
7934 static struct intel_quirk intel_quirks[] = {
7935  /* HP Mini needs pipe A force quirk (LP: #322104) */
7936  { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7937 
7938  /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7939  { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7940 
7941  /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7942  { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7943 
7944  /* 830/845 need to leave pipe A & dpll A up */
7945  { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7946  { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7947 
7948  /* Lenovo U160 cannot use SSC on LVDS */
7949  { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7950 
7951  /* Sony Vaio Y cannot use SSC on LVDS */
7952  { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7953 
7954  /* Acer Aspire 5734Z must invert backlight brightness */
7955  { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7956 };
7957 
7958 static void intel_init_quirks(struct drm_device *dev)
7959 {
7960  struct pci_dev *d = dev->pdev;
7961  int i;
7962 
7963  for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7964  struct intel_quirk *q = &intel_quirks[i];
7965 
7966  if (d->device == q->device &&
7967  (d->subsystem_vendor == q->subsystem_vendor ||
7968  q->subsystem_vendor == PCI_ANY_ID) &&
7969  (d->subsystem_device == q->subsystem_device ||
7971  q->hook(dev);
7972  }
7973  for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
7974  if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
7975  intel_dmi_quirks[i].hook(dev);
7976  }
7977 }
7978 
7979 /* Disable the VGA plane that we never use */
7980 static void i915_disable_vga(struct drm_device *dev)
7981 {
7982  struct drm_i915_private *dev_priv = dev->dev_private;
7983  u8 sr1;
7984  u32 vga_reg;
7985 
7986  if (HAS_PCH_SPLIT(dev))
7987  vga_reg = CPU_VGACNTRL;
7988  else
7989  vga_reg = VGACNTRL;
7990 
7991  vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7993  sr1 = inb(VGA_SR_DATA);
7994  outb(sr1 | 1<<5, VGA_SR_DATA);
7995  vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7996  udelay(300);
7997 
7998  I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7999  POSTING_READ(vga_reg);
8000 }
8001 
8003 {
8004  /* We attempt to init the necessary power wells early in the initialization
8005  * time, so the subsystems that expect power to be enabled can work.
8006  */
8008 
8009  intel_prepare_ddi(dev);
8010 
8012 
8013  mutex_lock(&dev->struct_mutex);
8015  mutex_unlock(&dev->struct_mutex);
8016 }
8017 
8019 {
8020  struct drm_i915_private *dev_priv = dev->dev_private;
8021  int i, ret;
8022 
8023  drm_mode_config_init(dev);
8024 
8025  dev->mode_config.min_width = 0;
8026  dev->mode_config.min_height = 0;
8027 
8028  dev->mode_config.preferred_depth = 24;
8029  dev->mode_config.prefer_shadow = 1;
8030 
8031  dev->mode_config.funcs = &intel_mode_funcs;
8032 
8033  intel_init_quirks(dev);
8034 
8035  intel_init_pm(dev);
8036 
8037  intel_init_display(dev);
8038 
8039  if (IS_GEN2(dev)) {
8040  dev->mode_config.max_width = 2048;
8041  dev->mode_config.max_height = 2048;
8042  } else if (IS_GEN3(dev)) {
8043  dev->mode_config.max_width = 4096;
8044  dev->mode_config.max_height = 4096;
8045  } else {
8046  dev->mode_config.max_width = 8192;
8047  dev->mode_config.max_height = 8192;
8048  }
8049  dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8050 
8051  DRM_DEBUG_KMS("%d display pipe%s available.\n",
8052  dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8053 
8054  for (i = 0; i < dev_priv->num_pipe; i++) {
8055  intel_crtc_init(dev, i);
8056  ret = intel_plane_init(dev, i);
8057  if (ret)
8058  DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8059  }
8060 
8061  intel_pch_pll_init(dev);
8062 
8063  /* Just disable it once at startup */
8064  i915_disable_vga(dev);
8065  intel_setup_outputs(dev);
8066 }
8067 
8068 static void
8069 intel_connector_break_all_links(struct intel_connector *connector)
8070 {
8071  connector->base.dpms = DRM_MODE_DPMS_OFF;
8072  connector->base.encoder = NULL;
8073  connector->encoder->connectors_active = false;
8074  connector->encoder->base.crtc = NULL;
8075 }
8076 
8077 static void intel_enable_pipe_a(struct drm_device *dev)
8078 {
8079  struct intel_connector *connector;
8080  struct drm_connector *crt = NULL;
8082 
8083  /* We can't just switch on the pipe A, we need to set things up with a
8084  * proper mode and output configuration. As a gross hack, enable pipe A
8085  * by enabling the load detect pipe once. */
8086  list_for_each_entry(connector,
8087  &dev->mode_config.connector_list,
8088  base.head) {
8089  if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8090  crt = &connector->base;
8091  break;
8092  }
8093  }
8094 
8095  if (!crt)
8096  return;
8097 
8100 
8101 
8102 }
8103 
8104 static bool
8105 intel_check_plane_mapping(struct intel_crtc *crtc)
8106 {
8107  struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8108  u32 reg, val;
8109 
8110  if (dev_priv->num_pipe == 1)
8111  return true;
8112 
8113  reg = DSPCNTR(!crtc->plane);
8114  val = I915_READ(reg);
8115 
8116  if ((val & DISPLAY_PLANE_ENABLE) &&
8117  (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8118  return false;
8119 
8120  return true;
8121 }
8122 
8123 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8124 {
8125  struct drm_device *dev = crtc->base.dev;
8126  struct drm_i915_private *dev_priv = dev->dev_private;
8127  u32 reg;
8128 
8129  /* Clear any frame start delays used for debugging left by the BIOS */
8130  reg = PIPECONF(crtc->pipe);
8132 
8133  /* We need to sanitize the plane -> pipe mapping first because this will
8134  * disable the crtc (and hence change the state) if it is wrong. Note
8135  * that gen4+ has a fixed plane -> pipe mapping. */
8136  if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8137  struct intel_connector *connector;
8138  bool plane;
8139 
8140  DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8141  crtc->base.base.id);
8142 
8143  /* Pipe has the wrong plane attached and the plane is active.
8144  * Temporarily change the plane mapping and disable everything
8145  * ... */
8146  plane = crtc->plane;
8147  crtc->plane = !plane;
8148  dev_priv->display.crtc_disable(&crtc->base);
8149  crtc->plane = plane;
8150 
8151  /* ... and break all links. */
8152  list_for_each_entry(connector, &dev->mode_config.connector_list,
8153  base.head) {
8154  if (connector->encoder->base.crtc != &crtc->base)
8155  continue;
8156 
8157  intel_connector_break_all_links(connector);
8158  }
8159 
8160  WARN_ON(crtc->active);
8161  crtc->base.enabled = false;
8162  }
8163 
8164  if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8165  crtc->pipe == PIPE_A && !crtc->active) {
8166  /* BIOS forgot to enable pipe A, this mostly happens after
8167  * resume. Force-enable the pipe to fix this, the update_dpms
8168  * call below we restore the pipe to the right state, but leave
8169  * the required bits on. */
8170  intel_enable_pipe_a(dev);
8171  }
8172 
8173  /* Adjust the state of the output pipe according to whether we
8174  * have active connectors/encoders. */
8175  intel_crtc_update_dpms(&crtc->base);
8176 
8177  if (crtc->active != crtc->base.enabled) {
8178  struct intel_encoder *encoder;
8179 
8180  /* This can happen either due to bugs in the get_hw_state
8181  * functions or because the pipe is force-enabled due to the
8182  * pipe A quirk. */
8183  DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8184  crtc->base.base.id,
8185  crtc->base.enabled ? "enabled" : "disabled",
8186  crtc->active ? "enabled" : "disabled");
8187 
8188  crtc->base.enabled = crtc->active;
8189 
8190  /* Because we only establish the connector -> encoder ->
8191  * crtc links if something is active, this means the
8192  * crtc is now deactivated. Break the links. connector
8193  * -> encoder links are only establish when things are
8194  * actually up, hence no need to break them. */
8195  WARN_ON(crtc->active);
8196 
8197  for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8198  WARN_ON(encoder->connectors_active);
8199  encoder->base.crtc = NULL;
8200  }
8201  }
8202 }
8203 
8204 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8205 {
8206  struct intel_connector *connector;
8207  struct drm_device *dev = encoder->base.dev;
8208 
8209  /* We need to check both for a crtc link (meaning that the
8210  * encoder is active and trying to read from a pipe) and the
8211  * pipe itself being active. */
8212  bool has_active_crtc = encoder->base.crtc &&
8213  to_intel_crtc(encoder->base.crtc)->active;
8214 
8215  if (encoder->connectors_active && !has_active_crtc) {
8216  DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8217  encoder->base.base.id,
8218  drm_get_encoder_name(&encoder->base));
8219 
8220  /* Connector is active, but has no active pipe. This is
8221  * fallout from our resume register restoring. Disable
8222  * the encoder manually again. */
8223  if (encoder->base.crtc) {
8224  DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8225  encoder->base.base.id,
8226  drm_get_encoder_name(&encoder->base));
8227  encoder->disable(encoder);
8228  }
8229 
8230  /* Inconsistent output/port/pipe state happens presumably due to
8231  * a bug in one of the get_hw_state functions. Or someplace else
8232  * in our code, like the register restore mess on resume. Clamp
8233  * things to off as a safer default. */
8234  list_for_each_entry(connector,
8235  &dev->mode_config.connector_list,
8236  base.head) {
8237  if (connector->encoder != encoder)
8238  continue;
8239 
8240  intel_connector_break_all_links(connector);
8241  }
8242  }
8243  /* Enabled encoders without active connectors will be fixed in
8244  * the crtc fixup. */
8245 }
8246 
8247 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8248  * and i915 state tracking structures. */
8250 {
8251  struct drm_i915_private *dev_priv = dev->dev_private;
8252  enum pipe pipe;
8253  u32 tmp;
8254  struct intel_crtc *crtc;
8255  struct intel_encoder *encoder;
8256  struct intel_connector *connector;
8257 
8258  for_each_pipe(pipe) {
8259  crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8260 
8261  tmp = I915_READ(PIPECONF(pipe));
8262  if (tmp & PIPECONF_ENABLE)
8263  crtc->active = true;
8264  else
8265  crtc->active = false;
8266 
8267  crtc->base.enabled = crtc->active;
8268 
8269  DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8270  crtc->base.base.id,
8271  crtc->active ? "enabled" : "disabled");
8272  }
8273 
8274  list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8275  base.head) {
8276  pipe = 0;
8277 
8278  if (encoder->get_hw_state(encoder, &pipe)) {
8279  encoder->base.crtc =
8280  dev_priv->pipe_to_crtc_mapping[pipe];
8281  } else {
8282  encoder->base.crtc = NULL;
8283  }
8284 
8285  encoder->connectors_active = false;
8286  DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8287  encoder->base.base.id,
8288  drm_get_encoder_name(&encoder->base),
8289  encoder->base.crtc ? "enabled" : "disabled",
8290  pipe);
8291  }
8292 
8293  list_for_each_entry(connector, &dev->mode_config.connector_list,
8294  base.head) {
8295  if (connector->get_hw_state(connector)) {
8296  connector->base.dpms = DRM_MODE_DPMS_ON;
8297  connector->encoder->connectors_active = true;
8298  connector->base.encoder = &connector->encoder->base;
8299  } else {
8300  connector->base.dpms = DRM_MODE_DPMS_OFF;
8301  connector->base.encoder = NULL;
8302  }
8303  DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8304  connector->base.base.id,
8305  drm_get_connector_name(&connector->base),
8306  connector->base.encoder ? "enabled" : "disabled");
8307  }
8308 
8309  /* HW state is read out, now we need to sanitize this mess. */
8310  list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8311  base.head) {
8312  intel_sanitize_encoder(encoder);
8313  }
8314 
8315  for_each_pipe(pipe) {
8316  crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8317  intel_sanitize_crtc(crtc);
8318  }
8319 
8320  intel_modeset_update_staged_output_state(dev);
8321 
8323 }
8324 
8326 {
8327  intel_modeset_init_hw(dev);
8328 
8329  intel_setup_overlay(dev);
8330 
8332 }
8333 
8335 {
8336  struct drm_i915_private *dev_priv = dev->dev_private;
8337  struct drm_crtc *crtc;
8338  struct intel_crtc *intel_crtc;
8339 
8341  mutex_lock(&dev->struct_mutex);
8342 
8344 
8345 
8346  list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8347  /* Skip inactive CRTCs */
8348  if (!crtc->fb)
8349  continue;
8350 
8351  intel_crtc = to_intel_crtc(crtc);
8352  intel_increase_pllclock(crtc);
8353  }
8354 
8355  intel_disable_fbc(dev);
8356 
8358 
8359  ironlake_teardown_rc6(dev);
8360 
8361  if (IS_VALLEYVIEW(dev))
8362  vlv_init_dpio(dev);
8363 
8364  mutex_unlock(&dev->struct_mutex);
8365 
8366  /* Disable the irq before mode object teardown, for the irq might
8367  * enqueue unpin/hotplug work. */
8368  drm_irq_uninstall(dev);
8369  cancel_work_sync(&dev_priv->hotplug_work);
8370  cancel_work_sync(&dev_priv->rps.work);
8371 
8372  /* flush any delayed tasks or pending work */
8374 
8376 }
8377 
8378 /*
8379  * Return which encoder is currently attached for connector.
8380  */
8382 {
8383  return &intel_attached_encoder(connector)->base;
8384 }
8385 
8387  struct intel_encoder *encoder)
8388 {
8389  connector->encoder = encoder;
8391  &encoder->base);
8392 }
8393 
8394 /*
8395  * set vga decode state - true == enable VGA decode
8396  */
8397 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8398 {
8399  struct drm_i915_private *dev_priv = dev->dev_private;
8400  u16 gmch_ctrl;
8401 
8402  pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8403  if (state)
8404  gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8405  else
8406  gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8407  pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8408  return 0;
8409 }
8410 
8411 #ifdef CONFIG_DEBUG_FS
8412 #include <linux/seq_file.h>
8413 
8414 struct intel_display_error_state {
8415  struct intel_cursor_error_state {
8416  u32 control;
8417  u32 position;
8418  u32 base;
8419  u32 size;
8420  } cursor[I915_MAX_PIPES];
8421 
8422  struct intel_pipe_error_state {
8423  u32 conf;
8424  u32 source;
8425 
8426  u32 htotal;
8427  u32 hblank;
8428  u32 hsync;
8429  u32 vtotal;
8430  u32 vblank;
8431  u32 vsync;
8432  } pipe[I915_MAX_PIPES];
8433 
8434  struct intel_plane_error_state {
8435  u32 control;
8436  u32 stride;
8437  u32 size;
8438  u32 pos;
8439  u32 addr;
8440  u32 surface;
8441  u32 tile_offset;
8442  } plane[I915_MAX_PIPES];
8443 };
8444 
8445 struct intel_display_error_state *
8446 intel_display_capture_error_state(struct drm_device *dev)
8447 {
8448  drm_i915_private_t *dev_priv = dev->dev_private;
8449  struct intel_display_error_state *error;
8450  int i;
8451 
8452  error = kmalloc(sizeof(*error), GFP_ATOMIC);
8453  if (error == NULL)
8454  return NULL;
8455 
8456  for_each_pipe(i) {
8457  error->cursor[i].control = I915_READ(CURCNTR(i));
8458  error->cursor[i].position = I915_READ(CURPOS(i));
8459  error->cursor[i].base = I915_READ(CURBASE(i));
8460 
8461  error->plane[i].control = I915_READ(DSPCNTR(i));
8462  error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8463  error->plane[i].size = I915_READ(DSPSIZE(i));
8464  error->plane[i].pos = I915_READ(DSPPOS(i));
8465  error->plane[i].addr = I915_READ(DSPADDR(i));
8466  if (INTEL_INFO(dev)->gen >= 4) {
8467  error->plane[i].surface = I915_READ(DSPSURF(i));
8468  error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8469  }
8470 
8471  error->pipe[i].conf = I915_READ(PIPECONF(i));
8472  error->pipe[i].source = I915_READ(PIPESRC(i));
8473  error->pipe[i].htotal = I915_READ(HTOTAL(i));
8474  error->pipe[i].hblank = I915_READ(HBLANK(i));
8475  error->pipe[i].hsync = I915_READ(HSYNC(i));
8476  error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8477  error->pipe[i].vblank = I915_READ(VBLANK(i));
8478  error->pipe[i].vsync = I915_READ(VSYNC(i));
8479  }
8480 
8481  return error;
8482 }
8483 
8484 void
8485 intel_display_print_error_state(struct seq_file *m,
8486  struct drm_device *dev,
8487  struct intel_display_error_state *error)
8488 {
8489  drm_i915_private_t *dev_priv = dev->dev_private;
8490  int i;
8491 
8492  seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8493  for_each_pipe(i) {
8494  seq_printf(m, "Pipe [%d]:\n", i);
8495  seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8496  seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8497  seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8498  seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8499  seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8500  seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8501  seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8502  seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8503 
8504  seq_printf(m, "Plane [%d]:\n", i);
8505  seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8506  seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8507  seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8508  seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8509  seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8510  if (INTEL_INFO(dev)->gen >= 4) {
8511  seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8512  seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8513  }
8514 
8515  seq_printf(m, "Cursor [%d]:\n", i);
8516  seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8517  seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8518  seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8519  }
8520 }
8521 #endif