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pci-quirks.c
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1 /*
2  * This file contains code to reset and initialize USB host controllers.
3  * Some of it includes work-arounds for PCI hardware and BIOS quirks.
4  * It may need to run early during booting -- before USB would normally
5  * initialize -- to ensure that Linux doesn't use any legacy modes.
6  *
7  * Copyright (c) 1999 Martin Mares <[email protected]>
8  * (and others)
9  */
10 
11 #include <linux/types.h>
12 #include <linux/kconfig.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/export.h>
18 #include <linux/acpi.h>
19 #include <linux/dmi.h>
20 #include "pci-quirks.h"
21 #include "xhci-ext-caps.h"
22 
23 
24 #define UHCI_USBLEGSUP 0xc0 /* legacy support */
25 #define UHCI_USBCMD 0 /* command register */
26 #define UHCI_USBINTR 4 /* interrupt register */
27 #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
28 #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
29 #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
30 #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
31 #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
32 #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
33 #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
34 
35 #define OHCI_CONTROL 0x04
36 #define OHCI_CMDSTATUS 0x08
37 #define OHCI_INTRSTATUS 0x0c
38 #define OHCI_INTRENABLE 0x10
39 #define OHCI_INTRDISABLE 0x14
40 #define OHCI_FMINTERVAL 0x34
41 #define OHCI_HCFS (3 << 6) /* hc functional state */
42 #define OHCI_HCR (1 << 0) /* host controller reset */
43 #define OHCI_OCR (1 << 3) /* ownership change request */
44 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
45 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
46 #define OHCI_INTR_OC (1 << 30) /* ownership change */
47 
48 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
49 #define EHCI_USBCMD 0 /* command register */
50 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
51 #define EHCI_USBSTS 4 /* status register */
52 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
53 #define EHCI_USBINTR 8 /* interrupt register */
54 #define EHCI_CONFIGFLAG 0x40 /* configured flag register */
55 #define EHCI_USBLEGSUP 0 /* legacy support register */
56 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
57 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
58 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
59 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
60 
61 /* AMD quirk use */
62 #define AB_REG_BAR_LOW 0xe0
63 #define AB_REG_BAR_HIGH 0xe1
64 #define AB_REG_BAR_SB700 0xf0
65 #define AB_INDX(addr) ((addr) + 0x00)
66 #define AB_DATA(addr) ((addr) + 0x04)
67 #define AX_INDXC 0x30
68 #define AX_DATAC 0x34
69 
70 #define NB_PCIE_INDX_ADDR 0xe0
71 #define NB_PCIE_INDX_DATA 0xe4
72 #define PCIE_P_CNTL 0x10040
73 #define BIF_NB 0x10002
74 #define NB_PIF0_PWRDOWN_0 0x01100012
75 #define NB_PIF0_PWRDOWN_1 0x01100013
76 
77 #define USB_INTEL_XUSB2PR 0xD0
78 #define USB_INTEL_USB2PRM 0xD4
79 #define USB_INTEL_USB3_PSSEN 0xD8
80 #define USB_INTEL_USB3PRM 0xDC
81 
82 static struct amd_chipset_info {
83  struct pci_dev *nb_dev;
84  struct pci_dev *smbus_dev;
85  int nb_type;
86  int sb_type;
87  int isoc_reqs;
88  int probe_count;
89  int probe_result;
90 } amd_chipset;
91 
92 static DEFINE_SPINLOCK(amd_lock);
93 
94 int usb_amd_find_chipset_info(void)
95 {
96  u8 rev = 0;
97  unsigned long flags;
98  struct amd_chipset_info info;
99  int ret;
100 
101  spin_lock_irqsave(&amd_lock, flags);
102 
103  /* probe only once */
104  if (amd_chipset.probe_count > 0) {
105  amd_chipset.probe_count++;
106  spin_unlock_irqrestore(&amd_lock, flags);
107  return amd_chipset.probe_result;
108  }
109  memset(&info, 0, sizeof(info));
110  spin_unlock_irqrestore(&amd_lock, flags);
111 
112  info.smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
113  if (info.smbus_dev) {
114  rev = info.smbus_dev->revision;
115  if (rev >= 0x40)
116  info.sb_type = 1;
117  else if (rev >= 0x30 && rev <= 0x3b)
118  info.sb_type = 3;
119  } else {
120  info.smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
121  0x780b, NULL);
122  if (!info.smbus_dev) {
123  ret = 0;
124  goto commit;
125  }
126 
127  rev = info.smbus_dev->revision;
128  if (rev >= 0x11 && rev <= 0x18)
129  info.sb_type = 2;
130  }
131 
132  if (info.sb_type == 0) {
133  if (info.smbus_dev) {
134  pci_dev_put(info.smbus_dev);
135  info.smbus_dev = NULL;
136  }
137  ret = 0;
138  goto commit;
139  }
140 
141  info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
142  if (info.nb_dev) {
143  info.nb_type = 1;
144  } else {
145  info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
146  if (info.nb_dev) {
147  info.nb_type = 2;
148  } else {
149  info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
150  0x9600, NULL);
151  if (info.nb_dev)
152  info.nb_type = 3;
153  }
154  }
155 
156  ret = info.probe_result = 1;
157  printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
158 
159 commit:
160 
161  spin_lock_irqsave(&amd_lock, flags);
162  if (amd_chipset.probe_count > 0) {
163  /* race - someone else was faster - drop devices */
164 
165  /* Mark that we where here */
166  amd_chipset.probe_count++;
167  ret = amd_chipset.probe_result;
168 
169  spin_unlock_irqrestore(&amd_lock, flags);
170 
171  if (info.nb_dev)
172  pci_dev_put(info.nb_dev);
173  if (info.smbus_dev)
174  pci_dev_put(info.smbus_dev);
175 
176  } else {
177  /* no race - commit the result */
178  info.probe_count++;
179  amd_chipset = info;
180  spin_unlock_irqrestore(&amd_lock, flags);
181  }
182 
183  return ret;
184 }
185 EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
186 
187 /*
188  * The hardware normally enables the A-link power management feature, which
189  * lets the system lower the power consumption in idle states.
190  *
191  * This USB quirk prevents the link going into that lower power state
192  * during isochronous transfers.
193  *
194  * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
195  * some AMD platforms may stutter or have breaks occasionally.
196  */
197 static void usb_amd_quirk_pll(int disable)
198 {
199  u32 addr, addr_low, addr_high, val;
200  u32 bit = disable ? 0 : 1;
201  unsigned long flags;
202 
203  spin_lock_irqsave(&amd_lock, flags);
204 
205  if (disable) {
206  amd_chipset.isoc_reqs++;
207  if (amd_chipset.isoc_reqs > 1) {
208  spin_unlock_irqrestore(&amd_lock, flags);
209  return;
210  }
211  } else {
212  amd_chipset.isoc_reqs--;
213  if (amd_chipset.isoc_reqs > 0) {
214  spin_unlock_irqrestore(&amd_lock, flags);
215  return;
216  }
217  }
218 
219  if (amd_chipset.sb_type == 1 || amd_chipset.sb_type == 2) {
220  outb_p(AB_REG_BAR_LOW, 0xcd6);
221  addr_low = inb_p(0xcd7);
222  outb_p(AB_REG_BAR_HIGH, 0xcd6);
223  addr_high = inb_p(0xcd7);
224  addr = addr_high << 8 | addr_low;
225 
226  outl_p(0x30, AB_INDX(addr));
227  outl_p(0x40, AB_DATA(addr));
228  outl_p(0x34, AB_INDX(addr));
229  val = inl_p(AB_DATA(addr));
230  } else if (amd_chipset.sb_type == 3) {
231  pci_read_config_dword(amd_chipset.smbus_dev,
232  AB_REG_BAR_SB700, &addr);
233  outl(AX_INDXC, AB_INDX(addr));
234  outl(0x40, AB_DATA(addr));
235  outl(AX_DATAC, AB_INDX(addr));
236  val = inl(AB_DATA(addr));
237  } else {
238  spin_unlock_irqrestore(&amd_lock, flags);
239  return;
240  }
241 
242  if (disable) {
243  val &= ~0x08;
244  val |= (1 << 4) | (1 << 9);
245  } else {
246  val |= 0x08;
247  val &= ~((1 << 4) | (1 << 9));
248  }
249  outl_p(val, AB_DATA(addr));
250 
251  if (!amd_chipset.nb_dev) {
252  spin_unlock_irqrestore(&amd_lock, flags);
253  return;
254  }
255 
256  if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
257  addr = PCIE_P_CNTL;
258  pci_write_config_dword(amd_chipset.nb_dev,
259  NB_PCIE_INDX_ADDR, addr);
260  pci_read_config_dword(amd_chipset.nb_dev,
261  NB_PCIE_INDX_DATA, &val);
262 
263  val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
264  val |= bit | (bit << 3) | (bit << 12);
265  val |= ((!bit) << 4) | ((!bit) << 9);
266  pci_write_config_dword(amd_chipset.nb_dev,
267  NB_PCIE_INDX_DATA, val);
268 
269  addr = BIF_NB;
270  pci_write_config_dword(amd_chipset.nb_dev,
271  NB_PCIE_INDX_ADDR, addr);
272  pci_read_config_dword(amd_chipset.nb_dev,
273  NB_PCIE_INDX_DATA, &val);
274  val &= ~(1 << 8);
275  val |= bit << 8;
276 
277  pci_write_config_dword(amd_chipset.nb_dev,
278  NB_PCIE_INDX_DATA, val);
279  } else if (amd_chipset.nb_type == 2) {
280  addr = NB_PIF0_PWRDOWN_0;
281  pci_write_config_dword(amd_chipset.nb_dev,
282  NB_PCIE_INDX_ADDR, addr);
283  pci_read_config_dword(amd_chipset.nb_dev,
284  NB_PCIE_INDX_DATA, &val);
285  if (disable)
286  val &= ~(0x3f << 7);
287  else
288  val |= 0x3f << 7;
289 
290  pci_write_config_dword(amd_chipset.nb_dev,
291  NB_PCIE_INDX_DATA, val);
292 
293  addr = NB_PIF0_PWRDOWN_1;
294  pci_write_config_dword(amd_chipset.nb_dev,
295  NB_PCIE_INDX_ADDR, addr);
296  pci_read_config_dword(amd_chipset.nb_dev,
297  NB_PCIE_INDX_DATA, &val);
298  if (disable)
299  val &= ~(0x3f << 7);
300  else
301  val |= 0x3f << 7;
302 
303  pci_write_config_dword(amd_chipset.nb_dev,
304  NB_PCIE_INDX_DATA, val);
305  }
306 
307  spin_unlock_irqrestore(&amd_lock, flags);
308  return;
309 }
310 
311 void usb_amd_quirk_pll_disable(void)
312 {
313  usb_amd_quirk_pll(1);
314 }
315 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
316 
317 void usb_amd_quirk_pll_enable(void)
318 {
319  usb_amd_quirk_pll(0);
320 }
321 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
322 
323 void usb_amd_dev_put(void)
324 {
325  struct pci_dev *nb, *smbus;
326  unsigned long flags;
327 
328  spin_lock_irqsave(&amd_lock, flags);
329 
330  amd_chipset.probe_count--;
331  if (amd_chipset.probe_count > 0) {
332  spin_unlock_irqrestore(&amd_lock, flags);
333  return;
334  }
335 
336  /* save them to pci_dev_put outside of spinlock */
337  nb = amd_chipset.nb_dev;
338  smbus = amd_chipset.smbus_dev;
339 
340  amd_chipset.nb_dev = NULL;
341  amd_chipset.smbus_dev = NULL;
342  amd_chipset.nb_type = 0;
343  amd_chipset.sb_type = 0;
344  amd_chipset.isoc_reqs = 0;
345  amd_chipset.probe_result = 0;
346 
347  spin_unlock_irqrestore(&amd_lock, flags);
348 
349  if (nb)
350  pci_dev_put(nb);
351  if (smbus)
352  pci_dev_put(smbus);
353 }
354 EXPORT_SYMBOL_GPL(usb_amd_dev_put);
355 
356 /*
357  * Make sure the controller is completely inactive, unable to
358  * generate interrupts or do DMA.
359  */
360 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
361 {
362  /* Turn off PIRQ enable and SMI enable. (This also turns off the
363  * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
364  */
365  pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
366 
367  /* Reset the HC - this will force us to get a
368  * new notification of any already connected
369  * ports due to the virtual disconnect that it
370  * implies.
371  */
372  outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
373  mb();
374  udelay(5);
375  if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
376  dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
377 
378  /* Just to be safe, disable interrupt requests and
379  * make sure the controller is stopped.
380  */
381  outw(0, base + UHCI_USBINTR);
382  outw(0, base + UHCI_USBCMD);
383 }
384 EXPORT_SYMBOL_GPL(uhci_reset_hc);
385 
386 /*
387  * Initialize a controller that was newly discovered or has just been
388  * resumed. In either case we can't be sure of its previous state.
389  *
390  * Returns: 1 if the controller was reset, 0 otherwise.
391  */
392 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
393 {
394  u16 legsup;
395  unsigned int cmd, intr;
396 
397  /*
398  * When restarting a suspended controller, we expect all the
399  * settings to be the same as we left them:
400  *
401  * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
402  * Controller is stopped and configured with EGSM set;
403  * No interrupts enabled except possibly Resume Detect.
404  *
405  * If any of these conditions are violated we do a complete reset.
406  */
407  pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
408  if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
409  dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
410  __func__, legsup);
411  goto reset_needed;
412  }
413 
414  cmd = inw(base + UHCI_USBCMD);
415  if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
416  !(cmd & UHCI_USBCMD_EGSM)) {
417  dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
418  __func__, cmd);
419  goto reset_needed;
420  }
421 
422  intr = inw(base + UHCI_USBINTR);
423  if (intr & (~UHCI_USBINTR_RESUME)) {
424  dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
425  __func__, intr);
426  goto reset_needed;
427  }
428  return 0;
429 
430 reset_needed:
431  dev_dbg(&pdev->dev, "Performing full reset\n");
432  uhci_reset_hc(pdev, base);
433  return 1;
434 }
435 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
436 
437 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
438 {
439  u16 cmd;
440  return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
441 }
442 
443 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
444 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
445 
446 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
447 {
448  unsigned long base = 0;
449  int i;
450 
451  if (!pio_enabled(pdev))
452  return;
453 
454  for (i = 0; i < PCI_ROM_RESOURCE; i++)
455  if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
456  base = pci_resource_start(pdev, i);
457  break;
458  }
459 
460  if (base)
461  uhci_check_and_reset_hc(pdev, base);
462 }
463 
464 static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)
465 {
466  return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
467 }
468 
469 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
470 {
471  void __iomem *base;
472  u32 control;
473  u32 fminterval;
474  int cnt;
475 
476  if (!mmio_resource_enabled(pdev, 0))
477  return;
478 
479  base = pci_ioremap_bar(pdev, 0);
480  if (base == NULL)
481  return;
482 
483  control = readl(base + OHCI_CONTROL);
484 
485 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
486 #ifdef __hppa__
487 #define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR)
488 #else
489 #define OHCI_CTRL_MASK OHCI_CTRL_RWC
490 
491  if (control & OHCI_CTRL_IR) {
492  int wait_time = 500; /* arbitrary; 5 seconds */
493  writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
494  writel(OHCI_OCR, base + OHCI_CMDSTATUS);
495  while (wait_time > 0 &&
496  readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
497  wait_time -= 10;
498  msleep(10);
499  }
500  if (wait_time <= 0)
501  dev_warn(&pdev->dev, "OHCI: BIOS handoff failed"
502  " (BIOS bug?) %08x\n",
503  readl(base + OHCI_CONTROL));
504  }
505 #endif
506 
507  /* disable interrupts */
508  writel((u32) ~0, base + OHCI_INTRDISABLE);
509 
510  /* Reset the USB bus, if the controller isn't already in RESET */
511  if (control & OHCI_HCFS) {
512  /* Go into RESET, preserving RWC (and possibly IR) */
513  writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
514  readl(base + OHCI_CONTROL);
515 
516  /* drive bus reset for at least 50 ms (7.1.7.5) */
517  msleep(50);
518  }
519 
520  /* software reset of the controller, preserving HcFmInterval */
521  fminterval = readl(base + OHCI_FMINTERVAL);
522  writel(OHCI_HCR, base + OHCI_CMDSTATUS);
523 
524  /* reset requires max 10 us delay */
525  for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */
526  if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
527  break;
528  udelay(1);
529  }
530  writel(fminterval, base + OHCI_FMINTERVAL);
531 
532  /* Now the controller is safely in SUSPEND and nothing can wake it up */
533  iounmap(base);
534 }
535 
536 static const struct dmi_system_id __devinitconst ehci_dmi_nohandoff_table[] = {
537  {
538  /* Pegatron Lucid (ExoPC) */
539  .matches = {
540  DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"),
541  DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"),
542  },
543  },
544  {
545  /* Pegatron Lucid (Ordissimo AIRIS) */
546  .matches = {
547  DMI_MATCH(DMI_BOARD_NAME, "M11JB"),
548  DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
549  },
550  },
551  {
552  /* Pegatron Lucid (Ordissimo) */
553  .matches = {
554  DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"),
555  DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
556  },
557  },
558  { }
559 };
560 
561 static void __devinit ehci_bios_handoff(struct pci_dev *pdev,
562  void __iomem *op_reg_base,
563  u32 cap, u8 offset)
564 {
565  int try_handoff = 1, tried_handoff = 0;
566 
567  /* The Pegatron Lucid tablet sporadically waits for 98 seconds trying
568  * the handoff on its unused controller. Skip it. */
569  if (pdev->vendor == 0x8086 && pdev->device == 0x283a) {
570  if (dmi_check_system(ehci_dmi_nohandoff_table))
571  try_handoff = 0;
572  }
573 
574  if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
575  dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
576 
577 #if 0
578 /* [email protected] reports that some systems need SMI forced on,
579  * but that seems dubious in general (the BIOS left it off intentionally)
580  * and is known to prevent some systems from booting. so we won't do this
581  * unless maybe we can determine when we're on a system that needs SMI forced.
582  */
583  /* BIOS workaround (?): be sure the pre-Linux code
584  * receives the SMI
585  */
586  pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
587  pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
588  val | EHCI_USBLEGCTLSTS_SOOE);
589 #endif
590 
591  /* some systems get upset if this semaphore is
592  * set for any other reason than forcing a BIOS
593  * handoff..
594  */
595  pci_write_config_byte(pdev, offset + 3, 1);
596  }
597 
598  /* if boot firmware now owns EHCI, spin till it hands it over. */
599  if (try_handoff) {
600  int msec = 1000;
601  while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
602  tried_handoff = 1;
603  msleep(10);
604  msec -= 10;
605  pci_read_config_dword(pdev, offset, &cap);
606  }
607  }
608 
609  if (cap & EHCI_USBLEGSUP_BIOS) {
610  /* well, possibly buggy BIOS... try to shut it down,
611  * and hope nothing goes too wrong
612  */
613  if (try_handoff)
614  dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
615  " (BIOS bug?) %08x\n", cap);
616  pci_write_config_byte(pdev, offset + 2, 0);
617  }
618 
619  /* just in case, always disable EHCI SMIs */
620  pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
621 
622  /* If the BIOS ever owned the controller then we can't expect
623  * any power sessions to remain intact.
624  */
625  if (tried_handoff)
626  writel(0, op_reg_base + EHCI_CONFIGFLAG);
627 }
628 
629 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
630 {
631  void __iomem *base, *op_reg_base;
632  u32 hcc_params, cap, val;
633  u8 offset, cap_length;
634  int wait_time, count = 256/4;
635 
636  if (!mmio_resource_enabled(pdev, 0))
637  return;
638 
639  base = pci_ioremap_bar(pdev, 0);
640  if (base == NULL)
641  return;
642 
643  cap_length = readb(base);
644  op_reg_base = base + cap_length;
645 
646  /* EHCI 0.96 and later may have "extended capabilities"
647  * spec section 5.1 explains the bios handoff, e.g. for
648  * booting from USB disk or using a usb keyboard
649  */
650  hcc_params = readl(base + EHCI_HCC_PARAMS);
651  offset = (hcc_params >> 8) & 0xff;
652  while (offset && --count) {
653  pci_read_config_dword(pdev, offset, &cap);
654 
655  switch (cap & 0xff) {
656  case 1:
657  ehci_bios_handoff(pdev, op_reg_base, cap, offset);
658  break;
659  case 0: /* Illegal reserved cap, set cap=0 so we exit */
660  cap = 0; /* then fallthrough... */
661  default:
662  dev_warn(&pdev->dev, "EHCI: unrecognized capability "
663  "%02x\n", cap & 0xff);
664  }
665  offset = (cap >> 8) & 0xff;
666  }
667  if (!count)
668  dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
669 
670  /*
671  * halt EHCI & disable its interrupts in any case
672  */
673  val = readl(op_reg_base + EHCI_USBSTS);
674  if ((val & EHCI_USBSTS_HALTED) == 0) {
675  val = readl(op_reg_base + EHCI_USBCMD);
676  val &= ~EHCI_USBCMD_RUN;
677  writel(val, op_reg_base + EHCI_USBCMD);
678 
679  wait_time = 2000;
680  do {
681  writel(0x3f, op_reg_base + EHCI_USBSTS);
682  udelay(100);
683  wait_time -= 100;
684  val = readl(op_reg_base + EHCI_USBSTS);
685  if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
686  break;
687  }
688  } while (wait_time > 0);
689  }
690  writel(0, op_reg_base + EHCI_USBINTR);
691  writel(0x3f, op_reg_base + EHCI_USBSTS);
692 
693  iounmap(base);
694 }
695 
696 /*
697  * handshake - spin reading a register until handshake completes
698  * @ptr: address of hc register to be read
699  * @mask: bits to look at in result of read
700  * @done: value of those bits when handshake succeeds
701  * @wait_usec: timeout in microseconds
702  * @delay_usec: delay in microseconds to wait between polling
703  *
704  * Polls a register every delay_usec microseconds.
705  * Returns 0 when the mask bits have the value done.
706  * Returns -ETIMEDOUT if this condition is not true after
707  * wait_usec microseconds have passed.
708  */
709 static int handshake(void __iomem *ptr, u32 mask, u32 done,
710  int wait_usec, int delay_usec)
711 {
712  u32 result;
713 
714  do {
715  result = readl(ptr);
716  result &= mask;
717  if (result == done)
718  return 0;
719  udelay(delay_usec);
720  wait_usec -= delay_usec;
721  } while (wait_usec > 0);
722  return -ETIMEDOUT;
723 }
724 
725 #define PCI_DEVICE_ID_INTEL_LYNX_POINT_XHCI 0x8C31
726 
727 bool usb_is_intel_ppt_switchable_xhci(struct pci_dev *pdev)
728 {
729  return pdev->class == PCI_CLASS_SERIAL_USB_XHCI &&
730  pdev->vendor == PCI_VENDOR_ID_INTEL &&
731  pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI;
732 }
733 
734 /* The Intel Lynx Point chipset also has switchable ports. */
735 bool usb_is_intel_lpt_switchable_xhci(struct pci_dev *pdev)
736 {
737  return pdev->class == PCI_CLASS_SERIAL_USB_XHCI &&
738  pdev->vendor == PCI_VENDOR_ID_INTEL &&
739  pdev->device == PCI_DEVICE_ID_INTEL_LYNX_POINT_XHCI;
740 }
741 
742 bool usb_is_intel_switchable_xhci(struct pci_dev *pdev)
743 {
744  return usb_is_intel_ppt_switchable_xhci(pdev) ||
745  usb_is_intel_lpt_switchable_xhci(pdev);
746 }
747 EXPORT_SYMBOL_GPL(usb_is_intel_switchable_xhci);
748 
749 /*
750  * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
751  * share some number of ports. These ports can be switched between either
752  * controller. Not all of the ports under the EHCI host controller may be
753  * switchable.
754  *
755  * The ports should be switched over to xHCI before PCI probes for any device
756  * start. This avoids active devices under EHCI being disconnected during the
757  * port switchover, which could cause loss of data on USB storage devices, or
758  * failed boot when the root file system is on a USB mass storage device and is
759  * enumerated under EHCI first.
760  *
761  * We write into the xHC's PCI configuration space in some Intel-specific
762  * registers to switch the ports over. The USB 3.0 terminations and the USB
763  * 2.0 data wires are switched separately. We want to enable the SuperSpeed
764  * terminations before switching the USB 2.0 wires over, so that USB 3.0
765  * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
766  */
767 void usb_enable_xhci_ports(struct pci_dev *xhci_pdev)
768 {
769  u32 ports_available;
770 
771  /* Don't switchover the ports if the user hasn't compiled the xHCI
772  * driver. Otherwise they will see "dead" USB ports that don't power
773  * the devices.
774  */
775  if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) {
776  dev_warn(&xhci_pdev->dev,
777  "CONFIG_USB_XHCI_HCD is turned off, "
778  "defaulting to EHCI.\n");
779  dev_warn(&xhci_pdev->dev,
780  "USB 3.0 devices will work at USB 2.0 speeds.\n");
781  return;
782  }
783 
784  /* Read USB3PRM, the USB 3.0 Port Routing Mask Register
785  * Indicate the ports that can be changed from OS.
786  */
787  pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM,
788  &ports_available);
789 
790  dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n",
791  ports_available);
792 
793  /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
794  * Register, to turn on SuperSpeed terminations for the
795  * switchable ports.
796  */
797  pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
798  cpu_to_le32(ports_available));
799 
800  pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
801  &ports_available);
802  dev_dbg(&xhci_pdev->dev, "USB 3.0 ports that are now enabled "
803  "under xHCI: 0x%x\n", ports_available);
804 
805  /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register
806  * Indicate the USB 2.0 ports to be controlled by the xHCI host.
807  */
808 
809  pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM,
810  &ports_available);
811 
812  dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n",
813  ports_available);
814 
815  /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
816  * switch the USB 2.0 power and data lines over to the xHCI
817  * host.
818  */
819  pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
820  cpu_to_le32(ports_available));
821 
822  pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
823  &ports_available);
824  dev_dbg(&xhci_pdev->dev, "USB 2.0 ports that are now switched over "
825  "to xHCI: 0x%x\n", ports_available);
826 }
827 EXPORT_SYMBOL_GPL(usb_enable_xhci_ports);
828 
829 void usb_disable_xhci_ports(struct pci_dev *xhci_pdev)
830 {
831  pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0);
832  pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0);
833 }
834 EXPORT_SYMBOL_GPL(usb_disable_xhci_ports);
835 
844 static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev)
845 {
846  void __iomem *base;
847  int ext_cap_offset;
848  void __iomem *op_reg_base;
849  u32 val;
850  int timeout;
851  int len = pci_resource_len(pdev, 0);
852 
853  if (!mmio_resource_enabled(pdev, 0))
854  return;
855 
856  base = ioremap_nocache(pci_resource_start(pdev, 0), len);
857  if (base == NULL)
858  return;
859 
860  /*
861  * Find the Legacy Support Capability register -
862  * this is optional for xHCI host controllers.
863  */
864  ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET);
865  do {
866  if ((ext_cap_offset + sizeof(val)) > len) {
867  /* We're reading garbage from the controller */
868  dev_warn(&pdev->dev,
869  "xHCI controller failing to respond");
870  return;
871  }
872 
873  if (!ext_cap_offset)
874  /* We've reached the end of the extended capabilities */
875  goto hc_init;
876 
877  val = readl(base + ext_cap_offset);
878  if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY)
879  break;
880  ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset);
881  } while (1);
882 
883  /* If the BIOS owns the HC, signal that the OS wants it, and wait */
884  if (val & XHCI_HC_BIOS_OWNED) {
885  writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
886 
887  /* Wait for 5 seconds with 10 microsecond polling interval */
888  timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
889  0, 5000, 10);
890 
891  /* Assume a buggy BIOS and take HC ownership anyway */
892  if (timeout) {
893  dev_warn(&pdev->dev, "xHCI BIOS handoff failed"
894  " (BIOS bug ?) %08x\n", val);
895  writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
896  }
897  }
898 
899  val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
900  /* Mask off (turn off) any enabled SMIs */
901  val &= XHCI_LEGACY_DISABLE_SMI;
902  /* Mask all SMI events bits, RW1C */
903  val |= XHCI_LEGACY_SMI_EVENTS;
904  /* Disable any BIOS SMIs and clear all SMI events*/
905  writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
906 
907 hc_init:
908  if (usb_is_intel_switchable_xhci(pdev))
909  usb_enable_xhci_ports(pdev);
910 
911  op_reg_base = base + XHCI_HC_LENGTH(readl(base));
912 
913  /* Wait for the host controller to be ready before writing any
914  * operational or runtime registers. Wait 5 seconds and no more.
915  */
916  timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
917  5000, 10);
918  /* Assume a buggy HC and start HC initialization anyway */
919  if (timeout) {
920  val = readl(op_reg_base + XHCI_STS_OFFSET);
921  dev_warn(&pdev->dev,
922  "xHCI HW not ready after 5 sec (HC bug?) "
923  "status = 0x%x\n", val);
924  }
925 
926  /* Send the halt and disable interrupts command */
927  val = readl(op_reg_base + XHCI_CMD_OFFSET);
928  val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
929  writel(val, op_reg_base + XHCI_CMD_OFFSET);
930 
931  /* Wait for the HC to halt - poll every 125 usec (one microframe). */
932  timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
933  XHCI_MAX_HALT_USEC, 125);
934  if (timeout) {
935  val = readl(op_reg_base + XHCI_STS_OFFSET);
936  dev_warn(&pdev->dev,
937  "xHCI HW did not halt within %d usec "
938  "status = 0x%x\n", XHCI_MAX_HALT_USEC, val);
939  }
940 
941  iounmap(base);
942 }
943 
944 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
945 {
946  /* Skip Netlogic mips SoC's internal PCI USB controller.
947  * This device does not need/support EHCI/OHCI handoff
948  */
949  if (pdev->vendor == 0x184e) /* vendor Netlogic */
950  return;
951  if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI &&
952  pdev->class != PCI_CLASS_SERIAL_USB_OHCI &&
953  pdev->class != PCI_CLASS_SERIAL_USB_EHCI &&
954  pdev->class != PCI_CLASS_SERIAL_USB_XHCI)
955  return;
956 
957  if (pci_enable_device(pdev) < 0) {
958  dev_warn(&pdev->dev, "Can't enable PCI device, "
959  "BIOS handoff failed.\n");
960  return;
961  }
962  if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
963  quirk_usb_handoff_uhci(pdev);
964  else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
965  quirk_usb_handoff_ohci(pdev);
966  else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
967  quirk_usb_disable_ehci(pdev);
968  else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
969  quirk_usb_handoff_xhci(pdev);
970  pci_disable_device(pdev);
971 }
972 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
973  PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);
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