Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
qla_dbg.c
Go to the documentation of this file.
1 /*
2  * QLogic Fibre Channel HBA Driver
3  * Copyright (c) 2003-2012 QLogic Corporation
4  *
5  * See LICENSE.qla2xxx for copyright and licensing details.
6  */
7 
8 /*
9  * Table for showing the current message id in use for particular level
10  * Change this table for addition of log/debug messages.
11  * ----------------------------------------------------------------------
12  * | Level | Last Value Used | Holes |
13  * ----------------------------------------------------------------------
14  * | Module Init and Probe | 0x0124 | 0x4b,0xba,0xfa |
15  * | Mailbox commands | 0x114f | 0x111a-0x111b |
16  * | | | 0x112c-0x112e |
17  * | | | 0x113a |
18  * | Device Discovery | 0x2087 | 0x2020-0x2022, |
19  * | | | 0x2016 |
20  * | Queue Command and IO tracing | 0x3030 | 0x3006-0x300b |
21  * | | | 0x3027-0x3028 |
22  * | | | 0x302d-0x302e |
23  * | DPC Thread | 0x401d | 0x4002,0x4013 |
24  * | Async Events | 0x5071 | 0x502b-0x502f |
25  * | | | 0x5047,0x5052 |
26  * | Timer Routines | 0x6011 | |
27  * | User Space Interactions | 0x70c3 | 0x7018,0x702e, |
28  * | | | 0x7039,0x7045, |
29  * | | | 0x7073-0x7075, |
30  * | | | 0x708c, |
31  * | | | 0x70a5,0x70a6, |
32  * | | | 0x70a8,0x70ab, |
33  * | | | 0x70ad-0x70ae |
34  * | Task Management | 0x803c | 0x8025-0x8026 |
35  * | | | 0x800b,0x8039 |
36  * | AER/EEH | 0x9011 | |
37  * | Virtual Port | 0xa007 | |
38  * | ISP82XX Specific | 0xb084 | 0xb002,0xb024 |
39  * | MultiQ | 0xc00c | |
40  * | Misc | 0xd010 | |
41  * | Target Mode | 0xe06f | |
42  * | Target Mode Management | 0xf071 | |
43  * | Target Mode Task Management | 0x1000b | |
44  * ----------------------------------------------------------------------
45  */
46 
47 #include "qla_def.h"
48 
49 #include <linux/delay.h>
50 
51 static uint32_t ql_dbg_offset = 0x800;
52 
53 static inline void
54 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
55 {
56  fw_dump->fw_major_version = htonl(ha->fw_major_version);
57  fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
58  fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
59  fw_dump->fw_attributes = htonl(ha->fw_attributes);
60 
61  fw_dump->vendor = htonl(ha->pdev->vendor);
62  fw_dump->device = htonl(ha->pdev->device);
63  fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
64  fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
65 }
66 
67 static inline void *
68 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
69 {
70  struct req_que *req = ha->req_q_map[0];
71  struct rsp_que *rsp = ha->rsp_q_map[0];
72  /* Request queue. */
73  memcpy(ptr, req->ring, req->length *
74  sizeof(request_t));
75 
76  /* Response queue. */
77  ptr += req->length * sizeof(request_t);
78  memcpy(ptr, rsp->ring, rsp->length *
79  sizeof(response_t));
80 
81  return ptr + (rsp->length * sizeof(response_t));
82 }
83 
84 static int
85 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
86  uint32_t ram_dwords, void **nxt)
87 {
88  int rval;
89  uint32_t cnt, stat, timer, dwords, idx;
90  uint16_t mb0;
91  struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
92  dma_addr_t dump_dma = ha->gid_list_dma;
93  uint32_t *dump = (uint32_t *)ha->gid_list;
94 
95  rval = QLA_SUCCESS;
96  mb0 = 0;
97 
98  WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
99  clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
100 
101  dwords = qla2x00_gid_list_size(ha) / 4;
102  for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
103  cnt += dwords, addr += dwords) {
104  if (cnt + dwords > ram_dwords)
105  dwords = ram_dwords - cnt;
106 
107  WRT_REG_WORD(&reg->mailbox1, LSW(addr));
108  WRT_REG_WORD(&reg->mailbox8, MSW(addr));
109 
110  WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
111  WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
112  WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
113  WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
114 
115  WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
116  WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
117  WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
118 
119  for (timer = 6000000; timer; timer--) {
120  /* Check for pending interrupts. */
121  stat = RD_REG_DWORD(&reg->host_status);
122  if (stat & HSRX_RISC_INT) {
123  stat &= 0xff;
124 
125  if (stat == 0x1 || stat == 0x2 ||
126  stat == 0x10 || stat == 0x11) {
127  set_bit(MBX_INTERRUPT,
128  &ha->mbx_cmd_flags);
129 
130  mb0 = RD_REG_WORD(&reg->mailbox0);
131 
132  WRT_REG_DWORD(&reg->hccr,
133  HCCRX_CLR_RISC_INT);
134  RD_REG_DWORD(&reg->hccr);
135  break;
136  }
137 
138  /* Clear this intr; it wasn't a mailbox intr */
139  WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
140  RD_REG_DWORD(&reg->hccr);
141  }
142  udelay(5);
143  }
144 
145  if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
146  rval = mb0 & MBS_MASK;
147  for (idx = 0; idx < dwords; idx++)
148  ram[cnt + idx] = swab32(dump[idx]);
149  } else {
150  rval = QLA_FUNCTION_FAILED;
151  }
152  }
153 
154  *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
155  return rval;
156 }
157 
158 static int
159 qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
160  uint32_t cram_size, void **nxt)
161 {
162  int rval;
163 
164  /* Code RAM. */
165  rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
166  if (rval != QLA_SUCCESS)
167  return rval;
168 
169  /* External Memory. */
170  return qla24xx_dump_ram(ha, 0x100000, *nxt,
171  ha->fw_memory_size - 0x100000 + 1, nxt);
172 }
173 
174 static uint32_t *
175 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
176  uint32_t count, uint32_t *buf)
177 {
178  uint32_t __iomem *dmp_reg;
179 
180  WRT_REG_DWORD(&reg->iobase_addr, iobase);
181  dmp_reg = &reg->iobase_window;
182  while (count--)
183  *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
184 
185  return buf;
186 }
187 
188 static inline int
189 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
190 {
191  int rval = QLA_SUCCESS;
192  uint32_t cnt;
193 
194  WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
195  for (cnt = 30000;
196  ((RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) == 0) &&
197  rval == QLA_SUCCESS; cnt--) {
198  if (cnt)
199  udelay(100);
200  else
201  rval = QLA_FUNCTION_TIMEOUT;
202  }
203 
204  return rval;
205 }
206 
207 static int
208 qla24xx_soft_reset(struct qla_hw_data *ha)
209 {
210  int rval = QLA_SUCCESS;
211  uint32_t cnt;
212  uint16_t mb0, wd;
213  struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
214 
215  /* Reset RISC. */
216  WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
217  for (cnt = 0; cnt < 30000; cnt++) {
218  if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
219  break;
220 
221  udelay(10);
222  }
223 
224  WRT_REG_DWORD(&reg->ctrl_status,
225  CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
226  pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
227 
228  udelay(100);
229  /* Wait for firmware to complete NVRAM accesses. */
230  mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
231  for (cnt = 10000 ; cnt && mb0; cnt--) {
232  udelay(5);
233  mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
234  barrier();
235  }
236 
237  /* Wait for soft-reset to complete. */
238  for (cnt = 0; cnt < 30000; cnt++) {
239  if ((RD_REG_DWORD(&reg->ctrl_status) &
240  CSRX_ISP_SOFT_RESET) == 0)
241  break;
242 
243  udelay(10);
244  }
245  WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
246  RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
247 
248  for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
249  rval == QLA_SUCCESS; cnt--) {
250  if (cnt)
251  udelay(100);
252  else
253  rval = QLA_FUNCTION_TIMEOUT;
254  }
255 
256  return rval;
257 }
258 
259 static int
260 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
261  uint32_t ram_words, void **nxt)
262 {
263  int rval;
264  uint32_t cnt, stat, timer, words, idx;
265  uint16_t mb0;
266  struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
267  dma_addr_t dump_dma = ha->gid_list_dma;
268  uint16_t *dump = (uint16_t *)ha->gid_list;
269 
270  rval = QLA_SUCCESS;
271  mb0 = 0;
272 
273  WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
274  clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
275 
276  words = qla2x00_gid_list_size(ha) / 2;
277  for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
278  cnt += words, addr += words) {
279  if (cnt + words > ram_words)
280  words = ram_words - cnt;
281 
282  WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
283  WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
284 
285  WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
286  WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
287  WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
288  WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
289 
290  WRT_MAILBOX_REG(ha, reg, 4, words);
291  WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
292 
293  for (timer = 6000000; timer; timer--) {
294  /* Check for pending interrupts. */
295  stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
296  if (stat & HSR_RISC_INT) {
297  stat &= 0xff;
298 
299  if (stat == 0x1 || stat == 0x2) {
300  set_bit(MBX_INTERRUPT,
301  &ha->mbx_cmd_flags);
302 
303  mb0 = RD_MAILBOX_REG(ha, reg, 0);
304 
305  /* Release mailbox registers. */
306  WRT_REG_WORD(&reg->semaphore, 0);
307  WRT_REG_WORD(&reg->hccr,
308  HCCR_CLR_RISC_INT);
309  RD_REG_WORD(&reg->hccr);
310  break;
311  } else if (stat == 0x10 || stat == 0x11) {
312  set_bit(MBX_INTERRUPT,
313  &ha->mbx_cmd_flags);
314 
315  mb0 = RD_MAILBOX_REG(ha, reg, 0);
316 
317  WRT_REG_WORD(&reg->hccr,
318  HCCR_CLR_RISC_INT);
319  RD_REG_WORD(&reg->hccr);
320  break;
321  }
322 
323  /* clear this intr; it wasn't a mailbox intr */
324  WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
325  RD_REG_WORD(&reg->hccr);
326  }
327  udelay(5);
328  }
329 
330  if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
331  rval = mb0 & MBS_MASK;
332  for (idx = 0; idx < words; idx++)
333  ram[cnt + idx] = swab16(dump[idx]);
334  } else {
335  rval = QLA_FUNCTION_FAILED;
336  }
337  }
338 
339  *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
340  return rval;
341 }
342 
343 static inline void
344 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
345  uint16_t *buf)
346 {
347  uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
348 
349  while (count--)
350  *buf++ = htons(RD_REG_WORD(dmp_reg++));
351 }
352 
353 static inline void *
354 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
355 {
356  if (!ha->eft)
357  return ptr;
358 
359  memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
360  return ptr + ntohl(ha->fw_dump->eft_size);
361 }
362 
363 static inline void *
364 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
365 {
366  uint32_t cnt;
367  uint32_t *iter_reg;
368  struct qla2xxx_fce_chain *fcec = ptr;
369 
370  if (!ha->fce)
371  return ptr;
372 
373  *last_chain = &fcec->type;
374  fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
375  fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
376  fce_calc_size(ha->fce_bufs));
377  fcec->size = htonl(fce_calc_size(ha->fce_bufs));
378  fcec->addr_l = htonl(LSD(ha->fce_dma));
379  fcec->addr_h = htonl(MSD(ha->fce_dma));
380 
381  iter_reg = fcec->eregs;
382  for (cnt = 0; cnt < 8; cnt++)
383  *iter_reg++ = htonl(ha->fce_mb[cnt]);
384 
385  memcpy(iter_reg, ha->fce, ntohl(fcec->size));
386 
387  return (char *)iter_reg + ntohl(fcec->size);
388 }
389 
390 static inline void *
391 qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr,
392  uint32_t **last_chain)
393 {
394  struct qla2xxx_mqueue_chain *q;
395  struct qla2xxx_mqueue_header *qh;
396  uint32_t num_queues;
397  int que;
398  struct {
399  int length;
400  void *ring;
401  } aq, *aqp;
402 
403  if (!ha->tgt.atio_q_length)
404  return ptr;
405 
406  num_queues = 1;
407  aqp = &aq;
408  aqp->length = ha->tgt.atio_q_length;
409  aqp->ring = ha->tgt.atio_ring;
410 
411  for (que = 0; que < num_queues; que++) {
412  /* aqp = ha->atio_q_map[que]; */
413  q = ptr;
414  *last_chain = &q->type;
415  q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
416  q->chain_size = htonl(
417  sizeof(struct qla2xxx_mqueue_chain) +
418  sizeof(struct qla2xxx_mqueue_header) +
419  (aqp->length * sizeof(request_t)));
420  ptr += sizeof(struct qla2xxx_mqueue_chain);
421 
422  /* Add header. */
423  qh = ptr;
424  qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
425  qh->number = htonl(que);
426  qh->size = htonl(aqp->length * sizeof(request_t));
427  ptr += sizeof(struct qla2xxx_mqueue_header);
428 
429  /* Add data. */
430  memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
431 
432  ptr += aqp->length * sizeof(request_t);
433  }
434 
435  return ptr;
436 }
437 
438 static inline void *
439 qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
440 {
441  struct qla2xxx_mqueue_chain *q;
442  struct qla2xxx_mqueue_header *qh;
443  struct req_que *req;
444  struct rsp_que *rsp;
445  int que;
446 
447  if (!ha->mqenable)
448  return ptr;
449 
450  /* Request queues */
451  for (que = 1; que < ha->max_req_queues; que++) {
452  req = ha->req_q_map[que];
453  if (!req)
454  break;
455 
456  /* Add chain. */
457  q = ptr;
458  *last_chain = &q->type;
459  q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
460  q->chain_size = htonl(
461  sizeof(struct qla2xxx_mqueue_chain) +
462  sizeof(struct qla2xxx_mqueue_header) +
463  (req->length * sizeof(request_t)));
464  ptr += sizeof(struct qla2xxx_mqueue_chain);
465 
466  /* Add header. */
467  qh = ptr;
468  qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
469  qh->number = htonl(que);
470  qh->size = htonl(req->length * sizeof(request_t));
471  ptr += sizeof(struct qla2xxx_mqueue_header);
472 
473  /* Add data. */
474  memcpy(ptr, req->ring, req->length * sizeof(request_t));
475  ptr += req->length * sizeof(request_t);
476  }
477 
478  /* Response queues */
479  for (que = 1; que < ha->max_rsp_queues; que++) {
480  rsp = ha->rsp_q_map[que];
481  if (!rsp)
482  break;
483 
484  /* Add chain. */
485  q = ptr;
486  *last_chain = &q->type;
487  q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
488  q->chain_size = htonl(
489  sizeof(struct qla2xxx_mqueue_chain) +
490  sizeof(struct qla2xxx_mqueue_header) +
491  (rsp->length * sizeof(response_t)));
492  ptr += sizeof(struct qla2xxx_mqueue_chain);
493 
494  /* Add header. */
495  qh = ptr;
496  qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
497  qh->number = htonl(que);
498  qh->size = htonl(rsp->length * sizeof(response_t));
499  ptr += sizeof(struct qla2xxx_mqueue_header);
500 
501  /* Add data. */
502  memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
503  ptr += rsp->length * sizeof(response_t);
504  }
505 
506  return ptr;
507 }
508 
509 static inline void *
510 qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
511 {
512  uint32_t cnt, que_idx;
513  uint8_t que_cnt;
514  struct qla2xxx_mq_chain *mq = ptr;
515  struct device_reg_25xxmq __iomem *reg;
516 
517  if (!ha->mqenable || IS_QLA83XX(ha))
518  return ptr;
519 
520  mq = ptr;
521  *last_chain = &mq->type;
522  mq->type = __constant_htonl(DUMP_CHAIN_MQ);
523  mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
524 
525  que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
526  ha->max_req_queues : ha->max_rsp_queues;
527  mq->count = htonl(que_cnt);
528  for (cnt = 0; cnt < que_cnt; cnt++) {
529  reg = (struct device_reg_25xxmq *) ((void *)
530  ha->mqiobase + cnt * QLA_QUE_PAGE);
531  que_idx = cnt * 4;
532  mq->qregs[que_idx] = htonl(RD_REG_DWORD(&reg->req_q_in));
533  mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(&reg->req_q_out));
534  mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(&reg->rsp_q_in));
535  mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(&reg->rsp_q_out));
536  }
537 
538  return ptr + sizeof(struct qla2xxx_mq_chain);
539 }
540 
541 void
542 qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
543 {
544  struct qla_hw_data *ha = vha->hw;
545 
546  if (rval != QLA_SUCCESS) {
547  ql_log(ql_log_warn, vha, 0xd000,
548  "Failed to dump firmware (%x).\n", rval);
549  ha->fw_dumped = 0;
550  } else {
551  ql_log(ql_log_info, vha, 0xd001,
552  "Firmware dump saved to temp buffer (%ld/%p).\n",
553  vha->host_no, ha->fw_dump);
554  ha->fw_dumped = 1;
555  qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
556  }
557 }
558 
564 void
565 qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
566 {
567  int rval;
568  uint32_t cnt;
569  struct qla_hw_data *ha = vha->hw;
570  struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
571  uint16_t __iomem *dmp_reg;
572  unsigned long flags;
573  struct qla2300_fw_dump *fw;
574  void *nxt;
575  struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
576 
577  flags = 0;
578 
579  if (!hardware_locked)
580  spin_lock_irqsave(&ha->hardware_lock, flags);
581 
582  if (!ha->fw_dump) {
583  ql_log(ql_log_warn, vha, 0xd002,
584  "No buffer available for dump.\n");
585  goto qla2300_fw_dump_failed;
586  }
587 
588  if (ha->fw_dumped) {
589  ql_log(ql_log_warn, vha, 0xd003,
590  "Firmware has been previously dumped (%p) "
591  "-- ignoring request.\n",
592  ha->fw_dump);
593  goto qla2300_fw_dump_failed;
594  }
595  fw = &ha->fw_dump->isp.isp23;
596  qla2xxx_prep_dump(ha, ha->fw_dump);
597 
598  rval = QLA_SUCCESS;
599  fw->hccr = htons(RD_REG_WORD(&reg->hccr));
600 
601  /* Pause RISC. */
602  WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
603  if (IS_QLA2300(ha)) {
604  for (cnt = 30000;
605  (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
606  rval == QLA_SUCCESS; cnt--) {
607  if (cnt)
608  udelay(100);
609  else
610  rval = QLA_FUNCTION_TIMEOUT;
611  }
612  } else {
613  RD_REG_WORD(&reg->hccr); /* PCI Posting. */
614  udelay(10);
615  }
616 
617  if (rval == QLA_SUCCESS) {
618  dmp_reg = &reg->flash_address;
619  for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
620  fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
621 
622  dmp_reg = &reg->u.isp2300.req_q_in;
623  for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
624  fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
625 
626  dmp_reg = &reg->u.isp2300.mailbox0;
627  for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
628  fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
629 
630  WRT_REG_WORD(&reg->ctrl_status, 0x40);
631  qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
632 
633  WRT_REG_WORD(&reg->ctrl_status, 0x50);
634  qla2xxx_read_window(reg, 48, fw->dma_reg);
635 
636  WRT_REG_WORD(&reg->ctrl_status, 0x00);
637  dmp_reg = &reg->risc_hw;
638  for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
639  fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
640 
641  WRT_REG_WORD(&reg->pcr, 0x2000);
642  qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
643 
644  WRT_REG_WORD(&reg->pcr, 0x2200);
645  qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
646 
647  WRT_REG_WORD(&reg->pcr, 0x2400);
648  qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
649 
650  WRT_REG_WORD(&reg->pcr, 0x2600);
651  qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
652 
653  WRT_REG_WORD(&reg->pcr, 0x2800);
654  qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
655 
656  WRT_REG_WORD(&reg->pcr, 0x2A00);
657  qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
658 
659  WRT_REG_WORD(&reg->pcr, 0x2C00);
660  qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
661 
662  WRT_REG_WORD(&reg->pcr, 0x2E00);
663  qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
664 
665  WRT_REG_WORD(&reg->ctrl_status, 0x10);
666  qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
667 
668  WRT_REG_WORD(&reg->ctrl_status, 0x20);
669  qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
670 
671  WRT_REG_WORD(&reg->ctrl_status, 0x30);
672  qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
673 
674  /* Reset RISC. */
675  WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
676  for (cnt = 0; cnt < 30000; cnt++) {
677  if ((RD_REG_WORD(&reg->ctrl_status) &
678  CSR_ISP_SOFT_RESET) == 0)
679  break;
680 
681  udelay(10);
682  }
683  }
684 
685  if (!IS_QLA2300(ha)) {
686  for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
687  rval == QLA_SUCCESS; cnt--) {
688  if (cnt)
689  udelay(100);
690  else
691  rval = QLA_FUNCTION_TIMEOUT;
692  }
693  }
694 
695  /* Get RISC SRAM. */
696  if (rval == QLA_SUCCESS)
697  rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
698  sizeof(fw->risc_ram) / 2, &nxt);
699 
700  /* Get stack SRAM. */
701  if (rval == QLA_SUCCESS)
702  rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
703  sizeof(fw->stack_ram) / 2, &nxt);
704 
705  /* Get data SRAM. */
706  if (rval == QLA_SUCCESS)
707  rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
708  ha->fw_memory_size - 0x11000 + 1, &nxt);
709 
710  if (rval == QLA_SUCCESS)
711  qla2xxx_copy_queues(ha, nxt);
712 
713  qla2xxx_dump_post_process(base_vha, rval);
714 
715 qla2300_fw_dump_failed:
716  if (!hardware_locked)
717  spin_unlock_irqrestore(&ha->hardware_lock, flags);
718 }
719 
725 void
726 qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
727 {
728  int rval;
729  uint32_t cnt, timer;
730  uint16_t risc_address;
731  uint16_t mb0, mb2;
732  struct qla_hw_data *ha = vha->hw;
733  struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
734  uint16_t __iomem *dmp_reg;
735  unsigned long flags;
736  struct qla2100_fw_dump *fw;
737  struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
738 
739  risc_address = 0;
740  mb0 = mb2 = 0;
741  flags = 0;
742 
743  if (!hardware_locked)
744  spin_lock_irqsave(&ha->hardware_lock, flags);
745 
746  if (!ha->fw_dump) {
747  ql_log(ql_log_warn, vha, 0xd004,
748  "No buffer available for dump.\n");
749  goto qla2100_fw_dump_failed;
750  }
751 
752  if (ha->fw_dumped) {
753  ql_log(ql_log_warn, vha, 0xd005,
754  "Firmware has been previously dumped (%p) "
755  "-- ignoring request.\n",
756  ha->fw_dump);
757  goto qla2100_fw_dump_failed;
758  }
759  fw = &ha->fw_dump->isp.isp21;
760  qla2xxx_prep_dump(ha, ha->fw_dump);
761 
762  rval = QLA_SUCCESS;
763  fw->hccr = htons(RD_REG_WORD(&reg->hccr));
764 
765  /* Pause RISC. */
766  WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
767  for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
768  rval == QLA_SUCCESS; cnt--) {
769  if (cnt)
770  udelay(100);
771  else
772  rval = QLA_FUNCTION_TIMEOUT;
773  }
774  if (rval == QLA_SUCCESS) {
775  dmp_reg = &reg->flash_address;
776  for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
777  fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
778 
779  dmp_reg = &reg->u.isp2100.mailbox0;
780  for (cnt = 0; cnt < ha->mbx_count; cnt++) {
781  if (cnt == 8)
782  dmp_reg = &reg->u_end.isp2200.mailbox8;
783 
784  fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
785  }
786 
787  dmp_reg = &reg->u.isp2100.unused_2[0];
788  for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
789  fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
790 
791  WRT_REG_WORD(&reg->ctrl_status, 0x00);
792  dmp_reg = &reg->risc_hw;
793  for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
794  fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
795 
796  WRT_REG_WORD(&reg->pcr, 0x2000);
797  qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
798 
799  WRT_REG_WORD(&reg->pcr, 0x2100);
800  qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
801 
802  WRT_REG_WORD(&reg->pcr, 0x2200);
803  qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
804 
805  WRT_REG_WORD(&reg->pcr, 0x2300);
806  qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
807 
808  WRT_REG_WORD(&reg->pcr, 0x2400);
809  qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
810 
811  WRT_REG_WORD(&reg->pcr, 0x2500);
812  qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
813 
814  WRT_REG_WORD(&reg->pcr, 0x2600);
815  qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
816 
817  WRT_REG_WORD(&reg->pcr, 0x2700);
818  qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
819 
820  WRT_REG_WORD(&reg->ctrl_status, 0x10);
821  qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
822 
823  WRT_REG_WORD(&reg->ctrl_status, 0x20);
824  qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
825 
826  WRT_REG_WORD(&reg->ctrl_status, 0x30);
827  qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
828 
829  /* Reset the ISP. */
830  WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
831  }
832 
833  for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
834  rval == QLA_SUCCESS; cnt--) {
835  if (cnt)
836  udelay(100);
837  else
838  rval = QLA_FUNCTION_TIMEOUT;
839  }
840 
841  /* Pause RISC. */
842  if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
843  (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
844 
845  WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
846  for (cnt = 30000;
847  (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
848  rval == QLA_SUCCESS; cnt--) {
849  if (cnt)
850  udelay(100);
851  else
852  rval = QLA_FUNCTION_TIMEOUT;
853  }
854  if (rval == QLA_SUCCESS) {
855  /* Set memory configuration and timing. */
856  if (IS_QLA2100(ha))
857  WRT_REG_WORD(&reg->mctr, 0xf1);
858  else
859  WRT_REG_WORD(&reg->mctr, 0xf2);
860  RD_REG_WORD(&reg->mctr); /* PCI Posting. */
861 
862  /* Release RISC. */
863  WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
864  }
865  }
866 
867  if (rval == QLA_SUCCESS) {
868  /* Get RISC SRAM. */
869  risc_address = 0x1000;
870  WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
871  clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
872  }
873  for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
874  cnt++, risc_address++) {
875  WRT_MAILBOX_REG(ha, reg, 1, risc_address);
876  WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
877 
878  for (timer = 6000000; timer != 0; timer--) {
879  /* Check for pending interrupts. */
880  if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
881  if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
882  set_bit(MBX_INTERRUPT,
883  &ha->mbx_cmd_flags);
884 
885  mb0 = RD_MAILBOX_REG(ha, reg, 0);
886  mb2 = RD_MAILBOX_REG(ha, reg, 2);
887 
888  WRT_REG_WORD(&reg->semaphore, 0);
889  WRT_REG_WORD(&reg->hccr,
890  HCCR_CLR_RISC_INT);
891  RD_REG_WORD(&reg->hccr);
892  break;
893  }
894  WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
895  RD_REG_WORD(&reg->hccr);
896  }
897  udelay(5);
898  }
899 
900  if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
901  rval = mb0 & MBS_MASK;
902  fw->risc_ram[cnt] = htons(mb2);
903  } else {
904  rval = QLA_FUNCTION_FAILED;
905  }
906  }
907 
908  if (rval == QLA_SUCCESS)
909  qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
910 
911  qla2xxx_dump_post_process(base_vha, rval);
912 
913 qla2100_fw_dump_failed:
914  if (!hardware_locked)
915  spin_unlock_irqrestore(&ha->hardware_lock, flags);
916 }
917 
918 void
919 qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
920 {
921  int rval;
922  uint32_t cnt;
923  uint32_t risc_address;
924  struct qla_hw_data *ha = vha->hw;
925  struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
926  uint32_t __iomem *dmp_reg;
927  uint32_t *iter_reg;
928  uint16_t __iomem *mbx_reg;
929  unsigned long flags;
930  struct qla24xx_fw_dump *fw;
931  uint32_t ext_mem_cnt;
932  void *nxt;
933  void *nxt_chain;
934  uint32_t *last_chain = NULL;
935  struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
936 
937  if (IS_QLA82XX(ha))
938  return;
939 
940  risc_address = ext_mem_cnt = 0;
941  flags = 0;
942 
943  if (!hardware_locked)
944  spin_lock_irqsave(&ha->hardware_lock, flags);
945 
946  if (!ha->fw_dump) {
947  ql_log(ql_log_warn, vha, 0xd006,
948  "No buffer available for dump.\n");
949  goto qla24xx_fw_dump_failed;
950  }
951 
952  if (ha->fw_dumped) {
953  ql_log(ql_log_warn, vha, 0xd007,
954  "Firmware has been previously dumped (%p) "
955  "-- ignoring request.\n",
956  ha->fw_dump);
957  goto qla24xx_fw_dump_failed;
958  }
959  fw = &ha->fw_dump->isp.isp24;
960  qla2xxx_prep_dump(ha, ha->fw_dump);
961 
962  fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
963 
964  /* Pause RISC. */
965  rval = qla24xx_pause_risc(reg);
966  if (rval != QLA_SUCCESS)
967  goto qla24xx_fw_dump_failed_0;
968 
969  /* Host interface registers. */
970  dmp_reg = &reg->flash_addr;
971  for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
972  fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
973 
974  /* Disable interrupts. */
975  WRT_REG_DWORD(&reg->ictrl, 0);
976  RD_REG_DWORD(&reg->ictrl);
977 
978  /* Shadow registers. */
979  WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
980  RD_REG_DWORD(&reg->iobase_addr);
981  WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
982  fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
983 
984  WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
985  fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
986 
987  WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
988  fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
989 
990  WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
991  fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
992 
993  WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
994  fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
995 
996  WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
997  fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
998 
999  WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1000  fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1001 
1002  /* Mailbox registers. */
1003  mbx_reg = &reg->mailbox0;
1004  for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1005  fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1006 
1007  /* Transfer sequence registers. */
1008  iter_reg = fw->xseq_gp_reg;
1009  iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1010  iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1011  iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1012  iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1013  iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1014  iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1015  iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1016  qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1017 
1018  qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
1019  qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1020 
1021  /* Receive sequence registers. */
1022  iter_reg = fw->rseq_gp_reg;
1023  iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1024  iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1025  iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1026  iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1027  iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1028  iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1029  iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1030  qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1031 
1032  qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
1033  qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1034  qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1035 
1036  /* Command DMA registers. */
1037  qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1038 
1039  /* Queues. */
1040  iter_reg = fw->req0_dma_reg;
1041  iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1042  dmp_reg = &reg->iobase_q;
1043  for (cnt = 0; cnt < 7; cnt++)
1044  *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1045 
1046  iter_reg = fw->resp0_dma_reg;
1047  iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1048  dmp_reg = &reg->iobase_q;
1049  for (cnt = 0; cnt < 7; cnt++)
1050  *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1051 
1052  iter_reg = fw->req1_dma_reg;
1053  iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1054  dmp_reg = &reg->iobase_q;
1055  for (cnt = 0; cnt < 7; cnt++)
1056  *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1057 
1058  /* Transmit DMA registers. */
1059  iter_reg = fw->xmt0_dma_reg;
1060  iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1061  qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1062 
1063  iter_reg = fw->xmt1_dma_reg;
1064  iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1065  qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1066 
1067  iter_reg = fw->xmt2_dma_reg;
1068  iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1069  qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1070 
1071  iter_reg = fw->xmt3_dma_reg;
1072  iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1073  qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1074 
1075  iter_reg = fw->xmt4_dma_reg;
1076  iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1077  qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1078 
1079  qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1080 
1081  /* Receive DMA registers. */
1082  iter_reg = fw->rcvt0_data_dma_reg;
1083  iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1084  qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1085 
1086  iter_reg = fw->rcvt1_data_dma_reg;
1087  iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1088  qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1089 
1090  /* RISC registers. */
1091  iter_reg = fw->risc_gp_reg;
1092  iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1093  iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1094  iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1095  iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1096  iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1097  iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1098  iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1099  qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1100 
1101  /* Local memory controller registers. */
1102  iter_reg = fw->lmc_reg;
1103  iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1104  iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1105  iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1106  iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1107  iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1108  iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1109  qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1110 
1111  /* Fibre Protocol Module registers. */
1112  iter_reg = fw->fpm_hdw_reg;
1113  iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1114  iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1115  iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1116  iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1117  iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1118  iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1119  iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1120  iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1121  iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1122  iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1123  iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1124  qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1125 
1126  /* Frame Buffer registers. */
1127  iter_reg = fw->fb_hdw_reg;
1128  iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1129  iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1130  iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1131  iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1132  iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1133  iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1134  iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1135  iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1136  iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1137  iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1138  qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1139 
1140  rval = qla24xx_soft_reset(ha);
1141  if (rval != QLA_SUCCESS)
1142  goto qla24xx_fw_dump_failed_0;
1143 
1144  rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1145  &nxt);
1146  if (rval != QLA_SUCCESS)
1147  goto qla24xx_fw_dump_failed_0;
1148 
1149  nxt = qla2xxx_copy_queues(ha, nxt);
1150 
1151  qla24xx_copy_eft(ha, nxt);
1152 
1153  nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
1154  nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1155  if (last_chain) {
1156  ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1157  *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1158  }
1159 
1160  /* Adjust valid length. */
1161  ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1162 
1163 qla24xx_fw_dump_failed_0:
1164  qla2xxx_dump_post_process(base_vha, rval);
1165 
1166 qla24xx_fw_dump_failed:
1167  if (!hardware_locked)
1168  spin_unlock_irqrestore(&ha->hardware_lock, flags);
1169 }
1170 
1171 void
1172 qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1173 {
1174  int rval;
1175  uint32_t cnt;
1176  uint32_t risc_address;
1177  struct qla_hw_data *ha = vha->hw;
1178  struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1179  uint32_t __iomem *dmp_reg;
1180  uint32_t *iter_reg;
1181  uint16_t __iomem *mbx_reg;
1182  unsigned long flags;
1183  struct qla25xx_fw_dump *fw;
1184  uint32_t ext_mem_cnt;
1185  void *nxt, *nxt_chain;
1186  uint32_t *last_chain = NULL;
1187  struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1188 
1189  risc_address = ext_mem_cnt = 0;
1190  flags = 0;
1191 
1192  if (!hardware_locked)
1193  spin_lock_irqsave(&ha->hardware_lock, flags);
1194 
1195  if (!ha->fw_dump) {
1196  ql_log(ql_log_warn, vha, 0xd008,
1197  "No buffer available for dump.\n");
1198  goto qla25xx_fw_dump_failed;
1199  }
1200 
1201  if (ha->fw_dumped) {
1202  ql_log(ql_log_warn, vha, 0xd009,
1203  "Firmware has been previously dumped (%p) "
1204  "-- ignoring request.\n",
1205  ha->fw_dump);
1206  goto qla25xx_fw_dump_failed;
1207  }
1208  fw = &ha->fw_dump->isp.isp25;
1209  qla2xxx_prep_dump(ha, ha->fw_dump);
1210  ha->fw_dump->version = __constant_htonl(2);
1211 
1212  fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1213 
1214  /* Pause RISC. */
1215  rval = qla24xx_pause_risc(reg);
1216  if (rval != QLA_SUCCESS)
1217  goto qla25xx_fw_dump_failed_0;
1218 
1219  /* Host/Risc registers. */
1220  iter_reg = fw->host_risc_reg;
1221  iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1222  qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1223 
1224  /* PCIe registers. */
1225  WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1226  RD_REG_DWORD(&reg->iobase_addr);
1227  WRT_REG_DWORD(&reg->iobase_window, 0x01);
1228  dmp_reg = &reg->iobase_c4;
1229  fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1230  fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1231  fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1232  fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1233 
1234  WRT_REG_DWORD(&reg->iobase_window, 0x00);
1235  RD_REG_DWORD(&reg->iobase_window);
1236 
1237  /* Host interface registers. */
1238  dmp_reg = &reg->flash_addr;
1239  for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1240  fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1241 
1242  /* Disable interrupts. */
1243  WRT_REG_DWORD(&reg->ictrl, 0);
1244  RD_REG_DWORD(&reg->ictrl);
1245 
1246  /* Shadow registers. */
1247  WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1248  RD_REG_DWORD(&reg->iobase_addr);
1249  WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1250  fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1251 
1252  WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1253  fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1254 
1255  WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1256  fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1257 
1258  WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1259  fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1260 
1261  WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1262  fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1263 
1264  WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1265  fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1266 
1267  WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1268  fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1269 
1270  WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1271  fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1272 
1273  WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1274  fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1275 
1276  WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1277  fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1278 
1279  WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1280  fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1281 
1282  /* RISC I/O register. */
1283  WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1284  fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1285 
1286  /* Mailbox registers. */
1287  mbx_reg = &reg->mailbox0;
1288  for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1289  fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1290 
1291  /* Transfer sequence registers. */
1292  iter_reg = fw->xseq_gp_reg;
1293  iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1294  iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1295  iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1296  iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1297  iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1298  iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1299  iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1300  qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1301 
1302  iter_reg = fw->xseq_0_reg;
1303  iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1304  iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1305  qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1306 
1307  qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1308 
1309  /* Receive sequence registers. */
1310  iter_reg = fw->rseq_gp_reg;
1311  iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1312  iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1313  iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1314  iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1315  iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1316  iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1317  iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1318  qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1319 
1320  iter_reg = fw->rseq_0_reg;
1321  iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1322  qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1323 
1324  qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1325  qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1326 
1327  /* Auxiliary sequence registers. */
1328  iter_reg = fw->aseq_gp_reg;
1329  iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1330  iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1331  iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1332  iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1333  iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1334  iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1335  iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1336  qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1337 
1338  iter_reg = fw->aseq_0_reg;
1339  iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1340  qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1341 
1342  qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1343  qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1344 
1345  /* Command DMA registers. */
1346  qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1347 
1348  /* Queues. */
1349  iter_reg = fw->req0_dma_reg;
1350  iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1351  dmp_reg = &reg->iobase_q;
1352  for (cnt = 0; cnt < 7; cnt++)
1353  *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1354 
1355  iter_reg = fw->resp0_dma_reg;
1356  iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1357  dmp_reg = &reg->iobase_q;
1358  for (cnt = 0; cnt < 7; cnt++)
1359  *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1360 
1361  iter_reg = fw->req1_dma_reg;
1362  iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1363  dmp_reg = &reg->iobase_q;
1364  for (cnt = 0; cnt < 7; cnt++)
1365  *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1366 
1367  /* Transmit DMA registers. */
1368  iter_reg = fw->xmt0_dma_reg;
1369  iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1370  qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1371 
1372  iter_reg = fw->xmt1_dma_reg;
1373  iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1374  qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1375 
1376  iter_reg = fw->xmt2_dma_reg;
1377  iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1378  qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1379 
1380  iter_reg = fw->xmt3_dma_reg;
1381  iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1382  qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1383 
1384  iter_reg = fw->xmt4_dma_reg;
1385  iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1386  qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1387 
1388  qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1389 
1390  /* Receive DMA registers. */
1391  iter_reg = fw->rcvt0_data_dma_reg;
1392  iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1393  qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1394 
1395  iter_reg = fw->rcvt1_data_dma_reg;
1396  iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1397  qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1398 
1399  /* RISC registers. */
1400  iter_reg = fw->risc_gp_reg;
1401  iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1402  iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1403  iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1404  iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1405  iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1406  iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1407  iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1408  qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1409 
1410  /* Local memory controller registers. */
1411  iter_reg = fw->lmc_reg;
1412  iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1413  iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1414  iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1415  iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1416  iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1417  iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1418  iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1419  qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1420 
1421  /* Fibre Protocol Module registers. */
1422  iter_reg = fw->fpm_hdw_reg;
1423  iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1424  iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1425  iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1426  iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1427  iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1428  iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1429  iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1430  iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1431  iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1432  iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1433  iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1434  qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1435 
1436  /* Frame Buffer registers. */
1437  iter_reg = fw->fb_hdw_reg;
1438  iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1439  iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1440  iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1441  iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1442  iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1443  iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1444  iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1445  iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1446  iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1447  iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1448  iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1449  qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1450 
1451  /* Multi queue registers */
1452  nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1453  &last_chain);
1454 
1455  rval = qla24xx_soft_reset(ha);
1456  if (rval != QLA_SUCCESS)
1457  goto qla25xx_fw_dump_failed_0;
1458 
1459  rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1460  &nxt);
1461  if (rval != QLA_SUCCESS)
1462  goto qla25xx_fw_dump_failed_0;
1463 
1464  nxt = qla2xxx_copy_queues(ha, nxt);
1465 
1466  nxt = qla24xx_copy_eft(ha, nxt);
1467 
1468  /* Chain entries -- started with MQ. */
1469  nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1470  nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
1471  nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1472  if (last_chain) {
1473  ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1474  *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1475  }
1476 
1477  /* Adjust valid length. */
1478  ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1479 
1480 qla25xx_fw_dump_failed_0:
1481  qla2xxx_dump_post_process(base_vha, rval);
1482 
1483 qla25xx_fw_dump_failed:
1484  if (!hardware_locked)
1485  spin_unlock_irqrestore(&ha->hardware_lock, flags);
1486 }
1487 
1488 void
1489 qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1490 {
1491  int rval;
1492  uint32_t cnt;
1493  uint32_t risc_address;
1494  struct qla_hw_data *ha = vha->hw;
1495  struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1496  uint32_t __iomem *dmp_reg;
1497  uint32_t *iter_reg;
1498  uint16_t __iomem *mbx_reg;
1499  unsigned long flags;
1500  struct qla81xx_fw_dump *fw;
1501  uint32_t ext_mem_cnt;
1502  void *nxt, *nxt_chain;
1503  uint32_t *last_chain = NULL;
1504  struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1505 
1506  risc_address = ext_mem_cnt = 0;
1507  flags = 0;
1508 
1509  if (!hardware_locked)
1510  spin_lock_irqsave(&ha->hardware_lock, flags);
1511 
1512  if (!ha->fw_dump) {
1513  ql_log(ql_log_warn, vha, 0xd00a,
1514  "No buffer available for dump.\n");
1515  goto qla81xx_fw_dump_failed;
1516  }
1517 
1518  if (ha->fw_dumped) {
1519  ql_log(ql_log_warn, vha, 0xd00b,
1520  "Firmware has been previously dumped (%p) "
1521  "-- ignoring request.\n",
1522  ha->fw_dump);
1523  goto qla81xx_fw_dump_failed;
1524  }
1525  fw = &ha->fw_dump->isp.isp81;
1526  qla2xxx_prep_dump(ha, ha->fw_dump);
1527 
1528  fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1529 
1530  /* Pause RISC. */
1531  rval = qla24xx_pause_risc(reg);
1532  if (rval != QLA_SUCCESS)
1533  goto qla81xx_fw_dump_failed_0;
1534 
1535  /* Host/Risc registers. */
1536  iter_reg = fw->host_risc_reg;
1537  iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1538  qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1539 
1540  /* PCIe registers. */
1541  WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1542  RD_REG_DWORD(&reg->iobase_addr);
1543  WRT_REG_DWORD(&reg->iobase_window, 0x01);
1544  dmp_reg = &reg->iobase_c4;
1545  fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1546  fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1547  fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1548  fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1549 
1550  WRT_REG_DWORD(&reg->iobase_window, 0x00);
1551  RD_REG_DWORD(&reg->iobase_window);
1552 
1553  /* Host interface registers. */
1554  dmp_reg = &reg->flash_addr;
1555  for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1556  fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1557 
1558  /* Disable interrupts. */
1559  WRT_REG_DWORD(&reg->ictrl, 0);
1560  RD_REG_DWORD(&reg->ictrl);
1561 
1562  /* Shadow registers. */
1563  WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1564  RD_REG_DWORD(&reg->iobase_addr);
1565  WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1566  fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1567 
1568  WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1569  fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1570 
1571  WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1572  fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1573 
1574  WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1575  fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1576 
1577  WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1578  fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1579 
1580  WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1581  fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1582 
1583  WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1584  fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1585 
1586  WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1587  fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1588 
1589  WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1590  fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1591 
1592  WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1593  fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1594 
1595  WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1596  fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1597 
1598  /* RISC I/O register. */
1599  WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1600  fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1601 
1602  /* Mailbox registers. */
1603  mbx_reg = &reg->mailbox0;
1604  for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1605  fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1606 
1607  /* Transfer sequence registers. */
1608  iter_reg = fw->xseq_gp_reg;
1609  iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1610  iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1611  iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1612  iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1613  iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1614  iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1615  iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1616  qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1617 
1618  iter_reg = fw->xseq_0_reg;
1619  iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1620  iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1621  qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1622 
1623  qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1624 
1625  /* Receive sequence registers. */
1626  iter_reg = fw->rseq_gp_reg;
1627  iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1628  iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1629  iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1630  iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1631  iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1632  iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1633  iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1634  qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1635 
1636  iter_reg = fw->rseq_0_reg;
1637  iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1638  qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1639 
1640  qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1641  qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1642 
1643  /* Auxiliary sequence registers. */
1644  iter_reg = fw->aseq_gp_reg;
1645  iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1646  iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1647  iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1648  iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1649  iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1650  iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1651  iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1652  qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1653 
1654  iter_reg = fw->aseq_0_reg;
1655  iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1656  qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1657 
1658  qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1659  qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1660 
1661  /* Command DMA registers. */
1662  qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1663 
1664  /* Queues. */
1665  iter_reg = fw->req0_dma_reg;
1666  iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1667  dmp_reg = &reg->iobase_q;
1668  for (cnt = 0; cnt < 7; cnt++)
1669  *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1670 
1671  iter_reg = fw->resp0_dma_reg;
1672  iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1673  dmp_reg = &reg->iobase_q;
1674  for (cnt = 0; cnt < 7; cnt++)
1675  *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1676 
1677  iter_reg = fw->req1_dma_reg;
1678  iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1679  dmp_reg = &reg->iobase_q;
1680  for (cnt = 0; cnt < 7; cnt++)
1681  *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1682 
1683  /* Transmit DMA registers. */
1684  iter_reg = fw->xmt0_dma_reg;
1685  iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1686  qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1687 
1688  iter_reg = fw->xmt1_dma_reg;
1689  iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1690  qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1691 
1692  iter_reg = fw->xmt2_dma_reg;
1693  iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1694  qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1695 
1696  iter_reg = fw->xmt3_dma_reg;
1697  iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1698  qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1699 
1700  iter_reg = fw->xmt4_dma_reg;
1701  iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1702  qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1703 
1704  qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1705 
1706  /* Receive DMA registers. */
1707  iter_reg = fw->rcvt0_data_dma_reg;
1708  iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1709  qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1710 
1711  iter_reg = fw->rcvt1_data_dma_reg;
1712  iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1713  qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1714 
1715  /* RISC registers. */
1716  iter_reg = fw->risc_gp_reg;
1717  iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1718  iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1719  iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1720  iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1721  iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1722  iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1723  iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1724  qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1725 
1726  /* Local memory controller registers. */
1727  iter_reg = fw->lmc_reg;
1728  iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1729  iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1730  iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1731  iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1732  iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1733  iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1734  iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1735  qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1736 
1737  /* Fibre Protocol Module registers. */
1738  iter_reg = fw->fpm_hdw_reg;
1739  iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1740  iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1741  iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1742  iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1743  iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1744  iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1745  iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1746  iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1747  iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1748  iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1749  iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1750  iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1751  iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1752  qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1753 
1754  /* Frame Buffer registers. */
1755  iter_reg = fw->fb_hdw_reg;
1756  iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1757  iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1758  iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1759  iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1760  iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1761  iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1762  iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1763  iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1764  iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1765  iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1766  iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1767  iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1768  qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1769 
1770  /* Multi queue registers */
1771  nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1772  &last_chain);
1773 
1774  rval = qla24xx_soft_reset(ha);
1775  if (rval != QLA_SUCCESS)
1776  goto qla81xx_fw_dump_failed_0;
1777 
1778  rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1779  &nxt);
1780  if (rval != QLA_SUCCESS)
1781  goto qla81xx_fw_dump_failed_0;
1782 
1783  nxt = qla2xxx_copy_queues(ha, nxt);
1784 
1785  nxt = qla24xx_copy_eft(ha, nxt);
1786 
1787  /* Chain entries -- started with MQ. */
1788  nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1789  nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
1790  nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1791  if (last_chain) {
1792  ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1793  *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1794  }
1795 
1796  /* Adjust valid length. */
1797  ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1798 
1799 qla81xx_fw_dump_failed_0:
1800  qla2xxx_dump_post_process(base_vha, rval);
1801 
1802 qla81xx_fw_dump_failed:
1803  if (!hardware_locked)
1804  spin_unlock_irqrestore(&ha->hardware_lock, flags);
1805 }
1806 
1807 void
1808 qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1809 {
1810  int rval;
1811  uint32_t cnt, reg_data;
1812  uint32_t risc_address;
1813  struct qla_hw_data *ha = vha->hw;
1814  struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1815  uint32_t __iomem *dmp_reg;
1816  uint32_t *iter_reg;
1817  uint16_t __iomem *mbx_reg;
1818  unsigned long flags;
1819  struct qla83xx_fw_dump *fw;
1820  uint32_t ext_mem_cnt;
1821  void *nxt, *nxt_chain;
1822  uint32_t *last_chain = NULL;
1823  struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1824 
1825  risc_address = ext_mem_cnt = 0;
1826  flags = 0;
1827 
1828  if (!hardware_locked)
1829  spin_lock_irqsave(&ha->hardware_lock, flags);
1830 
1831  if (!ha->fw_dump) {
1832  ql_log(ql_log_warn, vha, 0xd00c,
1833  "No buffer available for dump!!!\n");
1834  goto qla83xx_fw_dump_failed;
1835  }
1836 
1837  if (ha->fw_dumped) {
1838  ql_log(ql_log_warn, vha, 0xd00d,
1839  "Firmware has been previously dumped (%p) -- ignoring "
1840  "request...\n", ha->fw_dump);
1841  goto qla83xx_fw_dump_failed;
1842  }
1843  fw = &ha->fw_dump->isp.isp83;
1844  qla2xxx_prep_dump(ha, ha->fw_dump);
1845 
1846  fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1847 
1848  /* Pause RISC. */
1849  rval = qla24xx_pause_risc(reg);
1850  if (rval != QLA_SUCCESS)
1851  goto qla83xx_fw_dump_failed_0;
1852 
1853  WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1854  dmp_reg = &reg->iobase_window;
1855  reg_data = RD_REG_DWORD(dmp_reg);
1856  WRT_REG_DWORD(dmp_reg, 0);
1857 
1858  dmp_reg = &reg->unused_4_1[0];
1859  reg_data = RD_REG_DWORD(dmp_reg);
1860  WRT_REG_DWORD(dmp_reg, 0);
1861 
1862  WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1863  dmp_reg = &reg->unused_4_1[2];
1864  reg_data = RD_REG_DWORD(dmp_reg);
1865  WRT_REG_DWORD(dmp_reg, 0);
1866 
1867  /* select PCR and disable ecc checking and correction */
1868  WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1869  RD_REG_DWORD(&reg->iobase_addr);
1870  WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
1871 
1872  /* Host/Risc registers. */
1873  iter_reg = fw->host_risc_reg;
1874  iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1875  iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1876  qla24xx_read_window(reg, 0x7040, 16, iter_reg);
1877 
1878  /* PCIe registers. */
1879  WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1880  RD_REG_DWORD(&reg->iobase_addr);
1881  WRT_REG_DWORD(&reg->iobase_window, 0x01);
1882  dmp_reg = &reg->iobase_c4;
1883  fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1884  fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1885  fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1886  fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1887 
1888  WRT_REG_DWORD(&reg->iobase_window, 0x00);
1889  RD_REG_DWORD(&reg->iobase_window);
1890 
1891  /* Host interface registers. */
1892  dmp_reg = &reg->flash_addr;
1893  for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1894  fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1895 
1896  /* Disable interrupts. */
1897  WRT_REG_DWORD(&reg->ictrl, 0);
1898  RD_REG_DWORD(&reg->ictrl);
1899 
1900  /* Shadow registers. */
1901  WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1902  RD_REG_DWORD(&reg->iobase_addr);
1903  WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1904  fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1905 
1906  WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1907  fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1908 
1909  WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1910  fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1911 
1912  WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1913  fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1914 
1915  WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1916  fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1917 
1918  WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1919  fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1920 
1921  WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1922  fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1923 
1924  WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1925  fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1926 
1927  WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1928  fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1929 
1930  WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1931  fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1932 
1933  WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1934  fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1935 
1936  /* RISC I/O register. */
1937  WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1938  fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1939 
1940  /* Mailbox registers. */
1941  mbx_reg = &reg->mailbox0;
1942  for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1943  fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1944 
1945  /* Transfer sequence registers. */
1946  iter_reg = fw->xseq_gp_reg;
1947  iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
1948  iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
1949  iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
1950  iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
1951  iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
1952  iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
1953  iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
1954  iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
1955  iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1956  iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1957  iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1958  iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1959  iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1960  iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1961  iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1962  qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1963 
1964  iter_reg = fw->xseq_0_reg;
1965  iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1966  iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1967  qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1968 
1969  qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1970 
1971  qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
1972 
1973  /* Receive sequence registers. */
1974  iter_reg = fw->rseq_gp_reg;
1975  iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
1976  iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
1977  iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
1978  iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
1979  iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
1980  iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
1981  iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
1982  iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
1983  iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1984  iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1985  iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1986  iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1987  iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1988  iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1989  iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1990  qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1991 
1992  iter_reg = fw->rseq_0_reg;
1993  iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1994  qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1995 
1996  qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1997  qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1998  qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
1999 
2000  /* Auxiliary sequence registers. */
2001  iter_reg = fw->aseq_gp_reg;
2002  iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
2003  iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
2004  iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
2005  iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
2006  iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
2007  iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
2008  iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
2009  iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
2010  iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
2011  iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
2012  iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
2013  iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
2014  iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
2015  iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
2016  iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
2017  qla24xx_read_window(reg, 0xB170, 16, iter_reg);
2018 
2019  iter_reg = fw->aseq_0_reg;
2020  iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
2021  qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
2022 
2023  qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
2024  qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
2025  qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
2026 
2027  /* Command DMA registers. */
2028  iter_reg = fw->cmd_dma_reg;
2029  iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
2030  iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
2031  iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
2032  qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
2033 
2034  /* Queues. */
2035  iter_reg = fw->req0_dma_reg;
2036  iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
2037  dmp_reg = &reg->iobase_q;
2038  for (cnt = 0; cnt < 7; cnt++)
2039  *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2040 
2041  iter_reg = fw->resp0_dma_reg;
2042  iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
2043  dmp_reg = &reg->iobase_q;
2044  for (cnt = 0; cnt < 7; cnt++)
2045  *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2046 
2047  iter_reg = fw->req1_dma_reg;
2048  iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
2049  dmp_reg = &reg->iobase_q;
2050  for (cnt = 0; cnt < 7; cnt++)
2051  *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2052 
2053  /* Transmit DMA registers. */
2054  iter_reg = fw->xmt0_dma_reg;
2055  iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
2056  qla24xx_read_window(reg, 0x7610, 16, iter_reg);
2057 
2058  iter_reg = fw->xmt1_dma_reg;
2059  iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
2060  qla24xx_read_window(reg, 0x7630, 16, iter_reg);
2061 
2062  iter_reg = fw->xmt2_dma_reg;
2063  iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
2064  qla24xx_read_window(reg, 0x7650, 16, iter_reg);
2065 
2066  iter_reg = fw->xmt3_dma_reg;
2067  iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
2068  qla24xx_read_window(reg, 0x7670, 16, iter_reg);
2069 
2070  iter_reg = fw->xmt4_dma_reg;
2071  iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
2072  qla24xx_read_window(reg, 0x7690, 16, iter_reg);
2073 
2074  qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
2075 
2076  /* Receive DMA registers. */
2077  iter_reg = fw->rcvt0_data_dma_reg;
2078  iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
2079  qla24xx_read_window(reg, 0x7710, 16, iter_reg);
2080 
2081  iter_reg = fw->rcvt1_data_dma_reg;
2082  iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
2083  qla24xx_read_window(reg, 0x7730, 16, iter_reg);
2084 
2085  /* RISC registers. */
2086  iter_reg = fw->risc_gp_reg;
2087  iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
2088  iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
2089  iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
2090  iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
2091  iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
2092  iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
2093  iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
2094  qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
2095 
2096  /* Local memory controller registers. */
2097  iter_reg = fw->lmc_reg;
2098  iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
2099  iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
2100  iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
2101  iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
2102  iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
2103  iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
2104  iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
2105  qla24xx_read_window(reg, 0x3070, 16, iter_reg);
2106 
2107  /* Fibre Protocol Module registers. */
2108  iter_reg = fw->fpm_hdw_reg;
2109  iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
2110  iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
2111  iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
2112  iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
2113  iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
2114  iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
2115  iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
2116  iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
2117  iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
2118  iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
2119  iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
2120  iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
2121  iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
2122  iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
2123  iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
2124  qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
2125 
2126  /* RQ0 Array registers. */
2127  iter_reg = fw->rq0_array_reg;
2128  iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
2129  iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
2130  iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
2131  iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
2132  iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
2133  iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
2134  iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
2135  iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
2136  iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
2137  iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
2138  iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
2139  iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
2140  iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
2141  iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
2142  iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
2143  qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
2144 
2145  /* RQ1 Array registers. */
2146  iter_reg = fw->rq1_array_reg;
2147  iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
2148  iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
2149  iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
2150  iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
2151  iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
2152  iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
2153  iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
2154  iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
2155  iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
2156  iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
2157  iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
2158  iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
2159  iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
2160  iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
2161  iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
2162  qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
2163 
2164  /* RP0 Array registers. */
2165  iter_reg = fw->rp0_array_reg;
2166  iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
2167  iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
2168  iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
2169  iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
2170  iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
2171  iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
2172  iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
2173  iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
2174  iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
2175  iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
2176  iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
2177  iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
2178  iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
2179  iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
2180  iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
2181  qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
2182 
2183  /* RP1 Array registers. */
2184  iter_reg = fw->rp1_array_reg;
2185  iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
2186  iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
2187  iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
2188  iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
2189  iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
2190  iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
2191  iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
2192  iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
2193  iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
2194  iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
2195  iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
2196  iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
2197  iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
2198  iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
2199  iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
2200  qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
2201 
2202  iter_reg = fw->at0_array_reg;
2203  iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
2204  iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
2205  iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
2206  iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
2207  iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
2208  iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
2209  iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
2210  qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
2211 
2212  /* I/O Queue Control registers. */
2213  qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
2214 
2215  /* Frame Buffer registers. */
2216  iter_reg = fw->fb_hdw_reg;
2217  iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
2218  iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
2219  iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
2220  iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
2221  iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
2222  iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
2223  iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
2224  iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
2225  iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
2226  iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
2227  iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
2228  iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
2229  iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
2230  iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
2231  iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
2232  iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
2233  iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
2234  iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
2235  iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
2236  iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
2237  iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
2238  iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
2239  iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
2240  iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
2241  iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
2242  iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
2243  qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
2244 
2245  /* Multi queue registers */
2246  nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
2247  &last_chain);
2248 
2249  rval = qla24xx_soft_reset(ha);
2250  if (rval != QLA_SUCCESS) {
2251  ql_log(ql_log_warn, vha, 0xd00e,
2252  "SOFT RESET FAILED, forcing continuation of dump!!!\n");
2253  rval = QLA_SUCCESS;
2254 
2255  ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
2256 
2257  WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2258  RD_REG_DWORD(&reg->hccr);
2259 
2260  WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2261  RD_REG_DWORD(&reg->hccr);
2262 
2263  WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2264  RD_REG_DWORD(&reg->hccr);
2265 
2266  for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
2267  udelay(5);
2268 
2269  if (!cnt) {
2270  nxt = fw->code_ram;
2271  nxt += sizeof(fw->code_ram),
2272  nxt += (ha->fw_memory_size - 0x100000 + 1);
2273  goto copy_queue;
2274  } else
2275  ql_log(ql_log_warn, vha, 0xd010,
2276  "bigger hammer success?\n");
2277  }
2278 
2279  rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
2280  &nxt);
2281  if (rval != QLA_SUCCESS)
2282  goto qla83xx_fw_dump_failed_0;
2283 
2284 copy_queue:
2285  nxt = qla2xxx_copy_queues(ha, nxt);
2286 
2287  nxt = qla24xx_copy_eft(ha, nxt);
2288 
2289  /* Chain entries -- started with MQ. */
2290  nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
2291  nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2292  nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
2293  if (last_chain) {
2294  ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
2295  *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
2296  }
2297 
2298  /* Adjust valid length. */
2299  ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
2300 
2301 qla83xx_fw_dump_failed_0:
2302  qla2xxx_dump_post_process(base_vha, rval);
2303 
2304 qla83xx_fw_dump_failed:
2305  if (!hardware_locked)
2306  spin_unlock_irqrestore(&ha->hardware_lock, flags);
2307 }
2308 
2309 /****************************************************************************/
2310 /* Driver Debug Functions. */
2311 /****************************************************************************/
2312 
2313 static inline int
2314 ql_mask_match(uint32_t level)
2315 {
2316  if (ql2xextended_error_logging == 1)
2317  ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2318  return (level & ql2xextended_error_logging) == level;
2319 }
2320 
2321 /*
2322  * This function is for formatting and logging debug information.
2323  * It is to be used when vha is available. It formats the message
2324  * and logs it to the messages file.
2325  * parameters:
2326  * level: The level of the debug messages to be printed.
2327  * If ql2xextended_error_logging value is correctly set,
2328  * this message will appear in the messages file.
2329  * vha: Pointer to the scsi_qla_host_t.
2330  * id: This is a unique identifier for the level. It identifies the
2331  * part of the code from where the message originated.
2332  * msg: The message to be displayed.
2333  */
2334 void
2335 ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2336 {
2337  va_list va;
2338  struct va_format vaf;
2339 
2340  if (!ql_mask_match(level))
2341  return;
2342 
2343  va_start(va, fmt);
2344 
2345  vaf.fmt = fmt;
2346  vaf.va = &va;
2347 
2348  if (vha != NULL) {
2349  const struct pci_dev *pdev = vha->hw->pdev;
2350  /* <module-name> <pci-name> <msg-id>:<host> Message */
2351  pr_warn("%s [%s]-%04x:%ld: %pV",
2352  QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
2353  vha->host_no, &vaf);
2354  } else {
2355  pr_warn("%s [%s]-%04x: : %pV",
2356  QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
2357  }
2358 
2359  va_end(va);
2360 
2361 }
2362 
2363 /*
2364  * This function is for formatting and logging debug information.
2365  * It is to be used when vha is not available and pci is available,
2366  * i.e., before host allocation. It formats the message and logs it
2367  * to the messages file.
2368  * parameters:
2369  * level: The level of the debug messages to be printed.
2370  * If ql2xextended_error_logging value is correctly set,
2371  * this message will appear in the messages file.
2372  * pdev: Pointer to the struct pci_dev.
2373  * id: This is a unique id for the level. It identifies the part
2374  * of the code from where the message originated.
2375  * msg: The message to be displayed.
2376  */
2377 void
2378 ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2379  const char *fmt, ...)
2380 {
2381  va_list va;
2382  struct va_format vaf;
2383 
2384  if (pdev == NULL)
2385  return;
2386  if (!ql_mask_match(level))
2387  return;
2388 
2389  va_start(va, fmt);
2390 
2391  vaf.fmt = fmt;
2392  vaf.va = &va;
2393 
2394  /* <module-name> <dev-name>:<msg-id> Message */
2395  pr_warn("%s [%s]-%04x: : %pV",
2396  QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
2397 
2398  va_end(va);
2399 }
2400 
2401 /*
2402  * This function is for formatting and logging log messages.
2403  * It is to be used when vha is available. It formats the message
2404  * and logs it to the messages file. All the messages will be logged
2405  * irrespective of value of ql2xextended_error_logging.
2406  * parameters:
2407  * level: The level of the log messages to be printed in the
2408  * messages file.
2409  * vha: Pointer to the scsi_qla_host_t
2410  * id: This is a unique id for the level. It identifies the
2411  * part of the code from where the message originated.
2412  * msg: The message to be displayed.
2413  */
2414 void
2415 ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2416 {
2417  va_list va;
2418  struct va_format vaf;
2419  char pbuf[128];
2420 
2421  if (level > ql_errlev)
2422  return;
2423 
2424  if (vha != NULL) {
2425  const struct pci_dev *pdev = vha->hw->pdev;
2426  /* <module-name> <msg-id>:<host> Message */
2427  snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
2428  QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
2429  } else {
2430  snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2431  QL_MSGHDR, "0000:00:00.0", id);
2432  }
2433  pbuf[sizeof(pbuf) - 1] = 0;
2434 
2435  va_start(va, fmt);
2436 
2437  vaf.fmt = fmt;
2438  vaf.va = &va;
2439 
2440  switch (level) {
2441  case ql_log_fatal: /* FATAL LOG */
2442  pr_crit("%s%pV", pbuf, &vaf);
2443  break;
2444  case ql_log_warn:
2445  pr_err("%s%pV", pbuf, &vaf);
2446  break;
2447  case ql_log_info:
2448  pr_warn("%s%pV", pbuf, &vaf);
2449  break;
2450  default:
2451  pr_info("%s%pV", pbuf, &vaf);
2452  break;
2453  }
2454 
2455  va_end(va);
2456 }
2457 
2458 /*
2459  * This function is for formatting and logging log messages.
2460  * It is to be used when vha is not available and pci is available,
2461  * i.e., before host allocation. It formats the message and logs
2462  * it to the messages file. All the messages are logged irrespective
2463  * of the value of ql2xextended_error_logging.
2464  * parameters:
2465  * level: The level of the log messages to be printed in the
2466  * messages file.
2467  * pdev: Pointer to the struct pci_dev.
2468  * id: This is a unique id for the level. It identifies the
2469  * part of the code from where the message originated.
2470  * msg: The message to be displayed.
2471  */
2472 void
2473 ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2474  const char *fmt, ...)
2475 {
2476  va_list va;
2477  struct va_format vaf;
2478  char pbuf[128];
2479 
2480  if (pdev == NULL)
2481  return;
2482  if (level > ql_errlev)
2483  return;
2484 
2485  /* <module-name> <dev-name>:<msg-id> Message */
2486  snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2487  QL_MSGHDR, dev_name(&(pdev->dev)), id);
2488  pbuf[sizeof(pbuf) - 1] = 0;
2489 
2490  va_start(va, fmt);
2491 
2492  vaf.fmt = fmt;
2493  vaf.va = &va;
2494 
2495  switch (level) {
2496  case ql_log_fatal: /* FATAL LOG */
2497  pr_crit("%s%pV", pbuf, &vaf);
2498  break;
2499  case ql_log_warn:
2500  pr_err("%s%pV", pbuf, &vaf);
2501  break;
2502  case ql_log_info:
2503  pr_warn("%s%pV", pbuf, &vaf);
2504  break;
2505  default:
2506  pr_info("%s%pV", pbuf, &vaf);
2507  break;
2508  }
2509 
2510  va_end(va);
2511 }
2512 
2513 void
2514 ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
2515 {
2516  int i;
2517  struct qla_hw_data *ha = vha->hw;
2518  struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2519  struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
2520  struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
2521  uint16_t __iomem *mbx_reg;
2522 
2523  if (!ql_mask_match(level))
2524  return;
2525 
2526  if (IS_QLA82XX(ha))
2527  mbx_reg = &reg82->mailbox_in[0];
2528  else if (IS_FWI2_CAPABLE(ha))
2529  mbx_reg = &reg24->mailbox0;
2530  else
2531  mbx_reg = MAILBOX_REG(ha, reg, 0);
2532 
2533  ql_dbg(level, vha, id, "Mailbox registers:\n");
2534  for (i = 0; i < 6; i++)
2535  ql_dbg(level, vha, id,
2536  "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
2537 }
2538 
2539 
2540 void
2541 ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
2542  uint8_t *b, uint32_t size)
2543 {
2544  uint32_t cnt;
2545  uint8_t c;
2546 
2547  if (!ql_mask_match(level))
2548  return;
2549 
2550  ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
2551  "9 Ah Bh Ch Dh Eh Fh\n");
2552  ql_dbg(level, vha, id, "----------------------------------"
2553  "----------------------------\n");
2554 
2555  ql_dbg(level, vha, id, " ");
2556  for (cnt = 0; cnt < size;) {
2557  c = *b++;
2558  printk("%02x", (uint32_t) c);
2559  cnt++;
2560  if (!(cnt % 16))
2561  printk("\n");
2562  else
2563  printk(" ");
2564  }
2565  if (cnt % 16)
2566  ql_dbg(level, vha, id, "\n");
2567 }
Generated on Thu Jan 10 2013 14:23:32 for Linux Kernel by   doxygen 1.8.2