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qla_def.h
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1 /*
2  * QLogic Fibre Channel HBA Driver
3  * Copyright (c) 2003-2012 QLogic Corporation
4  *
5  * See LICENSE.qla2xxx for copyright and licensing details.
6  */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9 
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28 
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34 #include <scsi/scsi_bsg_fc.h>
35 
36 #include "qla_bsg.h"
37 #include "qla_nx.h"
38 #define QLA2XXX_DRIVER_NAME "qla2xxx"
39 #define QLA2XXX_APIDEV "ql2xapidev"
40 
41 /*
42  * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
43  * but that's fine as we don't look at the last 24 ones for
44  * ISP2100 HBAs.
45  */
46 #define MAILBOX_REGISTER_COUNT_2100 8
47 #define MAILBOX_REGISTER_COUNT_2200 24
48 #define MAILBOX_REGISTER_COUNT 32
49 
50 #define QLA2200A_RISC_ROM_VER 4
51 #define FPM_2300 6
52 #define FPM_2310 7
53 
54 #include "qla_settings.h"
55 
56 /*
57  * Data bit definitions
58  */
59 #define BIT_0 0x1
60 #define BIT_1 0x2
61 #define BIT_2 0x4
62 #define BIT_3 0x8
63 #define BIT_4 0x10
64 #define BIT_5 0x20
65 #define BIT_6 0x40
66 #define BIT_7 0x80
67 #define BIT_8 0x100
68 #define BIT_9 0x200
69 #define BIT_10 0x400
70 #define BIT_11 0x800
71 #define BIT_12 0x1000
72 #define BIT_13 0x2000
73 #define BIT_14 0x4000
74 #define BIT_15 0x8000
75 #define BIT_16 0x10000
76 #define BIT_17 0x20000
77 #define BIT_18 0x40000
78 #define BIT_19 0x80000
79 #define BIT_20 0x100000
80 #define BIT_21 0x200000
81 #define BIT_22 0x400000
82 #define BIT_23 0x800000
83 #define BIT_24 0x1000000
84 #define BIT_25 0x2000000
85 #define BIT_26 0x4000000
86 #define BIT_27 0x8000000
87 #define BIT_28 0x10000000
88 #define BIT_29 0x20000000
89 #define BIT_30 0x40000000
90 #define BIT_31 0x80000000
91 
92 #define LSB(x) ((uint8_t)(x))
93 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
94 
95 #define LSW(x) ((uint16_t)(x))
96 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
97 
98 #define LSD(x) ((uint32_t)((uint64_t)(x)))
99 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
100 
101 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
102 
103 /*
104  * I/O register
105 */
106 
107 #define RD_REG_BYTE(addr) readb(addr)
108 #define RD_REG_WORD(addr) readw(addr)
109 #define RD_REG_DWORD(addr) readl(addr)
110 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
111 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
112 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
113 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
114 #define WRT_REG_WORD(addr, data) writew(data,addr)
115 #define WRT_REG_DWORD(addr, data) writel(data,addr)
116 
117 /*
118  * ISP83XX specific remote register addresses
119  */
120 #define QLA83XX_LED_PORT0 0x00201320
121 #define QLA83XX_LED_PORT1 0x00201328
122 #define QLA83XX_IDC_DEV_STATE 0x22102384
123 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
124 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
125 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
126 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
127 #define QLA83XX_IDC_CONTROL 0x22102390
128 #define QLA83XX_IDC_AUDIT 0x22102394
129 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
130 #define QLA83XX_DRIVER_LOCKID 0x22102104
131 #define QLA83XX_DRIVER_LOCK 0x8111c028
132 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
133 #define QLA83XX_FLASH_LOCKID 0x22102100
134 #define QLA83XX_FLASH_LOCK 0x8111c010
135 #define QLA83XX_FLASH_UNLOCK 0x8111c014
136 #define QLA83XX_DEV_PARTINFO1 0x221023e0
137 #define QLA83XX_DEV_PARTINFO2 0x221023e4
138 #define QLA83XX_FW_HEARTBEAT 0x221020b0
139 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
140 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
141 
142 /* 83XX: Macros defining 8200 AEN Reason codes */
143 #define IDC_DEVICE_STATE_CHANGE BIT_0
144 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
145 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
146 #define IDC_HEARTBEAT_FAILURE BIT_3
147 
148 /* 83XX: Macros defining 8200 AEN Error-levels */
149 #define ERR_LEVEL_NON_FATAL 0x1
150 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
151 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
152 
153 /* 83XX: Macros for IDC Version */
154 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
155 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
156 
157 /* 83XX: Macros for scheduling dpc tasks */
158 #define QLA83XX_NIC_CORE_RESET 0x1
159 #define QLA83XX_IDC_STATE_HANDLER 0x2
160 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
161 
162 /* 83XX: Macros for defining IDC-Control bits */
163 #define QLA83XX_IDC_RESET_DISABLED BIT_0
164 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
165 
166 /* 83XX: Macros for different timeouts */
167 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
168 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
169 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
170 
171 /* 83XX: Macros for defining class in DEV-Partition Info register */
172 #define QLA83XX_CLASS_TYPE_NONE 0x0
173 #define QLA83XX_CLASS_TYPE_NIC 0x1
174 #define QLA83XX_CLASS_TYPE_FCOE 0x2
175 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
176 
177 /* 83XX: Macros for IDC Lock-Recovery stages */
178 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
179  * lock-recovery
180  */
181 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
182 
183 /* 83XX: Macros for IDC Audit type */
184 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
185  * dev-state change to NEED-RESET
186  * or NEED-QUIESCENT
187  */
188 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
189  * reset-recovery completion is
190  * second
191  */
192 
193 /*
194  * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
195  * 133Mhz slot.
196  */
197 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
198 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
199 
200 /*
201  * Fibre Channel device definitions.
202  */
203 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
204 #define MAX_FIBRE_DEVICES_2100 512
205 #define MAX_FIBRE_DEVICES_2400 2048
206 #define MAX_FIBRE_DEVICES_LOOP 128
207 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
208 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
209 #define MAX_FIBRE_LUNS 0xFFFF
210 #define MAX_HOST_COUNT 16
211 
212 /*
213  * Host adapter default definitions.
214  */
215 #define MAX_BUSES 1 /* We only have one bus today */
216 #define MIN_LUNS 8
217 #define MAX_LUNS MAX_FIBRE_LUNS
218 #define MAX_CMDS_PER_LUN 255
219 
220 /*
221  * Fibre Channel device definitions.
222  */
223 #define SNS_LAST_LOOP_ID_2100 0xfe
224 #define SNS_LAST_LOOP_ID_2300 0x7ff
225 
226 #define LAST_LOCAL_LOOP_ID 0x7d
227 #define SNS_FL_PORT 0x7e
228 #define FABRIC_CONTROLLER 0x7f
229 #define SIMPLE_NAME_SERVER 0x80
230 #define SNS_FIRST_LOOP_ID 0x81
231 #define MANAGEMENT_SERVER 0xfe
232 #define BROADCAST 0xff
233 
234 /*
235  * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
236  * valid range of an N-PORT id is 0 through 0x7ef.
237  */
238 #define NPH_LAST_HANDLE 0x7ef
239 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
240 #define NPH_SNS 0x7fc /* FFFFFC */
241 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
242 #define NPH_F_PORT 0x7fe /* FFFFFE */
243 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
244 
245 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
246 #include "qla_fw.h"
247 
248 /*
249  * Timeout timer counts in seconds
250  */
251 #define PORT_RETRY_TIME 1
252 #define LOOP_DOWN_TIMEOUT 60
253 #define LOOP_DOWN_TIME 255 /* 240 */
254 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
255 
256 /* Maximum outstanding commands in ISP queues (1-65535) */
257 #define MAX_OUTSTANDING_COMMANDS 1024
258 
259 /* ISP request and response entry counts (37-65535) */
260 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
261 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
262 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
263 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
264 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
265 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
266 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
267 
268 struct req_que;
269 
270 /*
271  * (sd.h is not exported, hence local inclusion)
272  * Data Integrity Field tuple.
273  */
274 struct sd_dif_tuple {
275  __be16 guard_tag; /* Checksum */
276  __be16 app_tag; /* Opaque storage */
277  __be32 ref_tag; /* Target LBA or indirect LBA */
278 };
279 
280 /*
281  * SCSI Request Block
282  */
283 struct srb_cmd {
284  struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
285  uint32_t request_sense_length;
286  uint8_t *request_sense_ptr;
287  void *ctx;
288 };
289 
290 /*
291  * SRB flag definitions
292  */
293 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
294 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
295 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
296 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
297 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
298 
299 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
300 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
301 
302 /*
303  * SRB extensions.
304  */
305 struct srb_iocb {
306  union {
307  struct {
308  uint16_t flags;
309 #define SRB_LOGIN_RETRIED BIT_0
310 #define SRB_LOGIN_COND_PLOGI BIT_1
311 #define SRB_LOGIN_SKIP_PRLI BIT_2
312  uint16_t data[2];
313  } logio;
314  struct {
315  /*
316  * Values for flags field below are as
317  * defined in tsk_mgmt_entry struct
318  * for control_flags field in qla_fw.h.
319  */
320  uint32_t flags;
321  uint32_t lun;
322  uint32_t data;
323  } tmf;
324  } u;
325 
326  struct timer_list timer;
327  void (*timeout)(void *);
328 };
329 
330 /* Values for srb_ctx type */
331 #define SRB_LOGIN_CMD 1
332 #define SRB_LOGOUT_CMD 2
333 #define SRB_ELS_CMD_RPT 3
334 #define SRB_ELS_CMD_HST 4
335 #define SRB_CT_CMD 5
336 #define SRB_ADISC_CMD 6
337 #define SRB_TM_CMD 7
338 #define SRB_SCSI_CMD 8
339 #define SRB_BIDI_CMD 9
340 
341 typedef struct srb {
342  atomic_t ref_count;
343  struct fc_port *fcport;
344  uint32_t handle;
345  uint16_t flags;
346  uint16_t type;
347  char *name;
348  int iocbs;
349  union {
350  struct srb_iocb iocb_cmd;
351  struct fc_bsg_job *bsg_job;
352  struct srb_cmd scmd;
353  } u;
354  void (*done)(void *, void *, int);
355  void (*free)(void *, void *);
356 } srb_t;
357 
358 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
359 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
360 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
361 
362 #define GET_CMD_SENSE_LEN(sp) \
363  (sp->u.scmd.request_sense_length)
364 #define SET_CMD_SENSE_LEN(sp, len) \
365  (sp->u.scmd.request_sense_length = len)
366 #define GET_CMD_SENSE_PTR(sp) \
367  (sp->u.scmd.request_sense_ptr)
368 #define SET_CMD_SENSE_PTR(sp, ptr) \
369  (sp->u.scmd.request_sense_ptr = ptr)
370 
371 struct msg_echo_lb {
372  dma_addr_t send_dma;
373  dma_addr_t rcv_dma;
374  uint16_t req_sg_cnt;
375  uint16_t rsp_sg_cnt;
376  uint16_t options;
377  uint32_t transfer_size;
378 };
379 
380 /*
381  * ISP I/O Register Set structure definitions.
382  */
383 struct device_reg_2xxx {
384  uint16_t flash_address; /* Flash BIOS address */
385  uint16_t flash_data; /* Flash BIOS data */
386  uint16_t unused_1[1]; /* Gap */
387  uint16_t ctrl_status; /* Control/Status */
388 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
389 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
390 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
391 
392  uint16_t ictrl; /* Interrupt control */
393 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
394 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
395 
396  uint16_t istatus; /* Interrupt status */
397 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
398 
399  uint16_t semaphore; /* Semaphore */
400  uint16_t nvram; /* NVRAM register. */
401 #define NVR_DESELECT 0
402 #define NVR_BUSY BIT_15
403 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
404 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
405 #define NVR_DATA_IN BIT_3
406 #define NVR_DATA_OUT BIT_2
407 #define NVR_SELECT BIT_1
408 #define NVR_CLOCK BIT_0
409 
410 #define NVR_WAIT_CNT 20000
411 
412  union {
413  struct {
414  uint16_t mailbox0;
415  uint16_t mailbox1;
416  uint16_t mailbox2;
417  uint16_t mailbox3;
418  uint16_t mailbox4;
419  uint16_t mailbox5;
420  uint16_t mailbox6;
421  uint16_t mailbox7;
422  uint16_t unused_2[59]; /* Gap */
423  } __attribute__((packed)) isp2100;
424  struct {
425  /* Request Queue */
426  uint16_t req_q_in; /* In-Pointer */
427  uint16_t req_q_out; /* Out-Pointer */
428  /* Response Queue */
429  uint16_t rsp_q_in; /* In-Pointer */
430  uint16_t rsp_q_out; /* Out-Pointer */
431 
432  /* RISC to Host Status */
433  uint32_t host_status;
434 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
435 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
436 
437  /* Host to Host Semaphore */
438  uint16_t host_semaphore;
439  uint16_t unused_3[17]; /* Gap */
440  uint16_t mailbox0;
441  uint16_t mailbox1;
442  uint16_t mailbox2;
443  uint16_t mailbox3;
444  uint16_t mailbox4;
445  uint16_t mailbox5;
446  uint16_t mailbox6;
447  uint16_t mailbox7;
448  uint16_t mailbox8;
449  uint16_t mailbox9;
450  uint16_t mailbox10;
451  uint16_t mailbox11;
452  uint16_t mailbox12;
453  uint16_t mailbox13;
454  uint16_t mailbox14;
455  uint16_t mailbox15;
456  uint16_t mailbox16;
457  uint16_t mailbox17;
458  uint16_t mailbox18;
459  uint16_t mailbox19;
460  uint16_t mailbox20;
461  uint16_t mailbox21;
462  uint16_t mailbox22;
463  uint16_t mailbox23;
464  uint16_t mailbox24;
465  uint16_t mailbox25;
466  uint16_t mailbox26;
467  uint16_t mailbox27;
468  uint16_t mailbox28;
469  uint16_t mailbox29;
470  uint16_t mailbox30;
471  uint16_t mailbox31;
472  uint16_t fb_cmd;
473  uint16_t unused_4[10]; /* Gap */
474  } __attribute__((packed)) isp2300;
475  } u;
476 
477  uint16_t fpm_diag_config;
478  uint16_t unused_5[0x4]; /* Gap */
479  uint16_t risc_hw;
480  uint16_t unused_5_1; /* Gap */
481  uint16_t pcr; /* Processor Control Register. */
482  uint16_t unused_6[0x5]; /* Gap */
483  uint16_t mctr; /* Memory Configuration and Timing. */
484  uint16_t unused_7[0x3]; /* Gap */
485  uint16_t fb_cmd_2100; /* Unused on 23XX */
486  uint16_t unused_8[0x3]; /* Gap */
487  uint16_t hccr; /* Host command & control register. */
488 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
489 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
490  /* HCCR commands */
491 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
492 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
493 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
494 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
495 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
496 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
497 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
498 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
499 
500  uint16_t unused_9[5]; /* Gap */
501  uint16_t gpiod; /* GPIO Data register. */
502  uint16_t gpioe; /* GPIO Enable register. */
503 #define GPIO_LED_MASK 0x00C0
504 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
505 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
506 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
507 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
508 #define GPIO_LED_ALL_OFF 0x0000
509 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
510 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
511 
512  union {
513  struct {
514  uint16_t unused_10[8]; /* Gap */
515  uint16_t mailbox8;
516  uint16_t mailbox9;
517  uint16_t mailbox10;
518  uint16_t mailbox11;
519  uint16_t mailbox12;
520  uint16_t mailbox13;
521  uint16_t mailbox14;
522  uint16_t mailbox15;
523  uint16_t mailbox16;
524  uint16_t mailbox17;
525  uint16_t mailbox18;
526  uint16_t mailbox19;
527  uint16_t mailbox20;
528  uint16_t mailbox21;
529  uint16_t mailbox22;
530  uint16_t mailbox23; /* Also probe reg. */
531  } __attribute__((packed)) isp2200;
532  } u_end;
533 };
534 
535 struct device_reg_25xxmq {
536  uint32_t req_q_in;
537  uint32_t req_q_out;
538  uint32_t rsp_q_in;
539  uint32_t rsp_q_out;
540 };
541 
542 typedef union {
543  struct device_reg_2xxx isp;
544  struct device_reg_24xx isp24;
545  struct device_reg_25xxmq isp25mq;
546  struct device_reg_82xx isp82;
547 } device_reg_t;
548 
549 #define ISP_REQ_Q_IN(ha, reg) \
550  (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
551  &(reg)->u.isp2100.mailbox4 : \
552  &(reg)->u.isp2300.req_q_in)
553 #define ISP_REQ_Q_OUT(ha, reg) \
554  (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
555  &(reg)->u.isp2100.mailbox4 : \
556  &(reg)->u.isp2300.req_q_out)
557 #define ISP_RSP_Q_IN(ha, reg) \
558  (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
559  &(reg)->u.isp2100.mailbox5 : \
560  &(reg)->u.isp2300.rsp_q_in)
561 #define ISP_RSP_Q_OUT(ha, reg) \
562  (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
563  &(reg)->u.isp2100.mailbox5 : \
564  &(reg)->u.isp2300.rsp_q_out)
565 
566 #define MAILBOX_REG(ha, reg, num) \
567  (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
568  (num < 8 ? \
569  &(reg)->u.isp2100.mailbox0 + (num) : \
570  &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
571  &(reg)->u.isp2300.mailbox0 + (num))
572 #define RD_MAILBOX_REG(ha, reg, num) \
573  RD_REG_WORD(MAILBOX_REG(ha, reg, num))
574 #define WRT_MAILBOX_REG(ha, reg, num, data) \
575  WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
576 
577 #define FB_CMD_REG(ha, reg) \
578  (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
579  &(reg)->fb_cmd_2100 : \
580  &(reg)->u.isp2300.fb_cmd)
581 #define RD_FB_CMD_REG(ha, reg) \
582  RD_REG_WORD(FB_CMD_REG(ha, reg))
583 #define WRT_FB_CMD_REG(ha, reg, data) \
584  WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
585 
586 typedef struct {
587  uint32_t out_mb; /* outbound from driver */
588  uint32_t in_mb; /* Incoming from RISC */
589  uint16_t mb[MAILBOX_REGISTER_COUNT];
590  long buf_size;
591  void *bufp;
592  uint32_t tov;
593  uint8_t flags;
594 #define MBX_DMA_IN BIT_0
595 #define MBX_DMA_OUT BIT_1
596 #define IOCTL_CMD BIT_2
597 } mbx_cmd_t;
598 
599 #define MBX_TOV_SECONDS 30
600 
601 /*
602  * ISP product identification definitions in mailboxes after reset.
603  */
604 #define PROD_ID_1 0x4953
605 #define PROD_ID_2 0x0000
606 #define PROD_ID_2a 0x5020
607 #define PROD_ID_3 0x2020
608 
609 /*
610  * ISP mailbox Self-Test status codes
611  */
612 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
613 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
614 #define MBS_BUSY 4 /* Busy. */
615 
616 /*
617  * ISP mailbox command complete status codes
618  */
619 #define MBS_COMMAND_COMPLETE 0x4000
620 #define MBS_INVALID_COMMAND 0x4001
621 #define MBS_HOST_INTERFACE_ERROR 0x4002
622 #define MBS_TEST_FAILED 0x4003
623 #define MBS_COMMAND_ERROR 0x4005
624 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
625 #define MBS_PORT_ID_USED 0x4007
626 #define MBS_LOOP_ID_USED 0x4008
627 #define MBS_ALL_IDS_IN_USE 0x4009
628 #define MBS_NOT_LOGGED_IN 0x400A
629 #define MBS_LINK_DOWN_ERROR 0x400B
630 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
631 
632 /*
633  * ISP mailbox asynchronous event status codes
634  */
635 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
636 #define MBA_RESET 0x8001 /* Reset Detected. */
637 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
638 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
639 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
640 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
641 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
642  /* occurred. */
643 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
644 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
645 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
646 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
647 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
648 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
649 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
650 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
651 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
652 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
653 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
654 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
655 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
656 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
657 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
658 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
659  /* used. */
660 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
661 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
662 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
663 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
664 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
665 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
666 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
667 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
668 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
669 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
670 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
671 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
672 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
673 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
674 
675 /* 83XX FCoE specific */
676 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
677 
678 /* Interrupt type codes */
679 #define INTR_ROM_MB_SUCCESS 0x1
680 #define INTR_ROM_MB_FAILED 0x2
681 #define INTR_MB_SUCCESS 0x10
682 #define INTR_MB_FAILED 0x11
683 #define INTR_ASYNC_EVENT 0x12
684 #define INTR_RSP_QUE_UPDATE 0x13
685 #define INTR_RSP_QUE_UPDATE_83XX 0x14
686 #define INTR_ATIO_QUE_UPDATE 0x1C
687 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
688 
689 /* ISP mailbox loopback echo diagnostic error code */
690 #define MBS_LB_RESET 0x17
691 /*
692  * Firmware options 1, 2, 3.
693  */
694 #define FO1_AE_ON_LIPF8 BIT_0
695 #define FO1_AE_ALL_LIP_RESET BIT_1
696 #define FO1_CTIO_RETRY BIT_3
697 #define FO1_DISABLE_LIP_F7_SW BIT_4
698 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
699 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
700 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
701 #define FO1_SET_EMPHASIS_SWING BIT_8
702 #define FO1_AE_AUTO_BYPASS BIT_9
703 #define FO1_ENABLE_PURE_IOCB BIT_10
704 #define FO1_AE_PLOGI_RJT BIT_11
705 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
706 #define FO1_AE_QUEUE_FULL BIT_13
707 
708 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
709 #define FO2_REV_LOOPBACK BIT_1
710 
711 #define FO3_ENABLE_EMERG_IOCB BIT_0
712 #define FO3_AE_RND_ERROR BIT_1
713 
714 /* 24XX additional firmware options */
715 #define ADD_FO_COUNT 3
716 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
717 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
718 
719 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
720 
721 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
722 
723 /*
724  * ISP mailbox commands
725  */
726 #define MBC_LOAD_RAM 1 /* Load RAM. */
727 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
728 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
729 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
730 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
731 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
732 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
733 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
734 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
735 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
736 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
737 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
738 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
739 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
740 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
741 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
742 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
743 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
744 #define MBC_RESET 0x18 /* Reset. */
745 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
746 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
747 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
748 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
749 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
750 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
751 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
752 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
753 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
754 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
755 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
756 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
757 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
758 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
759 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
760 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
761 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
762 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
763 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
764 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
765 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
766 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
767 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
768 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
769  /* Initialization Procedure */
770 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
771 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
772 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
773 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
774 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
775 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
776 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
777 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
778 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
779 #define MBC_LIP_RESET 0x6c /* LIP reset. */
780 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
781  /* commandd. */
782 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
783 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
784 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
785 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
786 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
787 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
788 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
789 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
790 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
791 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
792 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
793 
794 /*
795  * ISP24xx mailbox commands
796  */
797 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
798 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
799 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
800 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
801 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
802 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
803 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
804 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
805 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
806 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
807 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
808 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
809 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
810 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
811 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
812 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
813 #define MBC_PORT_RESET 0x120 /* Port Reset */
814 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
815 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
816 
817 /*
818  * ISP81xx mailbox commands
819  */
820 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
821 
822 /* Firmware return data sizes */
823 #define FCAL_MAP_SIZE 128
824 
825 /* Mailbox bit definitions for out_mb and in_mb */
826 #define MBX_31 BIT_31
827 #define MBX_30 BIT_30
828 #define MBX_29 BIT_29
829 #define MBX_28 BIT_28
830 #define MBX_27 BIT_27
831 #define MBX_26 BIT_26
832 #define MBX_25 BIT_25
833 #define MBX_24 BIT_24
834 #define MBX_23 BIT_23
835 #define MBX_22 BIT_22
836 #define MBX_21 BIT_21
837 #define MBX_20 BIT_20
838 #define MBX_19 BIT_19
839 #define MBX_18 BIT_18
840 #define MBX_17 BIT_17
841 #define MBX_16 BIT_16
842 #define MBX_15 BIT_15
843 #define MBX_14 BIT_14
844 #define MBX_13 BIT_13
845 #define MBX_12 BIT_12
846 #define MBX_11 BIT_11
847 #define MBX_10 BIT_10
848 #define MBX_9 BIT_9
849 #define MBX_8 BIT_8
850 #define MBX_7 BIT_7
851 #define MBX_6 BIT_6
852 #define MBX_5 BIT_5
853 #define MBX_4 BIT_4
854 #define MBX_3 BIT_3
855 #define MBX_2 BIT_2
856 #define MBX_1 BIT_1
857 #define MBX_0 BIT_0
858 
859 /*
860  * Firmware state codes from get firmware state mailbox command
861  */
862 #define FSTATE_CONFIG_WAIT 0
863 #define FSTATE_WAIT_AL_PA 1
864 #define FSTATE_WAIT_LOGIN 2
865 #define FSTATE_READY 3
866 #define FSTATE_LOSS_OF_SYNC 4
867 #define FSTATE_ERROR 5
868 #define FSTATE_REINIT 6
869 #define FSTATE_NON_PART 7
870 
871 #define FSTATE_CONFIG_CORRECT 0
872 #define FSTATE_P2P_RCV_LIP 1
873 #define FSTATE_P2P_CHOOSE_LOOP 2
874 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
875 #define FSTATE_FATAL_ERROR 4
876 #define FSTATE_LOOP_BACK_CONN 5
877 
878 /*
879  * Port Database structure definition
880  * Little endian except where noted.
881  */
882 #define PORT_DATABASE_SIZE 128 /* bytes */
883 typedef struct {
884  uint8_t options;
885  uint8_t control;
886  uint8_t master_state;
887  uint8_t slave_state;
888  uint8_t reserved[2];
889  uint8_t hard_address;
890  uint8_t reserved_1;
891  uint8_t port_id[4];
892  uint8_t node_name[WWN_SIZE];
893  uint8_t port_name[WWN_SIZE];
894  uint16_t execution_throttle;
895  uint16_t execution_count;
896  uint8_t reset_count;
897  uint8_t reserved_2;
898  uint16_t resource_allocation;
899  uint16_t current_allocation;
900  uint16_t queue_head;
901  uint16_t queue_tail;
902  uint16_t transmit_execution_list_next;
903  uint16_t transmit_execution_list_previous;
904  uint16_t common_features;
905  uint16_t total_concurrent_sequences;
906  uint16_t RO_by_information_category;
907  uint8_t recipient;
908  uint8_t initiator;
909  uint16_t receive_data_size;
910  uint16_t concurrent_sequences;
911  uint16_t open_sequences_per_exchange;
912  uint16_t lun_abort_flags;
913  uint16_t lun_stop_flags;
914  uint16_t stop_queue_head;
915  uint16_t stop_queue_tail;
916  uint16_t port_retry_timer;
917  uint16_t next_sequence_id;
918  uint16_t frame_count;
919  uint16_t PRLI_payload_length;
920  uint8_t prli_svc_param_word_0[2]; /* Big endian */
921  /* Bits 15-0 of word 0 */
922  uint8_t prli_svc_param_word_3[2]; /* Big endian */
923  /* Bits 15-0 of word 3 */
924  uint16_t loop_id;
925  uint16_t extended_lun_info_list_pointer;
926  uint16_t extended_lun_stop_list_pointer;
927 } port_database_t;
928 
929 /*
930  * Port database slave/master states
931  */
932 #define PD_STATE_DISCOVERY 0
933 #define PD_STATE_WAIT_DISCOVERY_ACK 1
934 #define PD_STATE_PORT_LOGIN 2
935 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
936 #define PD_STATE_PROCESS_LOGIN 4
937 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
938 #define PD_STATE_PORT_LOGGED_IN 6
939 #define PD_STATE_PORT_UNAVAILABLE 7
940 #define PD_STATE_PROCESS_LOGOUT 8
941 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
942 #define PD_STATE_PORT_LOGOUT 10
943 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
944 
945 
946 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
947 #define QLA_ZIO_DISABLED 0
948 #define QLA_ZIO_DEFAULT_TIMER 2
949 
950 /*
951  * ISP Initialization Control Block.
952  * Little endian except where noted.
953  */
954 #define ICB_VERSION 1
955 typedef struct {
956  uint8_t version;
957  uint8_t reserved_1;
958 
959  /*
960  * LSB BIT 0 = Enable Hard Loop Id
961  * LSB BIT 1 = Enable Fairness
962  * LSB BIT 2 = Enable Full-Duplex
963  * LSB BIT 3 = Enable Fast Posting
964  * LSB BIT 4 = Enable Target Mode
965  * LSB BIT 5 = Disable Initiator Mode
966  * LSB BIT 6 = Enable ADISC
967  * LSB BIT 7 = Enable Target Inquiry Data
968  *
969  * MSB BIT 0 = Enable PDBC Notify
970  * MSB BIT 1 = Non Participating LIP
971  * MSB BIT 2 = Descending Loop ID Search
972  * MSB BIT 3 = Acquire Loop ID in LIPA
973  * MSB BIT 4 = Stop PortQ on Full Status
974  * MSB BIT 5 = Full Login after LIP
975  * MSB BIT 6 = Node Name Option
976  * MSB BIT 7 = Ext IFWCB enable bit
977  */
978  uint8_t firmware_options[2];
979 
980  uint16_t frame_payload_size;
981  uint16_t max_iocb_allocation;
982  uint16_t execution_throttle;
983  uint8_t retry_count;
984  uint8_t retry_delay; /* unused */
985  uint8_t port_name[WWN_SIZE]; /* Big endian. */
986  uint16_t hard_address;
987  uint8_t inquiry_data;
988  uint8_t login_timeout;
989  uint8_t node_name[WWN_SIZE]; /* Big endian. */
990 
991  uint16_t request_q_outpointer;
992  uint16_t response_q_inpointer;
993  uint16_t request_q_length;
994  uint16_t response_q_length;
995  uint32_t request_q_address[2];
996  uint32_t response_q_address[2];
997 
998  uint16_t lun_enables;
999  uint8_t command_resource_count;
1000  uint8_t immediate_notify_resource_count;
1001  uint16_t timeout;
1002  uint8_t reserved_2[2];
1003 
1004  /*
1005  * LSB BIT 0 = Timer Operation mode bit 0
1006  * LSB BIT 1 = Timer Operation mode bit 1
1007  * LSB BIT 2 = Timer Operation mode bit 2
1008  * LSB BIT 3 = Timer Operation mode bit 3
1009  * LSB BIT 4 = Init Config Mode bit 0
1010  * LSB BIT 5 = Init Config Mode bit 1
1011  * LSB BIT 6 = Init Config Mode bit 2
1012  * LSB BIT 7 = Enable Non part on LIHA failure
1013  *
1014  * MSB BIT 0 = Enable class 2
1015  * MSB BIT 1 = Enable ACK0
1016  * MSB BIT 2 =
1017  * MSB BIT 3 =
1018  * MSB BIT 4 = FC Tape Enable
1019  * MSB BIT 5 = Enable FC Confirm
1020  * MSB BIT 6 = Enable command queuing in target mode
1021  * MSB BIT 7 = No Logo On Link Down
1022  */
1023  uint8_t add_firmware_options[2];
1024 
1025  uint8_t response_accumulation_timer;
1026  uint8_t interrupt_delay_timer;
1027 
1028  /*
1029  * LSB BIT 0 = Enable Read xfr_rdy
1030  * LSB BIT 1 = Soft ID only
1031  * LSB BIT 2 =
1032  * LSB BIT 3 =
1033  * LSB BIT 4 = FCP RSP Payload [0]
1034  * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1035  * LSB BIT 6 = Enable Out-of-Order frame handling
1036  * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1037  *
1038  * MSB BIT 0 = Sbus enable - 2300
1039  * MSB BIT 1 =
1040  * MSB BIT 2 =
1041  * MSB BIT 3 =
1042  * MSB BIT 4 = LED mode
1043  * MSB BIT 5 = enable 50 ohm termination
1044  * MSB BIT 6 = Data Rate (2300 only)
1045  * MSB BIT 7 = Data Rate (2300 only)
1046  */
1047  uint8_t special_options[2];
1048 
1049  uint8_t reserved_3[26];
1050 } init_cb_t;
1051 
1052 /*
1053  * Get Link Status mailbox command return buffer.
1054  */
1055 #define GLSO_SEND_RPS BIT_0
1056 #define GLSO_USE_DID BIT_3
1057 
1058 struct link_statistics {
1059  uint32_t link_fail_cnt;
1060  uint32_t loss_sync_cnt;
1061  uint32_t loss_sig_cnt;
1062  uint32_t prim_seq_err_cnt;
1063  uint32_t inval_xmit_word_cnt;
1064  uint32_t inval_crc_cnt;
1065  uint32_t lip_cnt;
1066  uint32_t unused1[0x1a];
1067  uint32_t tx_frames;
1068  uint32_t rx_frames;
1069  uint32_t dumped_frames;
1070  uint32_t unused2[2];
1071  uint32_t nos_rcvd;
1072 };
1073 
1074 /*
1075  * NVRAM Command values.
1076  */
1077 #define NV_START_BIT BIT_2
1078 #define NV_WRITE_OP (BIT_26+BIT_24)
1079 #define NV_READ_OP (BIT_26+BIT_25)
1080 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1081 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1082 #define NV_DELAY_COUNT 10
1083 
1084 /*
1085  * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1086  */
1087 typedef struct {
1088  /*
1089  * NVRAM header
1090  */
1091  uint8_t id[4];
1092  uint8_t nvram_version;
1093  uint8_t reserved_0;
1094 
1095  /*
1096  * NVRAM RISC parameter block
1097  */
1098  uint8_t parameter_block_version;
1099  uint8_t reserved_1;
1100 
1101  /*
1102  * LSB BIT 0 = Enable Hard Loop Id
1103  * LSB BIT 1 = Enable Fairness
1104  * LSB BIT 2 = Enable Full-Duplex
1105  * LSB BIT 3 = Enable Fast Posting
1106  * LSB BIT 4 = Enable Target Mode
1107  * LSB BIT 5 = Disable Initiator Mode
1108  * LSB BIT 6 = Enable ADISC
1109  * LSB BIT 7 = Enable Target Inquiry Data
1110  *
1111  * MSB BIT 0 = Enable PDBC Notify
1112  * MSB BIT 1 = Non Participating LIP
1113  * MSB BIT 2 = Descending Loop ID Search
1114  * MSB BIT 3 = Acquire Loop ID in LIPA
1115  * MSB BIT 4 = Stop PortQ on Full Status
1116  * MSB BIT 5 = Full Login after LIP
1117  * MSB BIT 6 = Node Name Option
1118  * MSB BIT 7 = Ext IFWCB enable bit
1119  */
1120  uint8_t firmware_options[2];
1121 
1122  uint16_t frame_payload_size;
1123  uint16_t max_iocb_allocation;
1124  uint16_t execution_throttle;
1125  uint8_t retry_count;
1126  uint8_t retry_delay; /* unused */
1127  uint8_t port_name[WWN_SIZE]; /* Big endian. */
1128  uint16_t hard_address;
1129  uint8_t inquiry_data;
1130  uint8_t login_timeout;
1131  uint8_t node_name[WWN_SIZE]; /* Big endian. */
1132 
1133  /*
1134  * LSB BIT 0 = Timer Operation mode bit 0
1135  * LSB BIT 1 = Timer Operation mode bit 1
1136  * LSB BIT 2 = Timer Operation mode bit 2
1137  * LSB BIT 3 = Timer Operation mode bit 3
1138  * LSB BIT 4 = Init Config Mode bit 0
1139  * LSB BIT 5 = Init Config Mode bit 1
1140  * LSB BIT 6 = Init Config Mode bit 2
1141  * LSB BIT 7 = Enable Non part on LIHA failure
1142  *
1143  * MSB BIT 0 = Enable class 2
1144  * MSB BIT 1 = Enable ACK0
1145  * MSB BIT 2 =
1146  * MSB BIT 3 =
1147  * MSB BIT 4 = FC Tape Enable
1148  * MSB BIT 5 = Enable FC Confirm
1149  * MSB BIT 6 = Enable command queuing in target mode
1150  * MSB BIT 7 = No Logo On Link Down
1151  */
1152  uint8_t add_firmware_options[2];
1153 
1154  uint8_t response_accumulation_timer;
1155  uint8_t interrupt_delay_timer;
1156 
1157  /*
1158  * LSB BIT 0 = Enable Read xfr_rdy
1159  * LSB BIT 1 = Soft ID only
1160  * LSB BIT 2 =
1161  * LSB BIT 3 =
1162  * LSB BIT 4 = FCP RSP Payload [0]
1163  * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1164  * LSB BIT 6 = Enable Out-of-Order frame handling
1165  * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1166  *
1167  * MSB BIT 0 = Sbus enable - 2300
1168  * MSB BIT 1 =
1169  * MSB BIT 2 =
1170  * MSB BIT 3 =
1171  * MSB BIT 4 = LED mode
1172  * MSB BIT 5 = enable 50 ohm termination
1173  * MSB BIT 6 = Data Rate (2300 only)
1174  * MSB BIT 7 = Data Rate (2300 only)
1175  */
1176  uint8_t special_options[2];
1177 
1178  /* Reserved for expanded RISC parameter block */
1179  uint8_t reserved_2[22];
1180 
1181  /*
1182  * LSB BIT 0 = Tx Sensitivity 1G bit 0
1183  * LSB BIT 1 = Tx Sensitivity 1G bit 1
1184  * LSB BIT 2 = Tx Sensitivity 1G bit 2
1185  * LSB BIT 3 = Tx Sensitivity 1G bit 3
1186  * LSB BIT 4 = Rx Sensitivity 1G bit 0
1187  * LSB BIT 5 = Rx Sensitivity 1G bit 1
1188  * LSB BIT 6 = Rx Sensitivity 1G bit 2
1189  * LSB BIT 7 = Rx Sensitivity 1G bit 3
1190  *
1191  * MSB BIT 0 = Tx Sensitivity 2G bit 0
1192  * MSB BIT 1 = Tx Sensitivity 2G bit 1
1193  * MSB BIT 2 = Tx Sensitivity 2G bit 2
1194  * MSB BIT 3 = Tx Sensitivity 2G bit 3
1195  * MSB BIT 4 = Rx Sensitivity 2G bit 0
1196  * MSB BIT 5 = Rx Sensitivity 2G bit 1
1197  * MSB BIT 6 = Rx Sensitivity 2G bit 2
1198  * MSB BIT 7 = Rx Sensitivity 2G bit 3
1199  *
1200  * LSB BIT 0 = Output Swing 1G bit 0
1201  * LSB BIT 1 = Output Swing 1G bit 1
1202  * LSB BIT 2 = Output Swing 1G bit 2
1203  * LSB BIT 3 = Output Emphasis 1G bit 0
1204  * LSB BIT 4 = Output Emphasis 1G bit 1
1205  * LSB BIT 5 = Output Swing 2G bit 0
1206  * LSB BIT 6 = Output Swing 2G bit 1
1207  * LSB BIT 7 = Output Swing 2G bit 2
1208  *
1209  * MSB BIT 0 = Output Emphasis 2G bit 0
1210  * MSB BIT 1 = Output Emphasis 2G bit 1
1211  * MSB BIT 2 = Output Enable
1212  * MSB BIT 3 =
1213  * MSB BIT 4 =
1214  * MSB BIT 5 =
1215  * MSB BIT 6 =
1216  * MSB BIT 7 =
1217  */
1218  uint8_t seriallink_options[4];
1219 
1220  /*
1221  * NVRAM host parameter block
1222  *
1223  * LSB BIT 0 = Enable spinup delay
1224  * LSB BIT 1 = Disable BIOS
1225  * LSB BIT 2 = Enable Memory Map BIOS
1226  * LSB BIT 3 = Enable Selectable Boot
1227  * LSB BIT 4 = Disable RISC code load
1228  * LSB BIT 5 = Set cache line size 1
1229  * LSB BIT 6 = PCI Parity Disable
1230  * LSB BIT 7 = Enable extended logging
1231  *
1232  * MSB BIT 0 = Enable 64bit addressing
1233  * MSB BIT 1 = Enable lip reset
1234  * MSB BIT 2 = Enable lip full login
1235  * MSB BIT 3 = Enable target reset
1236  * MSB BIT 4 = Enable database storage
1237  * MSB BIT 5 = Enable cache flush read
1238  * MSB BIT 6 = Enable database load
1239  * MSB BIT 7 = Enable alternate WWN
1240  */
1241  uint8_t host_p[2];
1242 
1243  uint8_t boot_node_name[WWN_SIZE];
1244  uint8_t boot_lun_number;
1245  uint8_t reset_delay;
1246  uint8_t port_down_retry_count;
1247  uint8_t boot_id_number;
1248  uint16_t max_luns_per_target;
1249  uint8_t fcode_boot_port_name[WWN_SIZE];
1250  uint8_t alternate_port_name[WWN_SIZE];
1251  uint8_t alternate_node_name[WWN_SIZE];
1252 
1253  /*
1254  * BIT 0 = Selective Login
1255  * BIT 1 = Alt-Boot Enable
1256  * BIT 2 =
1257  * BIT 3 = Boot Order List
1258  * BIT 4 =
1259  * BIT 5 = Selective LUN
1260  * BIT 6 =
1261  * BIT 7 = unused
1262  */
1263  uint8_t efi_parameters;
1264 
1265  uint8_t link_down_timeout;
1266 
1267  uint8_t adapter_id[16];
1268 
1269  uint8_t alt1_boot_node_name[WWN_SIZE];
1270  uint16_t alt1_boot_lun_number;
1271  uint8_t alt2_boot_node_name[WWN_SIZE];
1272  uint16_t alt2_boot_lun_number;
1273  uint8_t alt3_boot_node_name[WWN_SIZE];
1274  uint16_t alt3_boot_lun_number;
1275  uint8_t alt4_boot_node_name[WWN_SIZE];
1276  uint16_t alt4_boot_lun_number;
1277  uint8_t alt5_boot_node_name[WWN_SIZE];
1278  uint16_t alt5_boot_lun_number;
1279  uint8_t alt6_boot_node_name[WWN_SIZE];
1280  uint16_t alt6_boot_lun_number;
1281  uint8_t alt7_boot_node_name[WWN_SIZE];
1282  uint16_t alt7_boot_lun_number;
1283 
1284  uint8_t reserved_3[2];
1285 
1286  /* Offset 200-215 : Model Number */
1287  uint8_t model_number[16];
1288 
1289  /* OEM related items */
1290  uint8_t oem_specific[16];
1291 
1292  /*
1293  * NVRAM Adapter Features offset 232-239
1294  *
1295  * LSB BIT 0 = External GBIC
1296  * LSB BIT 1 = Risc RAM parity
1297  * LSB BIT 2 = Buffer Plus Module
1298  * LSB BIT 3 = Multi Chip Adapter
1299  * LSB BIT 4 = Internal connector
1300  * LSB BIT 5 =
1301  * LSB BIT 6 =
1302  * LSB BIT 7 =
1303  *
1304  * MSB BIT 0 =
1305  * MSB BIT 1 =
1306  * MSB BIT 2 =
1307  * MSB BIT 3 =
1308  * MSB BIT 4 =
1309  * MSB BIT 5 =
1310  * MSB BIT 6 =
1311  * MSB BIT 7 =
1312  */
1313  uint8_t adapter_features[2];
1314 
1315  uint8_t reserved_4[16];
1316 
1317  /* Subsystem vendor ID for ISP2200 */
1318  uint16_t subsystem_vendor_id_2200;
1319 
1320  /* Subsystem device ID for ISP2200 */
1321  uint16_t subsystem_device_id_2200;
1322 
1323  uint8_t reserved_5;
1324  uint8_t checksum;
1325 } nvram_t;
1326 
1327 /*
1328  * ISP queue - response queue entry definition.
1329  */
1330 typedef struct {
1331  uint8_t entry_type; /* Entry type. */
1332  uint8_t entry_count; /* Entry count. */
1333  uint8_t sys_define; /* System defined. */
1334  uint8_t entry_status; /* Entry Status. */
1335  uint32_t handle; /* System defined handle */
1336  uint8_t data[52];
1337  uint32_t signature;
1338 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1339 } response_t;
1340 
1341 /*
1342  * ISP queue - ATIO queue entry definition.
1343  */
1344 struct atio {
1345  uint8_t entry_type; /* Entry type. */
1346  uint8_t entry_count; /* Entry count. */
1347  uint8_t data[58];
1348  uint32_t signature;
1349 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1350 };
1351 
1352 typedef union {
1353  uint16_t extended;
1354  struct {
1355  uint8_t reserved;
1356  uint8_t standard;
1357  } id;
1358 } target_id_t;
1359 
1360 #define SET_TARGET_ID(ha, to, from) \
1361 do { \
1362  if (HAS_EXTENDED_IDS(ha)) \
1363  to.extended = cpu_to_le16(from); \
1364  else \
1365  to.id.standard = (uint8_t)from; \
1366 } while (0)
1367 
1368 /*
1369  * ISP queue - command entry structure definition.
1370  */
1371 #define COMMAND_TYPE 0x11 /* Command entry */
1372 typedef struct {
1373  uint8_t entry_type; /* Entry type. */
1374  uint8_t entry_count; /* Entry count. */
1375  uint8_t sys_define; /* System defined. */
1376  uint8_t entry_status; /* Entry Status. */
1377  uint32_t handle; /* System handle. */
1378  target_id_t target; /* SCSI ID */
1379  uint16_t lun; /* SCSI LUN */
1380  uint16_t control_flags; /* Control flags. */
1381 #define CF_WRITE BIT_6
1382 #define CF_READ BIT_5
1383 #define CF_SIMPLE_TAG BIT_3
1384 #define CF_ORDERED_TAG BIT_2
1385 #define CF_HEAD_TAG BIT_1
1386  uint16_t reserved_1;
1387  uint16_t timeout; /* Command timeout. */
1388  uint16_t dseg_count; /* Data segment count. */
1389  uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1390  uint32_t byte_count; /* Total byte count. */
1391  uint32_t dseg_0_address; /* Data segment 0 address. */
1392  uint32_t dseg_0_length; /* Data segment 0 length. */
1393  uint32_t dseg_1_address; /* Data segment 1 address. */
1394  uint32_t dseg_1_length; /* Data segment 1 length. */
1395  uint32_t dseg_2_address; /* Data segment 2 address. */
1396  uint32_t dseg_2_length; /* Data segment 2 length. */
1397 } cmd_entry_t;
1398 
1399 /*
1400  * ISP queue - 64-Bit addressing, command entry structure definition.
1401  */
1402 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1403 typedef struct {
1404  uint8_t entry_type; /* Entry type. */
1405  uint8_t entry_count; /* Entry count. */
1406  uint8_t sys_define; /* System defined. */
1407  uint8_t entry_status; /* Entry Status. */
1408  uint32_t handle; /* System handle. */
1409  target_id_t target; /* SCSI ID */
1410  uint16_t lun; /* SCSI LUN */
1411  uint16_t control_flags; /* Control flags. */
1412  uint16_t reserved_1;
1413  uint16_t timeout; /* Command timeout. */
1414  uint16_t dseg_count; /* Data segment count. */
1415  uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1416  uint32_t byte_count; /* Total byte count. */
1417  uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1418  uint32_t dseg_0_length; /* Data segment 0 length. */
1419  uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1420  uint32_t dseg_1_length; /* Data segment 1 length. */
1421 } cmd_a64_entry_t, request_t;
1422 
1423 /*
1424  * ISP queue - continuation entry structure definition.
1425  */
1426 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1427 typedef struct {
1428  uint8_t entry_type; /* Entry type. */
1429  uint8_t entry_count; /* Entry count. */
1430  uint8_t sys_define; /* System defined. */
1431  uint8_t entry_status; /* Entry Status. */
1432  uint32_t reserved;
1433  uint32_t dseg_0_address; /* Data segment 0 address. */
1434  uint32_t dseg_0_length; /* Data segment 0 length. */
1435  uint32_t dseg_1_address; /* Data segment 1 address. */
1436  uint32_t dseg_1_length; /* Data segment 1 length. */
1437  uint32_t dseg_2_address; /* Data segment 2 address. */
1438  uint32_t dseg_2_length; /* Data segment 2 length. */
1439  uint32_t dseg_3_address; /* Data segment 3 address. */
1440  uint32_t dseg_3_length; /* Data segment 3 length. */
1441  uint32_t dseg_4_address; /* Data segment 4 address. */
1442  uint32_t dseg_4_length; /* Data segment 4 length. */
1443  uint32_t dseg_5_address; /* Data segment 5 address. */
1444  uint32_t dseg_5_length; /* Data segment 5 length. */
1445  uint32_t dseg_6_address; /* Data segment 6 address. */
1446  uint32_t dseg_6_length; /* Data segment 6 length. */
1447 } cont_entry_t;
1448 
1449 /*
1450  * ISP queue - 64-Bit addressing, continuation entry structure definition.
1451  */
1452 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1453 typedef struct {
1454  uint8_t entry_type; /* Entry type. */
1455  uint8_t entry_count; /* Entry count. */
1456  uint8_t sys_define; /* System defined. */
1457  uint8_t entry_status; /* Entry Status. */
1458  uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1459  uint32_t dseg_0_length; /* Data segment 0 length. */
1460  uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1461  uint32_t dseg_1_length; /* Data segment 1 length. */
1462  uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1463  uint32_t dseg_2_length; /* Data segment 2 length. */
1464  uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1465  uint32_t dseg_3_length; /* Data segment 3 length. */
1466  uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1467  uint32_t dseg_4_length; /* Data segment 4 length. */
1468 } cont_a64_entry_t;
1469 
1470 #define PO_MODE_DIF_INSERT 0
1471 #define PO_MODE_DIF_REMOVE 1
1472 #define PO_MODE_DIF_PASS 2
1473 #define PO_MODE_DIF_REPLACE 3
1474 #define PO_MODE_DIF_TCP_CKSUM 6
1475 #define PO_ENABLE_DIF_BUNDLING BIT_8
1476 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1477 #define PO_DISABLE_INCR_REF_TAG BIT_5
1478 #define PO_DISABLE_GUARD_CHECK BIT_4
1479 /*
1480  * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1481  */
1482 struct crc_context {
1483  uint32_t handle; /* System handle. */
1484  uint32_t ref_tag;
1485  uint16_t app_tag;
1486  uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1487  uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1488  uint16_t guard_seed; /* Initial Guard Seed */
1489  uint16_t prot_opts; /* Requested Data Protection Mode */
1490  uint16_t blk_size; /* Data size in bytes */
1491  uint16_t runt_blk_guard; /* Guard value for runt block (tape
1492  * only) */
1493  uint32_t byte_count; /* Total byte count/ total data
1494  * transfer count */
1495  union {
1496  struct {
1497  uint32_t reserved_1;
1498  uint16_t reserved_2;
1499  uint16_t reserved_3;
1500  uint32_t reserved_4;
1501  uint32_t data_address[2];
1502  uint32_t data_length;
1503  uint32_t reserved_5[2];
1504  uint32_t reserved_6;
1505  } nobundling;
1506  struct {
1507  uint32_t dif_byte_count; /* Total DIF byte
1508  * count */
1509  uint16_t reserved_1;
1510  uint16_t dseg_count; /* Data segment count */
1511  uint32_t reserved_2;
1512  uint32_t data_address[2];
1513  uint32_t data_length;
1514  uint32_t dif_address[2];
1515  uint32_t dif_length; /* Data segment 0
1516  * length */
1517  } bundling;
1518  } u;
1519 
1520  struct fcp_cmnd fcp_cmnd;
1521  dma_addr_t crc_ctx_dma;
1522  /* List of DMA context transfers */
1523  struct list_head dsd_list;
1524 
1525  /* This structure should not exceed 512 bytes */
1526 };
1527 
1528 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1529 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1530 
1531 /*
1532  * ISP queue - status entry structure definition.
1533  */
1534 #define STATUS_TYPE 0x03 /* Status entry. */
1535 typedef struct {
1536  uint8_t entry_type; /* Entry type. */
1537  uint8_t entry_count; /* Entry count. */
1538  uint8_t sys_define; /* System defined. */
1539  uint8_t entry_status; /* Entry Status. */
1540  uint32_t handle; /* System handle. */
1541  uint16_t scsi_status; /* SCSI status. */
1542  uint16_t comp_status; /* Completion status. */
1543  uint16_t state_flags; /* State flags. */
1544  uint16_t status_flags; /* Status flags. */
1545  uint16_t rsp_info_len; /* Response Info Length. */
1546  uint16_t req_sense_length; /* Request sense data length. */
1547  uint32_t residual_length; /* Residual transfer length. */
1548  uint8_t rsp_info[8]; /* FCP response information. */
1549  uint8_t req_sense_data[32]; /* Request sense data. */
1550 } sts_entry_t;
1551 
1552 /*
1553  * Status entry entry status
1554  */
1555 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1556 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1557 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1558 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1559 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1560 #define RF_BUSY BIT_1 /* Busy */
1561 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1562  RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1563 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1564  RF_INV_E_TYPE)
1565 
1566 /*
1567  * Status entry SCSI status bit definitions.
1568  */
1569 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1570 #define SS_RESIDUAL_UNDER BIT_11
1571 #define SS_RESIDUAL_OVER BIT_10
1572 #define SS_SENSE_LEN_VALID BIT_9
1573 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1574 
1575 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1576 #define SS_BUSY_CONDITION BIT_3
1577 #define SS_CONDITION_MET BIT_2
1578 #define SS_CHECK_CONDITION BIT_1
1579 
1580 /*
1581  * Status entry completion status
1582  */
1583 #define CS_COMPLETE 0x0 /* No errors */
1584 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1585 #define CS_DMA 0x2 /* A DMA direction error. */
1586 #define CS_TRANSPORT 0x3 /* Transport error. */
1587 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1588 #define CS_ABORTED 0x5 /* System aborted command. */
1589 #define CS_TIMEOUT 0x6 /* Timeout error. */
1590 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1591 #define CS_DIF_ERROR 0xC /* DIF error detected */
1592 
1593 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1594 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1595 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1596  /* (selection timeout) */
1597 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1598 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1599 #define CS_PORT_BUSY 0x2B /* Port Busy */
1600 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1601 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1602 #define CS_UNKNOWN 0x81 /* Driver defined */
1603 #define CS_RETRY 0x82 /* Driver defined */
1604 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1605 
1606 #define CS_BIDIR_RD_OVERRUN 0x700
1607 #define CS_BIDIR_RD_WR_OVERRUN 0x707
1608 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
1609 #define CS_BIDIR_RD_UNDERRUN 0x1500
1610 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
1611 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
1612 #define CS_BIDIR_DMA 0x200
1613 /*
1614  * Status entry status flags
1615  */
1616 #define SF_ABTS_TERMINATED BIT_10
1617 #define SF_LOGOUT_SENT BIT_13
1618 
1619 /*
1620  * ISP queue - status continuation entry structure definition.
1621  */
1622 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1623 typedef struct {
1624  uint8_t entry_type; /* Entry type. */
1625  uint8_t entry_count; /* Entry count. */
1626  uint8_t sys_define; /* System defined. */
1627  uint8_t entry_status; /* Entry Status. */
1628  uint8_t data[60]; /* data */
1629 } sts_cont_entry_t;
1630 
1631 /*
1632  * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1633  * structure definition.
1634  */
1635 #define STATUS_TYPE_21 0x21 /* Status entry. */
1636 typedef struct {
1637  uint8_t entry_type; /* Entry type. */
1638  uint8_t entry_count; /* Entry count. */
1639  uint8_t handle_count; /* Handle count. */
1640  uint8_t entry_status; /* Entry Status. */
1641  uint32_t handle[15]; /* System handles. */
1642 } sts21_entry_t;
1643 
1644 /*
1645  * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1646  * structure definition.
1647  */
1648 #define STATUS_TYPE_22 0x22 /* Status entry. */
1649 typedef struct {
1650  uint8_t entry_type; /* Entry type. */
1651  uint8_t entry_count; /* Entry count. */
1652  uint8_t handle_count; /* Handle count. */
1653  uint8_t entry_status; /* Entry Status. */
1654  uint16_t handle[30]; /* System handles. */
1655 } sts22_entry_t;
1656 
1657 /*
1658  * ISP queue - marker entry structure definition.
1659  */
1660 #define MARKER_TYPE 0x04 /* Marker entry. */
1661 typedef struct {
1662  uint8_t entry_type; /* Entry type. */
1663  uint8_t entry_count; /* Entry count. */
1664  uint8_t handle_count; /* Handle count. */
1665  uint8_t entry_status; /* Entry Status. */
1666  uint32_t sys_define_2; /* System defined. */
1667  target_id_t target; /* SCSI ID */
1668  uint8_t modifier; /* Modifier (7-0). */
1669 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1670 #define MK_SYNC_ID 1 /* Synchronize ID */
1671 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1672 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1673  /* clear port changed, */
1674  /* use sequence number. */
1675  uint8_t reserved_1;
1676  uint16_t sequence_number; /* Sequence number of event */
1677  uint16_t lun; /* SCSI LUN */
1678  uint8_t reserved_2[48];
1679 } mrk_entry_t;
1680 
1681 /*
1682  * ISP queue - Management Server entry structure definition.
1683  */
1684 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1685 typedef struct {
1686  uint8_t entry_type; /* Entry type. */
1687  uint8_t entry_count; /* Entry count. */
1688  uint8_t handle_count; /* Handle count. */
1689  uint8_t entry_status; /* Entry Status. */
1690  uint32_t handle1; /* System handle. */
1691  target_id_t loop_id;
1692  uint16_t status;
1693  uint16_t control_flags; /* Control flags. */
1694  uint16_t reserved2;
1695  uint16_t timeout;
1696  uint16_t cmd_dsd_count;
1697  uint16_t total_dsd_count;
1698  uint8_t type;
1699  uint8_t r_ctl;
1700  uint16_t rx_id;
1701  uint16_t reserved3;
1702  uint32_t handle2;
1703  uint32_t rsp_bytecount;
1704  uint32_t req_bytecount;
1705  uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1706  uint32_t dseg_req_length; /* Data segment 0 length. */
1707  uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1708  uint32_t dseg_rsp_length; /* Data segment 1 length. */
1709 } ms_iocb_entry_t;
1710 
1711 
1712 /*
1713  * ISP queue - Mailbox Command entry structure definition.
1714  */
1715 #define MBX_IOCB_TYPE 0x39
1716 struct mbx_entry {
1717  uint8_t entry_type;
1718  uint8_t entry_count;
1719  uint8_t sys_define1;
1720  /* Use sys_define1 for source type */
1721 #define SOURCE_SCSI 0x00
1722 #define SOURCE_IP 0x01
1723 #define SOURCE_VI 0x02
1724 #define SOURCE_SCTP 0x03
1725 #define SOURCE_MP 0x04
1726 #define SOURCE_MPIOCTL 0x05
1727 #define SOURCE_ASYNC_IOCB 0x07
1728 
1729  uint8_t entry_status;
1730 
1731  uint32_t handle;
1732  target_id_t loop_id;
1733 
1734  uint16_t status;
1735  uint16_t state_flags;
1736  uint16_t status_flags;
1737 
1738  uint32_t sys_define2[2];
1739 
1740  uint16_t mb0;
1741  uint16_t mb1;
1742  uint16_t mb2;
1743  uint16_t mb3;
1744  uint16_t mb6;
1745  uint16_t mb7;
1746  uint16_t mb9;
1747  uint16_t mb10;
1748  uint32_t reserved_2[2];
1749  uint8_t node_name[WWN_SIZE];
1750  uint8_t port_name[WWN_SIZE];
1751 };
1752 
1753 /*
1754  * ISP request and response queue entry sizes
1755  */
1756 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1757 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1758 
1759 
1760 /*
1761  * 24 bit port ID type definition.
1762  */
1763 typedef union {
1764  uint32_t b24 : 24;
1765 
1766  struct {
1767 #ifdef __BIG_ENDIAN
1768  uint8_t domain;
1769  uint8_t area;
1770  uint8_t al_pa;
1771 #elif defined(__LITTLE_ENDIAN)
1772  uint8_t al_pa;
1773  uint8_t area;
1774  uint8_t domain;
1775 #else
1776 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1777 #endif
1778  uint8_t rsvd_1;
1779  } b;
1780 } port_id_t;
1781 #define INVALID_PORT_ID 0xFFFFFF
1782 
1783 /*
1784  * Switch info gathering structure.
1785  */
1786 typedef struct {
1787  port_id_t d_id;
1788  uint8_t node_name[WWN_SIZE];
1789  uint8_t port_name[WWN_SIZE];
1790  uint8_t fabric_port_name[WWN_SIZE];
1791  uint16_t fp_speed;
1792  uint8_t fc4_type;
1793 } sw_info_t;
1794 
1795 /* FCP-4 types */
1796 #define FC4_TYPE_FCP_SCSI 0x08
1797 #define FC4_TYPE_OTHER 0x0
1798 #define FC4_TYPE_UNKNOWN 0xff
1799 
1800 /*
1801  * Fibre channel port type.
1802  */
1803  typedef enum {
1804  FCT_UNKNOWN,
1805  FCT_RSCN,
1806  FCT_SWITCH,
1807  FCT_BROADCAST,
1808  FCT_INITIATOR,
1809  FCT_TARGET
1810 } fc_port_type_t;
1811 
1812 /*
1813  * Fibre channel port structure.
1814  */
1815 typedef struct fc_port {
1816  struct list_head list;
1817  struct scsi_qla_host *vha;
1818 
1819  uint8_t node_name[WWN_SIZE];
1820  uint8_t port_name[WWN_SIZE];
1821  port_id_t d_id;
1822  uint16_t loop_id;
1823  uint16_t old_loop_id;
1824 
1825  uint8_t fcp_prio;
1826 
1827  uint8_t fabric_port_name[WWN_SIZE];
1828  uint16_t fp_speed;
1829 
1830  fc_port_type_t port_type;
1831 
1832  atomic_t state;
1833  uint32_t flags;
1834 
1835  int login_retry;
1836 
1837  struct fc_rport *rport, *drport;
1838  u32 supported_classes;
1839 
1840  uint8_t fc4_type;
1841  uint8_t scan_state;
1842 } fc_port_t;
1843 
1844 #define QLA_FCPORT_SCAN_NONE 0
1845 #define QLA_FCPORT_SCAN_FOUND 1
1846 
1847 /*
1848  * Fibre channel port/lun states.
1849  */
1850 #define FCS_UNCONFIGURED 1
1851 #define FCS_DEVICE_DEAD 2
1852 #define FCS_DEVICE_LOST 3
1853 #define FCS_ONLINE 4
1854 
1855 static const char * const port_state_str[] = {
1856  "Unknown",
1857  "UNCONFIGURED",
1858  "DEAD",
1859  "LOST",
1860  "ONLINE"
1861 };
1862 
1863 /*
1864  * FC port flags.
1865  */
1866 #define FCF_FABRIC_DEVICE BIT_0
1867 #define FCF_LOGIN_NEEDED BIT_1
1868 #define FCF_FCP2_DEVICE BIT_2
1869 #define FCF_ASYNC_SENT BIT_3
1870 #define FCF_CONF_COMP_SUPPORTED BIT_4
1871 
1872 /* No loop ID flag. */
1873 #define FC_NO_LOOP_ID 0x1000
1874 
1875 /*
1876  * FC-CT interface
1877  *
1878  * NOTE: All structures are big-endian in form.
1879  */
1880 
1881 #define CT_REJECT_RESPONSE 0x8001
1882 #define CT_ACCEPT_RESPONSE 0x8002
1883 #define CT_REASON_INVALID_COMMAND_CODE 0x01
1884 #define CT_REASON_CANNOT_PERFORM 0x09
1885 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1886 #define CT_EXPL_ALREADY_REGISTERED 0x10
1887 
1888 #define NS_N_PORT_TYPE 0x01
1889 #define NS_NL_PORT_TYPE 0x02
1890 #define NS_NX_PORT_TYPE 0x7F
1891 
1892 #define GA_NXT_CMD 0x100
1893 #define GA_NXT_REQ_SIZE (16 + 4)
1894 #define GA_NXT_RSP_SIZE (16 + 620)
1895 
1896 #define GID_PT_CMD 0x1A1
1897 #define GID_PT_REQ_SIZE (16 + 4)
1898 
1899 #define GPN_ID_CMD 0x112
1900 #define GPN_ID_REQ_SIZE (16 + 4)
1901 #define GPN_ID_RSP_SIZE (16 + 8)
1902 
1903 #define GNN_ID_CMD 0x113
1904 #define GNN_ID_REQ_SIZE (16 + 4)
1905 #define GNN_ID_RSP_SIZE (16 + 8)
1906 
1907 #define GFT_ID_CMD 0x117
1908 #define GFT_ID_REQ_SIZE (16 + 4)
1909 #define GFT_ID_RSP_SIZE (16 + 32)
1910 
1911 #define RFT_ID_CMD 0x217
1912 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1913 #define RFT_ID_RSP_SIZE 16
1914 
1915 #define RFF_ID_CMD 0x21F
1916 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1917 #define RFF_ID_RSP_SIZE 16
1918 
1919 #define RNN_ID_CMD 0x213
1920 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1921 #define RNN_ID_RSP_SIZE 16
1922 
1923 #define RSNN_NN_CMD 0x239
1924 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1925 #define RSNN_NN_RSP_SIZE 16
1926 
1927 #define GFPN_ID_CMD 0x11C
1928 #define GFPN_ID_REQ_SIZE (16 + 4)
1929 #define GFPN_ID_RSP_SIZE (16 + 8)
1930 
1931 #define GPSC_CMD 0x127
1932 #define GPSC_REQ_SIZE (16 + 8)
1933 #define GPSC_RSP_SIZE (16 + 2 + 2)
1934 
1935 #define GFF_ID_CMD 0x011F
1936 #define GFF_ID_REQ_SIZE (16 + 4)
1937 #define GFF_ID_RSP_SIZE (16 + 128)
1938 
1939 /*
1940  * HBA attribute types.
1941  */
1942 #define FDMI_HBA_ATTR_COUNT 9
1943 #define FDMI_HBA_NODE_NAME 1
1944 #define FDMI_HBA_MANUFACTURER 2
1945 #define FDMI_HBA_SERIAL_NUMBER 3
1946 #define FDMI_HBA_MODEL 4
1947 #define FDMI_HBA_MODEL_DESCRIPTION 5
1948 #define FDMI_HBA_HARDWARE_VERSION 6
1949 #define FDMI_HBA_DRIVER_VERSION 7
1950 #define FDMI_HBA_OPTION_ROM_VERSION 8
1951 #define FDMI_HBA_FIRMWARE_VERSION 9
1952 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1953 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1954 
1955 struct ct_fdmi_hba_attr {
1956  uint16_t type;
1957  uint16_t len;
1958  union {
1959  uint8_t node_name[WWN_SIZE];
1960  uint8_t manufacturer[32];
1961  uint8_t serial_num[8];
1962  uint8_t model[16];
1963  uint8_t model_desc[80];
1964  uint8_t hw_version[16];
1965  uint8_t driver_version[32];
1966  uint8_t orom_version[16];
1967  uint8_t fw_version[16];
1968  uint8_t os_version[128];
1969  uint8_t max_ct_len[4];
1970  } a;
1971 };
1972 
1973 struct ct_fdmi_hba_attributes {
1974  uint32_t count;
1975  struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1976 };
1977 
1978 /*
1979  * Port attribute types.
1980  */
1981 #define FDMI_PORT_ATTR_COUNT 6
1982 #define FDMI_PORT_FC4_TYPES 1
1983 #define FDMI_PORT_SUPPORT_SPEED 2
1984 #define FDMI_PORT_CURRENT_SPEED 3
1985 #define FDMI_PORT_MAX_FRAME_SIZE 4
1986 #define FDMI_PORT_OS_DEVICE_NAME 5
1987 #define FDMI_PORT_HOST_NAME 6
1988 
1989 #define FDMI_PORT_SPEED_1GB 0x1
1990 #define FDMI_PORT_SPEED_2GB 0x2
1991 #define FDMI_PORT_SPEED_10GB 0x4
1992 #define FDMI_PORT_SPEED_4GB 0x8
1993 #define FDMI_PORT_SPEED_8GB 0x10
1994 #define FDMI_PORT_SPEED_16GB 0x20
1995 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
1996 
1997 struct ct_fdmi_port_attr {
1998  uint16_t type;
1999  uint16_t len;
2000  union {
2001  uint8_t fc4_types[32];
2002  uint32_t sup_speed;
2003  uint32_t cur_speed;
2004  uint32_t max_frame_size;
2005  uint8_t os_dev_name[32];
2006  uint8_t host_name[32];
2007  } a;
2008 };
2009 
2010 /*
2011  * Port Attribute Block.
2012  */
2013 struct ct_fdmi_port_attributes {
2014  uint32_t count;
2015  struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2016 };
2017 
2018 /* FDMI definitions. */
2019 #define GRHL_CMD 0x100
2020 #define GHAT_CMD 0x101
2021 #define GRPL_CMD 0x102
2022 #define GPAT_CMD 0x110
2023 
2024 #define RHBA_CMD 0x200
2025 #define RHBA_RSP_SIZE 16
2026 
2027 #define RHAT_CMD 0x201
2028 #define RPRT_CMD 0x210
2029 
2030 #define RPA_CMD 0x211
2031 #define RPA_RSP_SIZE 16
2032 
2033 #define DHBA_CMD 0x300
2034 #define DHBA_REQ_SIZE (16 + 8)
2035 #define DHBA_RSP_SIZE 16
2036 
2037 #define DHAT_CMD 0x301
2038 #define DPRT_CMD 0x310
2039 #define DPA_CMD 0x311
2040 
2041 /* CT command header -- request/response common fields */
2042 struct ct_cmd_hdr {
2043  uint8_t revision;
2044  uint8_t in_id[3];
2045  uint8_t gs_type;
2046  uint8_t gs_subtype;
2047  uint8_t options;
2048  uint8_t reserved;
2049 };
2050 
2051 /* CT command request */
2052 struct ct_sns_req {
2053  struct ct_cmd_hdr header;
2054  uint16_t command;
2055  uint16_t max_rsp_size;
2056  uint8_t fragment_id;
2057  uint8_t reserved[3];
2058 
2059  union {
2060  /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
2061  struct {
2062  uint8_t reserved;
2063  uint8_t port_id[3];
2064  } port_id;
2065 
2066  struct {
2067  uint8_t port_type;
2068  uint8_t domain;
2069  uint8_t area;
2070  uint8_t reserved;
2071  } gid_pt;
2072 
2073  struct {
2074  uint8_t reserved;
2075  uint8_t port_id[3];
2076  uint8_t fc4_types[32];
2077  } rft_id;
2078 
2079  struct {
2080  uint8_t reserved;
2081  uint8_t port_id[3];
2082  uint16_t reserved2;
2083  uint8_t fc4_feature;
2084  uint8_t fc4_type;
2085  } rff_id;
2086 
2087  struct {
2088  uint8_t reserved;
2089  uint8_t port_id[3];
2090  uint8_t node_name[8];
2091  } rnn_id;
2092 
2093  struct {
2094  uint8_t node_name[8];
2095  uint8_t name_len;
2096  uint8_t sym_node_name[255];
2097  } rsnn_nn;
2098 
2099  struct {
2100  uint8_t hba_indentifier[8];
2101  } ghat;
2102 
2103  struct {
2104  uint8_t hba_identifier[8];
2105  uint32_t entry_count;
2106  uint8_t port_name[8];
2107  struct ct_fdmi_hba_attributes attrs;
2108  } rhba;
2109 
2110  struct {
2111  uint8_t hba_identifier[8];
2112  struct ct_fdmi_hba_attributes attrs;
2113  } rhat;
2114 
2115  struct {
2116  uint8_t port_name[8];
2117  struct ct_fdmi_port_attributes attrs;
2118  } rpa;
2119 
2120  struct {
2121  uint8_t port_name[8];
2122  } dhba;
2123 
2124  struct {
2125  uint8_t port_name[8];
2126  } dhat;
2127 
2128  struct {
2129  uint8_t port_name[8];
2130  } dprt;
2131 
2132  struct {
2133  uint8_t port_name[8];
2134  } dpa;
2135 
2136  struct {
2137  uint8_t port_name[8];
2138  } gpsc;
2139 
2140  struct {
2141  uint8_t reserved;
2142  uint8_t port_name[3];
2143  } gff_id;
2144  } req;
2145 };
2146 
2147 /* CT command response header */
2148 struct ct_rsp_hdr {
2149  struct ct_cmd_hdr header;
2150  uint16_t response;
2151  uint16_t residual;
2152  uint8_t fragment_id;
2153  uint8_t reason_code;
2154  uint8_t explanation_code;
2155  uint8_t vendor_unique;
2156 };
2157 
2158 struct ct_sns_gid_pt_data {
2159  uint8_t control_byte;
2160  uint8_t port_id[3];
2161 };
2162 
2163 struct ct_sns_rsp {
2164  struct ct_rsp_hdr header;
2165 
2166  union {
2167  struct {
2168  uint8_t port_type;
2169  uint8_t port_id[3];
2170  uint8_t port_name[8];
2171  uint8_t sym_port_name_len;
2172  uint8_t sym_port_name[255];
2173  uint8_t node_name[8];
2174  uint8_t sym_node_name_len;
2175  uint8_t sym_node_name[255];
2176  uint8_t init_proc_assoc[8];
2177  uint8_t node_ip_addr[16];
2178  uint8_t class_of_service[4];
2179  uint8_t fc4_types[32];
2180  uint8_t ip_address[16];
2181  uint8_t fabric_port_name[8];
2182  uint8_t reserved;
2183  uint8_t hard_address[3];
2184  } ga_nxt;
2185 
2186  struct {
2187  /* Assume the largest number of targets for the union */
2188  struct ct_sns_gid_pt_data
2189  entries[MAX_FIBRE_DEVICES_MAX];
2190  } gid_pt;
2191 
2192  struct {
2193  uint8_t port_name[8];
2194  } gpn_id;
2195 
2196  struct {
2197  uint8_t node_name[8];
2198  } gnn_id;
2199 
2200  struct {
2201  uint8_t fc4_types[32];
2202  } gft_id;
2203 
2204  struct {
2205  uint32_t entry_count;
2206  uint8_t port_name[8];
2207  struct ct_fdmi_hba_attributes attrs;
2208  } ghat;
2209 
2210  struct {
2211  uint8_t port_name[8];
2212  } gfpn_id;
2213 
2214  struct {
2215  uint16_t speeds;
2216  uint16_t speed;
2217  } gpsc;
2218 
2219 #define GFF_FCP_SCSI_OFFSET 7
2220  struct {
2221  uint8_t fc4_features[128];
2222  } gff_id;
2223  } rsp;
2224 };
2225 
2226 struct ct_sns_pkt {
2227  union {
2228  struct ct_sns_req req;
2229  struct ct_sns_rsp rsp;
2230  } p;
2231 };
2232 
2233 /*
2234  * SNS command structures -- for 2200 compatibility.
2235  */
2236 #define RFT_ID_SNS_SCMD_LEN 22
2237 #define RFT_ID_SNS_CMD_SIZE 60
2238 #define RFT_ID_SNS_DATA_SIZE 16
2239 
2240 #define RNN_ID_SNS_SCMD_LEN 10
2241 #define RNN_ID_SNS_CMD_SIZE 36
2242 #define RNN_ID_SNS_DATA_SIZE 16
2243 
2244 #define GA_NXT_SNS_SCMD_LEN 6
2245 #define GA_NXT_SNS_CMD_SIZE 28
2246 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
2247 
2248 #define GID_PT_SNS_SCMD_LEN 6
2249 #define GID_PT_SNS_CMD_SIZE 28
2250 /*
2251  * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
2252  * adapters.
2253  */
2254 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
2255 
2256 #define GPN_ID_SNS_SCMD_LEN 6
2257 #define GPN_ID_SNS_CMD_SIZE 28
2258 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
2259 
2260 #define GNN_ID_SNS_SCMD_LEN 6
2261 #define GNN_ID_SNS_CMD_SIZE 28
2262 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
2263 
2264 struct sns_cmd_pkt {
2265  union {
2266  struct {
2267  uint16_t buffer_length;
2268  uint16_t reserved_1;
2269  uint32_t buffer_address[2];
2270  uint16_t subcommand_length;
2271  uint16_t reserved_2;
2272  uint16_t subcommand;
2273  uint16_t size;
2274  uint32_t reserved_3;
2275  uint8_t param[36];
2276  } cmd;
2277 
2278  uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2279  uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2280  uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2281  uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2282  uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2283  uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2284  } p;
2285 };
2286 
2287 struct fw_blob {
2288  char *name;
2289  uint32_t segs[4];
2290  const struct firmware *fw;
2291 };
2292 
2293 /* Return data from MBC_GET_ID_LIST call. */
2294 struct gid_list_info {
2295  uint8_t al_pa;
2296  uint8_t area;
2297  uint8_t domain;
2298  uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2299  uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2300  uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2301 };
2302 
2303 /* NPIV */
2304 typedef struct vport_info {
2305  uint8_t port_name[WWN_SIZE];
2306  uint8_t node_name[WWN_SIZE];
2307  int vp_id;
2308  uint16_t loop_id;
2309  unsigned long host_no;
2310  uint8_t port_id[3];
2311  int loop_state;
2312 } vport_info_t;
2313 
2314 typedef struct vport_params {
2315  uint8_t port_name[WWN_SIZE];
2316  uint8_t node_name[WWN_SIZE];
2317  uint32_t options;
2318 #define VP_OPTS_RETRY_ENABLE BIT_0
2319 #define VP_OPTS_VP_DISABLE BIT_1
2320 } vport_params_t;
2321 
2322 /* NPIV - return codes of VP create and modify */
2323 #define VP_RET_CODE_OK 0
2324 #define VP_RET_CODE_FATAL 1
2325 #define VP_RET_CODE_WRONG_ID 2
2326 #define VP_RET_CODE_WWPN 3
2327 #define VP_RET_CODE_RESOURCES 4
2328 #define VP_RET_CODE_NO_MEM 5
2329 #define VP_RET_CODE_NOT_FOUND 6
2330 
2331 struct qla_hw_data;
2332 struct rsp_que;
2333 /*
2334  * ISP operations
2335  */
2336 struct isp_operations {
2337 
2338  int (*pci_config) (struct scsi_qla_host *);
2339  void (*reset_chip) (struct scsi_qla_host *);
2340  int (*chip_diag) (struct scsi_qla_host *);
2341  void (*config_rings) (struct scsi_qla_host *);
2342  void (*reset_adapter) (struct scsi_qla_host *);
2343  int (*nvram_config) (struct scsi_qla_host *);
2344  void (*update_fw_options) (struct scsi_qla_host *);
2345  int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2346 
2347  char * (*pci_info_str) (struct scsi_qla_host *, char *);
2348  char * (*fw_version_str) (struct scsi_qla_host *, char *);
2349 
2350  irq_handler_t intr_handler;
2351  void (*enable_intrs) (struct qla_hw_data *);
2352  void (*disable_intrs) (struct qla_hw_data *);
2353 
2354  int (*abort_command) (srb_t *);
2355  int (*target_reset) (struct fc_port *, unsigned int, int);
2356  int (*lun_reset) (struct fc_port *, unsigned int, int);
2357  int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2358  uint8_t, uint8_t, uint16_t *, uint8_t);
2359  int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2360  uint8_t, uint8_t);
2361 
2362  uint16_t (*calc_req_entries) (uint16_t);
2363  void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2364  void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2365  void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2366  uint32_t);
2367 
2368  uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2369  uint32_t, uint32_t);
2370  int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2371  uint32_t);
2372 
2373  void (*fw_dump) (struct scsi_qla_host *, int);
2374 
2375  int (*beacon_on) (struct scsi_qla_host *);
2376  int (*beacon_off) (struct scsi_qla_host *);
2377  void (*beacon_blink) (struct scsi_qla_host *);
2378 
2379  uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2380  uint32_t, uint32_t);
2381  int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2382  uint32_t);
2383 
2384  int (*get_flash_version) (struct scsi_qla_host *, void *);
2385  int (*start_scsi) (srb_t *);
2386  int (*abort_isp) (struct scsi_qla_host *);
2387  int (*iospace_config)(struct qla_hw_data*);
2388 };
2389 
2390 /* MSI-X Support *************************************************************/
2391 
2392 #define QLA_MSIX_CHIP_REV_24XX 3
2393 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2394 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2395 
2396 #define QLA_MSIX_DEFAULT 0x00
2397 #define QLA_MSIX_RSP_Q 0x01
2398 
2399 #define QLA_MIDX_DEFAULT 0
2400 #define QLA_MIDX_RSP_Q 1
2401 #define QLA_PCI_MSIX_CONTROL 0xa2
2402 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
2403 
2404 struct scsi_qla_host;
2405 
2406 struct qla_msix_entry {
2407  int have_irq;
2408  uint32_t vector;
2409  uint16_t entry;
2410  struct rsp_que *rsp;
2411 };
2412 
2413 #define WATCH_INTERVAL 1 /* number of seconds */
2414 
2415 /* Work events. */
2416 enum qla_work_type {
2417  QLA_EVT_AEN,
2418  QLA_EVT_IDC_ACK,
2419  QLA_EVT_ASYNC_LOGIN,
2420  QLA_EVT_ASYNC_LOGIN_DONE,
2421  QLA_EVT_ASYNC_LOGOUT,
2422  QLA_EVT_ASYNC_LOGOUT_DONE,
2423  QLA_EVT_ASYNC_ADISC,
2424  QLA_EVT_ASYNC_ADISC_DONE,
2425  QLA_EVT_UEVENT,
2426 };
2427 
2428 
2429 struct qla_work_evt {
2430  struct list_head list;
2431  enum qla_work_type type;
2432  u32 flags;
2433 #define QLA_EVT_FLAG_FREE 0x1
2434 
2435  union {
2436  struct {
2437  enum fc_host_event_code code;
2438  u32 data;
2439  } aen;
2440  struct {
2441 #define QLA_IDC_ACK_REGS 7
2442  uint16_t mb[QLA_IDC_ACK_REGS];
2443  } idc_ack;
2444  struct {
2445  struct fc_port *fcport;
2446 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
2447  u16 data[2];
2448  } logio;
2449  struct {
2450  u32 code;
2451 #define QLA_UEVENT_CODE_FW_DUMP 0
2452  } uevent;
2453  } u;
2454 };
2455 
2456 struct qla_chip_state_84xx {
2457  struct list_head list;
2458  struct kref kref;
2459 
2460  void *bus;
2461  spinlock_t access_lock;
2462  struct mutex fw_update_mutex;
2463  uint32_t fw_update;
2464  uint32_t op_fw_version;
2465  uint32_t op_fw_size;
2466  uint32_t op_fw_seq_size;
2467  uint32_t diag_fw_version;
2468  uint32_t gold_fw_version;
2469 };
2470 
2471 struct qla_statistics {
2472  uint32_t total_isp_aborts;
2473  uint64_t input_bytes;
2474  uint64_t output_bytes;
2475 };
2476 
2477 struct bidi_statistics {
2478  unsigned long long io_count;
2479  unsigned long long transfer_bytes;
2480 };
2481 
2482 /* Multi queue support */
2483 #define MBC_INITIALIZE_MULTIQ 0x1f
2484 #define QLA_QUE_PAGE 0X1000
2485 #define QLA_MQ_SIZE 32
2486 #define QLA_MAX_QUEUES 256
2487 #define ISP_QUE_REG(ha, id) \
2488  ((ha->mqenable || IS_QLA83XX(ha)) ? \
2489  ((void *)(ha->mqiobase) +\
2490  (QLA_QUE_PAGE * id)) :\
2491  ((void *)(ha->iobase)))
2492 #define QLA_REQ_QUE_ID(tag) \
2493  ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2494 #define QLA_DEFAULT_QUE_QOS 5
2495 #define QLA_PRECONFIG_VPORTS 32
2496 #define QLA_MAX_VPORTS_QLA24XX 128
2497 #define QLA_MAX_VPORTS_QLA25XX 256
2498 /* Response queue data structure */
2499 struct rsp_que {
2500  dma_addr_t dma;
2501  response_t *ring;
2502  response_t *ring_ptr;
2503  uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2504  uint32_t __iomem *rsp_q_out;
2505  uint16_t ring_index;
2506  uint16_t out_ptr;
2507  uint16_t length;
2508  uint16_t options;
2509  uint16_t rid;
2510  uint16_t id;
2511  uint16_t vp_idx;
2512  struct qla_hw_data *hw;
2513  struct qla_msix_entry *msix;
2514  struct req_que *req;
2515  srb_t *status_srb; /* status continuation entry */
2516  struct work_struct q_work;
2517 };
2518 
2519 /* Request queue data structure */
2520 struct req_que {
2521  dma_addr_t dma;
2522  request_t *ring;
2523  request_t *ring_ptr;
2524  uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2525  uint32_t __iomem *req_q_out;
2526  uint16_t ring_index;
2527  uint16_t in_ptr;
2528  uint16_t cnt;
2529  uint16_t length;
2530  uint16_t options;
2531  uint16_t rid;
2532  uint16_t id;
2533  uint16_t qos;
2534  uint16_t vp_idx;
2535  struct rsp_que *rsp;
2536  srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2537  uint32_t current_outstanding_cmd;
2538  int max_q_depth;
2539 };
2540 
2541 /* Place holder for FW buffer parameters */
2542 struct qlfc_fw {
2543  void *fw_buf;
2544  dma_addr_t fw_dma;
2545  uint32_t len;
2546 };
2547 
2548 struct qlt_hw_data {
2549  /* Protected by hw lock */
2550  uint32_t enable_class_2:1;
2551  uint32_t enable_explicit_conf:1;
2552  uint32_t ini_mode_force_reverse:1;
2553  uint32_t node_name_set:1;
2554 
2555  dma_addr_t atio_dma; /* Physical address. */
2556  struct atio *atio_ring; /* Base virtual address */
2557  struct atio *atio_ring_ptr; /* Current address. */
2558  uint16_t atio_ring_index; /* Current index. */
2559  uint16_t atio_q_length;
2560 
2561  void *target_lport_ptr;
2562  struct qla_tgt_func_tmpl *tgt_ops;
2563  struct qla_tgt *qla_tgt;
2564  struct qla_tgt_cmd *cmds[MAX_OUTSTANDING_COMMANDS];
2565  uint16_t current_handle;
2566 
2567  struct qla_tgt_vp_map *tgt_vp_map;
2568  struct mutex tgt_mutex;
2569  struct mutex tgt_host_action_mutex;
2570 
2571  int saved_set;
2572  uint16_t saved_exchange_count;
2573  uint32_t saved_firmware_options_1;
2574  uint32_t saved_firmware_options_2;
2575  uint32_t saved_firmware_options_3;
2576  uint8_t saved_firmware_options[2];
2577  uint8_t saved_add_firmware_options[2];
2578 
2579  uint8_t tgt_node_name[WWN_SIZE];
2580 };
2581 
2582 /*
2583  * Qlogic host adapter specific data structure.
2584 */
2585 struct qla_hw_data {
2586  struct pci_dev *pdev;
2587  /* SRB cache. */
2588 #define SRB_MIN_REQ 128
2589  mempool_t *srb_mempool;
2590 
2591  volatile struct {
2592  uint32_t mbox_int :1;
2593  uint32_t mbox_busy :1;
2594  uint32_t disable_risc_code_load :1;
2595  uint32_t enable_64bit_addressing :1;
2596  uint32_t enable_lip_reset :1;
2597  uint32_t enable_target_reset :1;
2598  uint32_t enable_lip_full_login :1;
2599  uint32_t enable_led_scheme :1;
2600 
2601  uint32_t msi_enabled :1;
2602  uint32_t msix_enabled :1;
2603  uint32_t disable_serdes :1;
2604  uint32_t gpsc_supported :1;
2605  uint32_t npiv_supported :1;
2606  uint32_t pci_channel_io_perm_failure :1;
2607  uint32_t fce_enabled :1;
2608  uint32_t fac_supported :1;
2609 
2610  uint32_t chip_reset_done :1;
2611  uint32_t port0 :1;
2612  uint32_t running_gold_fw :1;
2613  uint32_t eeh_busy :1;
2614  uint32_t cpu_affinity_enabled :1;
2615  uint32_t disable_msix_handshake :1;
2616  uint32_t fcp_prio_enabled :1;
2617  uint32_t isp82xx_fw_hung:1;
2618  uint32_t nic_core_hung:1;
2619 
2620  uint32_t quiesce_owner:1;
2621  uint32_t thermal_supported:1;
2622  uint32_t nic_core_reset_hdlr_active:1;
2623  uint32_t nic_core_reset_owner:1;
2624  uint32_t isp82xx_no_md_cap:1;
2625  uint32_t host_shutting_down:1;
2626  uint32_t idc_compl_status:1;
2627  /* 32 bits */
2628  } flags;
2629 
2630  /* This spinlock is used to protect "io transactions", you must
2631  * acquire it before doing any IO to the card, eg with RD_REG*() and
2632  * WRT_REG*() for the duration of your entire commandtransaction.
2633  *
2634  * This spinlock is of lower priority than the io request lock.
2635  */
2636 
2637  spinlock_t hardware_lock ____cacheline_aligned;
2638  int bars;
2639  int mem_only;
2640  device_reg_t __iomem *iobase; /* Base I/O address */
2641  resource_size_t pio_address;
2642 
2643 #define MIN_IOBASE_LEN 0x100
2644 /* Multi queue data structs */
2645  device_reg_t __iomem *mqiobase;
2646  device_reg_t __iomem *msixbase;
2647  uint16_t msix_count;
2648  uint8_t mqenable;
2649  struct req_que **req_q_map;
2650  struct rsp_que **rsp_q_map;
2651  unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2652  unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2653  uint8_t max_req_queues;
2654  uint8_t max_rsp_queues;
2655  struct qla_npiv_entry *npiv_info;
2656  uint16_t nvram_npiv_size;
2657 
2658  uint16_t switch_cap;
2659 #define FLOGI_SEQ_DEL BIT_8
2660 #define FLOGI_MID_SUPPORT BIT_10
2661 #define FLOGI_VSAN_SUPPORT BIT_12
2662 #define FLOGI_SP_SUPPORT BIT_13
2663 
2664  uint8_t port_no; /* Physical port of adapter */
2665 
2666  /* Timeout timers. */
2667  uint8_t loop_down_abort_time; /* port down timer */
2668  atomic_t loop_down_timer; /* loop down timer */
2669  uint8_t link_down_timeout; /* link down timeout */
2670  uint16_t max_loop_id;
2671  uint16_t max_fibre_devices; /* Maximum number of targets */
2672 
2673  uint16_t fb_rev;
2674  uint16_t min_external_loopid; /* First external loop Id */
2675 
2676 #define PORT_SPEED_UNKNOWN 0xFFFF
2677 #define PORT_SPEED_1GB 0x00
2678 #define PORT_SPEED_2GB 0x01
2679 #define PORT_SPEED_4GB 0x03
2680 #define PORT_SPEED_8GB 0x04
2681 #define PORT_SPEED_16GB 0x05
2682 #define PORT_SPEED_10GB 0x13
2683  uint16_t link_data_rate; /* F/W operating speed */
2684 
2685  uint8_t current_topology;
2686  uint8_t prev_topology;
2687 #define ISP_CFG_NL 1
2688 #define ISP_CFG_N 2
2689 #define ISP_CFG_FL 4
2690 #define ISP_CFG_F 8
2691 
2692  uint8_t operating_mode; /* F/W operating mode */
2693 #define LOOP 0
2694 #define P2P 1
2695 #define LOOP_P2P 2
2696 #define P2P_LOOP 3
2697  uint8_t interrupts_on;
2698  uint32_t isp_abort_cnt;
2699 
2700 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2701 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2702 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2703 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
2704 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
2705  uint32_t device_type;
2706 #define DT_ISP2100 BIT_0
2707 #define DT_ISP2200 BIT_1
2708 #define DT_ISP2300 BIT_2
2709 #define DT_ISP2312 BIT_3
2710 #define DT_ISP2322 BIT_4
2711 #define DT_ISP6312 BIT_5
2712 #define DT_ISP6322 BIT_6
2713 #define DT_ISP2422 BIT_7
2714 #define DT_ISP2432 BIT_8
2715 #define DT_ISP5422 BIT_9
2716 #define DT_ISP5432 BIT_10
2717 #define DT_ISP2532 BIT_11
2718 #define DT_ISP8432 BIT_12
2719 #define DT_ISP8001 BIT_13
2720 #define DT_ISP8021 BIT_14
2721 #define DT_ISP2031 BIT_15
2722 #define DT_ISP8031 BIT_16
2723 #define DT_ISP_LAST (DT_ISP8031 << 1)
2724 
2725 #define DT_T10_PI BIT_25
2726 #define DT_IIDMA BIT_26
2727 #define DT_FWI2 BIT_27
2728 #define DT_ZIO_SUPPORTED BIT_28
2729 #define DT_OEM_001 BIT_29
2730 #define DT_ISP2200A BIT_30
2731 #define DT_EXTENDED_IDS BIT_31
2732 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2733 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2734 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2735 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2736 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2737 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2738 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2739 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2740 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2741 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2742 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2743 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2744 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2745 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2746 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2747 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
2748 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
2749 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
2750 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
2751 
2752 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2753  IS_QLA6312(ha) || IS_QLA6322(ha))
2754 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2755 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2756 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
2757 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
2758 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
2759 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2760  IS_QLA84XX(ha))
2761 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
2762  IS_QLA8031(ha))
2763 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2764  IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2765  IS_QLA82XX(ha) || IS_QLA83XX(ha))
2766 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2767 #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2768  IS_QLA83XX(ha)) && (ha)->flags.msix_enabled)
2769 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2770 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2771 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
2772 
2773 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
2774 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2775 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2776 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2777 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2778 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2779 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
2780 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha))
2781 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha)))
2782 /* Bit 21 of fw_attributes decides the MCTP capabilities */
2783 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
2784  ((ha)->fw_attributes_ext[0] & BIT_0))
2785 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha))
2786 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha))
2787 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
2788 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha))
2789 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
2790  (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
2791 
2792  /* HBA serial number */
2793  uint8_t serial0;
2794  uint8_t serial1;
2795  uint8_t serial2;
2796 
2797  /* NVRAM configuration data */
2798 #define MAX_NVRAM_SIZE 4096
2799 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
2800  uint16_t nvram_size;
2801  uint16_t nvram_base;
2802  void *nvram;
2803  uint16_t vpd_size;
2804  uint16_t vpd_base;
2805  void *vpd;
2806 
2807  uint16_t loop_reset_delay;
2808  uint8_t retry_count;
2809  uint8_t login_timeout;
2810  uint16_t r_a_tov;
2811  int port_down_retry_count;
2812  uint8_t mbx_count;
2813 
2814  uint32_t login_retry_count;
2815  /* SNS command interfaces. */
2816  ms_iocb_entry_t *ms_iocb;
2817  dma_addr_t ms_iocb_dma;
2818  struct ct_sns_pkt *ct_sns;
2819  dma_addr_t ct_sns_dma;
2820  /* SNS command interfaces for 2200. */
2821  struct sns_cmd_pkt *sns_cmd;
2822  dma_addr_t sns_cmd_dma;
2823 
2824 #define SFP_DEV_SIZE 256
2825 #define SFP_BLOCK_SIZE 64
2826  void *sfp_data;
2827  dma_addr_t sfp_data_dma;
2828 
2829 #define XGMAC_DATA_SIZE 4096
2830  void *xgmac_data;
2831  dma_addr_t xgmac_data_dma;
2832 
2833 #define DCBX_TLV_DATA_SIZE 4096
2834  void *dcbx_tlv;
2835  dma_addr_t dcbx_tlv_dma;
2836 
2837  struct task_struct *dpc_thread;
2838  uint8_t dpc_active; /* DPC routine is active */
2839 
2840  dma_addr_t gid_list_dma;
2841  struct gid_list_info *gid_list;
2842  int gid_list_info_size;
2843 
2844  /* Small DMA pool allocations -- maximum 256 bytes in length. */
2845 #define DMA_POOL_SIZE 256
2846  struct dma_pool *s_dma_pool;
2847 
2848  dma_addr_t init_cb_dma;
2849  init_cb_t *init_cb;
2850  int init_cb_size;
2851  dma_addr_t ex_init_cb_dma;
2852  struct ex_init_cb_81xx *ex_init_cb;
2853 
2854  void *async_pd;
2855  dma_addr_t async_pd_dma;
2856 
2857  void *swl;
2858 
2859  /* These are used by mailbox operations. */
2860  volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2861 
2862  mbx_cmd_t *mcp;
2863  unsigned long mbx_cmd_flags;
2864 #define MBX_INTERRUPT 1
2865 #define MBX_INTR_WAIT 2
2866 #define MBX_UPDATE_FLASH_ACTIVE 3
2867 
2868  struct mutex vport_lock; /* Virtual port synchronization */
2869  spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
2870  struct completion mbx_cmd_comp; /* Serialize mbx access */
2871  struct completion mbx_intr_comp; /* Used for completion notification */
2872  struct completion dcbx_comp; /* For set port config notification */
2873  int notify_dcbx_comp;
2874  struct mutex selflogin_lock;
2875 
2876  /* Basic firmware related information. */
2877  uint16_t fw_major_version;
2878  uint16_t fw_minor_version;
2879  uint16_t fw_subminor_version;
2880  uint16_t fw_attributes;
2881  uint16_t fw_attributes_h;
2882  uint16_t fw_attributes_ext[2];
2883  uint32_t fw_memory_size;
2884  uint32_t fw_transfer_size;
2885  uint32_t fw_srisc_address;
2886 #define RISC_START_ADDRESS_2100 0x1000
2887 #define RISC_START_ADDRESS_2300 0x800
2888 #define RISC_START_ADDRESS_2400 0x100000
2889  uint16_t fw_xcb_count;
2890 
2891  uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2892  uint8_t fw_seriallink_options[4];
2893  uint16_t fw_seriallink_options24[4];
2894 
2895  uint8_t mpi_version[3];
2896  uint32_t mpi_capabilities;
2897  uint8_t phy_version[3];
2898 
2899  /* Firmware dump information. */
2900  struct qla2xxx_fw_dump *fw_dump;
2901  uint32_t fw_dump_len;
2902  int fw_dumped;
2903  int fw_dump_reading;
2904  dma_addr_t eft_dma;
2905  void *eft;
2906 /* Current size of mctp dump is 0x086064 bytes */
2907 #define MCTP_DUMP_SIZE 0x086064
2908  dma_addr_t mctp_dump_dma;
2909  void *mctp_dump;
2910  int mctp_dumped;
2911  int mctp_dump_reading;
2912  uint32_t chain_offset;
2913  struct dentry *dfs_dir;
2914  struct dentry *dfs_fce;
2915  dma_addr_t fce_dma;
2916  void *fce;
2917  uint32_t fce_bufs;
2918  uint16_t fce_mb[8];
2919  uint64_t fce_wr, fce_rd;
2920  struct mutex fce_mutex;
2921 
2922  uint32_t pci_attr;
2923  uint16_t chip_revision;
2924 
2925  uint16_t product_id[4];
2926 
2927  uint8_t model_number[16+1];
2928 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2929  char model_desc[80];
2930  uint8_t adapter_id[16+1];
2931 
2932  /* Option ROM information. */
2933  char *optrom_buffer;
2934  uint32_t optrom_size;
2935  int optrom_state;
2936 #define QLA_SWAITING 0
2937 #define QLA_SREADING 1
2938 #define QLA_SWRITING 2
2939  uint32_t optrom_region_start;
2940  uint32_t optrom_region_size;
2941 
2942 /* PCI expansion ROM image information. */
2943 #define ROM_CODE_TYPE_BIOS 0
2944 #define ROM_CODE_TYPE_FCODE 1
2945 #define ROM_CODE_TYPE_EFI 3
2946  uint8_t bios_revision[2];
2947  uint8_t efi_revision[2];
2948  uint8_t fcode_revision[16];
2949  uint32_t fw_revision[4];
2950 
2951  uint32_t gold_fw_version[4];
2952 
2953  /* Offsets for flash/nvram access (set to ~0 if not used). */
2954  uint32_t flash_conf_off;
2955  uint32_t flash_data_off;
2956  uint32_t nvram_conf_off;
2957  uint32_t nvram_data_off;
2958 
2959  uint32_t fdt_wrt_disable;
2960  uint32_t fdt_erase_cmd;
2961  uint32_t fdt_block_size;
2962  uint32_t fdt_unprotect_sec_cmd;
2963  uint32_t fdt_protect_sec_cmd;
2964 
2965  uint32_t flt_region_flt;
2966  uint32_t flt_region_fdt;
2967  uint32_t flt_region_boot;
2968  uint32_t flt_region_fw;
2969  uint32_t flt_region_vpd_nvram;
2970  uint32_t flt_region_vpd;
2971  uint32_t flt_region_nvram;
2972  uint32_t flt_region_npiv_conf;
2973  uint32_t flt_region_gold_fw;
2974  uint32_t flt_region_fcp_prio;
2975  uint32_t flt_region_bootload;
2976 
2977  /* Needed for BEACON */
2978  uint16_t beacon_blink_led;
2979  uint8_t beacon_color_state;
2980 #define QLA_LED_GRN_ON 0x01
2981 #define QLA_LED_YLW_ON 0x02
2982 #define QLA_LED_ABR_ON 0x04
2983 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2984  /* ISP2322: red, green, amber. */
2985  uint16_t zio_mode;
2986  uint16_t zio_timer;
2987 
2988  struct qla_msix_entry *msix_entries;
2989 
2990  struct list_head vp_list; /* list of VP */
2991  unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
2992  sizeof(unsigned long)];
2993  uint16_t num_vhosts; /* number of vports created */
2994  uint16_t num_vsans; /* number of vsan created */
2995  uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
2996  int cur_vport_count;
2997 
2998  struct qla_chip_state_84xx *cs84xx;
2999  struct isp_operations *isp_ops;
3000  struct workqueue_struct *wq;
3001  struct qlfc_fw fw_buf;
3002 
3003  /* FCP_CMND priority support */
3004  struct qla_fcp_prio_cfg *fcp_prio_cfg;
3005 
3006  struct dma_pool *dl_dma_pool;
3007 #define DSD_LIST_DMA_POOL_SIZE 512
3008 
3009  struct dma_pool *fcp_cmnd_dma_pool;
3010  mempool_t *ctx_mempool;
3011 #define FCP_CMND_DMA_POOL_SIZE 512
3012 
3013  unsigned long nx_pcibase; /* Base I/O address */
3014  uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */
3015  unsigned long nxdb_wr_ptr; /* Door bell write pointer */
3016 
3017  uint32_t crb_win;
3018  uint32_t curr_window;
3019  uint32_t ddr_mn_window;
3020  unsigned long mn_win_crb;
3021  unsigned long ms_win_crb;
3022  int qdr_sn_window;
3023  uint32_t fcoe_dev_init_timeout;
3024  uint32_t fcoe_reset_timeout;
3025  rwlock_t hw_lock;
3026  uint16_t portnum; /* port number */
3027  int link_width;
3028  struct fw_blob *hablob;
3029  struct qla82xx_legacy_intr_set nx_legacy_intr;
3030 
3031  uint16_t gbl_dsd_inuse;
3032  uint16_t gbl_dsd_avail;
3033  struct list_head gbl_dsd_list;
3034 #define NUM_DSD_CHAIN 4096
3035 
3036  uint8_t fw_type;
3037  __le32 file_prd_off; /* File firmware product offset */
3038 
3039  uint32_t md_template_size;
3040  void *md_tmplt_hdr;
3041  dma_addr_t md_tmplt_hdr_dma;
3042  void *md_dump;
3043  uint32_t md_dump_size;
3044 
3045  void *loop_id_map;
3046 
3047  /* QLA83XX IDC specific fields */
3048  uint32_t idc_audit_ts;
3049 
3050  /* DPC low-priority workqueue */
3051  struct workqueue_struct *dpc_lp_wq;
3052  struct work_struct idc_aen;
3053  /* DPC high-priority workqueue */
3054  struct workqueue_struct *dpc_hp_wq;
3055  struct work_struct nic_core_reset;
3056  struct work_struct idc_state_handler;
3057  struct work_struct nic_core_unrecoverable;
3058 
3059  struct qlt_hw_data tgt;
3060 };
3061 
3062 /*
3063  * Qlogic scsi host structure
3064  */
3065 typedef struct scsi_qla_host {
3066  struct list_head list;
3067  struct list_head vp_fcports; /* list of fcports */
3068  struct list_head work_list;
3069  spinlock_t work_lock;
3070 
3071  /* Commonly used flags and state information. */
3072  struct Scsi_Host *host;
3073  unsigned long host_no;
3074  uint8_t host_str[16];
3075 
3076  volatile struct {
3077  uint32_t init_done :1;
3078  uint32_t online :1;
3079  uint32_t reset_active :1;
3080 
3081  uint32_t management_server_logged_in :1;
3082  uint32_t process_response_queue :1;
3083  uint32_t difdix_supported:1;
3084  uint32_t delete_progress:1;
3085  } flags;
3086 
3087  atomic_t loop_state;
3088 #define LOOP_TIMEOUT 1
3089 #define LOOP_DOWN 2
3090 #define LOOP_UP 3
3091 #define LOOP_UPDATE 4
3092 #define LOOP_READY 5
3093 #define LOOP_DEAD 6
3094 
3095  unsigned long dpc_flags;
3096 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
3097 #define RESET_ACTIVE 1
3098 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
3099 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
3100 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
3101 #define LOOP_RESYNC_ACTIVE 5
3102 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
3103 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
3104 #define RELOGIN_NEEDED 8
3105 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
3106 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
3107 #define BEACON_BLINK_NEEDED 11
3108 #define REGISTER_FDMI_NEEDED 12
3109 #define FCPORT_UPDATE_NEEDED 13
3110 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
3111 #define UNLOADING 15
3112 #define NPIV_CONFIG_NEEDED 16
3113 #define ISP_UNRECOVERABLE 17
3114 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
3115 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
3116 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
3117 #define SCR_PENDING 21 /* SCR in target mode */
3118 
3119  uint32_t device_flags;
3120 #define SWITCH_FOUND BIT_0
3121 #define DFLG_NO_CABLE BIT_1
3122 #define DFLG_DEV_FAILED BIT_5
3123 
3124  /* ISP configuration data. */
3125  uint16_t loop_id; /* Host adapter loop id */
3126  uint16_t self_login_loop_id; /* host adapter loop id
3127  * get it on self login
3128  */
3129  fc_port_t bidir_fcport; /* fcport used for bidir cmnds
3130  * no need of allocating it for
3131  * each command
3132  */
3133 
3134  port_id_t d_id; /* Host adapter port id */
3135  uint8_t marker_needed;
3136  uint16_t mgmt_svr_loop_id;
3137 
3138 
3139 
3140  /* Timeout timers. */
3141  uint8_t loop_down_abort_time; /* port down timer */
3142  atomic_t loop_down_timer; /* loop down timer */
3143  uint8_t link_down_timeout; /* link down timeout */
3144 
3145  uint32_t timer_active;
3146  struct timer_list timer;
3147 
3148  uint8_t node_name[WWN_SIZE];
3149  uint8_t port_name[WWN_SIZE];
3150  uint8_t fabric_node_name[WWN_SIZE];
3151 
3152  uint16_t fcoe_vlan_id;
3153  uint16_t fcoe_fcf_idx;
3154  uint8_t fcoe_vn_port_mac[6];
3155 
3156  uint32_t vp_abort_cnt;
3157 
3158  struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
3159  uint16_t vp_idx; /* vport ID */
3160 
3161  unsigned long vp_flags;
3162 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
3163 #define VP_CREATE_NEEDED 1
3164 #define VP_BIND_NEEDED 2
3165 #define VP_DELETE_NEEDED 3
3166 #define VP_SCR_NEEDED 4 /* State Change Request registration */
3167  atomic_t vp_state;
3168 #define VP_OFFLINE 0
3169 #define VP_ACTIVE 1
3170 #define VP_FAILED 2
3171 // #define VP_DISABLE 3
3172  uint16_t vp_err_state;
3173  uint16_t vp_prev_err_state;
3174 #define VP_ERR_UNKWN 0
3175 #define VP_ERR_PORTDWN 1
3176 #define VP_ERR_FAB_UNSUPPORTED 2
3177 #define VP_ERR_FAB_NORESOURCES 3
3178 #define VP_ERR_FAB_LOGOUT 4
3179 #define VP_ERR_ADAP_NORESOURCES 5
3180  struct qla_hw_data *hw;
3181  struct req_que *req;
3182  int fw_heartbeat_counter;
3183  int seconds_since_last_heartbeat;
3184  struct fc_host_statistics fc_host_stat;
3185  struct qla_statistics qla_stats;
3186  struct bidi_statistics bidi_stats;
3187 
3188  atomic_t vref_count;
3189 } scsi_qla_host_t;
3190 
3191 #define SET_VP_IDX 1
3192 #define SET_AL_PA 2
3193 #define RESET_VP_IDX 3
3194 #define RESET_AL_PA 4
3195 struct qla_tgt_vp_map {
3196  uint8_t idx;
3197  scsi_qla_host_t *vha;
3198 };
3199 
3200 /*
3201  * Macros to help code, maintain, etc.
3202  */
3203 #define LOOP_TRANSITION(ha) \
3204  (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
3205  test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
3206  atomic_read(&ha->loop_state) == LOOP_DOWN)
3207 
3208 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
3209  atomic_inc(&__vha->vref_count); \
3210  mb(); \
3211  if (__vha->flags.delete_progress) { \
3212  atomic_dec(&__vha->vref_count); \
3213  __bail = 1; \
3214  } else { \
3215  __bail = 0; \
3216  } \
3217 } while (0)
3218 
3219 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
3220  atomic_dec(&__vha->vref_count); \
3221 } while (0)
3222 
3223 /*
3224  * qla2x00 local function return status codes
3225  */
3226 #define MBS_MASK 0x3fff
3227 
3228 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
3229 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
3230 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
3231 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
3232 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
3233 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
3234 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
3235 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
3236 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
3237 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
3238 
3239 #define QLA_FUNCTION_TIMEOUT 0x100
3240 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
3241 #define QLA_FUNCTION_FAILED 0x102
3242 #define QLA_MEMORY_ALLOC_FAILED 0x103
3243 #define QLA_LOCK_TIMEOUT 0x104
3244 #define QLA_ABORTED 0x105
3245 #define QLA_SUSPENDED 0x106
3246 #define QLA_BUSY 0x107
3247 #define QLA_ALREADY_REGISTERED 0x109
3248 
3249 #define NVRAM_DELAY() udelay(10)
3250 
3251 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
3252 
3253 /*
3254  * Flash support definitions
3255  */
3256 #define OPTROM_SIZE_2300 0x20000
3257 #define OPTROM_SIZE_2322 0x100000
3258 #define OPTROM_SIZE_24XX 0x100000
3259 #define OPTROM_SIZE_25XX 0x200000
3260 #define OPTROM_SIZE_81XX 0x400000
3261 #define OPTROM_SIZE_82XX 0x800000
3262 #define OPTROM_SIZE_83XX 0x1000000
3263 
3264 #define OPTROM_BURST_SIZE 0x1000
3265 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
3266 
3267 #define QLA_DSDS_PER_IOCB 37
3268 
3269 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
3270 
3271 #define QLA_SG_ALL 1024
3272 
3273 enum nexus_wait_type {
3274  WAIT_HOST = 0,
3275  WAIT_TARGET,
3276  WAIT_LUN,
3277 };
3278 
3279 #include "qla_gbl.h"
3280 #include "qla_dbg.h"
3281 #include "qla_inline.h"
3282 #endif
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