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23 #ifndef __LINUX_XHCI_HCD_H
24 #define __LINUX_XHCI_HCD_H
28 #include <linux/kernel.h>
36 #define XHCI_SBRN_OFFSET (0x60)
39 #define MAX_HC_SLOTS 256
41 #define MAX_HC_PORTS 127
72 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
74 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
78 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
79 #define HCS_SLOTS_MASK 0xff
81 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
83 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
88 #define HCS_IST(p) (((p) >> 0) & 0xf)
90 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
93 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
97 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
99 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
103 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
105 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
109 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
111 #define HCC_PPC(p) ((p) & (1 << 3))
113 #define HCS_INDICATOR(p) ((p) & (1 << 4))
115 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
117 #define HCC_LTC(p) ((p) & (1 << 6))
119 #define HCC_NSS(p) ((p) & (1 << 7))
121 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
123 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
126 #define DBOFF_MASK (~0x3)
129 #define RTSOFF_MASK (~0x1f)
133 #define NUM_PORT_REGS 4
182 #define CMD_RUN XHCI_CMD_RUN
187 #define CMD_RESET (1 << 1)
189 #define CMD_EIE XHCI_CMD_EIE
191 #define CMD_HSEIE XHCI_CMD_HSEIE
194 #define CMD_LRESET (1 << 7)
196 #define CMD_CSS (1 << 8)
197 #define CMD_CRS (1 << 9)
199 #define CMD_EWE XHCI_CMD_EWE
205 #define CMD_PM_INDEX (1 << 11)
209 #define IMAN_IP (1 << 1)
210 #define IMAN_IE (1 << 0)
214 #define STS_HALT XHCI_STS_HALT
216 #define STS_FATAL (1 << 2)
218 #define STS_EINT (1 << 3)
220 #define STS_PORT (1 << 4)
223 #define STS_SAVE (1 << 8)
225 #define STS_RESTORE (1 << 9)
227 #define STS_SRE (1 << 10)
229 #define STS_CNR XHCI_STS_CNR
231 #define STS_HCE (1 << 12)
239 #define DEV_NOTE_MASK (0xffff)
240 #define ENABLE_DEV_NOTE(x) (1 << (x))
244 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
249 #define CMD_RING_PAUSE (1 << 1)
251 #define CMD_RING_ABORT (1 << 2)
253 #define CMD_RING_RUNNING (1 << 3)
256 #define CMD_RING_RSVD_BITS (0x3f)
260 #define MAX_DEVS(p) ((p) & 0xff)
265 #define PORT_CONNECT (1 << 0)
267 #define PORT_PE (1 << 1)
270 #define PORT_OC (1 << 3)
272 #define PORT_RESET (1 << 4)
277 #define PORT_PLS_MASK (0xf << 5)
278 #define XDEV_U0 (0x0 << 5)
279 #define XDEV_U2 (0x2 << 5)
280 #define XDEV_U3 (0x3 << 5)
281 #define XDEV_RESUME (0xf << 5)
283 #define PORT_POWER (1 << 9)
292 #define DEV_SPEED_MASK (0xf << 10)
293 #define XDEV_FS (0x1 << 10)
294 #define XDEV_LS (0x2 << 10)
295 #define XDEV_HS (0x3 << 10)
296 #define XDEV_SS (0x4 << 10)
297 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
298 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
299 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
300 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
301 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
303 #define SLOT_SPEED_FS (XDEV_FS << 10)
304 #define SLOT_SPEED_LS (XDEV_LS << 10)
305 #define SLOT_SPEED_HS (XDEV_HS << 10)
306 #define SLOT_SPEED_SS (XDEV_SS << 10)
308 #define PORT_LED_OFF (0 << 14)
309 #define PORT_LED_AMBER (1 << 14)
310 #define PORT_LED_GREEN (2 << 14)
311 #define PORT_LED_MASK (3 << 14)
313 #define PORT_LINK_STROBE (1 << 16)
315 #define PORT_CSC (1 << 17)
317 #define PORT_PEC (1 << 18)
323 #define PORT_WRC (1 << 19)
325 #define PORT_OCC (1 << 20)
327 #define PORT_RC (1 << 21)
341 #define PORT_PLC (1 << 22)
343 #define PORT_CEC (1 << 23)
348 #define PORT_CAS (1 << 24)
350 #define PORT_WKCONN_E (1 << 25)
352 #define PORT_WKDISC_E (1 << 26)
354 #define PORT_WKOC_E (1 << 27)
357 #define PORT_DEV_REMOVE (1 << 30)
359 #define PORT_WR (1 << 31)
362 #define DUPLICATE_ENTRY ((u8)(-1))
368 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
369 #define PORT_U1_TIMEOUT_MASK 0xff
371 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
372 #define PORT_U2_TIMEOUT_MASK (0xff << 8)
376 #define PORT_L1S_MASK 7
377 #define PORT_L1S_SUCCESS 1
378 #define PORT_RWE (1 << 3)
379 #define PORT_HIRD(p) (((p) & 0xf) << 4)
380 #define PORT_HIRD_MASK (0xf << 4)
381 #define PORT_L1DS(p) (((p) & 0xff) << 8)
382 #define PORT_HLE (1 << 16)
411 #define ER_IRQ_PENDING(p) ((p) & 0x1)
414 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
415 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
416 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
423 #define ER_IRQ_INTERVAL_MASK (0xffff)
425 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
429 #define ERST_SIZE_MASK (0xffff << 16)
435 #define ERST_DESI_MASK (0x7)
439 #define ERST_EHB (1 << 3)
440 #define ERST_PTR_MASK (0xf)
470 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
471 #define DB_VALUE_HOST 0x00000000
487 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
488 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
489 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
503 #define XHCI_CTX_TYPE_DEVICE 0x1
504 #define XHCI_CTX_TYPE_INPUT 0x2
534 #define ROUTE_STRING_MASK (0xfffff)
536 #define DEV_SPEED (0xf << 20)
539 #define DEV_MTT (0x1 << 25)
541 #define DEV_HUB (0x1 << 26)
543 #define LAST_CTX_MASK (0x1f << 27)
544 #define LAST_CTX(p) ((p) << 27)
545 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
546 #define SLOT_FLAG (1 << 0)
547 #define EP0_FLAG (1 << 1)
551 #define MAX_EXIT (0xffff)
553 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
554 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
556 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
564 #define TT_SLOT (0xff)
569 #define TT_PORT (0xff << 8)
570 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
574 #define DEV_ADDR_MASK (0xff)
577 #define SLOT_STATE (0x1f << 27)
578 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
580 #define SLOT_STATE_DISABLED 0
581 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
582 #define SLOT_STATE_DEFAULT 1
583 #define SLOT_STATE_ADDRESSED 2
584 #define SLOT_STATE_CONFIGURED 3
623 #define EP_STATE_MASK (0xf)
624 #define EP_STATE_DISABLED 0
625 #define EP_STATE_RUNNING 1
626 #define EP_STATE_HALTED 2
627 #define EP_STATE_STOPPED 3
628 #define EP_STATE_ERROR 4
630 #define EP_MULT(p) (((p) & 0x3) << 8)
631 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
635 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
636 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
637 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
638 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
639 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
641 #define EP_HAS_LSA (1 << 15)
648 #define FORCE_EVENT (0x1)
649 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
650 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
651 #define EP_TYPE(p) ((p) << 3)
652 #define ISOC_OUT_EP 1
653 #define BULK_OUT_EP 2
661 #define MAX_BURST(p) (((p)&0xff) << 8)
662 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
663 #define MAX_PACKET(p) (((p)&0xffff) << 16)
664 #define MAX_PACKET_MASK (0xffff << 16)
665 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
670 #define GET_MAX_PACKET(p) ((p) & 0x7ff)
673 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
674 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
675 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
678 #define EP_CTX_CYCLE_MASK (1 << 0)
694 #define EP_IS_ADDED(ctrl_ctx, i) \
695 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
696 #define EP_IS_DROPPED(ctrl_ctx, i) \
697 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
716 #define DROP_EP(x) (0x1 << x)
718 #define ADD_EP(x) (0x1 << x)
728 #define SCT_FOR_CTX(p) (((p) << 1) & 0x7)
738 #define SCT_SSA_128 6
739 #define SCT_SSA_256 7
757 #define SMALL_STREAM_ARRAY_SIZE 256
758 #define MEDIUM_STREAM_ARRAY_SIZE 1024
792 #define DMI_OVERHEAD 8
793 #define DMI_OVERHEAD_BURST 4
794 #define SS_OVERHEAD 8
795 #define SS_OVERHEAD_BURST 32
796 #define HS_OVERHEAD 26
797 #define FS_OVERHEAD 20
798 #define LS_OVERHEAD 128
804 #define TT_HS_OVERHEAD (31 + 94)
805 #define TT_DMI_OVERHEAD (25 + 12)
808 #define FS_BW_LIMIT 1285
809 #define TT_BW_LIMIT 1320
810 #define HS_BW_LIMIT 1607
811 #define SS_BW_LIMIT_IN 3906
812 #define DMI_BW_LIMIT_IN 3906
813 #define SS_BW_LIMIT_OUT 3906
814 #define DMI_BW_LIMIT_OUT 3906
817 #define FS_BW_RESERVED 10
818 #define HS_BW_RESERVED 20
819 #define SS_BW_RESERVED 10
830 #define SET_DEQ_PENDING (1 << 0)
831 #define EP_HALTED (1 << 1)
832 #define EP_HALT_PENDING (1 << 2)
834 #define EP_GETTING_STREAMS (1 << 3)
835 #define EP_HAS_STREAMS (1 << 4)
837 #define EP_GETTING_NO_STREAMS (1 << 5)
883 #define XHCI_MAX_INTERVAL 16
913 #define XHCI_MAX_RINGS_CACHED 31
976 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
979 #define COMP_CODE_MASK (0xff << 24)
980 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
981 #define COMP_SUCCESS 1
983 #define COMP_DB_ERR 2
985 #define COMP_BABBLE 3
987 #define COMP_TX_ERR 4
989 #define COMP_TRB_ERR 5
993 #define COMP_ENOMEM 7
995 #define COMP_BW_ERR 8
997 #define COMP_ENOSLOTS 9
999 #define COMP_STREAM_ERR 10
1001 #define COMP_EBADSLT 11
1003 #define COMP_EBADEP 12
1005 #define COMP_SHORT_TX 13
1007 #define COMP_UNDERRUN 14
1009 #define COMP_OVERRUN 15
1011 #define COMP_VF_FULL 16
1013 #define COMP_EINVAL 17
1015 #define COMP_BW_OVER 18
1017 #define COMP_CTX_STATE 19
1019 #define COMP_PING_ERR 20
1021 #define COMP_ER_FULL 21
1023 #define COMP_DEV_ERR 22
1025 #define COMP_MISSED_INT 23
1027 #define COMP_CMD_STOP 24
1029 #define COMP_CMD_ABORT 25
1031 #define COMP_STOP 26
1033 #define COMP_STOP_INVAL 27
1035 #define COMP_DBG_ABORT 28
1037 #define COMP_MEL_ERR 29
1040 #define COMP_BUFF_OVER 31
1042 #define COMP_ISSUES 32
1044 #define COMP_UNKNOWN 33
1046 #define COMP_STRID_ERR 34
1048 #define COMP_2ND_BW_ERR 35
1050 #define COMP_SPLIT_ERR 36
1060 #define LINK_TOGGLE (0x1<<1)
1073 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1074 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1077 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1078 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1080 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1081 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1082 #define LAST_EP_INDEX 30
1085 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1086 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1091 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1095 #define TRB_LEN(p) ((p) & 0x1ffff)
1097 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1098 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1099 #define TRB_TBC(p) (((p) & 0x3) << 7)
1100 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1103 #define TRB_CYCLE (1<<0)
1108 #define TRB_ENT (1<<1)
1110 #define TRB_ISP (1<<2)
1112 #define TRB_NO_SNOOP (1<<3)
1114 #define TRB_CHAIN (1<<4)
1116 #define TRB_IOC (1<<5)
1118 #define TRB_IDT (1<<6)
1121 #define TRB_BEI (1<<9)
1124 #define TRB_DIR_IN (1<<16)
1125 #define TRB_TX_TYPE(p) ((p) << 16)
1126 #define TRB_DATA_OUT 2
1127 #define TRB_DATA_IN 3
1130 #define TRB_SIA (1<<31)
1144 #define TRB_TYPE_BITMASK (0xfc00)
1145 #define TRB_TYPE(p) ((p) << 10)
1146 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1149 #define TRB_NORMAL 1
1155 #define TRB_STATUS 4
1160 #define TRB_EVENT_DATA 7
1162 #define TRB_TR_NOOP 8
1165 #define TRB_ENABLE_SLOT 9
1167 #define TRB_DISABLE_SLOT 10
1169 #define TRB_ADDR_DEV 11
1171 #define TRB_CONFIG_EP 12
1173 #define TRB_EVAL_CONTEXT 13
1175 #define TRB_RESET_EP 14
1177 #define TRB_STOP_RING 15
1179 #define TRB_SET_DEQ 16
1181 #define TRB_RESET_DEV 17
1183 #define TRB_FORCE_EVENT 18
1185 #define TRB_NEG_BANDWIDTH 19
1187 #define TRB_SET_LT 20
1189 #define TRB_GET_BW 21
1191 #define TRB_FORCE_HEADER 22
1193 #define TRB_CMD_NOOP 23
1197 #define TRB_TRANSFER 32
1199 #define TRB_COMPLETION 33
1201 #define TRB_PORT_STATUS 34
1203 #define TRB_BANDWIDTH_EVENT 35
1205 #define TRB_DOORBELL 36
1207 #define TRB_HC_EVENT 37
1209 #define TRB_DEV_NOTE 38
1211 #define TRB_MFINDEX_WRAP 39
1215 #define TRB_NEC_CMD_COMP 48
1217 #define TRB_NEC_GET_FW 49
1219 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1221 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1222 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1223 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1224 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1226 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1227 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1234 #define TRBS_PER_SEGMENT 64
1236 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1237 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1238 #define SEGMENT_SHIFT (__ffs(SEGMENT_SIZE))
1240 #define TRB_MAX_BUFF_SHIFT 16
1241 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1260 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1344 #define ERST_NUM_SEGS 1
1346 #define ERST_SIZE 64
1348 #define ERST_ENTRIES 1
1350 #define POLL_TIMEOUT 60
1352 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1387 static inline unsigned int hcd_index(
struct usb_hcd *hcd)
1389 if (hcd->speed == HCD_USB3)
1435 #define CMD_RING_STATE_RUNNING (1 << 0)
1436 #define CMD_RING_STATE_ABORTED (1 << 1)
1437 #define CMD_RING_STATE_STOPPED (1 << 2)
1463 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1485 #define XHCI_STATE_DYING (1 << 0)
1486 #define XHCI_STATE_HALTED (1 << 1)
1490 #define XHCI_LINK_TRB_QUIRK (1 << 0)
1491 #define XHCI_RESET_EP_QUIRK (1 << 1)
1492 #define XHCI_NEC_HOST (1 << 2)
1493 #define XHCI_AMD_PLL_FIX (1 << 3)
1494 #define XHCI_SPURIOUS_SUCCESS (1 << 4)
1504 #define XHCI_EP_LIMIT_QUIRK (1 << 5)
1505 #define XHCI_BROKEN_MSI (1 << 6)
1506 #define XHCI_RESET_ON_RESUME (1 << 7)
1507 #define XHCI_SW_BW_CHECKING (1 << 8)
1508 #define XHCI_AMD_0x96_HOST (1 << 9)
1509 #define XHCI_TRUST_TX_LENGTH (1 << 10)
1510 #define XHCI_LPM_SUPPORT (1 << 11)
1511 #define XHCI_INTEL_HOST (1 << 12)
1512 #define XHCI_SPURIOUS_REBOOT (1 << 13)
1513 #define XHCI_COMP_MODE_QUIRK (1 << 14)
1514 #define XHCI_AVOID_BEI (1 << 15)
1535 #define COMP_MODE_RCVRY_MSECS 2000
1539 static inline struct xhci_hcd *hcd_to_xhci(
struct usb_hcd *hcd)
1541 return *((
struct xhci_hcd **) (hcd->hcd_priv));
1544 static inline struct usb_hcd *xhci_to_hcd(
struct xhci_hcd *xhci)
1549 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1550 #define XHCI_DEBUG 1
1552 #define XHCI_DEBUG 0
1555 #define xhci_dbg(xhci, fmt, args...) \
1556 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1557 #define xhci_info(xhci, fmt, args...) \
1558 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1559 #define xhci_err(xhci, fmt, args...) \
1560 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1561 #define xhci_warn(xhci, fmt, args...) \
1562 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1563 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1564 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1568 static inline unsigned int xhci_readl(
const struct xhci_hcd *xhci,
1573 static inline void xhci_writel(
struct xhci_hcd *xhci,
1588 static inline u64 xhci_read_64(
const struct xhci_hcd *xhci,
1594 return val_lo + (val_hi << 32);
1596 static inline void xhci_write_64(
struct xhci_hcd *xhci,
1607 static inline int xhci_link_trb_quirk(
struct xhci_hcd *xhci)
1628 unsigned int slot_id,
unsigned int ep_index,
1638 struct usb_device *
udev);
1647 struct usb_device *
udev,
1652 int old_active_eps);
1666 struct usb_device *
udev,
struct usb_host_endpoint *ep,
1695 bool allocate_in_ctx,
bool allocate_completion,
1710 #if defined(CONFIG_USB_XHCI_PLATFORM) \
1711 || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
1738 #define xhci_suspend NULL
1739 #define xhci_resume NULL
1749 struct usb_device *hdev,
1750 struct usb_tt *
tt,
gfp_t mem_flags);
1752 struct usb_host_endpoint **eps,
unsigned int num_eps,
1753 unsigned int num_streams,
gfp_t mem_flags);
1755 struct usb_host_endpoint **eps,
unsigned int num_eps,
1762 struct usb_tt *
tt,
gfp_t mem_flags);
1787 int slot_id,
unsigned int ep_index);
1789 int slot_id,
unsigned int ep_index);
1791 int slot_id,
unsigned int ep_index);
1795 u32 slot_id,
bool command_must_succeed);
1797 u32 slot_id,
bool command_must_succeed);
1802 unsigned int slot_id,
unsigned int ep_index,
1803 unsigned int stream_id,
struct xhci_td *cur_td,
1806 unsigned int slot_id,
unsigned int ep_index,
1807 unsigned int stream_id,
1812 unsigned int slot_id,
unsigned int ep_index,
1818 unsigned int ep_index,
unsigned int stream_id);
1837 #define xhci_bus_suspend NULL
1838 #define xhci_bus_resume NULL