#include "NVPTXISelLowering.h"
#include "NVPTX.h"
#include "NVPTXTargetMachine.h"
#include "NVPTXTargetObjectFile.h"
#include "NVPTXUtilities.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/IR/CallSite.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <sstream>

Include dependency graph for NVPTXISelLowering.cpp:

Defines
#define	DEBUG_TYPE "nvptx-lower"
Enumerations
enum	OperandSignedness { Signed = 0, Unsigned, Unknown }
Functions
static bool	IsPTXVectorType (MVT VT)
static void	ComputePTXValueVTs (const TargetLowering &TLI, Type Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > Offsets=nullptr, uint64_t StartingOffset=0)
static unsigned	getOpcForTextureInstr (unsigned Intrinsic)
static unsigned	getOpcForSurfaceInstr (unsigned Intrinsic)
static SDValue	PerformADDCombineWithOperands (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const NVPTXSubtarget &Subtarget, CodeGenOpt::Level OptLevel)
static SDValue	PerformADDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const NVPTXSubtarget &Subtarget, CodeGenOpt::Level OptLevel)
static SDValue	PerformANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static bool	IsMulWideOperandDemotable (SDValue Op, unsigned OptSize, OperandSignedness &S)
static bool	AreMulWideOperandsDemotable (SDValue LHS, SDValue RHS, unsigned OptSize, bool &IsSigned)
static SDValue	TryMULWIDECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformMULCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, CodeGenOpt::Level OptLevel)
	PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
static SDValue	PerformSHLCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, CodeGenOpt::Level OptLevel)
	PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
static void	ReplaceLoadVector (SDNode N, SelectionDAG &DAG, const DataLayout TD, SmallVectorImpl< SDValue > &Results)
	ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
static void	ReplaceINTRINSIC_W_CHAIN (SDNode *N, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results)
Variables
static unsigned int	uniqueCallSite = 0
static cl::opt< bool >	sched4reg ("nvptx-sched4reg", cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false))
static cl::opt< unsigned >	FMAContractLevelOpt ("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden, cl::desc("NVPTX Specific: FMA contraction (0: don't do it"" 1: do it 2: do it aggressively"), cl::init(2))

Define Documentation

#define DEBUG_TYPE "nvptx-lower"

Definition at line 41 of file NVPTXISelLowering.cpp.

Enumeration Type Documentation

enum OperandSignedness

Enumerator:

Signed
Unsigned
Unknown

Definition at line 4022 of file NVPTXISelLowering.cpp.

Function Documentation

static bool AreMulWideOperandsDemotable	(	SDValue	LHS,
		SDValue	RHS,
		unsigned	OptSize,
		bool &	IsSigned
	)		`[static]`

AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can be demoted to OptSize bits without loss of information. If the operands contain a constant, it should appear as the RHS operand. The signedness of the operands is placed in IsSigned.

Definition at line 4058 of file NVPTXISelLowering.cpp.

References llvm::APInt::isIntN(), IsMulWideOperandDemotable(), llvm::APInt::isSignedIntN(), Signed, llvm::Unknown, and Unsigned.

Referenced by TryMULWIDECombine().

static void ComputePTXValueVTs	(	const TargetLowering &	TLI,
		Type *	Ty,
		SmallVectorImpl< EVT > &	ValueVTs,
		SmallVectorImpl< uint64_t > *	Offsets = `nullptr`,
		uint64_t	StartingOffset = `0`
	)		`[static]`

ComputePTXValueVTs - For the given Type Ty, returns the set of primitive EVTs that compose it. Unlike ComputeValueVTs, this will break apart vectors into their primitive components. NOTE: This is a band-aid for code that expects ComputeValueVTs to return the same number of types as the Ins/Outs arrays in LowerFormalArguments, LowerCall, and LowerReturn.

Definition at line 83 of file NVPTXISelLowering.cpp.

References llvm::ComputeValueVTs(), llvm::EVT::getStoreSize(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::isVector(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::SmallVectorTemplateCommon< T >::size().

Referenced by llvm::NVPTXTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerFormalArguments(), and llvm::NVPTXTargetLowering::LowerReturn().

static unsigned getOpcForSurfaceInstr ( unsigned Intrinsic ) [static]

Definition at line 2886 of file NVPTXISelLowering.cpp.

Referenced by llvm::NVPTXTargetLowering::getTgtMemIntrinsic().

static unsigned getOpcForTextureInstr ( unsigned Intrinsic ) [static]

Definition at line 2527 of file NVPTXISelLowering.cpp.

Referenced by llvm::NVPTXTargetLowering::getTgtMemIntrinsic().

static bool IsMulWideOperandDemotable	(	SDValue	Op,
		unsigned	OptSize,
		OperandSignedness &	S
	)		`[static]`

IsMulWideOperandDemotable - Checks if the provided DAG node is an operand that can be demoted to OptSize bits without loss of information. The signedness of the operand, if determinable, is placed in S.

Definition at line 4031 of file NVPTXISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, Signed, llvm::Unknown, Unsigned, and llvm::ISD::ZERO_EXTEND.

Referenced by AreMulWideOperandsDemotable().

static bool IsPTXVectorType ( MVT VT ) [static]

Definition at line 57 of file NVPTXISelLowering.cpp.

References llvm::MVT::SimpleTy, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i1, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v2i8, llvm::MVT::v4f32, llvm::MVT::v4i1, llvm::MVT::v4i16, llvm::MVT::v4i32, and llvm::MVT::v4i8.

Referenced by llvm::NVPTXTargetLowering::NVPTXTargetLowering().

static SDValue PerformADDCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const NVPTXSubtarget &	Subtarget,
		CodeGenOpt::Level	OptLevel
	)		`[static]`

PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.

Definition at line 3930 of file NVPTXISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), and PerformADDCombineWithOperands().

static SDValue PerformADDCombineWithOperands	(	SDNode *	N,
		SDValue	N0,
		SDValue	N1,
		TargetLowering::DAGCombinerInfo &	DCI,
		const NVPTXSubtarget &	Subtarget,
		CodeGenOpt::Level	OptLevel
	)		`[static]`

PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1. This is a helper for PerformADDCombine that is called with the default operands, and if that fails, with commuted operands.

Definition at line 3824 of file NVPTXISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FADD, llvm::ISD::FMA, llvm::ISD::FMUL, llvm::SDNode::getIROrder(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::NVPTXISD::IMAD, llvm::EVT::isInteger(), llvm::EVT::isVector(), llvm::ISD::MUL, llvm::CodeGenOpt::None, llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

Referenced by PerformADDCombine().

static SDValue PerformANDCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI
	)		`[static]`

static SDValue PerformMULCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		CodeGenOpt::Level	OptLevel
	)		`[static]`

PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.

Definition at line 4170 of file NVPTXISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::MipsISD::Ret, and TryMULWIDECombine().

static SDValue PerformSHLCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		CodeGenOpt::Level	OptLevel
	)		`[static]`

PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.

Definition at line 4184 of file NVPTXISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::MipsISD::Ret, and TryMULWIDECombine().

static void ReplaceINTRINSIC_W_CHAIN	(	SDNode *	N,
		SelectionDAG &	DAG,
		SmallVectorImpl< SDValue > &	Results
	)		`[static]`

Definition at line 4320 of file NVPTXISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::MVT::i16, llvm::MVT::i8, llvm::ISD::INTRINSIC_W_CHAIN, llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::NVPTXISD::LDGV2, llvm::NVPTXISD::LDGV4, llvm::NVPTXISD::LDUV2, llvm::NVPTXISD::LDUV4, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MVT::SimpleTy, and llvm::ISD::TRUNCATE.

static void ReplaceLoadVector	(	SDNode *	N,
		SelectionDAG &	DAG,
		const DataLayout *	TD,
		SmallVectorImpl< SDValue > &	Results
	)		`[static]`

ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.

Definition at line 4216 of file NVPTXISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::MemSDNode::getAlignment(), llvm::SelectionDAG::getContext(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), llvm::DataLayout::getPrefTypeAlignment(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::MVT::i16, llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::NVPTXISD::LoadV2, llvm::NVPTXISD::LoadV4, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MVT::SimpleTy, llvm::ISD::TRUNCATE, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v2i8, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, and llvm::MVT::v4i8.

static SDValue TryMULWIDECombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI
	)		`[static]`

TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform works on both multiply DAG nodes and SHL DAG nodes with a constant shift amount.

Definition at line 4104 of file NVPTXISelLowering.cpp.

References AreMulWideOperandsDemotable(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::MUL, llvm::NVPTXISD::MUL_WIDE_SIGNED, llvm::NVPTXISD::MUL_WIDE_UNSIGNED, llvm::APInt::sge(), llvm::ISD::SHL, Signed, llvm::APInt::slt(), std::swap(), and llvm::ISD::TRUNCATE.

Referenced by PerformMULCombine(), and PerformSHLCombine().

Variable Documentation

cl::opt<unsigned> FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden, cl::desc("NVPTX Specific: FMA contraction (0: don't do it"" 1: do it 2: do it aggressively"), cl::init(2)) [static]

Referenced by llvm::NVPTXTargetLowering::allowFMA().

cl::opt<bool> sched4reg("nvptx-sched4reg", cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false)) [static]

Referenced by llvm::NVPTXTargetLowering::NVPTXTargetLowering().

unsigned int uniqueCallSite = 0 [static]

Definition at line 45 of file NVPTXISelLowering.cpp.

Referenced by llvm::NVPTXTargetLowering::getPrototype(), and llvm::NVPTXTargetLowering::LowerCall().

Defines

Enumerations

Functions

Variables

Define Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation