#include "X86ISelLowering.h"
#include "Utils/X86ShuffleDecode.h"
#include "X86CallingConv.h"
#include "X86InstrBuilder.h"
#include "X86MachineFunctionInfo.h"
#include "X86TargetMachine.h"
#include "X86TargetObjectFile.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/VariadicFunction.h"
#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/CallSite.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalAlias.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetOptions.h"
#include "X86IntrinsicsInfo.h"
#include <bitset>
#include <numeric>
#include <cctype>
#include "X86GenCallingConv.inc"

Include dependency graph for X86ISelLowering.cpp:

Defines
#define	DEBUG_TYPE "x86-isel"
Enumerations
enum	StructReturnType { NotStructReturn, RegStructReturn, StackStructReturn }
Functions
	STATISTIC (NumTailCalls,"Number of tail calls")
static SDValue	getMOVL (SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1, SDValue V2)
static SDValue	ExtractSubVector (SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl, unsigned vectorWidth)
static SDValue	Extract128BitVector (SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl)
static SDValue	Extract256BitVector (SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl)
	Generate a DAG to grab 256-bits from a 512-bit vector.
static SDValue	InsertSubVector (SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl, unsigned vectorWidth)
static SDValue	Insert128BitVector (SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl)
static SDValue	Insert256BitVector (SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl)
static SDValue	Concat128BitVectors (SDValue V1, SDValue V2, EVT VT, unsigned NumElems, SelectionDAG &DAG, SDLoc dl)
static SDValue	Concat256BitVectors (SDValue V1, SDValue V2, EVT VT, unsigned NumElems, SelectionDAG &DAG, SDLoc dl)
static TargetLoweringObjectFile *	createTLOF (const Triple &TT)
static void	getMaxByValAlign (Type *Ty, unsigned &MaxAlign)
static StructReturnType	callIsStructReturn (const SmallVectorImpl< ISD::OutputArg > &Outs)
static StructReturnType	argsAreStructReturn (const SmallVectorImpl< ISD::InputArg > &Ins)
static SDValue	CreateCopyOfByValArgument (SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl)
static bool	IsTailCallConvention (CallingConv::ID CC)
static bool	IsCCallConvention (CallingConv::ID CC)
	Return true if the calling convention is a C calling convention.
static bool	FuncIsMadeTailCallSafe (CallingConv::ID CC, bool GuaranteedTailCallOpt)
static ArrayRef< MCPhysReg >	get64BitArgumentGPRs (CallingConv::ID CallConv, const X86Subtarget *Subtarget)
static ArrayRef< MCPhysReg >	get64BitArgumentXMMs (MachineFunction &MF, CallingConv::ID CallConv, const X86Subtarget *Subtarget)
static SDValue	EmitTailCallStoreRetAddr (SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT, unsigned SlotSize, int FPDiff, SDLoc dl)
static bool	MatchingStackOffset (SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo MFI, const MachineRegisterInfo MRI, const X86InstrInfo *TII)
static bool	MayFoldLoad (SDValue Op)
static bool	MayFoldIntoStore (SDValue Op)
static bool	isTargetShuffle (unsigned Opcode)
static SDValue	getTargetShuffleNode (unsigned Opc, SDLoc dl, EVT VT, SDValue V1, SelectionDAG &DAG)
static SDValue	getTargetShuffleNode (unsigned Opc, SDLoc dl, EVT VT, SDValue V1, unsigned TargetMask, SelectionDAG &DAG)
static SDValue	getTargetShuffleNode (unsigned Opc, SDLoc dl, EVT VT, SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG)
static SDValue	getTargetShuffleNode (unsigned Opc, SDLoc dl, EVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
static bool	isX86CCUnsigned (unsigned X86CC)
	Return true if the condition is an unsigned comparison operation.
static unsigned	TranslateX86CC (ISD::CondCode SetCCOpcode, bool isFP, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG)
static bool	hasFPCMov (unsigned X86CC)
static bool	isUndefOrInRange (int Val, int Low, int Hi)
static bool	isUndefOrEqual (int Val, int CmpVal)
static bool	isSequentialOrUndefInRange (ArrayRef< int > Mask, unsigned Pos, unsigned Size, int Low)
static bool	isPSHUFDMask (ArrayRef< int > Mask, MVT VT)
static bool	isPSHUFHWMask (ArrayRef< int > Mask, MVT VT, bool HasInt256)
static bool	isPSHUFLWMask (ArrayRef< int > Mask, MVT VT, bool HasInt256)
static bool	isAlignrMask (ArrayRef< int > Mask, MVT VT, bool InterLane)
	Return true if the mask specifies a shuffle of elements that is suitable for input to intralane (palignr) or interlane (valign) vector right-shift.
static bool	isPALIGNRMask (ArrayRef< int > Mask, MVT VT, const X86Subtarget *Subtarget)
	Return true if the node specifies a shuffle of elements that is suitable for input to PALIGNR.
static bool	isVALIGNMask (ArrayRef< int > Mask, MVT VT, const X86Subtarget *Subtarget)
	Return true if the node specifies a shuffle of elements that is suitable for input to VALIGN.
static void	CommuteVectorShuffleMask (SmallVectorImpl< int > &Mask, unsigned NumElems)
static bool	isSHUFPMask (ArrayRef< int > Mask, MVT VT, bool Commuted=false)
static bool	isMOVHLPSMask (ArrayRef< int > Mask, MVT VT)
static bool	isMOVHLPS_v_undef_Mask (ArrayRef< int > Mask, MVT VT)
static bool	isMOVLPMask (ArrayRef< int > Mask, MVT VT)
static bool	isMOVLHPSMask (ArrayRef< int > Mask, MVT VT)
static bool	isINSERTPSMask (ArrayRef< int > Mask, MVT VT)
static SDValue	Compact8x32ShuffleNode (ShuffleVectorSDNode *SVOp, SelectionDAG &DAG)
static bool	isUNPCKLMask (ArrayRef< int > Mask, MVT VT, bool HasInt256, bool V2IsSplat=false)
static bool	isUNPCKHMask (ArrayRef< int > Mask, MVT VT, bool HasInt256, bool V2IsSplat=false)
static bool	isUNPCKL_v_undef_Mask (ArrayRef< int > Mask, MVT VT, bool HasInt256)
static bool	isUNPCKH_v_undef_Mask (ArrayRef< int > Mask, MVT VT, bool HasInt256)
static bool	isINSERT64x4Mask (ArrayRef< int > Mask, MVT VT, unsigned int *Imm)
static bool	isMOVLMask (ArrayRef< int > Mask, EVT VT)
static bool	isVPERM2X128Mask (ArrayRef< int > Mask, MVT VT, bool HasFp256)
static unsigned	getShuffleVPERM2X128Immediate (ShuffleVectorSDNode *SVOp)
static bool	isPermImmMask (ArrayRef< int > Mask, MVT VT, unsigned &Imm8)
static bool	isVPERMILPMask (ArrayRef< int > Mask, MVT VT)
static bool	isCommutedMOVLMask (ArrayRef< int > Mask, MVT VT, bool V2IsSplat=false, bool V2IsUndef=false)
static bool	isMOVSHDUPMask (ArrayRef< int > Mask, MVT VT, const X86Subtarget *Subtarget)
static bool	isMOVSLDUPMask (ArrayRef< int > Mask, MVT VT, const X86Subtarget *Subtarget)
static bool	isMOVDDUPYMask (ArrayRef< int > Mask, MVT VT, bool HasFp256)
static bool	isMOVDDUPMask (ArrayRef< int > Mask, MVT VT)
static bool	isVEXTRACTIndex (SDNode *N, unsigned vecWidth)
static bool	isVINSERTIndex (SDNode *N, unsigned vecWidth)
static unsigned	getShuffleSHUFImmediate (ShuffleVectorSDNode *N)
static unsigned	getShufflePSHUFHWImmediate (ShuffleVectorSDNode *N)
static unsigned	getShufflePSHUFLWImmediate (ShuffleVectorSDNode *N)
static unsigned	getShuffleAlignrImmediate (ShuffleVectorSDNode *SVOp, bool InterLane)
	Return the appropriate immediate to shuffle the specified VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with VALIGN (if Interlane is true) instructions.
static unsigned	getShufflePALIGNRImmediate (ShuffleVectorSDNode *SVOp)
	Return the appropriate immediate to shuffle the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
static unsigned	getShuffleVALIGNImmediate (ShuffleVectorSDNode *SVOp)
	Return the appropriate immediate to shuffle the specified VECTOR_SHUFFLE mask with the VALIGN instruction.
static unsigned	getExtractVEXTRACTImmediate (SDNode *N, unsigned vecWidth)
static unsigned	getInsertVINSERTImmediate (SDNode *N, unsigned vecWidth)
static bool	isZero (SDValue V)
	isZero - Returns true if Elt is a constant integer zero
static bool	ShouldXformToMOVHLPS (ArrayRef< int > Mask, MVT VT)
static bool	isScalarLoadToVector (SDNode N, LoadSDNode *LD=nullptr)
static bool	WillBeConstantPoolLoad (SDNode *N)
static bool	ShouldXformToMOVLP (SDNode V1, SDNode V2, ArrayRef< int > Mask, MVT VT)
static bool	isZeroShuffle (ShuffleVectorSDNode *N)
static SDValue	getZeroVector (EVT VT, const X86Subtarget *Subtarget, SelectionDAG &DAG, SDLoc dl)
static SDValue	getOnesVector (MVT VT, bool HasInt256, SelectionDAG &DAG, SDLoc dl)
static void	NormalizeMask (SmallVectorImpl< int > &Mask, unsigned NumElems)
static SDValue	getUnpackl (SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, SDValue V2)
	getUnpackl - Returns a vector_shuffle node for an unpackl operation.
static SDValue	getUnpackh (SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, SDValue V2)
	getUnpackh - Returns a vector_shuffle node for an unpackh operation.
static SDValue	PromoteSplati8i16 (SDValue V, SelectionDAG &DAG, int &EltNo)
static SDValue	getLegalSplat (SelectionDAG &DAG, SDValue V, int EltNo)
	getLegalSplat - Generate a legal splat with supported x86 shuffles
static SDValue	PromoteSplat (ShuffleVectorSDNode *SV, SelectionDAG &DAG)
	PromoteSplat - Splat is promoted to target supported vector shuffles.
static SDValue	getShuffleVectorZeroOrUndef (SDValue V2, unsigned Idx, bool IsZero, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static bool	getTargetShuffleMask (SDNode *N, MVT VT, SmallVectorImpl< int > &Mask, bool &IsUnary)
static SDValue	getShuffleScalarElt (SDNode *N, unsigned Index, SelectionDAG &DAG, unsigned Depth)
static unsigned	getNumOfConsecutiveZeros (ShuffleVectorSDNode *SVOp, unsigned NumElems, bool ZerosFromLeft, SelectionDAG &DAG, unsigned PreferredNum=-1U)
static bool	isShuffleMaskConsecutive (ShuffleVectorSDNode *SVOp, unsigned MaskI, unsigned MaskE, unsigned OpIdx, unsigned NumElems, unsigned &OpNum)
static bool	isVectorShiftRight (ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, bool &isLeft, SDValue &ShVal, unsigned &ShAmt)
static bool	isVectorShiftLeft (ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, bool &isLeft, SDValue &ShVal, unsigned &ShAmt)
static bool	isVectorShift (ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, bool &isLeft, SDValue &ShVal, unsigned &ShAmt)
static SDValue	LowerBuildVectorv16i8 (SDValue Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget *Subtarget, const TargetLowering &TLI)
static SDValue	LowerBuildVectorv8i16 (SDValue Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget *Subtarget, const TargetLowering &TLI)
static SDValue	LowerBuildVectorv4x32 (SDValue Op, unsigned NumElems, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget *Subtarget, const TargetLowering &TLI)
	LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
static SDValue	getVShift (bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits, SelectionDAG &DAG, const TargetLowering &TLI, SDLoc dl)
static SDValue	LowerAsSplatVectorLoad (SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG)
static SDValue	EltsFromConsecutiveLoads (EVT VT, SmallVectorImpl< SDValue > &Elts, SDLoc &DL, SelectionDAG &DAG, bool isAfterLegalize)
static SDValue	LowerVectorBroadcast (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static int	getUnderlyingExtractedFromVec (SDValue &ExtractedFromVec, SDValue ExtIdx)
	For an EXTRACT_VECTOR_ELT with a constant index return the real underlying vector and index.
static SDValue	buildFromShuffleMostly (SDValue Op, SelectionDAG &DAG)
static bool	isHorizontalBinOp (const BuildVectorSDNode *N, unsigned Opcode, SelectionDAG &DAG, unsigned BaseIdx, unsigned LastIdx, SDValue &V0, SDValue &V1)
	Return true if `N` implements a horizontal binop and return the operands for the horizontal binop into V0 and V1.
static SDValue	ExpandHorizontalBinOp (const SDValue &V0, const SDValue &V1, SDLoc DL, SelectionDAG &DAG, unsigned X86Opcode, bool Mode, bool isUndefLO, bool isUndefHI)
	Emit a sequence of two 128-bit horizontal add/sub followed by a concat_vector.
static SDValue	matchAddSub (const BuildVectorSDNode BV, SelectionDAG &DAG, const X86Subtarget Subtarget)
	Try to fold a build_vector that performs an 'addsub' into the sequence of 'vadd + vsub + blendi'.
static SDValue	PerformBUILD_VECTORCombine (SDNode N, SelectionDAG &DAG, const X86Subtarget Subtarget)
static SDValue	LowerAVXCONCAT_VECTORS (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerCONCAT_VECTORS (SDValue Op, SelectionDAG &DAG)
static bool	isNoopShuffleMask (ArrayRef< int > Mask)
	Tiny helper function to identify a no-op mask.
static bool	isSingleInputShuffleMask (ArrayRef< int > Mask)
	Helper function to classify a mask as a single-input mask.
static SDValue	getV4X86ShuffleImm8ForMask (ArrayRef< int > Mask, SelectionDAG &DAG)
	Get a 4-lane 8-bit shuffle immediate for a mask.
static SDValue	lowerVectorShuffleAsBlend (SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, SelectionDAG &DAG)
	Try to emit a blend instruction for a shuffle.
static SDValue	lowerVectorShuffleAsByteRotate (SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, SelectionDAG &DAG)
	Try to lower a vector shuffle as a byte rotation.
static SDValue	lowerV2F64VectorShuffle (SDValue Op, SDValue V1, SDValue V2, const X86Subtarget *Subtarget, SelectionDAG &DAG)
	Handle lowering of 2-lane 64-bit floating point shuffles.
static SDValue	lowerV2I64VectorShuffle (SDValue Op, SDValue V1, SDValue V2, const X86Subtarget *Subtarget, SelectionDAG &DAG)
	Handle lowering of 2-lane 64-bit integer shuffles.
static SDValue	lowerV4F32VectorShuffle (SDValue Op, SDValue V1, SDValue V2, const X86Subtarget *Subtarget, SelectionDAG &DAG)
	Lower 4-lane 32-bit floating point shuffles.
static SDValue	lowerIntegerElementInsertionVectorShuffle (MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef< int > Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	lowerV4I32VectorShuffle (SDValue Op, SDValue V1, SDValue V2, const X86Subtarget *Subtarget, SelectionDAG &DAG)
	Lower 4-lane i32 vector shuffles.
static SDValue	lowerV8I16SingleInputVectorShuffle (SDLoc DL, SDValue V, MutableArrayRef< int > Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG)
	Lowering of single-input v8i16 shuffles is the cornerstone of SSE2 shuffle lowering, and the most complex part.
static bool	shouldLowerAsInterleaving (ArrayRef< int > Mask)
	Detect whether the mask pattern should be lowered through interleaving.
static SDValue	lowerV8I16BasicBlendVectorShuffle (SDLoc DL, SDValue V1, SDValue V2, MutableArrayRef< int > Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG)
	Blend two v8i16 vectors using a naive unpack strategy.
static SDValue	lowerV8I16VectorShuffle (SDValue Op, SDValue V1, SDValue V2, const X86Subtarget *Subtarget, SelectionDAG &DAG)
	Generic lowering of 8-lane i16 shuffles.
static int	canLowerByDroppingEvenElements (ArrayRef< int > Mask)
	Check whether a compaction lowering can be done by dropping even elements and compute how many times even elements must be dropped.
static SDValue	lowerV16I8VectorShuffle (SDValue Op, SDValue V1, SDValue V2, const X86Subtarget *Subtarget, SelectionDAG &DAG)
	Generic lowering of v16i8 shuffles.
static SDValue	lower128BitVectorShuffle (SDValue Op, SDValue V1, SDValue V2, MVT VT, const X86Subtarget *Subtarget, SelectionDAG &DAG)
	Dispatching routine to lower various 128-bit x86 vector shuffles.
static bool	isHalfCrossingShuffleMask (ArrayRef< int > Mask)
static SDValue	splitAndLower256BitVectorShuffle (SDValue Op, SDValue V1, SDValue V2, const X86Subtarget *Subtarget, SelectionDAG &DAG)
	Generic routine to split a 256-bit vector shuffle into 128-bit shuffles.
static SDValue	lowerV4F64VectorShuffle (SDValue Op, SDValue V1, SDValue V2, const X86Subtarget *Subtarget, SelectionDAG &DAG)
	Handle lowering of 4-lane 64-bit floating point shuffles.
static SDValue	lowerV4I64VectorShuffle (SDValue Op, SDValue V1, SDValue V2, const X86Subtarget *Subtarget, SelectionDAG &DAG)
	Handle lowering of 4-lane 64-bit integer shuffles.
static SDValue	lower256BitVectorShuffle (SDValue Op, SDValue V1, SDValue V2, MVT VT, const X86Subtarget *Subtarget, SelectionDAG &DAG)
	High-level routine to lower various 256-bit x86 vector shuffles.
static bool	canWidenShuffleElements (ArrayRef< int > Mask)
	Tiny helper function to test whether a shuffle mask could be simplified by widening the elements being shuffled.
static SDValue	lowerVectorShuffle (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
	Top-level lowering for x86 vector shuffles.
static bool	isBlendMask (ArrayRef< int > MaskVals, MVT VT, bool hasSSE41, bool hasInt256, unsigned *MaskOut=nullptr)
static SDValue	LowerVECTOR_SHUFFLEtoBlend (ShuffleVectorSDNode SVOp, unsigned MaskValue, const X86Subtarget Subtarget, SelectionDAG &DAG)
static bool	ShuffleCrosses128bitLane (MVT VT, unsigned InputIdx, unsigned OutputIdx)
static SDValue	getPSHUFB (ArrayRef< int > MaskVals, SDValue V1, SDLoc &dl, SelectionDAG &DAG)
static SDValue	LowerVECTOR_SHUFFLEv8i16 (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	LowerVECTOR_SHUFFLEv16i16 (SDValue Op, SelectionDAG &DAG)
	v16i16 shuffles
static SDValue	LowerVECTOR_SHUFFLEv16i8 (ShuffleVectorSDNode SVOp, const X86Subtarget Subtarget, SelectionDAG &DAG)
static SDValue	LowerVECTOR_SHUFFLEv32i8 (ShuffleVectorSDNode SVOp, const X86Subtarget Subtarget, SelectionDAG &DAG)
static SDValue	RewriteAsNarrowerShuffle (ShuffleVectorSDNode *SVOp, SelectionDAG &DAG)
static SDValue	getVZextMovL (MVT VT, MVT OpVT, SDValue SrcOp, SelectionDAG &DAG, const X86Subtarget *Subtarget, SDLoc dl)
static SDValue	LowerVECTOR_SHUFFLE_256 (ShuffleVectorSDNode *SVOp, SelectionDAG &DAG)
static SDValue	LowerVECTOR_SHUFFLE_128v4 (ShuffleVectorSDNode *SVOp, SelectionDAG &DAG)
static bool	MayFoldVectorLoad (SDValue V)
static SDValue	getMOVDDup (SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG)
static SDValue	getMOVLowToHigh (SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2)
static SDValue	getMOVHighToLow (SDValue &Op, SDLoc &dl, SelectionDAG &DAG)
static SDValue	getMOVLP (SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2)
static SDValue	NarrowVectorLoadToElement (LoadSDNode *Load, unsigned Index, SelectionDAG &DAG)
static SDValue	getINSERTPS (ShuffleVectorSDNode *SVOp, SDLoc &dl, SelectionDAG &DAG)
static SDValue	LowerVectorIntExtend (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	NormalizeVectorShuffle (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static bool	BUILD_VECTORtoBlendMask (BuildVectorSDNode *BuildVector, unsigned &MaskValue)
static SDValue	LowerVSELECTtoBlend (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	LowerEXTRACT_VECTOR_ELT_SSE4 (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerSCALAR_TO_VECTOR (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerEXTRACT_SUBVECTOR (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	LowerINSERT_SUBVECTOR (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	GetTLSADDR (SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode GA, SDValue InFlag, const EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags, bool LocalDynamic=false)
static SDValue	LowerToTLSGeneralDynamicModel32 (GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT)
static SDValue	LowerToTLSGeneralDynamicModel64 (GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT)
static SDValue	LowerToTLSLocalDynamicModel (GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT, bool is64Bit)
static SDValue	LowerToTLSExecModel (GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT, TLSModel::Model model, bool is64Bit, bool isPIC)
static SDValue	LowerShiftParts (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerAVXExtend (SDValue Op, SelectionDAG &DAG, const X86Subtarget *Subtarget)
static SDValue	LowerZERO_EXTEND_AVX512 (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerANY_EXTEND (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	LowerZERO_EXTEND (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	LowerFP_EXTEND (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerFABSorFNEG (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerFCOPYSIGN (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerFGETSIGN (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerVectorAllZeroTest (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static bool	hasNonFlagsUse (SDValue Op)
	return true if `Op` has a use that doesn't just read flags.
static bool	isAllOnes (SDValue V)
static int	translateX86FSETCC (ISD::CondCode SetCCOpcode, SDValue &Op0, SDValue &Op1)
	Turns an ISD::CondCode into a value suitable for SSE floating point mask CMPs.
static SDValue	Lower256IntVSETCC (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerIntVSETCC_AVX512 (SDValue Op, SelectionDAG &DAG, const X86Subtarget *Subtarget)
static SDValue	ChangeVSETULTtoVSETULE (SDLoc dl, SDValue Op1, SelectionDAG &DAG)
	Try to turn a VSETULT into a VSETULE by modifying its second operand `Op1`. If non-trivial (for example because it's not constant) return an empty value.
static SDValue	LowerVSETCC (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static bool	isX86LogicalCmp (SDValue Op)
static bool	isTruncWithZeroHighBitsInput (SDValue V, SelectionDAG &DAG)
static SDValue	LowerSIGN_EXTEND_AVX512 (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerSIGN_EXTEND (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	LowerExtendedLoad (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static bool	isAndOrOfSetCCs (SDValue Op, unsigned &Opc)
static bool	isXor1OfSetCC (SDValue Op)
static SDValue	LowerVACOPY (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	getTargetVShiftByConstNode (unsigned Opc, SDLoc dl, MVT VT, SDValue SrcOp, uint64_t ShiftAmt, SelectionDAG &DAG)
static SDValue	getTargetVShiftNode (unsigned Opc, SDLoc dl, MVT VT, SDValue SrcOp, SDValue ShAmt, SelectionDAG &DAG)
static SDValue	getVectorMaskingNode (SDValue Op, SDValue Mask, SDValue PreservedSrc, SelectionDAG &DAG)
	Return (vselect `Mask`, `Op`, `PreservedSrc`) along with the necessary casting for `Mask` when lowering masking intrinsics.
static unsigned	getOpcodeForFMAIntrinsic (unsigned IntNo)
static SDValue	LowerINTRINSIC_WO_CHAIN (SDValue Op, SelectionDAG &DAG)
static SDValue	getGatherNode (unsigned Opc, SDValue Op, SelectionDAG &DAG, SDValue Src, SDValue Mask, SDValue Base, SDValue Index, SDValue ScaleOp, SDValue Chain, const X86Subtarget *Subtarget)
static SDValue	getScatterNode (unsigned Opc, SDValue Op, SelectionDAG &DAG, SDValue Src, SDValue Mask, SDValue Base, SDValue Index, SDValue ScaleOp, SDValue Chain)
static SDValue	getPrefetchNode (unsigned Opc, SDValue Op, SelectionDAG &DAG, SDValue Mask, SDValue Base, SDValue Index, SDValue ScaleOp, SDValue Chain)
static void	getReadPerformanceCounter (SDNode N, SDLoc DL, SelectionDAG &DAG, const X86Subtarget Subtarget, SmallVectorImpl< SDValue > &Results)
static void	getReadTimeStampCounter (SDNode N, SDLoc DL, unsigned Opcode, SelectionDAG &DAG, const X86Subtarget Subtarget, SmallVectorImpl< SDValue > &Results)
static SDValue	LowerREADCYCLECOUNTER (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	LowerINTRINSIC_W_CHAIN (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	LowerADJUST_TRAMPOLINE (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerCTLZ (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerCTLZ_ZERO_UNDEF (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerCTTZ (SDValue Op, SelectionDAG &DAG)
static SDValue	Lower256IntArith (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerADD (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerSUB (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerMUL (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	LowerMUL_LOHI (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	LowerScalarImmediateShift (SDValue Op, SelectionDAG &DAG, const X86Subtarget *Subtarget)
static SDValue	LowerScalarVariableShift (SDValue Op, SelectionDAG &DAG, const X86Subtarget *Subtarget)
static SDValue	LowerShift (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	LowerXALUO (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerATOMIC_FENCE (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	LowerCMP_SWAP (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	LowerBITCAST (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static SDValue	LowerLOAD_SUB (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerATOMIC_STORE (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerADDC_ADDE_SUBC_SUBE (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerFSINCOS (SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
static void	ReplaceATOMIC_LOAD (SDNode *Node, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
static MachineBasicBlock *	EmitXBegin (MachineInstr MI, MachineBasicBlock MBB, const TargetInstrInfo *TII)
	Utility function to emit xbegin specifying the start of an RTM region.
static MachineBasicBlock *	EmitPCMPSTRM (MachineInstr MI, MachineBasicBlock BB, const TargetInstrInfo *TII)
static MachineBasicBlock *	EmitPCMPSTRI (MachineInstr MI, MachineBasicBlock BB, const TargetInstrInfo *TII)
static MachineBasicBlock *	EmitMonitor (MachineInstr MI, MachineBasicBlock BB, const TargetInstrInfo TII, const X86Subtarget Subtarget)
static bool	checkAndUpdateEFLAGSKill (MachineBasicBlock::iterator SelectItr, MachineBasicBlock BB, const TargetRegisterInfo TRI)
static bool	isShuffleHigh128VectorInsertLow (ShuffleVectorSDNode *SVOp)
static bool	isShuffleLow128VectorInsertHigh (ShuffleVectorSDNode *SVOp)
static SDValue	PerformShuffleCombine256 (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
	PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
static bool	combineX86ShuffleChain (SDValue Op, SDValue Root, ArrayRef< int > Mask, int Depth, bool HasPSHUFB, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
	Combine an arbitrary chain of shuffles into a single instruction if possible.
static bool	combineX86ShufflesRecursively (SDValue Op, SDValue Root, ArrayRef< int > RootMask, int Depth, bool HasPSHUFB, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
	Fully generic combining of x86 shuffle instructions.
static SmallVector< int, 4 >	getPSHUFShuffleMask (SDValue N)
	Get the PSHUF-style mask from PSHUF node.
static SDValue	combineRedundantDWordShuffle (SDValue N, MutableArrayRef< int > Mask, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
	Search for a combinable shuffle across a chain ending in pshufd.
static bool	combineRedundantHalfShuffle (SDValue N, MutableArrayRef< int > Mask, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
	Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
static SDValue	PerformTargetShuffleCombine (SDValue N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
	Try to combine x86 target specific shuffles.
static SDValue	combineShuffleToAddSub (SDNode *N, SelectionDAG &DAG)
	Try to combine a shuffle into a target-specific add-sub node.
static SDValue	PerformShuffleCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
	PerformShuffleCombine - Performs several different shuffle combines.
static SDValue	PerformTruncateCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
static SDValue	XFormVExtractWithShuffleIntoLoad (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformEXTRACT_VECTOR_ELTCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static std::pair< unsigned, bool >	matchIntegerMINMAX (SDValue Cond, EVT VT, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const X86Subtarget *Subtarget)
	Matches a VSELECT onto min/max or return 0 if the node doesn't match.
static SDValue	TransformVSELECTtoBlendVECTOR_SHUFFLE (SDNode N, SelectionDAG &DAG, const X86Subtarget Subtarget)
static SDValue	PerformSELECTCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
static SDValue	checkBoolTestSetCCCombine (SDValue Cmp, X86::CondCode &CC)
static SDValue	PerformCMOVCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
	Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL].
static SDValue	PerformINTRINSIC_WO_CHAINCombine (SDNode N, SelectionDAG &DAG, const X86Subtarget Subtarget)
static SDValue	PerformMulCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformSHLCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performShiftToAllZeros (SDNode N, SelectionDAG &DAG, const X86Subtarget Subtarget)
	Returns a vector of 0s if the node in input is a vector logical shift by a constant amount which is known to be bigger than or equal to the vector element size in bits.
static SDValue	PerformShiftCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
	PerformShiftCombine - Combine shifts.
static SDValue	CMPEQCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
static bool	CanFoldXORWithAllOnes (const SDNode *N)
static SDValue	WidenMaskArithmetic (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
static SDValue	PerformAndCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
static SDValue	PerformOrCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
static SDValue	performIntegerAbsCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformXorCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
static SDValue	PerformLOADCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
	PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
static SDValue	PerformSTORECombine (SDNode N, SelectionDAG &DAG, const X86Subtarget Subtarget)
	PerformSTORECombine - Do target-specific dag combines on STORE nodes.
static bool	isHorizontalBinOp (SDValue &LHS, SDValue &RHS, bool IsCommutative)
static SDValue	PerformFADDCombine (SDNode N, SelectionDAG &DAG, const X86Subtarget Subtarget)
	PerformFADDCombine - Do target-specific dag combines on floating point adds.
static SDValue	PerformFSUBCombine (SDNode N, SelectionDAG &DAG, const X86Subtarget Subtarget)
	PerformFSUBCombine - Do target-specific dag combines on floating point subs.
static SDValue	PerformFORCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformFMinFMaxCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformFANDCombine (SDNode *N, SelectionDAG &DAG)
	PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
static SDValue	PerformFANDNCombine (SDNode *N, SelectionDAG &DAG)
	PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes.
static SDValue	PerformBTCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformVZEXT_MOVLCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformSIGN_EXTEND_INREGCombine (SDNode N, SelectionDAG &DAG, const X86Subtarget Subtarget)
static SDValue	PerformSExtCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
static SDValue	PerformFMACombine (SDNode N, SelectionDAG &DAG, const X86Subtarget Subtarget)
static SDValue	PerformZExtCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
static SDValue	PerformISDSETCCCombine (SDNode N, SelectionDAG &DAG, const X86Subtarget Subtarget)
static SDValue	PerformINSERTPSCombine (SDNode N, SelectionDAG &DAG, const X86Subtarget Subtarget)
static SDValue	MaterializeSETB (SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG, MVT VT)
static SDValue	PerformSETCCCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
static SDValue	PerformBrCondCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
static SDValue	performVectorCompareAndMaskUnaryOpCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformSINT_TO_FPCombine (SDNode N, SelectionDAG &DAG, const X86TargetLowering XTLI)
static SDValue	PerformADCCombine (SDNode *N, SelectionDAG &DAG, X86TargetLowering::DAGCombinerInfo &DCI)
static SDValue	OptimizeConditionalInDecrement (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformAddCombine (SDNode N, SelectionDAG &DAG, const X86Subtarget Subtarget)
	PerformADDCombine - Do target-specific dag combines on integer adds.
static SDValue	PerformSubCombine (SDNode N, SelectionDAG &DAG, const X86Subtarget Subtarget)
static SDValue	performVZEXTCombine (SDNode N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget Subtarget)
	performVZEXTCombine - Performs build vector combines
static bool	clobbersFlagRegisters (const SmallVector< StringRef, 4 > &AsmPieces)
Variables
static cl::opt< bool >	ExperimentalVectorWideningLegalization ("x86-experimental-vector-widening-legalization", cl::init(false), cl::desc("Enable an experimental vector type legalization through widening ""rather than promotion."), cl::Hidden)
static cl::opt< bool >	ExperimentalVectorShuffleLowering ("x86-experimental-vector-shuffle-lowering", cl::init(false), cl::desc("Enable an experimental vector shuffle lowering code path."), cl::Hidden)
static const VariadicFunction1 < bool, ArrayRef< int >, int, isShuffleEquivalentImpl >	isShuffleEquivalent = {}
	Checks whether a shuffle mask is equivalent to an explicit list of arguments.

Define Documentation

#define DEBUG_TYPE "x86-isel"

Definition at line 58 of file X86ISelLowering.cpp.

Enumeration Type Documentation

enum StructReturnType

CallIsStructReturn - Determines whether a call uses struct return semantics.

Enumerator:

NotStructReturn
RegStructReturn
StackStructReturn

Definition at line 2208 of file X86ISelLowering.cpp.

Function Documentation

static StructReturnType argsAreStructReturn ( const SmallVectorImpl< ISD::InputArg > & Ins ) [static]

ArgsAreStructReturn - Determines whether a function uses struct return semantics.

Definition at line 2229 of file X86ISelLowering.cpp.

References llvm::SmallVectorBase::empty(), llvm::ISD::ArgFlagsTy::isInReg(), llvm::ISD::ArgFlagsTy::isSRet(), NotStructReturn, RegStructReturn, and StackStructReturn.

static bool BUILD_VECTORtoBlendMask	(	BuildVectorSDNode *	BuildVector,
		unsigned &	MaskValue
	)		`[static]`

Definition at line 10785 of file X86ISelLowering.cpp.

References llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), and isZero().

Referenced by LowerVSELECTtoBlend(), and TransformVSELECTtoBlendVECTOR_SHUFFLE().

static SDValue buildFromShuffleMostly	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

static StructReturnType callIsStructReturn ( const SmallVectorImpl< ISD::OutputArg > & Outs ) [static]

Definition at line 2214 of file X86ISelLowering.cpp.

References llvm::SmallVectorBase::empty(), llvm::ISD::ArgFlagsTy::isInReg(), llvm::ISD::ArgFlagsTy::isSRet(), NotStructReturn, RegStructReturn, and StackStructReturn.

static bool CanFoldXORWithAllOnes ( const SDNode * N ) [static]

CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector so it can be folded inside ANDNP.

Definition at line 21887 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::ISD::INSERT_SUBVECTOR, llvm::EVT::is256BitVector(), llvm::ISD::isBuildVectorAllOnes(), and llvm::ISD::UNDEF.

Referenced by PerformAndCombine().

static int canLowerByDroppingEvenElements ( ArrayRef< int > Mask ) [static]

Check whether a compaction lowering can be done by dropping even elements and compute how many times even elements must be dropped.

This handles shuffles which take every Nth element where N is a power of two. Example shuffle masks:

N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14 N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12 N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28 N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8 N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24

Any of these lanes can of course be undef.

This routine only supports N <= 3. FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here for larger N.

Returns:: N above, or the number of times even elements must be dropped if there is such a number. Otherwise returns zero.

Definition at line 8473 of file X86ISelLowering.cpp.

References llvm::array_lengthof(), llvm::isPowerOf2_32(), isSingleInputShuffleMask(), and llvm::ArrayRef< T >::size().

Referenced by lowerV16I8VectorShuffle().

static bool canWidenShuffleElements ( ArrayRef< int > Mask ) [static]

Tiny helper function to test whether a shuffle mask could be simplified by widening the elements being shuffled.

Definition at line 9060 of file X86ISelLowering.cpp.

References llvm::ArrayRef< T >::size().

Referenced by combineX86ShufflesRecursively(), lowerVectorShuffle(), and PerformTargetShuffleCombine().

static SDValue ChangeVSETULTtoVSETULE	(	SDLoc	dl,
		SDValue	Op1,
		SelectionDAG &	DAG
	)		`[static]`

Try to turn a VSETULT into a VSETULE by modifying its second operand Op1. If non-trivial (for example because it's not constant) return an empty value.

Definition at line 13295 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::ConstantSDNode::isOpaque(), and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().

Referenced by LowerVSETCC().

static bool checkAndUpdateEFLAGSKill	(	MachineBasicBlock::iterator	SelectItr,
		MachineBasicBlock *	BB,
		const TargetRegisterInfo *	TRI
	)		`[static]`

Definition at line 18467 of file X86ISelLowering.cpp.

References llvm::MachineInstr::definesRegister(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::isLiveIn(), llvm::MachineInstr::readsRegister(), llvm::MachineBasicBlock::succ_begin(), and llvm::MachineBasicBlock::succ_end().

static SDValue checkBoolTestSetCCCombine	(	SDValue	Cmp,
		X86::CondCode &	CC
	)		`[static]`

static bool clobbersFlagRegisters ( const SmallVector< StringRef, 4 > & AsmPieces ) [static]

Definition at line 23514 of file X86ISelLowering.cpp.

References llvm::SmallVectorTemplateCommon< T >::begin(), llvm::SmallVectorTemplateCommon< T >::end(), and llvm::SmallVectorTemplateCommon< T >::size().

static SDValue CMPEQCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 21787 of file X86ISelLowering.cpp.

References AND, llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::ISD::BR_CC, llvm::ISD::BRCOND, llvm::ARMISD::CMP, MSP430CC::COND_E, MSP430CC::COND_NE, llvm::X86::COND_NP, llvm::X86::COND_P, llvm::ISD::CopyToReg, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::X86ISD::FSETCC, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), isAndOrOfSetCCs(), llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT, llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), and llvm::ISD::ZERO_EXTEND.

Referenced by PerformAndCombine(), and PerformOrCombine().

static SDValue combineRedundantDWordShuffle	(	SDValue	N,
		MutableArrayRef< int >	Mask,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI
	)		`[static]`

Search for a combinable shuffle across a chain ending in pshufd.

We walk up the chain and look for a combinable shuffle, skipping over shuffles that we could hoist this shuffle's transformation past without altering anything.

Definition at line 19866 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SmallVectorBase::empty(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getPSHUFShuffleMask(), getV4X86ShuffleImm8ForMask(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::SDNode::isOnlyUserOf(), llvm_unreachable, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::X86ISD::UNPCKH, and llvm::X86ISD::UNPCKL.

Referenced by PerformTargetShuffleCombine().

static bool combineRedundantHalfShuffle	(	SDValue	N,
		MutableArrayRef< int >	Mask,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI
	)		`[static]`

Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.

We walk up the chain, skipping shuffles of the other half and looking through shuffles which switch halves trying to find a shuffle of the same pair of dwords.

Definition at line 19998 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getPSHUFShuffleMask(), getV4X86ShuffleImm8ForMask(), llvm::SDValue::hasOneUse(), llvm::X86ISD::PSHUFHW, and llvm::X86ISD::PSHUFLW.

Referenced by PerformTargetShuffleCombine().

static SDValue combineShuffleToAddSub	(	SDNode *	N,
		SelectionDAG &	DAG
	)		`[static]`

Try to combine a shuffle into a target-specific add-sub node.

We combine this directly on the abstract vector shuffle nodes so it is easier to generically match. We also insert dummy vector shuffle nodes for the operands which explicitly discard the lanes which are unused by this operation to try to flow through the rest of the combiner the fact that they're unused.

Definition at line 20171 of file X86ISelLowering.cpp.

References llvm::X86ISD::ADDSUB, llvm::ISD::FADD, llvm::ISD::FSUB, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), isShuffleEquivalent, and llvm::ISD::VECTOR_SHUFFLE.

Referenced by PerformShuffleCombine().

static bool combineX86ShuffleChain	(	SDValue	Op,
		SDValue	Root,
		ArrayRef< int >	Mask,
		int	Depth,
		bool	HasPSHUFB,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

Combine an arbitrary chain of shuffles into a single instruction if possible.

This is the leaf of the recursive combinine below. When we have found some chain of single-use x86 shuffle instructions and accumulated the combined shuffle mask represented by them, this will try to pattern match that mask into either a single instruction if there is a special purpose instruction for this operation, or into a PSHUFB instruction which is a fully general instruction but should only be used to replace chains over a certain depth.

Definition at line 19524 of file X86ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::equals(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::isFloatingPoint(), llvm_unreachable, llvm::HexagonISD::Lo, llvm::X86ISD::MOVDDUP, llvm::X86ISD::MOVHLPS, llvm::X86ISD::MOVLHPS, llvm::X86ISD::MOVSHDUP, llvm::X86ISD::MOVSLDUP, llvm::X86ISD::PSHUFB, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ArrayRef< T >::size(), llvm::SM_SentinelZero, llvm::X86ISD::UNPCKH, and llvm::X86ISD::UNPCKL.

Referenced by combineX86ShufflesRecursively().

static bool combineX86ShufflesRecursively	(	SDValue	Op,
		SDValue	Root,
		ArrayRef< int >	RootMask,
		int	Depth,
		bool	HasPSHUFB,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

Fully generic combining of x86 shuffle instructions.

This should be the last combine run over the x86 shuffle instructions. Once they have been fully optimized, this will recursively consider all chains of single-use shuffle instructions, build a generic model of the cumulative shuffle operation, and check for simpler instructions which implement this operation. We use this primarily for two purposes:

1) Collapse generic shuffles to specialized single instructions when equivalent. In most cases, this is just an encoding size win, but sometimes we will collapse multiple generic shuffles into a single special-purpose shuffle. 2) Look for sequences of shuffle instructions with 3 or more total instructions, and replace them with the slightly more expensive SSSE3 PSHUFB instruction if available. We do this as the last combining step to ensure we avoid using PSHUFB if we can implement the shuffle with a suitable short sequence of other instructions. The PHUFB will either use a register or have to read from memory and so is slightly (but only slightly) more expensive than the other shuffle instructions.

Because this is inherently a quadratic operation (for each shuffle in a chain, we recurse up the chain), the depth is limited to 8 instructions. This should never be an issue in practice as the shuffle lowering doesn't produce sequences of more than 8 instructions.

FIXME: We will currently miss some cases where the redundant shuffling would simplify under the threshold for PSHUFB formation because of combine-ordering. To fix this, we should do the redundant instruction combining in this recursive walk.

Definition at line 19715 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, canWidenShuffleElements(), combineX86ShuffleChain(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), getTargetShuffleMask(), llvm::MVT::getVectorNumElements(), llvm::SDValue::hasOneUse(), llvm::SDNode::isOnlyUserOf(), isTargetShuffle(), llvm::MVT::isVector(), llvm::X86ISD::PSHUFB, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::SmallVectorImpl< T >::reserve(), llvm::SmallVectorImpl< T >::resize(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::ArrayRef< T >::size(), llvm::SM_SentinelZero, llvm::X86ISD::UNPCKH, and llvm::X86ISD::UNPCKL.

Referenced by PerformShuffleCombine().

static void CommuteVectorShuffleMask	(	SmallVectorImpl< int > &	Mask,
		unsigned	NumElems
	)		`[static]`

CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming the two vector operands have swapped position.

Definition at line 4025 of file X86ISelLowering.cpp.

Referenced by isHorizontalBinOp(), LowerVECTOR_SHUFFLE_128v4(), LowerVECTOR_SHUFFLEv32i8(), and LowerVECTOR_SHUFFLEv8i16().

static SDValue Compact8x32ShuffleNode	(	ShuffleVectorSDNode *	SVOp,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 4214 of file X86ISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getVectorShuffle(), isUndefOrEqual(), and llvm::ISD::UNDEF.

Referenced by LowerVECTOR_SHUFFLE_256().

static SDValue Concat128BitVectors	(	SDValue	V1,
		SDValue	V2,
		EVT	VT,
		unsigned	NumElems,
		SelectionDAG &	DAG,
		SDLoc	dl
	)		`[static]`

Concat two 128-bit vectors into a 256 bit vector using VINSERTF128 instructions. This is used because creating CONCAT_VECTOR nodes of BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower large BUILD_VECTORS.

Definition at line 181 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getUNDEF(), and Insert128BitVector().

Referenced by getOnesVector(), and LowerAVXCONCAT_VECTORS().

static SDValue Concat256BitVectors	(	SDValue	V1,
		SDValue	V2,
		EVT	VT,
		unsigned	NumElems,
		SelectionDAG &	DAG,
		SDLoc	dl
	)		`[static]`

Definition at line 188 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getUNDEF(), and Insert256BitVector().

Referenced by LowerAVXCONCAT_VECTORS().

static SDValue CreateCopyOfByValArgument	(	SDValue	Src,
		SDValue	Dst,
		SDValue	Chain,
		ISD::ArgFlagsTy	Flags,
		SelectionDAG &	DAG,
		SDLoc	dl
	)		`[static]`

CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" with size and alignment information specified by the specific parameter attribute. The copy will be passed as a byval function parameter.

Definition at line 2246 of file X86ISelLowering.cpp.

References llvm::ISD::ArgFlagsTy::getByValAlign(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::SelectionDAG::getConstant(), and llvm::SelectionDAG::getMemcpy().

static TargetLoweringObjectFile* createTLOF ( const Triple & TT ) [static]

Definition at line 195 of file X86ISelLowering.cpp.

References llvm::Triple::getArch(), llvm::Triple::isKnownWindowsMSVCEnvironment(), llvm::Triple::isOSBinFormatCOFF(), llvm::Triple::isOSBinFormatELF(), llvm::Triple::isOSBinFormatMachO(), llvm::Triple::isOSLinux(), llvm_unreachable, and llvm::Triple::x86_64.

static SDValue EltsFromConsecutiveLoads	(	EVT	VT,
		SmallVectorImpl< SDValue > &	Elts,
		SDLoc &	DL,
		SelectionDAG &	DAG,
		bool	isAfterLegalize
	)		`[static]`

EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a vector of type 'VT', see if the elements can be replaced by a single large load which has the same value as a build_vector whose operands are 'elts'.

Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a

FIXME: we'd also like to handle the case where the last elements are zero rather than undef via VZEXT_LOAD, but we do not detect that case today. There's even a handy isZeroNode for that purpose.

Definition at line 5896 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::SDNode::hasAnyUseOfValue(), llvm::SelectionDAG::InferPtrAlignment(), llvm::SelectionDAG::isConsecutiveLoad(), llvm::MemSDNode::isInvariant(), llvm::ISD::isNON_EXTLoad(), llvm::MemSDNode::isNonTemporal(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isTypeLegal(), llvm::MemSDNode::isVolatile(), llvm::AArch64DB::LD, llvm::ISD::LOAD, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::ISD::TokenFactor, llvm::ISD::UNDEF, llvm::SelectionDAG::UpdateNodeOperands(), and llvm::X86ISD::VZEXT_LOAD.

Referenced by PerformShuffleCombine().

static MachineBasicBlock* EmitMonitor	(	MachineInstr *	MI,
		MachineBasicBlock *	BB,
		const TargetInstrInfo *	TII,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 18104 of file X86ISelLowering.cpp.

References llvm::MachineInstrBuilder::addOperand(), llvm::X86::AddrNumOperands, llvm::BuildMI(), llvm::TargetOpcode::COPY, llvm::N86::EAX, llvm::N86::ECX, llvm::N86::EDX, llvm::MachineInstr::eraseFromParent(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

static MachineBasicBlock* EmitPCMPSTRI	(	MachineInstr *	MI,
		MachineBasicBlock *	BB,
		const TargetInstrInfo *	TII
	)		`[static]`

static MachineBasicBlock* EmitPCMPSTRM	(	MachineInstr *	MI,
		MachineBasicBlock *	BB,
		const TargetInstrInfo *	TII
	)		`[static]`

Definition at line 18032 of file X86ISelLowering.cpp.

static SDValue EmitTailCallStoreRetAddr	(	SelectionDAG &	DAG,
		MachineFunction &	MF,
		SDValue	Chain,
		SDValue	RetAddrFrIdx,
		EVT	PtrVT,
		unsigned	SlotSize,
		int	FPDiff,
		SDLoc	dl
	)		`[static]`

EmitTailCallStoreRetAddr - Emit a store of the return address if tail call optimization is performed and it is required (FPDiff!=0).

Definition at line 2712 of file X86ISelLowering.cpp.

References llvm::MachineFrameInfo::CreateFixedObject(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), and llvm::SelectionDAG::getStore().

static MachineBasicBlock* EmitXBegin	(	MachineInstr *	MI,
		MachineBasicBlock *	MBB,
		const TargetInstrInfo *	TII
	)		`[static]`

Utility function to emit xbegin specifying the start of an RTM region.

Definition at line 17974 of file X86ISelLowering.cpp.

static SDValue ExpandHorizontalBinOp	(	const SDValue &	V0,
		const SDValue &	V1,
		SDLoc	DL,
		SelectionDAG &	DAG,
		unsigned	X86Opcode,
		bool	Mode,
		bool	isUndefLO,
		bool	isUndefHI
	)		`[static]`

Emit a sequence of two 128-bit horizontal add/sub followed by a concat_vector.

This is a helper function of PerformBUILD_VECTORCombine. This function expects two 256-bit vectors called V0 and V1. At first, each vector is split into two separate 128-bit vectors. Then, the resulting 128-bit vectors are used to implement two horizontal binary operations.

The kind of horizontal binary operation is defined by X86Opcode.

Mode specifies how the 128-bit parts of V0 and V1 are passed in input to the two new horizontal binop. When Mode is set, the first horizontal binop dag node would take as input the lower 128-bit of V0 and the upper 128-bit of V0. The second horizontal binop dag node would take as input the lower 128-bit of V1 and the upper 128-bit of V1. Example: HADD V0_LO, V0_HI HADD V1_LO, V1_HI

Otherwise, the first horizontal binop dag node takes as input the lower 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1. Example: HADD V0_LO, V1_LO HADD V0_HI, V1_HI

If isUndefLO is set, then the algorithm propagates UNDEF to the lower 128-bits of the result. If isUndefHI is set, then UNDEF is propagated to the upper 128-bits of the result.

Definition at line 6440 of file X86ISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, Extract128BitVector(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::AArch64CC::HI, llvm::EVT::is256BitVector(), llvm::AArch64CC::LO, and llvm::ISD::UNDEF.

Referenced by PerformBUILD_VECTORCombine().

static SDValue Extract128BitVector	(	SDValue	Vec,
		unsigned	IdxVal,
		SelectionDAG &	DAG,
		SDLoc	dl
	)		`[static]`

Generate a DAG to grab 128-bits from a vector > 128 bits. This sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128 or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4 instructions or a simple subregister reference. Idx is an index in the 128 bits we want. It need not be aligned to a 128-bit bounday. That makes lowering EXTRACT_VECTOR_ELT operations easier.

Definition at line 119 of file X86ISelLowering.cpp.

References ExtractSubVector(), llvm::SDValue::getValueType(), llvm::EVT::is256BitVector(), and llvm::EVT::is512BitVector().

Referenced by ExpandHorizontalBinOp(), Lower256IntArith(), Lower256IntVSETCC(), LowerEXTRACT_SUBVECTOR(), LowerShift(), LowerVECTOR_SHUFFLE_256(), LowerVectorBroadcast(), PerformSELECTCombine(), PerformShuffleCombine256(), PerformSTORECombine(), and PromoteSplat().

static SDValue Extract256BitVector	(	SDValue	Vec,
		unsigned	IdxVal,
		SelectionDAG &	DAG,
		SDLoc	dl
	)		`[static]`

Generate a DAG to grab 256-bits from a 512-bit vector.

Definition at line 127 of file X86ISelLowering.cpp.

References ExtractSubVector(), llvm::SDValue::getValueType(), and llvm::EVT::is512BitVector().

Referenced by LowerEXTRACT_SUBVECTOR().

static SDValue ExtractSubVector	(	SDValue	Vec,
		unsigned	IdxVal,
		SelectionDAG &	DAG,
		SDLoc	dl,
		unsigned	vectorWidth
	)		`[static]`

Definition at line 77 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::makeArrayRef(), llvm::SDNode::op_begin(), and llvm::ISD::UNDEF.

Referenced by Extract128BitVector(), and Extract256BitVector().

static bool FuncIsMadeTailCallSafe	(	CallingConv::ID	CC,
		bool	GuaranteedTailCallOpt
	)		`[static]`

FuncIsMadeTailCallSafe - Return true if the function is being made into a tailcall target by changing its ABI.

Definition at line 2283 of file X86ISelLowering.cpp.

References IsTailCallConvention().

static ArrayRef<MCPhysReg> get64BitArgumentGPRs	(	CallingConv::ID	CallConv,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 2330 of file X86ISelLowering.cpp.

References llvm::sys::path::begin(), llvm::sys::path::end(), and llvm::makeArrayRef().

static ArrayRef<MCPhysReg> get64BitArgumentXMMs	(	MachineFunction &	MF,
		CallingConv::ID	CallConv,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 2348 of file X86ISelLowering.cpp.

References llvm::sys::path::begin(), llvm::sys::path::end(), llvm::Function::getAttributes(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getTarget(), llvm::makeArrayRef(), llvm::None, llvm::TargetMachine::Options, and llvm::TargetOptions::UseSoftFloat.

static unsigned getExtractVEXTRACTImmediate	(	SDNode *	N,
		unsigned	vecWidth
	)		`[static]`

Definition at line 4868 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), and llvm_unreachable.

Referenced by llvm::X86::getExtractVEXTRACT128Immediate(), and llvm::X86::getExtractVEXTRACT256Immediate().

static SDValue getGatherNode	(	unsigned	Opc,
		SDValue	Op,
		SelectionDAG &	DAG,
		SDValue	Src,
		SDValue	Mask,
		SDValue	Base,
		SDValue	Index,
		SDValue	ScaleOp,
		SDValue	Chain,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 15290 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getRegister(), llvm::ConstantSDNode::getSExtValue(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), getZeroVector(), llvm::ConstantSDNode::getZExtValue(), and llvm::ISD::UNDEF.

Referenced by LowerINTRINSIC_W_CHAIN().

static SDValue getINSERTPS	(	ShuffleVectorSDNode *	SVOp,
		SDLoc &	dl,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 10198 of file X86ISelLowering.cpp.

References llvm::ArrayRef< T >::begin(), llvm::ArrayRef< T >::end(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getVectorElementType(), llvm::ISD::INSERT_VECTOR_ELT, llvm::X86ISD::INSERTPS, MayFoldLoad(), NarrowVectorLoadToElement(), llvm::ISD::SCALAR_TO_VECTOR, and llvm::NVPTX::PTXLdStInstCode::V2.

static unsigned getInsertVINSERTImmediate	(	SDNode *	N,
		unsigned	vecWidth
	)		`[static]`

Definition at line 4883 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), and llvm_unreachable.

Referenced by llvm::X86::getInsertVINSERT128Immediate(), and llvm::X86::getInsertVINSERT256Immediate().

static SDValue getLegalSplat	(	SelectionDAG &	DAG,
		SDValue	V,
		int	EltNo
	)		`[static]`

getLegalSplat - Generate a legal splat with supported x86 shuffles

Definition at line 5194 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), and llvm_unreachable.

Referenced by PromoteSplat().

static void getMaxByValAlign	(	Type *	Ty,
		unsigned &	MaxAlign
	)		`[static]`

getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment.

Definition at line 1740 of file X86ISelLowering.cpp.

static SDValue getMOVDDup	(	SDValue &	Op,
		SDLoc &	dl,
		SDValue	V1,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 10077 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), getTargetShuffleNode(), and llvm::X86ISD::MOVDDUP.

static SDValue getMOVHighToLow	(	SDValue &	Op,
		SDLoc &	dl,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 10107 of file X86ISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), getTargetShuffleNode(), llvm::X86ISD::MOVHLPS, llvm::ISD::UNDEF, and llvm::NVPTX::PTXLdStInstCode::V2.

static SDValue getMOVL	(	SelectionDAG &	DAG,
		SDLoc	dl,
		EVT	VT,
		SDValue	V1,
		SDValue	V2
	)		`[static]`

getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd operation of specified width.

Definition at line 5138 of file X86ISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

static SDValue getMOVLowToHigh	(	SDValue &	Op,
		SDLoc &	dl,
		SelectionDAG &	DAG,
		bool	HasSSE2
	)		`[static]`

Definition at line 10088 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), getTargetShuffleNode(), llvm::X86ISD::MOVLHPD, llvm::X86ISD::MOVLHPS, and llvm::NVPTX::PTXLdStInstCode::V2.

static SDValue getMOVLP	(	SDValue &	Op,
		SDLoc &	dl,
		SelectionDAG &	DAG,
		bool	HasSSE2
	)		`[static]`

Definition at line 10123 of file X86ISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMask(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getOperand(), getShuffleSHUFImmediate(), llvm::SDValue::getSimpleValueType(), getTargetShuffleNode(), llvm::MVT::getVectorNumElements(), isMOVLMask(), MayFoldIntoStore(), MayFoldVectorLoad(), llvm::X86ISD::MOVLPD, llvm::X86ISD::MOVLPS, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSS, llvm::X86ISD::SHUFP, and llvm::NVPTX::PTXLdStInstCode::V2.

static unsigned getNumOfConsecutiveZeros	(	ShuffleVectorSDNode *	SVOp,
		unsigned	NumElems,
		bool	ZerosFromLeft,
		SelectionDAG &	DAG,
		unsigned	PreferredNum = `-1U`
	)		`[static]`

getNumOfConsecutiveZeros - Return the number of elements of a vector shuffle operation which come from a consecutively from a zero. The search can start in two different directions, from left or right. We count undefs as zeros until PreferredNum is reached.

Definition at line 5507 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), getShuffleScalarElt(), llvm::X86::isZeroNode(), and llvm::ISD::UNDEF.

Referenced by isVectorShiftLeft(), and isVectorShiftRight().

static SDValue getOnesVector	(	MVT	VT,
		bool	HasInt256,
		SelectionDAG &	DAG,
		SDLoc	dl
	)		`[static]`

getOnesVector - Returns a vector of specified type with all bits set. Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their original type, ensuring they get CSE'd.

Definition at line 5104 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, Concat128BitVectors(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::isVector(), and llvm_unreachable.

static unsigned getOpcodeForFMAIntrinsic ( unsigned IntNo ) [static]

Definition at line 14858 of file X86ISelLowering.cpp.

References llvm::X86ISD::FMADD, llvm::X86ISD::FMADDSUB, llvm::X86ISD::FMSUB, llvm::X86ISD::FMSUBADD, llvm::X86ISD::FNMADD, llvm::X86ISD::FNMSUB, and llvm_unreachable.

Referenced by LowerINTRINSIC_WO_CHAIN().

static SDValue getPrefetchNode	(	unsigned	Opc,
		SDValue	Op,
		SelectionDAG &	DAG,
		SDValue	Mask,
		SDValue	Base,
		SDValue	Index,
		SDValue	ScaleOp,
		SDValue	Chain
	)		`[static]`

Definition at line 15340 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::ConstantSDNode::getSExtValue(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::getVectorNumElements(), and llvm::ConstantSDNode::getZExtValue().

Referenced by LowerINTRINSIC_W_CHAIN().

static SDValue getPSHUFB	(	ArrayRef< int >	MaskVals,
		SDValue	V1,
		SDLoc &	dl,
		SelectionDAG &	DAG
	)		`[static]`

Generate a PSHUFB if possible. Selects elements from V1 according to MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to shuffle the element at InputIdx in V1 to OutputIdx in the result. If MaskVals refers to elements outside of V1 or is undef (-1), insert a zero.

Definition at line 9267 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::X86ISD::PSHUFB, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), ShuffleCrosses128bitLane(), and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by LowerVECTOR_SHUFFLEv16i16(), LowerVECTOR_SHUFFLEv32i8(), and LowerVECTOR_SHUFFLEv8i16().

static SmallVector<int, 4> getPSHUFShuffleMask ( SDValue N ) [static]

Get the PSHUF-style mask from PSHUF node.

This is a very minor wrapper around getTargetShuffleMask to easy forming v4 PSHUF-style masks that can be reused with such instructions.

Definition at line 19837 of file X86ISelLowering.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::SmallVectorImpl< T >::erase(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getSimpleValueType(), getTargetShuffleMask(), llvm_unreachable, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, and llvm::SmallVectorImpl< T >::resize().

Referenced by combineRedundantDWordShuffle(), combineRedundantHalfShuffle(), and PerformTargetShuffleCombine().

static void getReadPerformanceCounter	(	SDNode *	N,
		SDLoc	DL,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget,
		SmallVectorImpl< SDValue > &	Results
	)		`[static]`

static void getReadTimeStampCounter	(	SDNode *	N,
		SDLoc	DL,
		unsigned	Opcode,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget,
		SmallVectorImpl< SDValue > &	Results
	)		`[static]`

static SDValue getScatterNode	(	unsigned	Opc,
		SDValue	Op,
		SelectionDAG &	DAG,
		SDValue	Src,
		SDValue	Mask,
		SDValue	Base,
		SDValue	Index,
		SDValue	ScaleOp,
		SDValue	Chain
	)		`[static]`

Definition at line 15317 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::ConstantSDNode::getSExtValue(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), and llvm::ConstantSDNode::getZExtValue().

Referenced by LowerINTRINSIC_W_CHAIN().

static unsigned getShuffleAlignrImmediate	(	ShuffleVectorSDNode *	SVOp,
		bool	InterLane
	)		`[static]`

Return the appropriate immediate to shuffle the specified VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with VALIGN (if Interlane is true) instructions.

Definition at line 4831 of file X86ISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), and llvm::MVT::is512BitVector().

Referenced by getShufflePALIGNRImmediate(), and getShuffleVALIGNImmediate().

static unsigned getShufflePALIGNRImmediate ( ShuffleVectorSDNode * SVOp ) [static]

Return the appropriate immediate to shuffle the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.

Definition at line 4857 of file X86ISelLowering.cpp.

References getShuffleAlignrImmediate().

static unsigned getShufflePSHUFHWImmediate ( ShuffleVectorSDNode * N ) [static]

getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.

Definition at line 4782 of file X86ISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getSimpleValueType(), and llvm::MVT::getVectorNumElements().

Referenced by LowerVECTOR_SHUFFLEv8i16().

static unsigned getShufflePSHUFLWImmediate ( ShuffleVectorSDNode * N ) [static]

getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.

Definition at line 4806 of file X86ISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getSimpleValueType(), and llvm::MVT::getVectorNumElements().

Referenced by LowerVECTOR_SHUFFLEv8i16().

static SDValue getShuffleScalarElt	(	SDNode *	N,
		unsigned	Index,
		SelectionDAG &	DAG,
		unsigned	Depth
	)		`[static]`

getShuffleScalarElt - Returns the scalar element that will make up the ith element of the result of the vector shuffle.

Definition at line 5441 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), getTargetShuffleMask(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), isTargetShuffle(), llvm::EVT::isVector(), and llvm::ISD::SCALAR_TO_VECTOR.

Referenced by getNumOfConsecutiveZeros(), and PerformShuffleCombine().

static unsigned getShuffleSHUFImmediate ( ShuffleVectorSDNode * N ) [static]

getShuffleSHUFImmediate - Return the appropriate immediate to shuffle the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. Handles 128-bit and 256-bit.

Definition at line 4752 of file X86ISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), and llvm::MVT::getVectorNumElements().

Referenced by getMOVLP().

static unsigned getShuffleVALIGNImmediate ( ShuffleVectorSDNode * SVOp ) [static]

Return the appropriate immediate to shuffle the specified VECTOR_SHUFFLE mask with the VALIGN instruction.

Definition at line 4863 of file X86ISelLowering.cpp.

References getShuffleAlignrImmediate().

static SDValue getShuffleVectorZeroOrUndef	(	SDValue	V2,
		unsigned	Idx,
		bool	IsZero,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified vector of zero or undef vector. This produces a shuffle where the low element of V2 is swizzled into the zero/undef vector, landing at element Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).

Definition at line 5262 of file X86ISelLowering.cpp.

References llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), getZeroVector(), and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().

static unsigned getShuffleVPERM2X128Immediate ( ShuffleVectorSDNode * SVOp ) [static]

getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.

Definition at line 4491 of file X86ISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getSimpleValueType(), and llvm::MVT::getVectorNumElements().

static bool getTargetShuffleMask	(	SDNode *	N,
		MVT	VT,
		SmallVectorImpl< int > &	Mask,
		bool &	IsUnary
	)		`[static]`

getTargetShuffleMask - Calculates the shuffle mask corresponding to the target specific opcode. Returns true if the Mask could be calculated. Sets IsUnary to true if only uses one source. Note that this will set IsUnary for shuffles which use a single input multiple times, and in those cases it will adjust the mask to only have indices within that single input.

Definition at line 5282 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::DecodeMOVHLPSMask(), llvm::DecodeMOVLHPSMask(), llvm::DecodeMOVSHDUPMask(), llvm::DecodeMOVSLDUPMask(), llvm::DecodePALIGNRMask(), llvm::DecodePSHUFBMask(), llvm::DecodePSHUFHWMask(), llvm::DecodePSHUFLWMask(), llvm::DecodePSHUFMask(), llvm::DecodeSHUFPMask(), llvm::DecodeUNPCKHMask(), llvm::DecodeUNPCKLMask(), llvm::DecodeVPERM2X128Mask(), llvm::DecodeVPERMMask(), llvm::dyn_cast(), llvm::SmallVectorBase::empty(), llvm::APInt::getLoBits(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::APInt::getZExtValue(), llvm::EVT::isInteger(), llvm::EVT::isVector(), llvm_unreachable, llvm::APInt::lshr(), llvm::X86ISD::MOVDDUP, llvm::X86ISD::MOVHLPS, llvm::X86ISD::MOVLHPD, llvm::X86ISD::MOVLHPS, llvm::X86ISD::MOVLPD, llvm::X86ISD::MOVLPS, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSHDUP, llvm::X86ISD::MOVSLDUP, llvm::X86ISD::MOVSS, llvm::X86ISD::PALIGNR, llvm::X86ISD::PSHUFB, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::X86ISD::SHUFP, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, llvm::X86ISD::VPERM2X128, llvm::X86ISD::VPERMI, llvm::X86ISD::VPERMILP, and llvm::ARMISD::Wrapper.

Referenced by combineX86ShufflesRecursively(), getPSHUFShuffleMask(), getShuffleScalarElt(), and XFormVExtractWithShuffleIntoLoad().

static SDValue getTargetShuffleNode	(	unsigned	Opc,
		SDLoc	dl,
		EVT	VT,
		SDValue	V1,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 3566 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm_unreachable, llvm::X86ISD::MOVDDUP, llvm::X86ISD::MOVSHDUP, and llvm::X86ISD::MOVSLDUP.

Referenced by getMOVDDup(), getMOVHighToLow(), getMOVLowToHigh(), getMOVLP(), LowerShift(), LowerVECTOR_SHUFFLEv8i16(), and PerformSELECTCombine().

static SDValue getTargetShuffleNode	(	unsigned	Opc,
		SDLoc	dl,
		EVT	VT,
		SDValue	V1,
		unsigned	TargetMask,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 3577 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm_unreachable, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::X86ISD::VPERMI, and llvm::X86ISD::VPERMILP.

static SDValue getTargetShuffleNode	(	unsigned	Opc,
		SDLoc	dl,
		EVT	VT,
		SDValue	V1,
		SDValue	V2,
		unsigned	TargetMask,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 3591 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm_unreachable, llvm::X86ISD::PALIGNR, llvm::X86ISD::SHUFP, llvm::X86ISD::VALIGN, and llvm::X86ISD::VPERM2X128.

static SDValue getTargetShuffleNode	(	unsigned	Opc,
		SDLoc	dl,
		EVT	VT,
		SDValue	V1,
		SDValue	V2,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 3605 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm_unreachable, llvm::X86ISD::MOVHLPS, llvm::X86ISD::MOVLHPD, llvm::X86ISD::MOVLHPS, llvm::X86ISD::MOVLPD, llvm::X86ISD::MOVLPS, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSS, llvm::X86ISD::UNPCKH, and llvm::X86ISD::UNPCKL.

static SDValue getTargetVShiftByConstNode	(	unsigned	Opc,
		SDLoc	dl,
		MVT	VT,
		SDValue	SrcOp,
		uint64_t	ShiftAmt,
		SelectionDAG &	DAG
	)		`[static]`

static SDValue getTargetVShiftNode	(	unsigned	Opc,
		SDLoc	dl,
		MVT	VT,
		SDValue	SrcOp,
		SDValue	ShAmt,
		SelectionDAG &	DAG
	)		`[static]`

static SDValue GetTLSADDR	(	SelectionDAG &	DAG,
		SDValue	Chain,
		GlobalAddressSDNode *	GA,
		SDValue *	InFlag,
		const EVT	PtrVT,
		unsigned	ReturnReg,
		unsigned char	OperandFlags,
		bool	LocalDynamic = `false`
	)		`[static]`

Definition at line 11513 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getFrameInfo(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::TLSModel::LocalDynamic, llvm::MachineFrameInfo::setAdjustsStack(), llvm::X86ISD::TLSADDR, and llvm::X86ISD::TLSBASEADDR.

Referenced by LowerToTLSGeneralDynamicModel32(), LowerToTLSGeneralDynamicModel64(), and LowerToTLSLocalDynamicModel().

static int getUnderlyingExtractedFromVec	(	SDValue &	ExtractedFromVec,
		SDValue	ExtIdx
	)		`[static]`

For an EXTRACT_VECTOR_ELT with a constant index return the real underlying vector and index.

Modifies ExtractedFromVec to the real vector and returns the real index.

Definition at line 6136 of file X86ISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), and isUndefOrInRange().

Referenced by buildFromShuffleMostly().

static SDValue getUnpackh	(	SelectionDAG &	DAG,
		SDLoc	dl,
		MVT	VT,
		SDValue	V1,
		SDValue	V2
	)		`[static]`

getUnpackh - Returns a vector_shuffle node for an unpackh operation.

Definition at line 5161 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by LowerAVXExtend(), and PromoteSplati8i16().

static SDValue getUnpackl	(	SelectionDAG &	DAG,
		SDLoc	dl,
		MVT	VT,
		SDValue	V1,
		SDValue	V2
	)		`[static]`

getUnpackl - Returns a vector_shuffle node for an unpackl operation.

Definition at line 5149 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by LowerAVXExtend(), and PromoteSplati8i16().

static SDValue getV4X86ShuffleImm8ForMask	(	ArrayRef< int >	Mask,
		SelectionDAG &	DAG
	)		`[static]`

Get a 4-lane 8-bit shuffle immediate for a mask.

This helper function produces an 8-bit shuffle immediate corresponding to the ubiquitous shuffle encoding scheme used in x86 instructions for shuffling 4 lanes. It can be used with most of the PSHUF instructions for example.

NB: We rely heavily on "undef" masks preserving the input lane.

Definition at line 7199 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), and llvm::ArrayRef< T >::size().

Referenced by combineRedundantDWordShuffle(), combineRedundantHalfShuffle(), lowerV2I64VectorShuffle(), lowerV4F32VectorShuffle(), lowerV4I32VectorShuffle(), lowerV8I16SingleInputVectorShuffle(), and PerformTargetShuffleCombine().

static SDValue getVectorMaskingNode	(	SDValue	Op,
		SDValue	Mask,
		SDValue	PreservedSrc,
		SelectionDAG &	DAG
	)		`[static]`

Return (vselect Mask, Op, PreservedSrc) along with the necessary casting for Mask when lowering masking intrinsics.

Definition at line 14845 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::isSimple(), and llvm::ISD::VSELECT.

Referenced by LowerINTRINSIC_WO_CHAIN().

static SDValue getVShift	(	bool	isLeft,
		EVT	VT,
		SDValue	SrcOp,
		unsigned	NumBits,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		SDLoc	dl
	)		`[static]`

getVShift - Return a vector logical shift node.

Definition at line 5800 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getScalarShiftAmountTy(), llvm::SDValue::getValueType(), llvm::EVT::is128BitVector(), llvm::X86ISD::VSHLDQ, and llvm::X86ISD::VSRLDQ.

static SDValue getVZextMovL	(	MVT	VT,
		MVT	OpVT,
		SDValue	SrcOp,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget,
		SDLoc	dl
	)		`[static]`

getVZextMovL - Return a zero-extending vector move low node.

Definition at line 9774 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), isScalarLoadToVector(), llvm::AArch64DB::LD, llvm::ISD::SCALAR_TO_VECTOR, and llvm::X86ISD::VZEXT_MOVL.

Referenced by NormalizeVectorShuffle().

static SDValue getZeroVector	(	EVT	VT,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG,
		SDLoc	dl
	)		`[static]`

getZeroVector - Returns a vector of specified type with all zero elements.

Definition at line 5057 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetConstantFP(), llvm::EVT::getVectorNumElements(), llvm::EVT::is128BitVector(), llvm::EVT::is256BitVector(), llvm::EVT::is512BitVector(), llvm::EVT::isVector(), and llvm_unreachable.

Referenced by getGatherNode(), getShuffleVectorZeroOrUndef(), LowerAVXExtend(), LowerBuildVectorv16i8(), LowerBuildVectorv8i16(), LowerScalarImmediateShift(), lowerV16I8VectorShuffle(), LowerVSETCC(), NormalizeVectorShuffle(), performShiftToAllZeros(), and PerformShuffleCombine256().

static bool hasFPCMov ( unsigned X86CC ) [static]

hasFPCMov - is there a floating point cmov for the specific X86 condition code. Current x86 isa includes the following FP cmov instructions: fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.

Definition at line 3800 of file X86ISelLowering.cpp.

References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, MSP430CC::COND_E, MSP430CC::COND_NE, llvm::X86::COND_NP, and llvm::X86::COND_P.

Referenced by PerformCMOVCombine().

static bool hasNonFlagsUse ( SDValue Op ) [static]

return true if Op has a use that doesn't just read flags.

Definition at line 12786 of file X86ISelLowering.cpp.

References llvm::ISD::BRCOND, llvm::SDNode::getOpcode(), llvm::SDNode::use_iterator::getOperandNo(), llvm::SDNode::hasOneUse(), llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::TRUNCATE, llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

static SDValue Insert128BitVector	(	SDValue	Result,
		SDValue	Vec,
		unsigned	IdxVal,
		SelectionDAG &	DAG,
		SDLoc	dl
	)		`[static]`

Generate a DAG to put 128-bits into a vector > 128 bits. This sets things up to match to an AVX VINSERTF128/VINSERTI128 or AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a simple superregister reference. Idx is an index in the 128 bits we want. It need not be aligned to a 128-bit bounday. That makes lowering INSERT_VECTOR_ELT operations easier.

Definition at line 163 of file X86ISelLowering.cpp.

References llvm::SDValue::getValueType(), InsertSubVector(), and llvm::EVT::is128BitVector().

Referenced by Concat128BitVectors(), LowerINSERT_SUBVECTOR(), LowerSCALAR_TO_VECTOR(), PerformLOADCombine(), and PerformShuffleCombine256().

static SDValue Insert256BitVector	(	SDValue	Result,
		SDValue	Vec,
		unsigned	IdxVal,
		SelectionDAG &	DAG,
		SDLoc	dl
	)		`[static]`

Definition at line 170 of file X86ISelLowering.cpp.

References llvm::SDValue::getValueType(), InsertSubVector(), and llvm::EVT::is256BitVector().

Referenced by Concat256BitVectors(), and LowerINSERT_SUBVECTOR().

static SDValue InsertSubVector	(	SDValue	Result,
		SDValue	Vec,
		unsigned	IdxVal,
		SelectionDAG &	DAG,
		SDLoc	dl,
		unsigned	vectorWidth
	)		`[static]`

Definition at line 133 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::ISD::INSERT_SUBVECTOR, and llvm::ISD::UNDEF.

Referenced by Insert128BitVector(), and Insert256BitVector().

static bool isAlignrMask	(	ArrayRef< int >	Mask,
		MVT	VT,
		bool	InterLane
	)		`[static]`

Return true if the mask specifies a shuffle of elements that is suitable for input to intralane (palignr) or interlane (valign) vector right-shift.

Definition at line 3934 of file X86ISelLowering.cpp.

References llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), isUndefOrEqual(), and isUndefOrInRange().

Referenced by isPALIGNRMask(), and isVALIGNMask().

static bool isAllOnes ( SDValue V ) [static]

Definition at line 13101 of file X86ISelLowering.cpp.

References llvm::dyn_cast(), and llvm::ConstantSDNode::isAllOnesValue().

Referenced by PerformSELECTCombine().

static bool isAndOrOfSetCCs	(	SDValue	Op,
		unsigned &	Opc
	)		`[static]`

Definition at line 14174 of file X86ISelLowering.cpp.

References AND, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), OR, and llvm::ISD::SETCC.

Referenced by CMPEQCombine().

static bool isBlendMask	(	ArrayRef< int >	MaskVals,
		MVT	VT,
		bool	hasSSE41,
		bool	hasInt256,
		unsigned *	MaskOut = `nullptr`
	)		`[static]`

Definition at line 9179 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), and llvm::MVT::is512BitVector().

Referenced by LowerVECTOR_SHUFFLEtoBlend().

static bool IsCCallConvention ( CallingConv::ID CC ) [static]

Return true if the calling convention is a C calling convention.

Definition at line 2264 of file X86ISelLowering.cpp.

References llvm::CallingConv::C, llvm::CallingConv::X86_64_SysV, and llvm::CallingConv::X86_64_Win64.

static bool isCommutedMOVLMask	(	ArrayRef< int >	Mask,
		MVT	VT,
		bool	V2IsSplat = `false`,
		bool	V2IsUndef = `false`
	)		`[static]`

isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse of what x86 movss want. X86 movs requires the lowest element to be lowest element of vector 2 and the other elements to come from vector 1 in order.

Definition at line 4590 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), isUndefOrEqual(), and isUndefOrInRange().

Referenced by NormalizeVectorShuffle().

static bool isHalfCrossingShuffleMask ( ArrayRef< int > Mask ) [static]

Definition at line 8844 of file X86ISelLowering.cpp.

References llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().

Referenced by lowerV4F64VectorShuffle(), and lowerV4I64VectorShuffle().

static bool isHorizontalBinOp	(	const BuildVectorSDNode *	N,
		unsigned	Opcode,
		SelectionDAG &	DAG,
		unsigned	BaseIdx,
		unsigned	LastIdx,
		SDValue &	V0,
		SDValue &	V1
	)		`[static]`

Return true if N implements a horizontal binop and return the operands for the horizontal binop into V0 and V1.

This is a helper function of PerformBUILD_VECTORCombine. This function checks that the build_vector N in input implements a horizontal operation. Parameter Opcode defines the kind of horizontal operation to match. For example, if Opcode is equal to ISD::ADD, then this function checks if N implements a horizontal arithmetic add; if instead Opcode is equal to ISD::SUB, then this function checks if this is a horizontal arithmetic sub.

This function only analyzes elements of N whose indices are in range [BaseIdx, LastIdx).

Definition at line 6332 of file X86ISelLowering.cpp.

References ADD, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SDNode::hasOneUse(), llvm::EVT::isVector(), and llvm::ISD::UNDEF.

Referenced by PerformAddCombine(), PerformBUILD_VECTORCombine(), PerformFADDCombine(), PerformFSUBCombine(), and PerformSubCombine().

static bool isHorizontalBinOp	(	SDValue &	LHS,
		SDValue &	RHS,
		bool	IsCommutative
	)		`[static]`

isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" and return the operands for the horizontal operation in LHS and RHS. A horizontal operation performs the binary operation on successive elements of its first operand, then on successive elements of its second operand, returning the resulting values in a vector. For example, if A = < float a0, float a1, float a2, float a3 > and B = < float b0, float b1, float b2, float b3 > then the result of doing a horizontal operation on A and B is A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. In short, LHS and RHS are inspected to see if LHS op RHS is of the form A horizontal-op B, for some already available A and B, and if so then LHS is set to A, RHS to B, and the routine returns 'true'. Note that the binary operation should have the property that if one of the operands is UNDEF then the result is UNDEF.

Definition at line 22565 of file X86ISelLowering.cpp.

References llvm::ARM_PROC::A, llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::ArrayRef< T >::begin(), llvm::CallingConv::C, CommuteVectorShuffleMask(), llvm::ArrayRef< T >::end(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::ISD::UNDEF, and llvm::ISD::VECTOR_SHUFFLE.

static bool isINSERT64x4Mask	(	ArrayRef< int >	Mask,
		MVT	VT,
		unsigned int *	Imm
	)		`[static]`

Definition at line 4412 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::MVT::is512BitVector(), and isSequentialOrUndefInRange().

static bool isINSERTPSMask	(	ArrayRef< int >	Mask,
		MVT	VT
	)		`[static]`

isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to INSERTPS. i. e: If all but one element come from the same vector.

Definition at line 4182 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), and llvm::MVT::is128BitVector().

static bool isMOVDDUPMask	(	ArrayRef< int >	Mask,
		MVT	VT
	)		`[static]`

isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to 128-bit version of MOVDDUP.

Definition at line 4682 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), and isUndefOrEqual().

static bool isMOVDDUPYMask	(	ArrayRef< int >	Mask,
		MVT	VT,
		bool	HasFp256
	)		`[static]`

isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to 256-bit version of MOVDDUP.

Definition at line 4662 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::MVT::is256BitVector(), and isUndefOrEqual().

static bool isMOVHLPS_v_undef_Mask	(	ArrayRef< int >	Mask,
		MVT	VT
	)		`[static]`

isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, <2, 3, 2, 3>

Definition at line 4120 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), and isUndefOrEqual().

static bool isMOVHLPSMask	(	ArrayRef< int >	Mask,
		MVT	VT
	)		`[static]`

isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVHLPS.

Definition at line 4101 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), and isUndefOrEqual().

static bool isMOVLHPSMask	(	ArrayRef< int >	Mask,
		MVT	VT
	)		`[static]`

isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVLHPS.

Definition at line 4159 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), and isUndefOrEqual().

static bool isMOVLMask	(	ArrayRef< int >	Mask,
		EVT	VT
	)		`[static]`

isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVSS, MOVSD, and MOVD, i.e. setting the lowest element.

Definition at line 4436 of file X86ISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::is128BitVector(), and isUndefOrEqual().

Referenced by getMOVLP(), and NormalizeVectorShuffle().

static bool isMOVLPMask	(	ArrayRef< int >	Mask,
		MVT	VT
	)		`[static]`

isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.

Definition at line 4137 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), and isUndefOrEqual().

static bool isMOVSHDUPMask	(	ArrayRef< int >	Mask,
		MVT	VT,
		const X86Subtarget *	Subtarget
	)		`[static]`

isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVSHDUP. Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>

Definition at line 4614 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), and isUndefOrEqual().

static bool isMOVSLDUPMask	(	ArrayRef< int >	Mask,
		MVT	VT,
		const X86Subtarget *	Subtarget
	)		`[static]`

isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVSLDUP. Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>

Definition at line 4638 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), and isUndefOrEqual().

static bool isNoopShuffleMask ( ArrayRef< int > Mask ) [static]

Tiny helper function to identify a no-op mask.

This is a somewhat boring predicate function. It checks whether the mask array input, which is assumed to be a single-input shuffle mask of the kind used by the X86 shuffle instructions (not a fully general ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an in-place shuffle are 'no-op's.

Definition at line 7134 of file X86ISelLowering.cpp.

References llvm::ArrayRef< T >::size().

Referenced by lowerV4F32VectorShuffle(), lowerV8I16SingleInputVectorShuffle(), lowerVectorShuffleAsByteRotate(), and PerformTargetShuffleCombine().

static bool isPALIGNRMask	(	ArrayRef< int >	Mask,
		MVT	VT,
		const X86Subtarget *	Subtarget
	)		`[static]`

Return true if the node specifies a shuffle of elements that is suitable for input to PALIGNR.

Definition at line 4002 of file X86ISelLowering.cpp.

References llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), and isAlignrMask().

static bool isPermImmMask	(	ArrayRef< int >	Mask,
		MVT	VT,
		unsigned &	Imm8
	)		`[static]`

Definition at line 4514 of file X86ISelLowering.cpp.

References llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), and isUndefOrInRange().

static bool isPSHUFDMask	(	ArrayRef< int >	Mask,
		MVT	VT
	)		`[static]`

isPSHUFDMask - Return true if the node specifies a shuffle of elements that is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference the second operand.

Definition at line 3865 of file X86ISelLowering.cpp.

static bool isPSHUFHWMask	(	ArrayRef< int >	Mask,
		MVT	VT,
		bool	HasInt256
	)		`[static]`

isPSHUFHWMask - Return true if the node specifies a shuffle of elements that is suitable for input to PSHUFHW.

Definition at line 3875 of file X86ISelLowering.cpp.

References isSequentialOrUndefInRange(), and isUndefOrInRange().

static bool isPSHUFLWMask	(	ArrayRef< int >	Mask,
		MVT	VT,
		bool	HasInt256
	)		`[static]`

isPSHUFLWMask - Return true if the node specifies a shuffle of elements that is suitable for input to PSHUFLW.

Definition at line 3904 of file X86ISelLowering.cpp.

References isSequentialOrUndefInRange(), and isUndefOrInRange().

static bool isScalarLoadToVector	(	SDNode *	N,
		LoadSDNode **	LD = `nullptr`
	)		`[static]`

isScalarLoadToVector - Returns true if the node is a scalar load that is promoted to a vector. It also returns the LoadSDNode by reference if required.

Definition at line 4963 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::isNON_EXTLoad(), llvm::AArch64DB::LD, and llvm::ISD::SCALAR_TO_VECTOR.

Referenced by getVZextMovL(), and ShouldXformToMOVLP().

static bool isSequentialOrUndefInRange	(	ArrayRef< int >	Mask,
		unsigned	Pos,
		unsigned	Size,
		int	Low
	)		`[static]`

isSequentialOrUndefInRange - Return true if every element in Mask, beginning from position Pos and ending in Pos+Size, falls within the specified sequential range (L, L+Pos]. or is undef.

Definition at line 3854 of file X86ISelLowering.cpp.

References isUndefOrEqual().

Referenced by isINSERT64x4Mask(), isPSHUFHWMask(), isPSHUFLWMask(), and isVPERM2X128Mask().

static bool isShuffleHigh128VectorInsertLow ( ShuffleVectorSDNode * SVOp ) [static]

isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the same as extracting the high 128-bit part of 256-bit vector and then inserting the result into the low part of a new 256-bit vector

Definition at line 19391 of file X86ISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), and isUndefOrEqual().

Referenced by PerformShuffleCombine256().

static bool isShuffleLow128VectorInsertHigh ( ShuffleVectorSDNode * SVOp ) [static]

isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the same as extracting the low 128-bit part of 256-bit vector and then inserting the result into the high part of a new 256-bit vector

Definition at line 19407 of file X86ISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), and isUndefOrEqual().

Referenced by PerformShuffleCombine256().

static bool isShuffleMaskConsecutive	(	ShuffleVectorSDNode *	SVOp,
		unsigned	MaskI,
		unsigned	MaskE,
		unsigned	OpIdx,
		unsigned	NumElems,
		unsigned &	OpNum
	)		`[static]`

isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE) correspond consecutively to elements from one of the vector operands, starting from its index OpIdx. Also tell OpNum which source vector operand.

Definition at line 5533 of file X86ISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt().

Referenced by isVectorShiftLeft(), and isVectorShiftRight().

static bool isSHUFPMask	(	ArrayRef< int >	Mask,
		MVT	VT,
		bool	Commuted = `false`
	)		`[static]`

isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to 128/256-bit SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be reverse of what x86 shuffles want.

Definition at line 4042 of file X86ISelLowering.cpp.

References llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), and isUndefOrInRange().

static bool isSingleInputShuffleMask ( ArrayRef< int > Mask ) [static]

Helper function to classify a mask as a single-input mask.

This isn't a generic single-input test because in the vector shuffle lowering we canonicalize single inputs to be the first input operand. This means we can more quickly test for a single input by only checking whether an input from the second operand exists. We also assume that the size of mask corresponds to the size of the input vectors which isn't true in the fully general case.

Definition at line 7149 of file X86ISelLowering.cpp.

Referenced by canLowerByDroppingEvenElements(), lowerV16I8VectorShuffle(), lowerV2F64VectorShuffle(), lowerV2I64VectorShuffle(), and lowerV4F64VectorShuffle().

static bool IsTailCallConvention ( CallingConv::ID CC ) [static]

IsTailCallConvention - Return true if the calling convention is one that supports tail call optimization.

Definition at line 2258 of file X86ISelLowering.cpp.

References llvm::CallingConv::Fast, llvm::CallingConv::GHC, and llvm::CallingConv::HiPE.

Referenced by FuncIsMadeTailCallSafe().

static bool isTargetShuffle ( unsigned Opcode ) [static]

static bool isTruncWithZeroHighBitsInput	(	SDValue	V,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 13659 of file X86ISelLowering.cpp.

References llvm::tgtok::Bits, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SelectionDAG::MaskedValueIsZero(), and llvm::ISD::TRUNCATE.

static bool isUndefOrEqual	(	int	Val,
		int	CmpVal
	)		`[static]`

isUndefOrEqual - Val is either less than zero (undef) or equal to the specified value.

Definition at line 3847 of file X86ISelLowering.cpp.

Referenced by Compact8x32ShuffleNode(), isAlignrMask(), isCommutedMOVLMask(), isMOVDDUPMask(), isMOVDDUPYMask(), isMOVHLPS_v_undef_Mask(), isMOVHLPSMask(), isMOVLHPSMask(), isMOVLMask(), isMOVLPMask(), isMOVSHDUPMask(), isMOVSLDUPMask(), isSequentialOrUndefInRange(), isShuffleHigh128VectorInsertLow(), isShuffleLow128VectorInsertHigh(), isUNPCKH_v_undef_Mask(), isUNPCKHMask(), isUNPCKL_v_undef_Mask(), isUNPCKLMask(), isVPERMILPMask(), PerformShuffleCombine256(), ShouldXformToMOVHLPS(), and ShouldXformToMOVLP().

static bool isUndefOrInRange	(	int	Val,
		int	Low,
		int	Hi
	)		`[static]`

isUndefOrInRange - Return true if Val is undef or if its value falls within the specified range (L, H].

Definition at line 3841 of file X86ISelLowering.cpp.

References llvm::HexagonISD::Hi.

Referenced by getUnderlyingExtractedFromVec(), isAlignrMask(), isCommutedMOVLMask(), isPermImmMask(), isPSHUFHWMask(), isPSHUFLWMask(), isSHUFPMask(), and isVPERMILPMask().

static bool isUNPCKH_v_undef_Mask	(	ArrayRef< int >	Mask,
		MVT	VT,
		bool	HasInt256
	)		`[static]`

isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, <2, 2, 3, 3>

Definition at line 4379 of file X86ISelLowering.cpp.

References llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), and isUndefOrEqual().

static bool isUNPCKHMask	(	ArrayRef< int >	Mask,
		MVT	VT,
		bool	HasInt256,
		bool	V2IsSplat = `false`
	)		`[static]`

isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to UNPCKH.

Definition at line 4298 of file X86ISelLowering.cpp.

References llvm::MVT::getScalarType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), and isUndefOrEqual().

static bool isUNPCKL_v_undef_Mask	(	ArrayRef< int >	Mask,
		MVT	VT,
		bool	HasInt256
	)		`[static]`

isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, <0, 0, 1, 1>

Definition at line 4336 of file X86ISelLowering.cpp.

References llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), and isUndefOrEqual().

static bool isUNPCKLMask	(	ArrayRef< int >	Mask,
		MVT	VT,
		bool	HasInt256,
		bool	V2IsSplat = `false`
	)		`[static]`

isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to UNPCKL.

Definition at line 4259 of file X86ISelLowering.cpp.

References llvm::MVT::getScalarType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), and isUndefOrEqual().

static bool isVALIGNMask	(	ArrayRef< int >	Mask,
		MVT	VT,
		const X86Subtarget *	Subtarget
	)		`[static]`

Return true if the node specifies a shuffle of elements that is suitable for input to VALIGN.

Definition at line 4015 of file X86ISelLowering.cpp.

References llvm::MVT::is512BitVector(), and isAlignrMask().

static bool isVectorShift	(	ShuffleVectorSDNode *	SVOp,
		SelectionDAG &	DAG,
		bool &	isLeft,
		SDValue &	ShVal,
		unsigned &	ShAmt
	)		`[static]`

isVectorShift - Returns true if the shuffle can be implemented as a logical left or right shift of a vector.

Definition at line 5631 of file X86ISelLowering.cpp.

References llvm::SDNode::getSimpleValueType(), llvm::MVT::is128BitVector(), isVectorShiftLeft(), and isVectorShiftRight().

static bool isVectorShiftLeft	(	ShuffleVectorSDNode *	SVOp,
		SelectionDAG &	DAG,
		bool &	isLeft,
		SDValue &	ShVal,
		unsigned &	ShAmt
	)		`[static]`

isVectorShiftLeft - Returns true if the shuffle can be implemented as a logical left shift of a vector.

Definition at line 5596 of file X86ISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), getNumOfConsecutiveZeros(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getVectorNumElements(), and isShuffleMaskConsecutive().

Referenced by isVectorShift().

static bool isVectorShiftRight	(	ShuffleVectorSDNode *	SVOp,
		SelectionDAG &	DAG,
		bool &	isLeft,
		SDValue &	ShVal,
		unsigned &	ShAmt
	)		`[static]`

isVectorShiftRight - Returns true if the shuffle can be implemented as a logical left shift of a vector.

Definition at line 5561 of file X86ISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), getNumOfConsecutiveZeros(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getVectorNumElements(), and isShuffleMaskConsecutive().

Referenced by isVectorShift().

static bool isVEXTRACTIndex	(	SDNode *	N,
		unsigned	vecWidth
	)		`[static]`

isVEXTRACTIndex - Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector extract that is suitable for instruction that extract 128 or 256 bit vectors

Definition at line 4699 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), and llvm::MVT::getVectorElementType().

Referenced by llvm::X86::isVEXTRACT128Index(), and llvm::X86::isVEXTRACT256Index().

static bool isVINSERTIndex	(	SDNode *	N,
		unsigned	vecWidth
	)		`[static]`

isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR operand specifies a subvector insert that is suitable for input to insertion of 128 or 256-bit subvectors

Definition at line 4718 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), and llvm::MVT::getVectorElementType().

Referenced by llvm::X86::isVINSERT128Index(), and llvm::X86::isVINSERT256Index().

static bool isVPERM2X128Mask	(	ArrayRef< int >	Mask,
		MVT	VT,
		bool	HasFp256
	)		`[static]`

isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered as permutations between 128-bit chunks or halves. As an example: this shuffle bellow: vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> The first half comes from the second half of V1 and the second half from the the second half of V2.

Definition at line 4460 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::MVT::is256BitVector(), and isSequentialOrUndefInRange().

static bool isVPERMILPMask	(	ArrayRef< int >	Mask,
		MVT	VT
	)		`[static]`

isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to VPERMILPD*. Note that VPERMIL mask matching is different depending whether theunderlying type is 32 or 64. In the VPERMILPS the high half of the mask should point to the same elements of the low, but to the higher half of the source. In VPERMILPD the two lanes could be shuffled independently of each other with the same restriction that lanes can't be crossed. Also handles PSHUFDY.

Definition at line 4558 of file X86ISelLowering.cpp.

References llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), isUndefOrEqual(), and isUndefOrInRange().

static bool isX86CCUnsigned ( unsigned X86CC ) [static]

Return true if the condition is an unsigned comparison operation.

Definition at line 3692 of file X86ISelLowering.cpp.

References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, MSP430CC::COND_E, llvm::X86::COND_G, MSP430CC::COND_GE, MSP430CC::COND_L, llvm::X86::COND_LE, MSP430CC::COND_NE, and llvm_unreachable.

static bool isX86LogicalCmp ( SDValue Op ) [static]

Definition at line 13634 of file X86ISelLowering.cpp.

References llvm::AArch64ISD::ADC, ADD, AND, llvm::ARMISD::CMP, llvm::COMI, DEC, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getResNo(), INC, OR, llvm::X86ISD::SAHF, llvm::X86ISD::SBB, llvm::X86ISD::SMUL, SUB, llvm::X86ISD::UCOMI, llvm::AMDGPUISD::UMUL, and XOR.

static bool isXor1OfSetCC ( SDValue Op ) [static]

Definition at line 14186 of file X86ISelLowering.cpp.

References llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::SETCC, and XOR.

static bool isZero ( SDValue V ) [static]

isZero - Returns true if Elt is a constant integer zero

Definition at line 4927 of file X86ISelLowering.cpp.

References llvm::CallingConv::C, llvm::dyn_cast(), and llvm::ConstantSDNode::isNullValue().

Referenced by BUILD_VECTORtoBlendMask(), llvm::X86::isZeroNode(), and PerformSELECTCombine().

static bool isZeroShuffle ( ShuffleVectorSDNode * N ) [static]

isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved to an zero vector. FIXME: move to dag combiner / method on ShuffleVectorSDNode

Definition at line 5030 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorAllZeros(), llvm::X86::isZeroNode(), llvm::ISD::UNDEF, and llvm::NVPTX::PTXLdStInstCode::V2.

Referenced by NormalizeVectorShuffle().

static SDValue lower128BitVectorShuffle	(	SDValue	Op,
		SDValue	V1,
		SDValue	V2,
		MVT	VT,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Dispatching routine to lower various 128-bit x86 vector shuffles.

This routine breaks down the specific type of 128-bit shuffle and dispatches to the lowering routines accordingly.

Definition at line 8822 of file X86ISelLowering.cpp.

References llvm_unreachable, lowerV16I8VectorShuffle(), lowerV2F64VectorShuffle(), lowerV2I64VectorShuffle(), lowerV4F32VectorShuffle(), lowerV4I32VectorShuffle(), lowerV8I16VectorShuffle(), and llvm::MVT::SimpleTy.

Referenced by lowerVectorShuffle().

static SDValue lower256BitVectorShuffle	(	SDValue	Op,
		SDValue	V1,
		SDValue	V2,
		MVT	VT,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

High-level routine to lower various 256-bit x86 vector shuffles.

This routine either breaks down the specific type of a 256-bit x86 vector shuffle or splits it into two 128-bit shuffles and fuses the results back together based on the available instructions.

Definition at line 9035 of file X86ISelLowering.cpp.

References llvm_unreachable, lowerV4F64VectorShuffle(), lowerV4I64VectorShuffle(), llvm::MVT::SimpleTy, and splitAndLower256BitVectorShuffle().

Referenced by lowerVectorShuffle().

static SDValue Lower256IntArith	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 16000 of file X86ISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, Extract128BitVector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::is256BitVector(), and llvm::MVT::isInteger().

Referenced by LowerADD(), LowerMUL(), and LowerSUB().

static SDValue Lower256IntVSETCC	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 13224 of file X86ISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, Extract128BitVector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::is256BitVector(), and llvm::ISD::SETCC.

Referenced by LowerVSETCC().

static SDValue LowerADD	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 16027 of file X86ISelLowering.cpp.

References llvm::SDValue::getSimpleValueType(), llvm::MVT::is256BitVector(), llvm::MVT::isInteger(), and Lower256IntArith().

static SDValue LowerADDC_ADDE_SUBC_SUBE	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 17171 of file X86ISelLowering.cpp.

References llvm::AArch64ISD::ADC, ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getVTList(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::X86ISD::SBB, SUB, llvm::ISD::SUBC, and llvm::ISD::SUBE.

static SDValue LowerADJUST_TRAMPOLINE	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 15697 of file X86ISelLowering.cpp.

References llvm::SDValue::getOperand().

static SDValue LowerANY_EXTEND	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 12328 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), and LowerAVXExtend().

static SDValue LowerAsSplatVectorLoad	(	SDValue	SrcOp,
		MVT	VT,
		SDLoc	dl,
		SelectionDAG &	DAG
	)		`[static]`

static SDValue LowerATOMIC_FENCE	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 17002 of file X86ISelLowering.cpp.

References llvm::CrossThread, llvm::N86::ESP, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), llvm::X86ISD::MEMBARRIER, llvm::X86ISD::MFENCE, and llvm::SequentiallyConsistent.

static SDValue LowerATOMIC_STORE	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 17146 of file X86ISelLowering.cpp.

References llvm::ISD::ATOMIC_SWAP, llvm::SelectionDAG::getAtomic(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::TargetLoweringBase::isTypeLegal(), Node, and llvm::SequentiallyConsistent.

static SDValue LowerAVXCONCAT_VECTORS	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 7078 of file X86ISelLowering.cpp.

References Concat128BitVectors(), Concat256BitVectors(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOperand(), llvm::MVT::getScalarType(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorNumElements(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), llvm::NVPTX::PTXLdStInstCode::V2, and llvm::NVPTX::PTXLdStInstCode::V4.

Referenced by LowerCONCAT_VECTORS().

static SDValue LowerAVXExtend	(	SDValue	Op,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

static SDValue LowerBITCAST	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 17079 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::isVector(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

static SDValue LowerBuildVectorv16i8	(	SDValue	Op,
		unsigned	NonZeros,
		unsigned	NumNonZero,
		unsigned	NumZero,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget,
		const TargetLowering &	TLI
	)		`[static]`

LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.

Definition at line 5647 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), getZeroVector(), llvm::ISD::INSERT_VECTOR_ELT, OR, llvm::ISD::SHL, and llvm::ISD::ZERO_EXTEND.

static SDValue LowerBuildVectorv4x32	(	SDValue	Op,
		unsigned	NumElems,
		unsigned	NonZeros,
		unsigned	NumNonZero,
		unsigned	NumZero,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget,
		const TargetLowering &	TLI
	)		`[static]`

LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.

Definition at line 5726 of file X86ISelLowering.cpp.

References llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::X86ISD::INSERTPS, llvm::X86::isZeroNode(), and llvm::ISD::UNDEF.

static SDValue LowerBuildVectorv8i16	(	SDValue	Op,
		unsigned	NonZeros,
		unsigned	NumNonZero,
		unsigned	NumZero,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget,
		const TargetLowering &	TLI
	)		`[static]`

LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.

Definition at line 5695 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), getZeroVector(), and llvm::ISD::INSERT_VECTOR_ELT.

static SDValue LowerCMP_SWAP	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

static SDValue LowerCONCAT_VECTORS	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 7102 of file X86ISelLowering.cpp.

References llvm::SDValue::getNumOperands(), llvm::SDValue::getSimpleValueType(), LLVM_ATTRIBUTE_UNUSED, and LowerAVXCONCAT_VECTORS().

static SDValue LowerCTLZ	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 15919 of file X86ISelLowering.cpp.

References llvm::X86ISD::BSR, llvm::ARMISD::CMOV, MSP430CC::COND_E, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::ISD::TRUNCATE, XOR, and llvm::ISD::ZERO_EXTEND.

static SDValue LowerCTLZ_ZERO_UNDEF	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 15953 of file X86ISelLowering.cpp.

References llvm::X86ISD::BSR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getVTList(), llvm::ISD::TRUNCATE, XOR, and llvm::ISD::ZERO_EXTEND.

static SDValue LowerCTTZ	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 15978 of file X86ISelLowering.cpp.

References llvm::X86ISD::BSF, llvm::ARMISD::CMOV, MSP430CC::COND_E, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDValue::getValue(), and llvm::SelectionDAG::getVTList().

static SDValue LowerExtendedLoad	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 13973 of file X86ISelLowering.cpp.

static SDValue LowerEXTRACT_SUBVECTOR	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 11261 of file X86ISelLowering.cpp.

References Extract128BitVector(), Extract256BitVector(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), and llvm::MVT::is512BitVector().

static SDValue LowerEXTRACT_VECTOR_ELT_SSE4	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

static SDValue LowerFABSorFNEG	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

static SDValue LowerFCOPYSIGN	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

static SDValue LowerFGETSIGN	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 12681 of file X86ISelLowering.cpp.

References AND, llvm::X86ISD::FGETSIGNx86, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), and llvm::SDValue::getSimpleValueType().

static SDValue LowerFP_EXTEND	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 12536 of file X86ISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), and llvm::X86ISD::VFPEXT.

static SDValue LowerFSINCOS	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 17197 of file X86ISelLowering.cpp.

References llvm::CallingConv::C, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getExternalSymbol(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::TargetLowering::ArgListEntry::isSExt, llvm::TargetLowering::ArgListEntry::isZExt, llvm::TargetLowering::LowerCallTo(), llvm::ISD::MERGE_VALUES, llvm::TargetLowering::ArgListEntry::Node, llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), and llvm::TargetLowering::ArgListEntry::Ty.

static SDValue LowerINSERT_SUBVECTOR	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 11287 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), Insert128BitVector(), Insert256BitVector(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), and llvm::MVT::is512BitVector().

static SDValue lowerIntegerElementInsertionVectorShuffle	(	MVT	VT,
		SDLoc	DL,
		SDValue	V1,
		SDValue	V2,
		ArrayRef< int >	Mask,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 7608 of file X86ISelLowering.cpp.

References llvm::ArrayRef< T >::begin(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ArrayRef< T >::end(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getScalarShiftAmountTy(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::ISD::isBuildVectorAllZeros(), llvm::X86::isZeroNode(), llvm::ISD::SCALAR_TO_VECTOR, llvm::ArrayRef< T >::size(), llvm::ISD::UNDEF, llvm::NVPTX::PTXLdStInstCode::V2, llvm::X86ISD::VSHLDQ, llvm::X86ISD::VZEXT_MOVL, and llvm::ISD::ZERO_EXTEND.

Referenced by lowerV16I8VectorShuffle(), lowerV4I32VectorShuffle(), and lowerV8I16VectorShuffle().

static SDValue LowerINTRINSIC_W_CHAIN	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 15472 of file X86ISelLowering.cpp.

static SDValue LowerINTRINSIC_WO_CHAIN	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 14906 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::COMI, llvm::X86::COND_A, llvm::X86::COND_B, MSP430CC::COND_E, MSP430CC::COND_INVALID, llvm::X86::COND_O, llvm::X86::COND_S, llvm::X86::CUR_DIRECTION, llvm::AArch64ISD::FMAX, llvm::AArch64ISD::FMIN, llvm::SelectionDAG::getConstant(), llvm::getIntrinsicWithoutChain(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), getOpcodeForFMAIntrinsic(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), getTargetVShiftNode(), llvm::SDValue::getValueType(), getVectorMaskingNode(), llvm::SelectionDAG::getVTList(), llvm::INTR_TYPE_1OP, llvm::INTR_TYPE_2OP, llvm::INTR_TYPE_3OP, llvm::X86ISD::KORTEST, llvm_unreachable, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::SDNode::op_begin(), llvm::SDNode::op_end(), llvm::IntrinsicData::Opc0, llvm::IntrinsicData::Opc1, llvm::X86ISD::PACKSS, llvm::X86ISD::PACKUS, llvm::X86ISD::PCMPESTRI, llvm::X86ISD::PCMPISTRI, llvm::X86ISD::PMULDQ, llvm::X86ISD::PMULUDQ, llvm::X86ISD::PSHUFB, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::X86ISD::PSIGN, llvm::X86ISD::PTEST, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::X86ISD::TESTP, TranslateX86CC(), llvm::IntrinsicData::Type, llvm::X86ISD::VALIGN, llvm::X86ISD::VPERMV, llvm::VSHIFT, and llvm::ISD::ZERO_EXTEND.

static SDValue LowerIntVSETCC_AVX512	(	SDValue	Op,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

static SDValue LowerLOAD_SUB	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 17131 of file X86ISelLowering.cpp.

References llvm::ISD::ATOMIC_LOAD_ADD, llvm::SelectionDAG::getAtomic(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), Node, and SUB.

static SDValue LowerMUL	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 16041 of file X86ISelLowering.cpp.

References llvm::ARM_PROC::A, ADD, llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), getTargetVShiftByConstNode(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::is256BitVector(), Lower256IntArith(), llvm::X86ISD::PMULUDQ, llvm::X86ISD::VSHLI, and llvm::X86ISD::VSRLI.

static SDValue LowerMUL_LOHI	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 16165 of file X86ISelLowering.cpp.

References ADD, AND, llvm::ISD::BITCAST, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::X86ISD::PMULDQ, llvm::X86ISD::PMULUDQ, llvm::ISD::SMUL_LOHI, llvm::ISD::SRA, and SUB.

static SDValue LowerREADCYCLECOUNTER	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 15462 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), getReadTimeStampCounter(), and llvm::X86ISD::RDTSC_DAG.

static SDValue LowerSCALAR_TO_VECTOR	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 11230 of file X86ISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), Insert128BitVector(), llvm::MVT::is128BitVector(), and llvm::ISD::SCALAR_TO_VECTOR.

static SDValue LowerScalarImmediateShift	(	SDValue	Op,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

static SDValue LowerScalarVariableShift	(	SDValue	Op,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 16412 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::ISD::BUILD_VECTOR, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getIntPtrConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), getTargetVShiftNode(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), llvm::ISD::INSERT_VECTOR_ELT, llvm_unreachable, llvm::ISD::SHL, llvm::MVT::SimpleTy, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, llvm::ISD::UNDEF, llvm::ISD::VECTOR_SHUFFLE, llvm::AArch64ISD::VSHL, llvm::X86ISD::VSHLI, llvm::X86ISD::VSRA, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRL, llvm::X86ISD::VSRLI, and llvm::ISD::ZERO_EXTEND.

Referenced by LowerShift().

static SDValue LowerShift	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 16556 of file X86ISelLowering.cpp.

References ADD, AND, llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, Extract128BitVector(), llvm::ISD::FP_TO_SINT, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MVT::getScalarType(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSizeInBits(), getTargetShuffleNode(), getTargetVShiftByConstNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::APInt::getZExtValue(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isVector(), LowerScalarImmediateShift(), LowerScalarVariableShift(), llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSS, llvm::ISD::MUL, llvm::X86ISD::PCMPEQ, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::ISD::SHL, llvm::APInt::shl(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, llvm::ISD::UNDEF, llvm::NVPTX::PTXLdStInstCode::V2, llvm::ISD::VSELECT, llvm::X86ISD::VSHLI, and llvm::ISD::ZERO_EXTEND.

static SDValue LowerShiftParts	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and take a 2 x i32 value to shift plus a shift amount.

Definition at line 11799 of file X86ISelLowering.cpp.

References AND, llvm::ARMISD::CMOV, llvm::ARMISD::CMP, MSP430CC::COND_NE, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::HexagonISD::Hi, llvm::HexagonISD::Lo, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::X86ISD::SHLD, llvm::X86ISD::SHRD, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, and llvm::ISD::SRL.

static SDValue LowerSIGN_EXTEND	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 13916 of file X86ISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::getScalarType(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::is512BitVector(), LowerSIGN_EXTEND_AVX512(), and llvm::X86ISD::VSEXT.

static SDValue LowerSIGN_EXTEND_AVX512	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 13885 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getConstantPool(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::is512BitVector(), llvm::X86ISD::VBROADCASTM, llvm::X86ISD::VSEXT, and llvm::X86ISD::VTRUNC.

Referenced by LowerSIGN_EXTEND().

static SDValue LowerSUB	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 16034 of file X86ISelLowering.cpp.

References llvm::SDValue::getSimpleValueType(), llvm::MVT::is256BitVector(), llvm::MVT::isInteger(), and Lower256IntArith().

static SDValue LowerToTLSExecModel	(	GlobalAddressSDNode *	GA,
		SelectionDAG &	DAG,
		const EVT	PtrVT,
		TLSModel::Model	model,
		bool	is64Bit,
		bool	isPIC
	)		`[static]`

static SDValue LowerToTLSGeneralDynamicModel32	(	GlobalAddressSDNode *	GA,
		SelectionDAG &	DAG,
		const EVT	PtrVT
	)		`[static]`

Definition at line 11544 of file X86ISelLowering.cpp.

References llvm::N86::EAX, llvm::N86::EBX, llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getNode(), GetTLSADDR(), llvm::SDValue::getValue(), llvm::PPCISD::GlobalBaseReg, and llvm::MipsII::MO_TLSGD.

static SDValue LowerToTLSGeneralDynamicModel64	(	GlobalAddressSDNode *	GA,
		SelectionDAG &	DAG,
		const EVT	PtrVT
	)		`[static]`

Definition at line 11558 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getEntryNode(), GetTLSADDR(), and llvm::MipsII::MO_TLSGD.

static SDValue LowerToTLSLocalDynamicModel	(	GlobalAddressSDNode *	GA,
		SelectionDAG &	DAG,
		const EVT	PtrVT,
		bool	is64Bit
	)		`[static]`

static SDValue lowerV16I8VectorShuffle	(	SDValue	Op,
		SDValue	V1,
		SDValue	V2,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Generic lowering of v16i8 shuffles.

This is a hybrid strategy to lower v16i8 vectors. It first attempts to detect any complexity reducing interleaving. If that doesn't help, it uses UNPCK to spread the i8 elements across two i16-element vectors, and uses the existing lowering for v8i16 blends on each half, finally PACK-ing them back together.

Definition at line 8527 of file X86ISelLowering.cpp.

References AND, llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::MutableArrayRef< T >::begin(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, canLowerByDroppingEvenElements(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::MutableArrayRef< T >::end(), llvm::SmallVectorImpl< T >::erase(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), getZeroVector(), I, isSingleInputShuffleMask(), lowerIntegerElementInsertionVectorShuffle(), lowerVectorShuffleAsByteRotate(), OR, llvm::X86ISD::PACKUS, llvm::X86ISD::PSHUFB, shouldLowerAsInterleaving(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::ArrayRef< T >::size(), llvm::MutableArrayRef< T >::slice(), llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, and llvm::NVPTX::PTXLdStInstCode::V2.

Referenced by lower128BitVectorShuffle().

static SDValue lowerV2F64VectorShuffle	(	SDValue	Op,
		SDValue	V1,
		SDValue	V2,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Handle lowering of 2-lane 64-bit floating point shuffles.

This is the basis function for the 2-lane 64-bit shuffles as we have full support for floating point shuffles but not integer shuffles. These instructions will incur a domain crossing penalty on some chips though so it is better to avoid lowering through this for integer vectors where possible.

Definition at line 7363 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), isShuffleEquivalent, isSingleInputShuffleMask(), lowerVectorShuffleAsBlend(), llvm::X86ISD::SHUFP, llvm::X86ISD::UNPCKH, and llvm::X86ISD::UNPCKL.

Referenced by lower128BitVectorShuffle().

static SDValue lowerV2I64VectorShuffle	(	SDValue	Op,
		SDValue	V1,
		SDValue	V2,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Handle lowering of 2-lane 64-bit integer shuffles.

Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by the integer unit to minimize domain crossing penalties. However, for blends it falls back to the floating point shuffle operation with appropriate bit casting.

Definition at line 7406 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), getV4X86ShuffleImm8ForMask(), llvm::SelectionDAG::getVectorShuffle(), isShuffleEquivalent, isSingleInputShuffleMask(), lowerVectorShuffleAsBlend(), llvm::X86ISD::PSHUFD, llvm::X86ISD::UNPCKH, and llvm::X86ISD::UNPCKL.

Referenced by lower128BitVectorShuffle().

static SDValue lowerV4F32VectorShuffle	(	SDValue	Op,
		SDValue	V1,
		SDValue	V2,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Lower 4-lane 32-bit floating point shuffles.

Uses instructions exclusively from the floating point unit to minimize domain crossing penalties, as these are sufficient to implement all v4f32 shuffles.

Definition at line 7457 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), getV4X86ShuffleImm8ForMask(), llvm::X86ISD::INSERTPS, llvm::ISD::isBuildVectorAllZeros(), isNoopShuffleMask(), isShuffleEquivalent, llvm::X86::isZeroNode(), lowerVectorShuffleAsBlend(), llvm::X86ISD::SHUFP, std::swap(), llvm::ISD::UNDEF, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, and llvm::NVPTX::PTXLdStInstCode::V2.

Referenced by lower128BitVectorShuffle().

static SDValue lowerV4F64VectorShuffle	(	SDValue	Op,
		SDValue	V1,
		SDValue	V2,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Handle lowering of 4-lane 64-bit floating point shuffles.

Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2 isn't available.

Definition at line 8924 of file X86ISelLowering.cpp.

References llvm::X86ISD::BLENDI, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), isHalfCrossingShuffleMask(), isShuffleEquivalent, isSingleInputShuffleMask(), llvm::X86ISD::SHUFP, splitAndLower256BitVectorShuffle(), llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, and llvm::X86ISD::VPERMILP.

Referenced by lower256BitVectorShuffle(), and lowerV4I64VectorShuffle().

static SDValue lowerV4I32VectorShuffle	(	SDValue	Op,
		SDValue	V1,
		SDValue	V2,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Lower 4-lane i32 vector shuffles.

We try to handle these with integer-domain shuffles where we can, but for blends we use the floating point domain blend instructions.

Definition at line 7687 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), getV4X86ShuffleImm8ForMask(), llvm::SelectionDAG::getVectorShuffle(), isShuffleEquivalent, lowerIntegerElementInsertionVectorShuffle(), lowerVectorShuffleAsBlend(), llvm::X86ISD::PSHUFD, llvm::X86ISD::UNPCKH, and llvm::X86ISD::UNPCKL.

Referenced by lower128BitVectorShuffle().

static SDValue lowerV4I64VectorShuffle	(	SDValue	Op,
		SDValue	V1,
		SDValue	V2,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Handle lowering of 4-lane 64-bit integer shuffles.

Largely delegates to common code when we have AVX2 and to the floating-point code when we only have AVX.

Definition at line 9005 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), isHalfCrossingShuffleMask(), lowerV4F64VectorShuffle(), and splitAndLower256BitVectorShuffle().

Referenced by lower256BitVectorShuffle().

static SDValue lowerV8I16BasicBlendVectorShuffle	(	SDLoc	DL,
		SDValue	V1,
		SDValue	V2,
		MutableArrayRef< int >	Mask,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Blend two v8i16 vectors using a naive unpack strategy.

This strategy only works when the inputs from each vector fit into a single half of that vector, and generally there are not so many inputs as to leave the in-place shuffles required highly constrained (and thus expensive). It shifts all the inputs into a single side of both input vectors and then uses an unpack to interleave these inputs in a single vector. At that point, we will fall back on the generic single input shuffle lowering.

Definition at line 8246 of file X86ISelLowering.cpp.

References llvm::sys::path::begin(), llvm::ArrayRef< T >::empty(), llvm::sys::path::end(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::ArrayRef< T >::size(), llvm::X86ISD::UNPCKH, and llvm::X86ISD::UNPCKL.

Referenced by lowerV8I16VectorShuffle().

static SDValue lowerV8I16SingleInputVectorShuffle	(	SDLoc	DL,
		SDValue	V,
		MutableArrayRef< int >	Mask,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Lowering of single-input v8i16 shuffles is the cornerstone of SSE2 shuffle lowering, and the most complex part.

The lowering strategy is to try to form pairs of input lanes which are targeted at the same half of the final vector, and then use a dword shuffle to place them onto the right half, and finally unpack the paired lanes into their final position.

The exact breakdown of how to form these dword pairs and align them on the correct sides is really tricky. See the comments within the function for more of the details.

Definition at line 7758 of file X86ISelLowering.cpp.

References llvm::sys::path::begin(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::ArrayRef< T >::begin(), llvm::MutableArrayRef< T >::begin(), llvm::ISD::BITCAST, llvm::SmallVectorTemplateCommon< T, typename >::data(), llvm::ArrayRef< T >::empty(), llvm::sys::path::end(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::ArrayRef< T >::end(), llvm::MutableArrayRef< T >::end(), llvm::SmallVectorImpl< T >::erase(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), getV4X86ShuffleImm8ForMask(), llvm::SelectionDAG::getVectorShuffle(), isNoopShuffleMask(), isShuffleEquivalent, llvm_unreachable, lowerVectorShuffleAsByteRotate(), llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::ArrayRef< T >::size(), llvm::MutableArrayRef< T >::slice(), std::swap(), llvm::X86ISD::UNPCKH, and llvm::X86ISD::UNPCKL.

Referenced by lowerV8I16VectorShuffle().

static SDValue lowerV8I16VectorShuffle	(	SDValue	Op,
		SDValue	V1,
		SDValue	V2,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Generic lowering of 8-lane i16 shuffles.

This handles both single-input shuffles and combined shuffle/blends with two inputs. The single input shuffles are immediately delegated to a dedicated lowering routine.

The blends are lowered in one of three fundamental ways. If there are few enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle of the input is significantly cheaper when lowered as an interleaving of the two inputs, try to interleave them. Otherwise, blend the low and high halves of the inputs separately (making them have relatively few inputs) and then concatenate them.

Definition at line 8366 of file X86ISelLowering.cpp.

References llvm::MutableArrayRef< T >::begin(), llvm::ISD::BITCAST, llvm::MutableArrayRef< T >::end(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getVectorShuffle(), lowerIntegerElementInsertionVectorShuffle(), lowerV8I16BasicBlendVectorShuffle(), lowerV8I16SingleInputVectorShuffle(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsByteRotate(), shouldLowerAsInterleaving(), llvm::ArrayRef< T >::size(), and llvm::X86ISD::UNPCKL.

Referenced by lower128BitVectorShuffle().

static SDValue LowerVACOPY	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 14713 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMemcpy(), and llvm::SDValue::getOperand().

static SDValue LowerVECTOR_SHUFFLE_128v4	(	ShuffleVectorSDNode *	SVOp,
		SelectionDAG &	DAG
	)		`[static]`

LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 4 elements, and match them with several different shuffle types.

Definition at line 9923 of file X86ISelLowering.cpp.

References CommuteVectorShuffleMask(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::is128BitVector(), std::swap(), and llvm::NVPTX::PTXLdStInstCode::V2.

static SDValue LowerVECTOR_SHUFFLE_256	(	ShuffleVectorSDNode *	SVOp,
		SelectionDAG &	DAG
	)		`[static]`

LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles which could not be matched by any known target speficic shuffle

Definition at line 9810 of file X86ISelLowering.cpp.

References llvm::array_lengthof(), llvm::ISD::BUILD_VECTOR, llvm::SmallVectorImpl< T >::clear(), Compact8x32ShuffleNode(), llvm::ISD::CONCAT_VECTORS, Extract128BitVector(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getIntPtrConstant(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().

static SDValue LowerVECTOR_SHUFFLEtoBlend	(	ShuffleVectorSDNode *	SVOp,
		unsigned	MaskValue,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 9224 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::X86ISD::BLENDI, llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), isBlendMask(), llvm::MipsISD::Ret, and llvm::NVPTX::PTXLdStInstCode::V2.

static SDValue LowerVECTOR_SHUFFLEv16i16	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

v16i16 shuffles

FIXME: We only support generation of a single pshufb currently. We can generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as well (e.g 2 x pshufb + 1 x por).

Definition at line 9552 of file X86ISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), getPSHUFB(), llvm::ISD::UNDEF, and llvm::NVPTX::PTXLdStInstCode::V2.

static SDValue LowerVECTOR_SHUFFLEv16i8	(	ShuffleVectorSDNode *	SVOp,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 9569 of file X86ISelLowering.cpp.

References AND, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SmallVectorImpl< T >::clear(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isBuildVectorAllZeros(), llvm::ShuffleVectorSDNode::isSplat(), OR, PromoteSplat(), llvm::X86ISD::PSHUFB, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SHL, llvm::ISD::SRL, llvm::ISD::UNDEF, and llvm::NVPTX::PTXLdStInstCode::V2.

static SDValue LowerVECTOR_SHUFFLEv32i8	(	ShuffleVectorSDNode *	SVOp,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 9698 of file X86ISelLowering.cpp.

References CommuteVectorShuffleMask(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), getPSHUFB(), llvm::SDNode::getSimpleValueType(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::UNDEF, and llvm::NVPTX::PTXLdStInstCode::V2.

static SDValue LowerVECTOR_SHUFFLEv8i16	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

static SDValue LowerVectorAllZeroTest	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 12694 of file X86ISelLowering.cpp.

static SDValue LowerVectorBroadcast	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

LowerVectorBroadcast - Attempt to use the vbroadcast instruction to generate a splat value for the following cases: 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant. 2. A splat shuffle which uses a scalar_to_vector node which comes from a scalar load, or a constant. The VBROADCAST node is returned when a pattern is found, or SDValue() otherwise.

Definition at line 5996 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::ISD::Constant, llvm::ISD::ConstantFP, Extract128BitVector(), llvm::SelectionDAG::getConstantPool(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::MVT::getVectorNumElements(), llvm::SDValue::hasOneUse(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), llvm::EVT::isInteger(), llvm::ISD::isNormalLoad(), llvm::ShuffleVectorSDNode::isSplat(), llvm::EVT::isVector(), llvm::ISD::SCALAR_TO_VECTOR, llvm::X86ISD::VBROADCAST, and llvm::ISD::VECTOR_SHUFFLE.

Referenced by NormalizeVectorShuffle().

static SDValue LowerVectorIntExtend	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 10286 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getIntPtrConstant(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::MVT::is256BitVector(), llvm::MVT::isInteger(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isTypeLegal(), llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::UNDEF, llvm::NVPTX::PTXLdStInstCode::V2, and llvm::X86ISD::VZEXT.

Referenced by NormalizeVectorShuffle().

static SDValue lowerVectorShuffle	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Top-level lowering for x86 vector shuffles.

This handles decomposition, canonicalization, and lowering of all x86 vector shuffles. Most of the specific lowering strategies are encapsulated above in helper routines. The canonicalization attempts to widen shuffles to involve fewer lanes of wider elements, consolidate symmetric patterns s.t. only one of the two inputs needs to be tested, etc.

Definition at line 9077 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, canWidenShuffleElements(), llvm::SelectionDAG::getCommutedVectorShuffle(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::isInteger(), llvm_unreachable, lower128BitVectorShuffle(), lower256BitVectorShuffle(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::UNDEF, and llvm::NVPTX::PTXLdStInstCode::V2.

static SDValue lowerVectorShuffleAsBlend	(	SDLoc	DL,
		MVT	VT,
		SDValue	V1,
		SDValue	V2,
		ArrayRef< int >	Mask,
		SelectionDAG &	DAG
	)		`[static]`

Try to emit a blend instruction for a shuffle.

This doesn't do any checks for the availability of instructions for blending these values. It relies on the availability of the X86ISD::BLENDI pattern to be matched in the backend with the type given. What it does check for is that the shuffle mask is in fact a blend.

Definition at line 7221 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::X86ISD::BLENDI, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorNumElements(), llvm::MVT::isFloatingPoint(), and llvm::ArrayRef< T >::size().

Referenced by lowerV2F64VectorShuffle(), lowerV2I64VectorShuffle(), lowerV4F32VectorShuffle(), lowerV4I32VectorShuffle(), and lowerV8I16VectorShuffle().

static SDValue lowerVectorShuffleAsByteRotate	(	SDLoc	DL,
		MVT	VT,
		SDValue	V1,
		SDValue	V2,
		ArrayRef< int >	Mask,
		SelectionDAG &	DAG
	)		`[static]`

Try to lower a vector shuffle as a byte rotation.

We have a generic PALIGNR instruction in x86 that will do an arbitrary byte-rotation of a the concatentation of two vectors. This routine will try to generically lower a vector shuffle through such an instruction. It does not check for the availability of PALIGNR-based lowerings, only the applicability of this strategy to the given mask. This matches shuffle vectors that look like:

v8i16 [11, 12, 13, 14, 15, 0, 1, 2]

Essentially it concatenates V1 and V2, shifts right by some number of elements, and takes the low elements as the result. Note that while this is specified as a *right shift* because x86 is little-endian, it is a *left rotate* of the vector lanes.

Note that this only handles 128-bit vector widths currently.

Definition at line 7276 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::HexagonISD::Hi, isNoopShuffleMask(), llvm::HexagonISD::Lo, llvm::X86ISD::PALIGNR, llvm::ArrayRef< T >::size(), and llvm::NVPTX::PTXLdStInstCode::V2.

Referenced by lowerV16I8VectorShuffle(), lowerV8I16SingleInputVectorShuffle(), and lowerV8I16VectorShuffle().

static SDValue LowerVSELECTtoBlend	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 10820 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::X86ISD::BLENDI, BUILD_VECTORtoBlendMask(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::is512BitVector(), llvm::ISD::isBuildVectorOfConstantSDNodes(), and llvm::MipsISD::Ret.

static SDValue LowerVSETCC	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 13322 of file X86ISelLowering.cpp.

References AND, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, ChangeVSETULTtoVSETULE(), llvm::X86ISD::CMPM, llvm::X86ISD::CMPP, EQ, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), getZeroVector(), llvm::AArch64CC::GT, llvm::MVT::is256BitVector(), llvm::EVT::is512BitVector(), llvm::MVT::isFloatingPoint(), llvm_unreachable, Lower256IntVSETCC(), LowerIntVSETCC_AVX512(), OR, llvm::X86ISD::PCMPEQ, llvm::X86ISD::PCMPGT, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::X86ISD::SUBUS, std::swap(), translateX86FSETCC(), llvm::ISD::TRUNCATE, llvm::AMDGPUISD::UMAX, llvm::AMDGPUISD::UMIN, and XOR.

static SDValue LowerXALUO	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

static SDValue LowerZERO_EXTEND	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 12339 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), LowerAVXExtend(), and LowerZERO_EXTEND_AVX512().

static SDValue LowerZERO_EXTEND_AVX512	(	SDValue	Op,
		SelectionDAG &	DAG
	)		`[static]`

static SDValue matchAddSub	(	const BuildVectorSDNode *	BV,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

Try to fold a build_vector that performs an 'addsub' into the sequence of 'vadd + vsub + blendi'.

Definition at line 6480 of file X86ISelLowering.cpp.

References llvm::X86ISD::ADDSUB, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FSUB, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), std::swap(), and llvm::ISD::UNDEF.

Referenced by PerformBUILD_VECTORCombine().

static bool MatchingStackOffset	(	SDValue	Arg,
		unsigned	Offset,
		ISD::ArgFlagsTy	Flags,
		MachineFrameInfo *	MFI,
		const MachineRegisterInfo *	MRI,
		const X86InstrInfo *	TII
	)		`[static]`

MatchingStackOffset - Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack.

Definition at line 3264 of file X86ISelLowering.cpp.

References llvm::ISD::CopyFromReg, llvm::tgtok::Def, llvm::dyn_cast(), llvm::ISD::FrameIndex, llvm::ISD::ArgFlagsTy::getByValSize(), llvm::MachineOperand::getIndex(), llvm::FrameIndexSDNode::getIndex(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::SDValue::getOpcode(), llvm::MachineInstr::getOpcode(), llvm::SDValue::getOperand(), llvm::MachineInstr::getOperand(), getReg(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::MachineRegisterInfo::getVRegDef(), llvm::ISD::ArgFlagsTy::isByVal(), llvm::MachineOperand::isFI(), and llvm::MachineFrameInfo::isFixedObjectIndex().

static std::pair<unsigned, bool> matchIntegerMINMAX	(	SDValue	Cond,
		EVT	VT,
		SDValue	LHS,
		SDValue	RHS,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

Matches a VSELECT onto min/max or return 0 if the node doesn't match.

Definition at line 20532 of file X86ISelLowering.cpp.

References llvm::SDValue::getOperand(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::isEqualTo(), llvm::EVT::isVector(), llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::MVT::SimpleTy, llvm::AMDGPUISD::SMAX, llvm::AMDGPUISD::SMIN, llvm::AMDGPUISD::UMAX, and llvm::AMDGPUISD::UMIN.

Referenced by PerformSELECTCombine().

static SDValue MaterializeSETB	(	SDLoc	DL,
		SDValue	EFLAGS,
		SelectionDAG &	DAG,
		MVT	VT
	)		`[static]`

Definition at line 23028 of file X86ISelLowering.cpp.

References AND, llvm::X86::COND_B, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::X86ISD::SETCC_CARRY, and llvm::ISD::TRUNCATE.

Referenced by PerformSETCCCombine().

static bool MayFoldIntoStore ( SDValue Op ) [static]

Definition at line 3534 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDValue::hasOneUse(), llvm::ISD::isNormalStore(), and llvm::SDNode::use_begin().

Referenced by getMOVLP().

static bool MayFoldLoad ( SDValue Op ) [static]

Definition at line 3530 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDValue::hasOneUse(), and llvm::ISD::isNormalLoad().

Referenced by getINSERTPS(), MayFoldVectorLoad(), and PerformINSERTPSCombine().

static bool MayFoldVectorLoad ( SDValue V ) [static]

Definition at line 10062 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), MayFoldLoad(), llvm::ISD::SCALAR_TO_VECTOR, and llvm::ISD::UNDEF.

Referenced by getMOVLP().

static SDValue NarrowVectorLoadToElement	(	LoadSDNode *	Load,
		unsigned	Index,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 10179 of file X86ISelLowering.cpp.

References ADD, llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getStoreSize(), and llvm::MVT::getVectorElementType().

Referenced by getINSERTPS(), and PerformINSERTPSCombine().

static void NormalizeMask	(	SmallVectorImpl< int > &	Mask,
		unsigned	NumElems
	)		`[static]`

NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements that point to V2 points to its first element.

Definition at line 5128 of file X86ISelLowering.cpp.

static SDValue NormalizeVectorShuffle	(	SDValue	Op,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 10373 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), getVZextMovL(), getZeroVector(), llvm::ISD::isBuildVectorAllZeros(), isCommutedMOVLMask(), isMOVLMask(), llvm::ShuffleVectorSDNode::isSplat(), isZeroShuffle(), LowerVectorBroadcast(), LowerVectorIntExtend(), RewriteAsNarrowerShuffle(), and llvm::NVPTX::PTXLdStInstCode::V2.

static SDValue OptimizeConditionalInDecrement	(	SDNode *	N,
		SelectionDAG &	DAG
	)		`[static]`

static SDValue PerformADCCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		X86TargetLowering::DAGCombinerInfo &	DCI
	)		`[static]`

Definition at line 23192 of file X86ISelLowering.cpp.

References AND, llvm::X86::COND_B, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::X86::isZeroNode(), llvm::X86ISD::SETCC_CARRY, and llvm::SDValue::use_empty().

static SDValue PerformAddCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

PerformADDCombine - Do target-specific dag combines on integer adds.

Definition at line 23257 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::X86ISD::HADD, isHorizontalBinOp(), and OptimizeConditionalInDecrement().

static SDValue PerformAndCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

static SDValue PerformBrCondCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 23086 of file X86ISelLowering.cpp.

References llvm::ISD::BRCOND, checkBoolTestSetCCCombine(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), and llvm::SDNode::getVTList().

static SDValue PerformBTCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI
	)		`[static]`

Definition at line 22769 of file X86ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), and llvm::Log2_32().

static SDValue PerformBUILD_VECTORCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

static SDValue PerformCMOVCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL].

Definition at line 21358 of file X86ISelLowering.cpp.

References ADD, llvm::X86ISD::BSF, llvm::X86ISD::BSR, checkBoolTestSetCCCombine(), llvm::ARMISD::CMOV, llvm::ARMISD::CMP, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), MSP430CC::COND_E, MSP430CC::COND_NE, llvm::SelectionDAG::getConstant(), llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), GetOppositeBranchCondition(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDNode::getVTList(), hasFPCMov(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::SelectionDAG::isKnownNeverZero(), llvm::ISD::MUL, llvm::ISD::SETCC, llvm::ISD::SHL, SUB, std::swap(), llvm::SDValue::use_empty(), and llvm::ISD::ZERO_EXTEND.

static SDValue PerformEXTRACT_VECTOR_ELTCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI
	)		`[static]`

PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index generation and convert it from being a bunch of shuffles and extracts to a simple store and scalar loads to extract the elements.

Definition at line 20436 of file X86ISelLowering.cpp.

References ADD, llvm::SmallVectorTemplateCommon< T >::begin(), llvm::ISD::BITCAST, llvm::SelectionDAG::CreateStackTemporary(), llvm::SmallVectorTemplateCommon< T >::end(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::X86ISD::MMX_MOVD2W, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SIGN_EXTEND, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), XFormVExtractWithShuffleIntoLoad(), and llvm::ISD::ZERO_EXTEND.

static SDValue PerformFADDCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

PerformFADDCombine - Do target-specific dag combines on floating point adds.

Definition at line 22677 of file X86ISelLowering.cpp.

References llvm::X86ISD::FHADD, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), and isHorizontalBinOp().

static SDValue PerformFANDCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		`[static]`

PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.

Definition at line 22744 of file X86ISelLowering.cpp.

References llvm::SDNode::getOperand().

static SDValue PerformFANDNCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		`[static]`

PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes.

Definition at line 22757 of file X86ISelLowering.cpp.

References llvm::SDNode::getOperand().

static SDValue PerformFMACombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 22855 of file X86ISelLowering.cpp.

References llvm::ARM_PROC::A, llvm::X86ISD::FMADD, llvm::X86ISD::FMSUB, llvm::ISD::FNEG, llvm::X86ISD::FNMADD, llvm::X86ISD::FNMSUB, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), and llvm::TargetLoweringBase::isTypeLegal().

static SDValue PerformFMinFMaxCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		`[static]`

PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.

Definition at line 22723 of file X86ISelLowering.cpp.

References llvm::AArch64ISD::FMAX, llvm::X86ISD::FMAXC, llvm::AArch64ISD::FMIN, llvm::X86ISD::FMINC, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTarget(), llvm::SDNode::getValueType(), llvm_unreachable, llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.

static SDValue PerformFORCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		`[static]`

PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.

Definition at line 22708 of file X86ISelLowering.cpp.

References llvm::X86ISD::FOR, llvm::X86ISD::FXOR, llvm::SDNode::getOpcode(), and llvm::SDNode::getOperand().

static SDValue PerformFSUBCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

PerformFSUBCombine - Do target-specific dag combines on floating point subs.

Definition at line 22692 of file X86ISelLowering.cpp.

References llvm::X86ISD::FHSUB, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), and isHorizontalBinOp().

static SDValue PerformINSERTPSCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 22998 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::X86ISD::INSERTPS, MayFoldLoad(), NarrowVectorLoadToElement(), and llvm::ISD::SCALAR_TO_VECTOR.

static SDValue performIntegerAbsCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		`[static]`

static SDValue PerformINTRINSIC_WO_CHAINCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 21529 of file X86ISelLowering.cpp.

References llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::APInt::getZExtValue(), llvm::ConstantSDNode::isAllOnesValue(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ConstantSDNode::isNullValue(), llvm::EVT::isVector(), and llvm::ISD::SRA.

static SDValue PerformISDSETCCCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

static SDValue PerformLOADCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

PerformLOADCombine - Do target-specific dag combines on LOAD nodes.

Definition at line 22274 of file X86ISelLowering.cpp.

References ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getLoad(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), Insert128BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::MemSDNode::isInvariant(), llvm::MemSDNode::isNonTemporal(), llvm::MemSDNode::isVolatile(), llvm::ISD::NON_EXTLOAD, and llvm::ISD::TokenFactor.

static SDValue PerformMulCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI
	)		`[static]`

PerformMulCombine - Optimize a single multiply with constant into two in order to implement it with two cheaper instructions, e.g. LEA + SHL, LEA + LEA.

Definition at line 21634 of file X86ISelLowering.cpp.

References ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isPowerOf2_64(), llvm::Log2_64(), llvm::X86ISD::MUL_IMM, llvm::ISD::SHL, std::swap(), and llvm::SDNode::use_begin().

static SDValue PerformOrCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 22062 of file X86ISelLowering.cpp.

References AND, llvm::X86ISD::ANDNP, llvm::ISD::BITCAST, llvm::tgtok::Bits, CMPEQCombine(), llvm::dyn_cast(), llvm::Function::getAttributes(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::SDValue::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::ISD::isBuildVectorAllZeros(), llvm::X86ISD::PSIGN, llvm::ISD::SHL, llvm::X86ISD::SHLD, llvm::X86ISD::SHRD, llvm::ISD::SRA, llvm::ISD::SRL, SUB, std::swap(), llvm::ISD::TRUNCATE, llvm::ISD::VSELECT, llvm::X86ISD::VSRAI, X, and Y.

static SDValue PerformSELECTCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT nodes.

Definition at line 20658 of file X86ISelLowering.cpp.

static SDValue PerformSETCCCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 23042 of file X86ISelLowering.cpp.

References checkBoolTestSetCCCombine(), llvm::X86::COND_A, llvm::X86::COND_B, llvm::SelectionDAG::getConstant(), llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SDNode::getVTList(), MaterializeSETB(), llvm::ISD::SETCC, and SUB.

static SDValue PerformSExtCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 22836 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isVector(), and WidenMaskArithmetic().

static SDValue PerformShiftCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

PerformShiftCombine - Combine shifts.

Definition at line 21767 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), performShiftToAllZeros(), PerformSHLCombine(), llvm::ISD::SHL, and llvm::ISD::SRA.

static SDValue performShiftToAllZeros	(	SDNode *	N,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

Returns a vector of 0s if the node in input is a vector logical shift by a constant amount which is known to be bigger than or equal to the vector element size in bits.

Definition at line 21739 of file X86ISelLowering.cpp.

References llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), getZeroVector(), llvm::APInt::trunc(), and llvm::APInt::uge().

Referenced by PerformShiftCombine().

static SDValue PerformSHLCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 21694 of file X86ISelLowering.cpp.

References ADD, AND, llvm::ISD::ANY_EXTEND, llvm::ISD::Constant, llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::isVector(), llvm::X86ISD::SETCC_CARRY, llvm::APInt::shl(), and llvm::ISD::ZERO_EXTEND.

Referenced by PerformShiftCombine().

static SDValue PerformShuffleCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

PerformShuffleCombine - Performs several different shuffle combines.

Definition at line 20220 of file X86ISelLowering.cpp.

References ADD, llvm::ISD::BITCAST, combineShuffleToAddSub(), combineX86ShufflesRecursively(), EltsFromConsecutiveLoads(), llvm::ISD::FADD, llvm::ISD::FMUL, llvm::ISD::FSUB, llvm::ShuffleVectorSDNode::getMask(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), getShuffleScalarElt(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::SDValue::hasOneUse(), llvm::EVT::is128BitVector(), llvm::EVT::is256BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::TargetLoweringBase::isOperationLegal(), isTargetShuffle(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::ISD::MUL, PerformShuffleCombine256(), PerformTargetShuffleCombine(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), SUB, llvm::ISD::UNDEF, and llvm::ISD::VECTOR_SHUFFLE.

static SDValue PerformShuffleCombine256	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.

Definition at line 19421 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::ISD::CONCAT_VECTORS, Extract128BitVector(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), getZeroVector(), llvm::SDNode::hasAnyUseOfValue(), llvm::SDNode::hasNUsesOfValue(), Insert128BitVector(), llvm::ISD::isBuildVectorAllZeros(), isShuffleHigh128VectorInsertLow(), isShuffleLow128VectorInsertHigh(), isUndefOrEqual(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::TokenFactor, llvm::ISD::UNDEF, llvm::SelectionDAG::UpdateNodeOperands(), and llvm::X86ISD::VZEXT_LOAD.

Referenced by PerformShuffleCombine().

static SDValue PerformSIGN_EXTEND_INREGCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 22801 of file X86ISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::ISD::isNormalLoad(), llvm::EVT::isVector(), llvm::ISD::LOAD, llvm::ISD::SIGN_EXTEND, and llvm::ISD::SIGN_EXTEND_INREG.

static SDValue PerformSINT_TO_FPCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const X86TargetLowering *	XTLI
	)		`[static]`

Definition at line 23153 of file X86ISelLowering.cpp.

References llvm::MemSDNode::getChain(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::ISD::isNON_EXTLoad(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), llvm::ISD::LOAD, P, performVectorCompareAndMaskUnaryOpCombine(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::SINT_TO_FP.

static SDValue PerformSTORECombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

PerformSTORECombine - Do target-specific dag combines on STORE nodes.

Definition at line 22321 of file X86ISelLowering.cpp.

static SDValue PerformSubCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 23272 of file X86ISelLowering.cpp.

References ADD, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), llvm::X86ISD::HSUB, isHorizontalBinOp(), OptimizeConditionalInDecrement(), and XOR.

static SDValue PerformTargetShuffleCombine	(	SDValue	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

Try to combine x86 target specific shuffles.

Definition at line 20061 of file X86ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::sys::path::begin(), llvm::ISD::BITCAST, canWidenShuffleElements(), combineRedundantDWordShuffle(), combineRedundantHalfShuffle(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::sys::path::end(), llvm::lltok::equal, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getPSHUFShuffleMask(), llvm::SDValue::getSimpleValueType(), getV4X86ShuffleImm8ForMask(), llvm::SDValue::hasOneUse(), isNoopShuffleMask(), llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::X86ISD::UNPCKH, and llvm::X86ISD::UNPCKL.

Referenced by PerformShuffleCombine().

static SDValue PerformTruncateCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

PerformTruncateCombine - Converts truncate operation to a sequence of vector shuffle operations. It is possible when we truncate 256-bit vector to 128-bit vector

Definition at line 20335 of file X86ISelLowering.cpp.

static SDValue performVectorCompareAndMaskUnaryOpCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 23107 of file X86ISelLowering.cpp.

References AND, llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::isVector(), and llvm::ISD::SETCC.

Referenced by PerformSINT_TO_FPCombine().

static SDValue PerformVZEXT_MOVLCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 22788 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), and llvm::X86ISD::VZEXT_LOAD.

static SDValue performVZEXTCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

performVZEXTCombine - Performs build vector combines

Definition at line 23306 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), and llvm::X86ISD::VZEXT.

static SDValue PerformXorCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 22258 of file X86ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), and performIntegerAbsCombine().

static SDValue PerformZExtCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 22895 of file X86ISelLowering.cpp.

References AND, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::EVT::is256BitVector(), llvm::X86ISD::SETCC_CARRY, llvm::ISD::TRUNCATE, and WidenMaskArithmetic().

static SDValue PromoteSplat	(	ShuffleVectorSDNode *	SV,
		SelectionDAG &	DAG
	)		`[static]`

PromoteSplat - Splat is promoted to target supported vector shuffles.

Definition at line 5220 of file X86ISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, Extract128BitVector(), getLegalSplat(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), and PromoteSplati8i16().

Referenced by LowerVECTOR_SHUFFLEv16i8(), and LowerVECTOR_SHUFFLEv8i16().

static SDValue PromoteSplati8i16	(	SDValue	V,
		SelectionDAG &	DAG,
		int &	EltNo
	)		`[static]`

Definition at line 5176 of file X86ISelLowering.cpp.

References llvm::SDValue::getSimpleValueType(), getUnpackh(), getUnpackl(), and llvm::MVT::getVectorNumElements().

Referenced by PromoteSplat().

static void ReplaceATOMIC_LOAD	(	SDNode *	Node,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG
	)		`[static]`

Definition at line 17339 of file X86ISelLowering.cpp.

References llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::SelectionDAG::getAtomicCmpSwap(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), Node, and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().

static SDValue RewriteAsNarrowerShuffle	(	ShuffleVectorSDNode *	SVOp,
		SelectionDAG &	DAG
	)		`[static]`

RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be done when every pair / quad of shuffle mask elements point to elements in the right sequence. e.g. vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>

Definition at line 9732 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MVT::SimpleTy, and llvm::NVPTX::PTXLdStInstCode::V2.

Referenced by NormalizeVectorShuffle().

static bool shouldLowerAsInterleaving ( ArrayRef< int > Mask ) [static]

Detect whether the mask pattern should be lowered through interleaving.

This essentially tests whether viewing the mask as an interleaving of two sub-sequences reduces the cross-input traffic of a blend operation. If so, lowering it through interleaving is a significantly better strategy.

Definition at line 8206 of file X86ISelLowering.cpp.

References llvm::ArrayRef< T >::size().

Referenced by lowerV16I8VectorShuffle(), and lowerV8I16VectorShuffle().

static bool ShouldXformToMOVHLPS	(	ArrayRef< int >	Mask,
		MVT	VT
	)		`[static]`

ShouldXformToMOVHLPS - Return true if the node should be transformed to match movhlps. The lower half elements should come from upper half of V1 (and in order), and the upper half elements should come from the upper half of V2 (and in order).

Definition at line 4946 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), and isUndefOrEqual().

static bool ShouldXformToMOVLP	(	SDNode *	V1,
		SDNode *	V2,
		ArrayRef< int >	Mask,
		MVT	VT
	)		`[static]`

ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to match movlp{s|d}. The lower half elements should come from lower half of V1 (and in order), and the upper half elements should come from the upper half of V2 (and in order). And since V1 will become the source of the MOVLP, it must be either a vector load or a scalar load to vector.

Definition at line 5002 of file X86ISelLowering.cpp.

References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::ISD::isNON_EXTLoad(), isScalarLoadToVector(), isUndefOrEqual(), and WillBeConstantPoolLoad().

static bool ShuffleCrosses128bitLane	(	MVT	VT,
		unsigned	InputIdx,
		unsigned	OutputIdx
	)		`[static]`

In vector type VT, return true if the element at index InputIdx falls on a different 128-bit lane than OutputIdx.

Definition at line 9256 of file X86ISelLowering.cpp.

References llvm::MVT::getSizeInBits(), and llvm::MVT::getVectorElementType().

Referenced by getPSHUFB().

static SDValue splitAndLower256BitVectorShuffle	(	SDValue	Op,
		SDValue	V1,
		SDValue	V2,
		const X86Subtarget *	Subtarget,
		SelectionDAG &	DAG
	)		`[static]`

Generic routine to split a 256-bit vector shuffle into 128-bit shuffles.

There is a severely limited set of shuffles available in AVX1 for 256-bit vectors resulting in routinely needing to split the shuffle into two 128-bit shuffles. This can be done generically for any 256-bit vector shuffle and so we encode the logic here for specific shuffle lowering routines to bail to when they exhaust the features avaible to more directly handle the shuffle.

Definition at line 8863 of file X86ISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarType(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::HexagonISD::Hi, llvm::HexagonISD::Lo, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and llvm::ArrayRef< T >::slice().

Referenced by lower256BitVectorShuffle(), lowerV4F64VectorShuffle(), and lowerV4I64VectorShuffle().

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"
	)

static SDValue TransformVSELECTtoBlendVECTOR_SHUFFLE	(	SDNode *	N,
		SelectionDAG &	DAG,
		const X86Subtarget *	Subtarget
	)		`[static]`

Definition at line 20606 of file X86ISelLowering.cpp.

References BUILD_VECTORtoBlendMask(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::is512BitVector(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::UNDEF.

Referenced by PerformSELECTCombine().

static unsigned TranslateX86CC	(	ISD::CondCode	SetCCOpcode,
		bool	isFP,
		SDValue &	LHS,
		SDValue &	RHS,
		SelectionDAG &	DAG
	)		`[static]`

TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 specific condition code, returning the condition code and the LHS/RHS of the comparison to make.

Definition at line 3712 of file X86ISelLowering.cpp.

References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, MSP430CC::COND_E, llvm::X86::COND_G, MSP430CC::COND_GE, MSP430CC::COND_INVALID, MSP430CC::COND_L, llvm::X86::COND_LE, MSP430CC::COND_NE, llvm::X86::COND_NP, llvm::X86::COND_NS, llvm::X86::COND_P, llvm::X86::COND_S, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::ISD::getSetCCSwappedOperands(), llvm::SDValue::getValueType(), llvm::ISD::isNON_EXTLoad(), llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, and std::swap().

Referenced by LowerINTRINSIC_WO_CHAIN().

static int translateX86FSETCC	(	ISD::CondCode	SetCCOpcode,
		SDValue &	Op0,
		SDValue &	Op1
	)		`[static]`

Turns an ISD::CondCode into a value suitable for SSE floating point mask CMPs.

Definition at line 13179 of file X86ISelLowering.cpp.

References llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, and std::swap().

Referenced by LowerVSETCC().

static SDValue WidenMaskArithmetic	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const X86Subtarget *	Subtarget
	)		`[static]`

static bool WillBeConstantPoolLoad ( SDNode * N ) [static]

Definition at line 4976 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), and llvm::ISD::UNDEF.

Referenced by ShouldXformToMOVLP().

static SDValue XFormVExtractWithShuffleIntoLoad	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI
	)		`[static]`

XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target specific shuffle of a load can be folded into a single element load. Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but shuffles have been customed lowered so we need to handle those here.

Definition at line 20345 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::DataLayout::getABITypeAlignment(), llvm::MemSDNode::getAlignment(), llvm::SelectionDAG::getContext(), llvm::TargetLoweringBase::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetLoweringInfo(), getTargetShuffleMask(), llvm::EVT::getTypeForEVT(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::SDNode::hasNUsesOfValue(), llvm::SDValue::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), isTargetShuffle(), llvm::MemSDNode::isVolatile(), and llvm::ISD::LOAD.

Referenced by PerformEXTRACT_VECTOR_ELTCombine().

Variable Documentation

cl::opt<bool> ExperimentalVectorShuffleLowering("x86-experimental-vector-shuffle-lowering", cl::init(false), cl::desc("Enable an experimental vector shuffle lowering code path."), cl::Hidden) [static]

cl::opt<bool> ExperimentalVectorWideningLegalization("x86-experimental-vector-widening-legalization", cl::init(false), cl::desc("Enable an experimental vector type legalization through widening ""rather than promotion."), cl::Hidden) [static]

const VariadicFunction1< bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {} [static]

Checks whether a shuffle mask is equivalent to an explicit list of arguments.

This is a fast way to test a shuffle mask against a fixed pattern:

if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }

It returns true if the mask is exactly as wide as the argument list, and each element of the mask is either -1 (signifying undef) or the value given in the argument.

Definition at line 7189 of file X86ISelLowering.cpp.

Referenced by combineShuffleToAddSub(), lowerV2F64VectorShuffle(), lowerV2I64VectorShuffle(), lowerV4F32VectorShuffle(), lowerV4F64VectorShuffle(), lowerV4I32VectorShuffle(), and lowerV8I16SingleInputVectorShuffle().

Defines

Enumerations

Functions

Variables

Define Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation